TWI739142B - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

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TWI739142B
TWI739142B TW108128494A TW108128494A TWI739142B TW I739142 B TWI739142 B TW I739142B TW 108128494 A TW108128494 A TW 108128494A TW 108128494 A TW108128494 A TW 108128494A TW I739142 B TWI739142 B TW I739142B
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dies
circuit layer
redistributed
circuit substrate
layer
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TW108128494A
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TW202107573A (zh
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蔡佩君
徐宏欣
張簡上煜
林南君
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力成科技股份有限公司
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Priority to TW108128494A priority Critical patent/TWI739142B/zh
Priority to US16/568,256 priority patent/US20210050296A1/en
Priority to CN201910984748.2A priority patent/CN112397462B/zh
Publication of TW202107573A publication Critical patent/TW202107573A/zh
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Publication of TWI739142B publication Critical patent/TWI739142B/zh

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Abstract

一種半導體封裝結構，其包括線路基板、重佈線路層以及至少二晶粒。線路基板具有第一表面與第一表面的第二表面。重佈線路層位於第一表面上。重佈線路層與線路基板電性連接。重佈線路層的相對的側壁的間隔小於線路基板的相對的側壁的間隔。重佈線路層與線路基板直接接觸。至少二晶粒配置於重佈線路層上。至少二晶粒中的每一者具有面向線路基板的主動面。至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者電性連接。另提供一種半導體封裝結構的製造方法。

Description

半導體封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種半導體封裝結構及其製造方法。
為了使得電子產品能達到輕薄短小的設計，半導體封裝技術亦跟著日益進展，以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。對於多功能半導體封裝而言，如何在微型化半導體封裝結構的同時還能夠提升半導體封裝結構的電性能力及/或效能實為本領域的技術人員的一大挑戰。
本發明提供一種半導體封裝結構及其製造方法，其可以在微型化半導體封裝結構的同時還能夠提升半導體封裝結構的電性能力及/或效能。
本發明提供一種半導體封裝結構，其包括線路基板、重佈線路層以及至少二晶粒。線路基板具有第一表面與第一表面的第二表面。重佈線路層位於第一表面上。重佈線路層與線路基板電性連接。重佈線路層的相對的側壁的間隔小於線路基板的相對的側壁的間隔。重佈線路層與線路基板直接接觸。至少二晶粒配置於重佈線路層上。至少二晶粒中的每一者具有面向線路基板的主動面。至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者電性連接。
本發明提供一種半導體封裝結構的製造方法，其至少包括以下步驟。提供線路基板。線路基板具有第一表面與相對於第一表面的第二表面。形成重佈線路層於第一表面上。重佈線路層與線路基板電性連接。重佈線路層的相對的側壁的間隔小於線路基板的相對的側壁的間隔。重佈線路層與線路基板直接接觸。配置至少二晶粒於重佈線路層上。至少二晶粒中的每一者具有面向線路基板的主動面。至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者電性連接。
基於上述，本發明的半導體封裝結構由於至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者電性連接，因此可以降低線路基板的繞線密度、減少線路基板的厚度，進而可以微型化半導體封裝結構並降低生產成本。再者，由於重佈線路層相較於線路基板可以具有較佳的細線距，因此，至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者進行電性連接可以縮短相鄰二晶粒之間的間距，進而提升半導體封裝結構的電性能力及/或效能。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1D是依據本發明一實施例的半導體封裝結構100的部分製造方法的部分剖面示意圖。
請參照圖1A，在本實施例中，半導體封裝結構100的製造過程可以包括以下步驟。首先，提供線路基板110。線路基板110具有第一表面110a以及相對於第一表面110a的第二表面110b。在一些實施例中，線路基板110可以為印刷電路板（Printed Circuit Board, PCB）、有機基板（organic substrate）或高密度內連線基板。在此，本發明不限制線路基板110的種類，只要線路基板110中具有適宜的繞線（routing）線路可以提供後續製程中所需的電性連接，皆屬於本發明的保護範圍。
請參照圖1B，於線路基板110的第一表面110a上形成重佈線路層120，其中重佈線路層120與線路基板110電性連接。在本實施例中，重佈線路層120的相對的側壁120s的間隔小於線路基板110的相對的側壁110s的間隔。舉例而言，重佈線路層120的側壁120s可以是內縮於線路基板110的側壁110s，以暴露出線路基板110的第一表面110a的一部分。重佈線路層120未全面性覆蓋線路基板110的第一表面110a，重佈線路層120可以是局部覆蓋線路基板110的第一表面110a。在此，本發明不限制重佈線路層120局部覆蓋線路基板110的面積大小，可視後續上方配置的晶粒數量而定。
在本實施例中，重佈線路層120與線路基板110可以是直接接觸。舉例而言，重佈線路層120不屬於線路基板110的一部分。重佈線路層120可以是直接藉由沉積（deposition）、微影（photolithography）及蝕刻（etching）等製程而形成於線路基板110的第一表面110a上。
重佈線路層120可以包括交替堆疊的多個介電層122與多個圖案化導電層124。在一實施例中，例如可以將銅、鋁或鎳等導電材料藉由濺鍍（sputtering）、蒸鍍（evaporation）或電鍍（electroplating）製程形成於介電層122上，然後藉由微影及蝕刻製程對導電材料進行圖案化，以形成圖案化導電層124。在一些其他實施例中，圖案化導電層124可以形成於介電層122之前。介電層122以及圖案化導電層124的形成順序可以視設計需求而進行調整。介電層122的材質可以包括無機材料或有機材料，無機材料例如可以是氧化矽、氮化矽、碳化矽、氮氧化矽或類似的無機介電材料，有機材料例如可以是聚醯亞胺（polyimide, PI）、丁基環丁烯（butylcyclobutene, BCB）或類似的有機介電材料，於本發明中並不加以限制。
請參照圖1C，形成重佈線路層120之後，於重佈線路層120上配置至少二晶粒。在一些實施例中，如圖1C、圖1D、圖2、圖3、圖4以及圖5所描述的示例性實施例所示，至少二晶粒可以包括第一晶粒130以及第二晶粒140。然而，本發明不限於此，所述至少二晶粒的數量可以是三個或更多晶粒。在一些實施例中，至少二晶粒中的晶粒可以具有不同功能。然而，本發明不限於此，至少二晶粒中的一些或全部晶粒可以具有相同功能。
在本實施例中，至少二晶粒中的每一者具有面向線路基板110的主動面以及相對於主動面的背面。舉例而言，第一晶粒130具有主動面130a以及相對於主動面130a的背面130b，而第二晶粒140具有主動面140a以及相對於主動面140a的背面140b，且第一晶粒130以及第二晶粒140例如是以覆晶（flip-chip）方式配置於重佈線路層120遠離線路基板110的表面上。
至少二晶粒中的一者藉由重佈線路層120與至少二晶粒中的其他者電性連接。舉例而言，第一晶粒130可以藉由重佈線路層120與第二晶粒140電性連接。在一實施例中，相鄰的第一晶粒130與第二晶粒140之間具有部份圖案化導電層124，以用於第一晶粒130與第二晶粒140之間的電性連接。在一實施例中，部分圖案化導電層124可以是由第一晶粒130的下方延伸至第二晶粒140的下方。在一實施例中，相鄰的第一晶粒130與第二晶粒140之間具有間距S，且間距S於線路基板110上的正投影可以與圖案化導電層124於線路基板110上的正投影部分重疊。
由於至少二晶粒中的一者藉由重佈線路層120與至少二晶粒中的其他者電性連接，以於至少二晶粒之間進行內連線，因此可以降低線路基板110的繞線密度、減少線路基板110的厚度，進而可以微型化半導體封裝結構100並降低生產成本。此外，重佈線路層120相較於線路基板110可以具有較佳的細線距（line-and-space, L/S），舉例而言，重佈線路層120的細線距可以是小於5微米/5微米，因此，至少二晶粒中的一者藉由重佈線路層120與至少二晶粒中的其他者進行電性連接可以縮短相鄰二晶粒之間的間距（如第一晶粒130與第二晶粒140之間的間距S），進而提升半導體封裝結構100的電性能力及/或效能。在一實施例中，由於至少二晶粒中的一者藉由重佈線路層120與至少二晶粒中的其他者電性連接，因此，可以省略為了連接至少二晶粒，而對線路基板110的頂層線路（如圖1A中虛線框框區域）的製程或材料進行全面性的替換的步驟。
請繼續參照圖1C，在一些實施例中，配置至少二晶粒之後，可以於至少二晶粒及重佈線路層120之間形成底膠150。然而，本發明不限於此，在其他實施例中，可以不形成底膠150於至少二晶粒及重佈線路層120之間。底膠150可以是在重佈線路層120的相對的側壁120s之間延伸。底膠150可以藉由毛細填充膠（capillary underfill filling, CUF）的方式形成，且底膠150可以包括聚合物材料、樹脂或二氧化矽添加物。
請參照圖1D，配置至少二晶粒之後，形成多個導電端子160於第二表面110b上，而多個導電端子160與線路基板110電性連接。在一實施例中，重佈線路層120與線路基板110位於至少二晶粒與多個導電端子160之間，因此，至少二晶粒可以藉由重佈線路層120及線路基板110與導電端子160電性連接，進而可以進一步增加半導體封裝結構100中I/O連接的數目。
應說明的是，圖式中的線路佈局（layout）僅為示意用，因此，於圖式中，線路基板110與重佈線路層120中部分未連接的線路實際上也可以視線路設計需求經由導通孔或其他方向的導電件進行電性連接。
經過上述製程後即可大致上完成本實施例之半導體封裝結構100的製作。半導體封裝結構100包括線路基板110、重佈線路層120以及至少二晶粒（第一晶粒130以及第二晶粒140）。線路基板具有第一表面110a與相對於第一表面110a的第二表面110b。重佈線路層120位於第一表面110a上。重佈線路層120與線路基板110電性連接。重佈線路層120的相對的側壁120s的間隔小於線路基板110的相對的側壁110s的間隔。重佈線路層120與線路基板110直接接觸。至少二晶粒中的每一者具有面向線路基板110的主動面。至少二晶粒中的一者藉由重佈線路層120與至少二晶粒中的其他者電性連接。
在半導體封裝結構100中，由於至少二晶粒中的一者藉由重佈線路層120與至少二晶粒中的其他者電性連接，因此可以在微型化半導體封裝結構100的同時還能夠提升半導體封裝結構100的電性能力及/或效能。
在此必須說明的是，以下實施例沿用上述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明，關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖2是依據本發明另一實施例的半導體封裝結構200的部分剖面示意圖。請參考圖2，本實施例的半導體封裝結構200類似於上述實施例的半導體封裝結構100，而其差別在於：本實施例的半導體封裝結構200更包括密封體270。密封體270可以包封至少二晶粒（第一晶粒130以及第二晶粒140）與重佈線路層120，且密封體270覆蓋重佈線路層120的相對的側壁120s，因此，密封體270可以保護半導體封裝結構200中的電子元件，且可以降低半導體封裝結構200的翹曲（warpage）問題。
圖3是依據本發明又一實施例的半導體封裝結構300的部分剖面示意圖。請參考圖3，本實施例的半導體封裝結構300類似於上述實施例的半導體封裝結構200，而其差別在於：本實施例的半導體封裝結構300不形成底膠150於至少二晶粒（第一晶粒130以及第二晶粒140）及重佈線路層120之間。
圖4是依據本發明再一實施例的半導體封裝結構400的部分剖面示意圖。本實施例的半導體封裝結構400類似於上述實施例的半導體封裝結構100，而其差別在於：本實施例的半導體封裝結構400更包括金屬環480。金屬環480可以位於第一表面110上且圍繞至少二晶粒（第一晶粒130以及第二晶粒140），因此，金屬環480可以保護半導體封裝結構400中的電子元件，且可以降低半導體封裝結構400的翹曲問題。在一實施例中，金屬環480的底面480b與重佈線路層120的底面120b可以是基本上共面（coplanar），但本發明不限於此。
圖5是依據本發明又再一實施例的半導體封裝結構的部分剖面示意圖。本實施例的半導體封裝結構500類似於上述實施例的半導體封裝結構100，而其差別在於：本實施例的半導體封裝結構500更包括封蓋590。封蓋590至少覆蓋至少二晶粒（第一晶粒130以及第二晶粒140）相對於主動面的背面，因此，封蓋590可以保護半導體封裝結構500中的電子元件，且可以降低半導體封裝結構500的翹曲問題。在一實施例中，封蓋590圍封至少二晶粒與重佈線路層120，但本發明不限於此。在一實施例中，封蓋590可以與至少二晶粒（第一晶粒130以及第二晶粒140）以及重佈線路層120之間構成多個空腔。
綜上所述，本發明的半導體封裝結構由於至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者電性連接，因此可以降低線路基板的繞線密度、減少線路基板的厚度，進而可以微型化半導體封裝結構並降低生產成本。再者，由於重佈線路層相較於線路基板可以具有較佳的細線距，因此，至少二晶粒中的一者藉由重佈線路層與至少二晶粒中的其他者進行電性連接可以縮短相鄰二晶粒之間的間距，進而提升半導體封裝結構的電性能力及/或效能。此外，本發明的半導體封裝結構可以更包括密封體、金屬環或封蓋，因此可以進一步保護半導體封裝結構中的電子元件，降低半導體封裝結構的翹曲問題。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200、300、400、500:半導體封裝結構 110:線路基板 110a:第一表面 110b:第二表面 120:重佈線路層 120s、110s:側壁 120b、480b:底面 122:介電層 124:圖案化導電層 130:第一晶粒 130a、140a:主動面 130b、140b:背面 140:第二晶粒 150:底膠 160:導電端子 270:密封體 480:金屬環 590:封蓋 S:間距
圖1A至圖1D是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。 圖2是依據本發明另一實施例的半導體封裝結構的部分剖面示意圖。 圖3是依據本發明又一實施例的半導體封裝結構的部分剖面示意圖。 圖4是依據本發明再一實施例的半導體封裝結構的部分剖面示意圖。 圖5是依據本發明又再一實施例的半導體封裝結構的部分剖面示意圖。
100:半導體封裝結構
110:線路基板
110b:第二表面
120:重佈線路層
130:第一晶粒
140:第二晶粒
150:底膠
160:導電端子

Claims (9)

  1. 一種半導體封裝結構，包括：線路基板，具有第一表面與相對於所述第一表面的第二表面；重佈線路層，位於所述第一表面上，其中：所述重佈線路層與所述線路基板電性連接；所述重佈線路層的相對的側壁的間隔小於所述線路基板的相對的側壁的間隔；所述重佈線路層與所述線路基板直接接觸；所述重佈線路層包括交替堆疊的多個介電層與多個圖案化導電層，所述至少二晶粒中的相鄰兩者之間具有部分所述圖案化導電層，且部分所述圖案化導電層由所述至少二晶粒中的一者的下方延伸至所述至少二晶粒中的其他者的下方；且所述重佈線路層直接形成於所述線路基板的所述第一表面上；以及至少二晶粒，配置於所述重佈線路層上，其中：所述至少二晶粒中的每一者具有面向所述線路基板的主動面；且所述至少二晶粒中的一者直接藉由所述重佈線路層與所述至少二晶粒中的其他者電性連接。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中所述重佈線路層暴露出所述線路基板的所述第一表面的一部分。
  3. 如申請專利範圍第1項所述的半導體封裝結構，更包括底膠，填充於所述至少二晶粒及所述重佈線路層之間，且所述底膠在所述重佈線路層的相對的所述側壁之間延伸。
  4. 如申請專利範圍第1項所述的半導體封裝結構，更包括密封體，包封所述至少二晶粒與所述重佈線路層，且所述密封體覆蓋所述重佈線路層的相對的所述側壁。
  5. 如申請專利範圍第1項所述的半導體封裝結構，更包括金屬環，位於所述第一表面上且圍繞所述至少二晶粒，且所述金屬環的底面與所述重佈線路層的底面基本上共面。
  6. 如申請專利範圍第1項所述的半導體封裝結構，更包括封蓋，至少覆蓋所述至少二晶粒相對於所述主動面的背面，且所述封蓋圍封所述至少二晶粒與所述重佈線路層。
  7. 如申請專利範圍第6項所述的半導體封裝結構，其中所述封蓋與所述至少二晶粒以及所述重佈線路層之間構成多個空腔。
  8. 如申請專利範圍第1項所述的半導體封裝結構，更包括多個導電端子，位於所述第二表面上且所述多個導電端子與所述線路基板電性連接。
  9. 一種半導體封裝結構的製造方法，包括：提供線路基板，其中所述線路基板具有第一表面與相對於所述第一表面的第二表面；形成重佈線路層於所述第一表面上，其中： 所述重佈線路層與所述線路基板電性連接；所述重佈線路層的相對的側壁的間隔小於所述線路基板的相對的側壁的間隔；所述重佈線路層與所述線路基板直接接觸；所述重佈線路層包括交替堆疊的多個介電層與多個圖案化導電層，所述至少二晶粒中的相鄰兩者之間具有部分所述圖案化導電層，且部分所述圖案化導電層由所述至少二晶粒中的一者的下方延伸至所述至少二晶粒中的其他者的下方；且所述重佈線路層直接形成於所述線路基板的所述第一表面上；以及配置至少二晶粒於所述重佈線路層上，其中：所述至少二晶粒中的每一者具有面向所述線路基板的主動面；且所述至少二晶粒中的一者直接藉由所述重佈線路層與所述至少二晶粒中的其他者電性連接。
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