TW201810570A - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

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Publication number
TW201810570A
TW201810570A TW105131833A TW105131833A TW201810570A TW 201810570 A TW201810570 A TW 201810570A TW 105131833 A TW105131833 A TW 105131833A TW 105131833 A TW105131833 A TW 105131833A TW 201810570 A TW201810570 A TW 201810570A
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manufacturing
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TW105131833A
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TWI615932B (zh
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施信益
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美光科技公司
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Abstract

本發明披露一種半導體封裝，包含：內連部件，被成型模料環繞包覆，其中內連部件包含第一重佈線層結構；第二重佈線層結構，設於內連部件上；複數個第一連結件，設於第二重佈線層結構上；研磨停止層，覆蓋於內連部件的表面上；複數個第二連接件，設於研磨停止層中；以及至少一半導體晶粒設於第二連接件上。

Description

半導體封裝及其製作方法
本發明係有關於半導體封裝技術領域，更特定言之，本發明係有關於一種製作具有高密度及混合式中介層基板的半導體內連裝置的方法。
如本領域所已知的，在2.5D積體電路(IC)封裝中，多個晶粒或晶片通常被設置在矽中介層上。矽中介層藉由使用穿矽通孔(through substrate via或through silicon via, 下稱TSV)技術達到晶粒之間的內連及外部的輸出/輸入(I/O)。然後，矽中介層通常經由C4凸塊設置在一封裝基板上。
然而，TSV矽中介層是相對昂貴的，因此，本領域仍需要一種改進的半導體封裝，其具有無TSV的中介層，而這樣的中介層仍可以提供非常細間距的內連結構。
美國專利公開號US 2015/0371965 A1揭露一種製作高密度電路薄膜的方法。此先前技術的缺點之一是在切割電路薄膜重佈線層I之前移除臨時載板I。由於移除了臨時載板I，缺乏足夠的機械支撐，使電路薄膜重佈線層I的處裡變得困難且產品良率也因此較低。
本發明的一主要目的在提供一種改良的方法，用於製作具有一半導體裝置，其具有混合式、無TSV之中介層基板。
本發明的另一目的在提供一種改良的方法，用於製作具有高良率的半導體裝置。
本發明一方面，提出一種半導體裝置的製作方法。首先提供第一載板，其上設有研磨停止層。之後，於研磨停止層上形成重佈線層結構。接著，對重佈線層結構與第一載板進行一第一切割製程，構成彼此分離的個別的內連部件。然後，將複數內連部件重排並安置在第二載板上。接著，形成成型模料，使其覆蓋複數該內連部件。再去除該第二載板，以顯露出各內連部件的第一重佈線層結構的表面。之後，於第一重佈線層結構的顯露出的表面上與成型模料上，形成第二重佈線層結構。然後，於第二重佈線層結構上形成第一連接件。再使該第一連接件與一第三載板接合。接著研磨成型模料與第一載板。之後完全去除第一載板以顯露出研磨停止層。然後，於研磨停止層中形成複數開口。最後，分別於開口中形成第二連接件。
本發明一方面，提供一種半導體封裝，包含：內連部件，被一成型模料環繞包覆，其中內連部件包含第一重佈線層結構；第二重佈線層結構，設於內連部件與成型模料上，其中第二重佈線層結構與第一重佈線層結構電連接；複數個第一連結件，設於第二重佈線層結構上；研磨停止層，覆蓋於內連部件的表面上； 複數個第二連接件，設於研磨停止層中；以及至少一半導體晶粒設於第二連接件上。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
於下文中，係加以陳述本發明之具體實施方式，該些具體實施方式可參考相對應的圖式，俾使該些圖式構成實施方式之一部分。同時也藉由說明，揭露本發明可據以施行之方式。該等實施例已被清楚地描述足夠的細節，俾使該技術領域中具有通常技術者可據以實施本發明。其他實施例亦可被加以施行，且對於其結構上所做之改變仍屬本發明所涵蓋之範疇。
因此，下文的細節描述將不被視為一種限定，且本發明所涵蓋之範疇僅被所附之申請專利範圍以及其同意義的涵蓋範圍。本發明之一或多個實施例將參照附圖描述，其中，相同元件符號始終用以表示相同元件，且其中闡述的結構未必按比例所繪製。
本發明之一或多個實施例將參照附圖描述，其中，相同元件符號始終用以表示相同元件，且其中闡述的結構未必按比例所繪製。術語「晶粒」、「晶片」「半導體晶片」及「半導體晶粒」於整個說明書中可互換使用。
文中所使用的術語「晶圓」及「基板」包括任何具有暴露表面之結構，於該表面上根據本發明沉積一層，例如，形成諸如重佈線層的電路結構。術語「基板」被理解為包括半導體晶圓，但不限於此。術語「基板」亦可用以指加工過程中之半導體結構，且可包括已被製造在其上之其它層。
請參考第1圖至第16圖。第1圖至第16圖係根據本發明之實施例所繪示的製作半導體封裝的示例性方法的剖面圖。
如第1圖所示，首先，提供一第一載板110。根據本發明一實施例，第一載板110可包含矽或金屬，較佳包含矽。例如，第一載板110可為一晶圓形狀矽載板。接著，在第一載板110的第一表面上沉積一研磨停止層111。研磨停止層111可包含介電層或鈍化層，例如：研磨停止層111可包含氮化矽，氧化矽，或它們的組合。
如第2圖所示，隨後，於研磨停止層111上形成第一重佈線層(RDL)結構200。根據本發明一實施例，第一RDL結構200可包含至少一介電層201以及至少一繞線層202。應理解的是，第一RDL結構200可包含多層介電材料及多層繞線層。複數個凸塊墊204係形成於第一RDL 200中且電連接至繞線層202。
如第3圖所示，進行一切割製程，以構成彼此分離的個別的內連部件10。內連部件10係被動元件，即無主動電路被形成在每個內連部件10上。
值得注意的是，在進行切割製程時，第一載板110仍與第一RDL結構200接合在一起，並未分離，以提供足夠的機械支持。如果第一載板110在切割製程之前被移除，厚度很薄的第一RDL結構200（約10微米厚）會變得難以處理，且將降低良率。
隨後，如第4圖所示，將複數內連部件10重排並安置在第二載板120上。第二載板120可包含黏著層121。第二載板120可包含矽或玻璃，但不限於此。第二載板120可為晶圓形狀或矩形面板形狀。被翻面的內連部件10可重排並安置在黏著層121上。根據本發明一實施例，繞線層202的暴露表面係與黏著層121直接接觸。
如第5圖所示，形成一成型模料300，使其覆蓋複數內連部件10及黏著層121的上表面。然後，對成型模料300進行一固化製程。根據本發明一實施例，成型模料300可包含環氧樹脂和矽石填料的混合物，但不限於此。
可選地，成型模料300的上部分可被拋光或研磨去除，使得第一載板110的表面被顯露出來，且與成型模料300的第一表面300a齊平。
如第6圖所示，在形成成型模料300之後，移除第二載板120及黏著層121，以顯露出繞線層202。此時，第一重佈線層結構200的上表面200a與成型模料300的第二表面300b齊平。
然後，如第7圖所示，於成型模料300的第二表面300b及第一重佈線層結構200的繞線層202上，形成第二重佈線層結構400。根據本發明一實施例，第二重佈線層結構400可透過使用印刷電路板(PCB)製程來製作。
根據本發明一實施例，第二重佈線層結構400可包含一介電層401以及一繞線層402。介電層401可包含增層絕緣膜(Ajinomoto build-up film, ABF)、預浸材(prepreg)、聚醯亞胺(polyimide)、苯環丁烯(Benzocyclobutene, BCB)，或其類似物。繞線層402可包含銅，但不限於此。繞線層402係電連接至繞線層202。
根據本發明一實施例，在第二重佈線層結構400中形成複數個焊墊404。焊墊404透過防焊層403中的開口被分別顯露出來。
接著，如第8圖所示，複數個第一連接件420，例如錫凸塊、錫球、或其類似物形成於相應的焊墊404上。例如，第一連接件420可為球型格柵陣列(ball grid array, BGA)錫球，但不限於此。根據本發明一實施例，複數個第一連接件420可具有一球間距(或凸塊間距)，其等同於一主機板或一印刷電路板上的球墊間距。
如第9圖所示，隨後，使第一連接件420與第三載板130接合。根據本發明一實施例，第三載板130可包含矽或玻璃，但不限於此。第三載板130可為晶圓形狀或矩形面板形狀。根據本發明一實施例，第三載板130與第二載板120具有相同形狀。在第三載板130上可設置黏著層131。第一連接件420係與黏著層131直接接觸。
然後，如第10圖所示，對成型模料300的第一表面300a與第一載板110進行一研磨製程，以去除至少一部份的成型模料300及至少一部份的各第一載板110。
如第11圖所示，根據本發明一實施例，各第一載板110的剩餘部分可利用濕式蝕刻或乾式蝕刻去除。在完全去除各第一載板110之後，形成一凹陷處510。研磨停止層111從凹陷處510中被顯露出來。
如第12圖所示，在去除第一載板110之後，進行一拋光製程以移除一部份的成型模料300，其中拋光製程會停止於研磨停止層111上，此時，使得研磨停止層111的上表面與成型模料300的第一表面300a齊平。
如第13圖所示，進行光微影製程及蝕刻製程，以於研磨停止層111中形成複數開口111a，其中開口111a分別顯露出凸塊墊204。
如第14圖所示，隨後，分別於開口111a中形成第二連接件620，諸如微凸塊。第二連接件620可包含金、銀、銅、鎳、鎢、或它們的組合。第二連接件620具有一細間距，其等同於被設置到內連部件10上的各半導體晶粒的主表面上的輸出/輸入墊（I/O pad）間距。
然後，如第15圖所示，至少一第一半導體晶粒11及至少一第二半導體晶粒12設於內連部件10上。第一半導體晶粒11及第二半導體晶粒12可以是覆晶晶片，使其主動面朝下面向第二連接件620。第一半導體晶粒11及第二半導體晶粒12係藉由第二連接件620電連接第一RDL結構200。
第一半導體晶粒11及第二半導體晶粒12是具有一定功能的主動積體電路晶片，例如，圖形處理單元(GPU)、中央處理單元(CPU)、記憶體晶片等。根據本發明一實施例，第一半導體晶粒11及第二半導體晶粒12可被一起設置於一封裝內，且可為具有其特定功能之不同的晶片。可選地，底膠(圖未示)可被應用於各晶粒的下方。
最後，如第16圖所示，利用本領域已知的方法將第三載板130及黏著層131去除。接著，進行一切割製程，構成彼此分離的個別的半導體封裝1。應理解的是，雖然在附圖中繪示各封裝包含兩個晶粒，但在一些實施例中，各半導體封裝1可以包含單個晶粒。根據本發明實施例，沒有使用成型模料以覆蓋至少一該半導體晶粒。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
110‧‧‧第一載板
111‧‧‧研磨停止層
200‧‧‧第一重佈線層(RDL)結構
201‧‧‧介電層
202‧‧‧繞線層
204‧‧‧凸塊墊
10‧‧‧內連部件
120‧‧‧第二載板
121‧‧‧黏著層
300‧‧‧成型模料
300a‧‧‧第一表面
200a‧‧‧上表面
300b‧‧‧第二表面
400‧‧‧第二重佈線層結構
401‧‧‧介電層
402‧‧‧繞線層
404‧‧‧焊墊
403‧‧‧防焊層
420‧‧‧第一連接件
130‧‧‧第三載板
131‧‧‧黏著層
510‧‧‧凹陷處
111a‧‧‧開口
620‧‧‧第二連接件
11‧‧‧第一半導體晶粒
12‧‧‧第二半導體晶粒
1‧‧‧半導體封裝
附圖包括對本發明的實施例提供進一步的理解，及被併入且構成說明書中的一部份。圖示說明一些本發明的實施例，並與說明書一起用於解釋其原理。 第1圖至第16圖係根據本發明之實施例所繪示的製作半導體封裝的示例性方法的剖面圖。
111‧‧‧研磨停止層
200‧‧‧第一重佈線層(RDL)結構
201‧‧‧介電層
202‧‧‧繞線層
204‧‧‧凸塊墊
300‧‧‧成型模料
300a‧‧‧第一表面
300b‧‧‧第二表面
400‧‧‧第二重佈線層結構
401‧‧‧介電層
402‧‧‧繞線層
404‧‧‧焊墊
403‧‧‧防焊層
420‧‧‧第一連接件
620‧‧‧第二連接件
11‧‧‧第一半導體晶粒
12‧‧‧第二半導體晶粒
1‧‧‧半導體封裝

Claims (18)

  1. 一種半導體裝置的製作方法，包含： 提供一第一載板，其上設有一研磨停止層； 於該研磨停止層上形成一重佈線層結構； 對該重佈線層結構與該第一載板進行一第一切割製程，構成彼此分離的個別的內連部件； 將複數該內連部件重排並安置在一第二載板上； 形成一成型模料，使其覆蓋複數該內連部件； 去除該第二載板，以顯露出各該內連部件的該第一重佈線層結構的一表面； 於該第一重佈線層結構的顯露出的該表面上與該成型模料上，形成一第二重佈線層結構； 於該第二重佈線層結構上形成第一連接件； 使該第一連接件與一第三載板接合； 研磨該成型模料與該第一載板； 完全去除該第一載板的剩餘部分，如此形成一凹陷處； 拋光該成型模料，使得該研磨停止層的一上表面與該成型模料的一上表面齊平； 於該研磨停止層中形成複數開口；以及 分別於該開口中形成第二連接件。
  2. 如申請專利範圍第1項所述的一種半導體裝置的製作方法，其中在分別於該開口中形成第二連接件後，另包含有： 於該第二連接件上設置半導體晶粒； 去除該第三載板；以及 進行一第二切割製程，構成彼此分離的個別的半導體封裝。
  3. 如申請專利範圍第1項所述的一種半導體裝置的製作方法，其中該研磨停止層包含氮化矽、氧化矽或其組合。
  4. 如申請專利範圍第1項所述的一種半導體裝置的製作方法，其中該第一載板包含矽。
  5. 如申請專利範圍第1項所述的一種半導體裝置的製作方法，其中該第二載板包含玻璃或矽，其中該第二載板具有一晶圓形狀或一矩形面板形狀。
  6. 如申請專利範圍第5項所述的一種半導體裝置的製作方法，其中該第三載板包含玻璃或矽，其中該第三載板與該第二載板具有相同形狀。
  7. 如申請專利範圍第2項所述的一種半導體裝置的製作方法，其中該第一連接件為球型格柵陣列（Ball Grid Array，BGA）錫球。
  8. 如申請專利範圍第7項所述的一種半導體裝置的製作方法，其中該第一連接件具有一球間距，其等同於一主機板或一印刷電路板上的球墊間距。
  9. 如申請專利範圍第8項所述的一種半導體裝置的製作方法，其中該第二連接件為微凸塊（micro bumps）。
  10. 如申請專利範圍第9項所述的一種半導體裝置的製作方法，其中該第二連接件具有一細間距，其等同於各該半導體晶粒的主表面上的輸出/輸入墊（I/O pad）間距。
  11. 如申請專利範圍第1項所述的一種半導體裝置的製作方法，其中該第一載板的該剩餘部分係利用一濕蝕刻或一乾蝕刻製程完全去除。
  12. 一種半導體封裝，包含： 一內連部件，被一成型模料環繞包覆，其中該內連部件包含一第一重佈線層結構； 一第二重佈線層結構，設於該內連部件與該成型模料上，其中該第二重佈線層結構與該第一重佈線層結構電連接； 複數個第一連結件，設於該第二重佈線層結構上； 一研磨停止層，覆蓋於該內連部件的一表面上； 複數個第二連接件，設於該研磨停止層中；以及 至少一半導體晶粒設於該第二連接件上。
  13. 如申請專利範圍第12項所述的半導體封裝，其中該研磨停止層包含氮化矽、氧化矽或其組合。
  14. 如申請專利範圍第12項所述的半導體封裝，其中該第一連接件為球型格柵陣列（Ball Grid Array，BGA）錫球。
  15. 如申請專利範圍第14項所述的半導體封裝，其中該第一連接件具有一球間距，其等同於一主機板或一印刷電路板上的球墊間距。
  16. 如申請專利範圍第15項所述的半導體封裝，其中該第二連接件為微凸塊（micro bumps）。
  17. 如申請專利範圍第16項所述的半導體封裝，其中該第二連接件具有一細間距，其等同於各該半導體晶粒的主表面上的輸出/輸入墊（I/O pad）間距。
  18. 如申請專利範圍第12項所述的半導體封裝，其中該研磨停止層的一上表面與該成型模料的一上表面齊平。
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