TWI732644B - 形成封裝結構的方法 - Google Patents

形成封裝結構的方法 Download PDF

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TWI732644B
TWI732644B TW109126441A TW109126441A TWI732644B TW I732644 B TWI732644 B TW I732644B TW 109126441 A TW109126441 A TW 109126441A TW 109126441 A TW109126441 A TW 109126441A TW I732644 B TWI732644 B TW I732644B
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Taiwan
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substrate
protruding structure
forming
protruding
height
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TW109126441A
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TW202114085A (zh
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黃冠育
黃松輝
侯上勇
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台灣積體電路製造股份有限公司
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Abstract

提供一種形成封裝結構的方法。方法包括在第一基板的第一表面上方形成晶粒結構，以及在第一基板的第二表面下方形成複數個電連接器。方法也包括在第一基板的第二表面下方形成第一突出結構，並且電連接器被第一突出結構圍繞。方法更包括在第二基板上方形成第二突出結構，以及將第一基板接合至第二基板。電連接器被第二突出結構圍繞，並且第一突出結構不與第二突出結構重疊。

Description

形成封裝結構的方法
本揭露實施例係有關於一種封裝結構，特別係有關於一種形成封裝結構的方法。
半導體裝置被使用於各種電子應用中，像是個人電腦、行動電話、數位相機以及其他電子設備。通常藉由在半導體基板上方依序地沉積材料的絕緣或介電層、導電層、以及半導電層，並且使用微影圖案化各種材料層以在其上形成電路構件以及元件來製造半導體裝置。通常在單個半導體晶圓上製造許多積體電路，並且藉由沿著切割道（scribe line）在積體電路之間進行切割來單粒化（singulate）晶圓上的各個晶粒。通常將各個晶粒分別封裝在例如多晶片模組中或其他類型的封裝中。
已經開始開發像是封裝上封裝（package on package, PoP）的新封裝技術，其中具有裝置晶粒的頂部封裝與另一裝置晶粒接合至底部封裝。藉由採用新的封裝技術，具有不同或相似功能的各種封裝被整合在一起。
儘管現有的封裝結構以及製造封裝結構的方法通常已經足以滿足其預期目的，但是它們並非在所有方面都是完全令人滿意的。
根據本揭露的一些實施例，提供一種形成封裝結構的方法。方法包括在第一基板的第一表面上方形成晶粒結構，在第一基板的第二表面下方形成複數個電連接器。方法也包括在第一基板的第二表面下方形成第一突出結構，並且電連接器被第一突出結構圍繞。此方法更包括在第二基板上方形成第二突出結構，以及將第一基板接合至第二基板。電連接器被第二突出結構圍繞，並且第一突出結構不與第二突出結構重疊。
根據本揭露的一些實施例，提供一種形成封裝結構的方法。方法包括在第一基板的第一表面上方形成晶粒結構，在第一基板的第二表面下方形成複數個電連接器。方法也包括在電連接器旁邊形成第一突出結構，從第一基板的第二表面加壓第一區域中的複數個電連接器的一部分，使得第一區域中的電連接器的每一個具有實質底部平坦的表面。方法更包括在第二基板上方形成第二突出結構以及第三突出結構，並且第二突出結構以及第三突出結構為不同的高度。方法包括將第一基板接合至第二基板，並且第一突出結構位於第二突出結構以及該第三突出結構之間。
根據本揭露的一些實施例，提供一種形成封裝結構的方法。方法包括在第一基板上方形成晶粒結構，並且在第一基板下方形成複數個電連接器。方法也包括在第一基板下方形成第一支撐結構，並且第一支撐結構具有第一高度，方法更包括對電連接器執行加壓製程，使得電連接器包括第一組被加壓電連接器以及第二組未被加壓電連接器。方法更包括使用電連接器將第一基板接合到第二基板，並且第一組被加壓電連接器中的一個具有第二高度。第二組未被加壓電連接器中的一個具有第三高度。第一高度小於第二高度，並且第二高度小於第三高度。
以下的揭露提供各種許多不同的實施例或範例以實行本揭露之不同特徵。以下敘述各個構件以及排列方式的特定範例，以簡化本揭露。當然，這些僅為範例且非意圖作為限制。例如，若說明書敘述了第一特徵形成於第二特徵上方或之上，即表示可包括上述第一特徵與上述第二特徵係直接接觸的實施例，亦可包括有額外的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可未直接接觸的實施例。除此之外，在各種範例中，本揭露可能使用重複的標號及/或標示。這樣的重複係為了簡化以及清楚之目的，並不表示所討論的各種實施例及/或配置之間的關聯。
描述了實施例的一些變形。經由各種視圖以及說明性實施例，相似的參考標號用於指示相似的元件。應理解的是，可以在方法之前、期間以及之後提供附加操作，並且對於方法的其他實施例，可以代替或消除所描述的一些操作。
也可以包括其他特徵以及製程。例如，可以包括測試結構以輔助三維封裝或三維積體電路（3DIC）裝置的驗證測試。測試結構可以包括例如形成在重分佈層（redistribution layer）中或基板上的測試墊，此測試墊允許三維封裝或三維積體電路、使用探針以及/或探針卡等的測試。驗證測試可以在中間結構以及最終結構上進行。此外，本文揭露的結構以及方法可以與結合了已知良好晶粒的中間驗證的測試方法連結使用，以增加良率並降低成本。
提供了用於半導體裝置結構的實施例及其形成方法。第1A圖至第1M圖示出了根據本揭露的一些實施例的形成封裝結構100a的各個階段的剖面圖。封裝結構可以是基板上晶圓上晶片（chip-on-wafer-on-substrate, CoWoS）封裝或另一種合適的封裝。封裝結構包括形成在第一基板上的晶粒結構，並且第一基板接合到第二基板。為了防止第一基板的翹曲（warpage），在第一基板的下方形成突出結構，並且在第二基板的上方形成另一個突出結構。第一突出結構被配置為提供基板的機構以及結構支撐。第一突出結構以及第二突出結構在第一基板以及第二基板之間。
參考第1A圖，提供第一基板102。第一基板102包括第一表面102a以及第二表面102b。基板102可以由矽或其他半導體材料製成。替代地或另外地，基板102可以包括像是鍺的其他元素半導體材料。在一些實施例中，基板102由化合物半導體製成，像是碳化矽、砷化鎵、砷化銦、或磷化銦。在一些實施例中，基板102由合金半導體製成，例如矽鍺、碳化矽鍺、磷化砷化鎵、或磷化銦鎵。在一些實施例中，基板102包括磊晶層。例如，基板102具有上覆於塊材半導體（bulk semiconductor）的磊晶層。
複數個導電結構104形成在第一基板102中。導電結構104從第一基板102的第一表面102a延伸朝向第一基板102的第二表面102b。
在一些實施例中，藉由形成從第一基板102的第一表面102a延伸的複數個溝槽（未圖示）來形成導電結構104。然後，在每個溝槽中形成導電結構104。在一些實施例中，在形成導電結構104之前，在溝槽中形成阻擋層（未圖示）。
之後，如第1B圖所示，在導電結構104以及第一基板102上方形成內連線結構110。內連線結構110可以使用作為用於配線的重分佈層（Redistribution Layer, RDL）結構。內連線結構110包括多個導電層106以及形成在多個介電層108中的導電墊112。在一些實施例中，導電墊112在介電層108的頂部的頂表面處暴露或從其突出以用作接合墊。
介電層108可以由一種或多種聚合物材料製成、或包括一種或多種聚合物材料。（多種）聚合物材料可以包括聚苯並噁唑（polybenzoxazole, PBO）、聚酰亞胺（polyimide, PI）、一種或多種其他合適的聚合物材料、或其組合。在一些實施例中，一些或所有介電層108由聚合物材料以外的介電材料製成、或包括聚合物材料以外的介電材料。介電材料可以包括氧化矽、碳化矽、氮化矽、氮氧化矽、一種或多種其他合適的材料、或其組合。
導電層106以及導電墊112可以由銅（Cu）、銅合金、鋁（Al）、鋁合金、鎢（W）、鎢合金、鈦（Ti）、鈦合金、鉭（Ta）、或鉭合金製成。在一些實施例中，導電層106以及導電墊112藉由電鍍、化學鍍、印刷、化學氣相沉積（chemical vapor deposition, CVD）製程、或物理氣相沉積（physical vapor deposition, PVD）製程形成。
之後，如第1C圖所示，根據本揭露的一些實施例，在第一基板102上方形成半導體晶粒120。半導體晶粒120包括基板121以及在基板121上方的內連線結構122。半導體晶粒120的內連線結構122包括複數個導電層124。
在一些實施例中，半導體晶粒120是從晶圓上切割的，並且可以是「已知良好的晶圓（known-good-die）」。半導體晶粒120可以是晶片上系統（system-on-chip, SoC）晶片或記憶體晶粒。在一些其他實施例中，半導體晶粒120是積體電路上系統（system on integrated circuit, SoIC）裝置，積體電路系統裝置包括具有積體功能的兩個或更多個晶片。在一些實施例中，記憶體晶粒包括靜態隨機存取記憶體（static random access memory, SRAM）裝置、動態隨機存取記憶體（dynamic random access memory, DRAM）裝置、高帶寬記憶體（high bandwidth memory, HBM）、或另一記憶體晶粒。半導體晶粒120的數量不限於一個，並且可以根據實際應用來調整數量。
在一些實施例中，在半導體晶粒120的導電層124下方形成複數個導電墊126，並且每個導電墊126藉由複數個導電連接器128接合到每個導電墊112。
導電墊126由金屬材料製成，例如銅（Cu）、銅合金、鋁（Al）、鋁合金、鎢（W）、鎢合金、鈦（Ti）、鈦合金、鉭（Ta）、或鉭合金製成。在一些實施例中，導電墊126藉由電鍍、化學鍍、印刷、化學氣相沉積（CVD）製程、或物理氣相（PVD）沉積製程形成。
導電連接器128由像是錫（Sn）、錫銀（SnAg）、錫鉛（SnPb）、錫銅（SnCu）、錫銀銅（SnAgCu）、錫銀鋅（SnAgZn）、錫鋅（SnZn）、錫鉍銦（SnBiIn）、錫銦（SnIn）、錫金（SnAu）、錫鋅銦（SnZnIn）、錫銀銻（SnAgSb）或其他合適的材料。在一些實施例中，導電連接器128藉由電鍍、化學鍍、印刷、化學氣相沉積（CVD）製程、或物理氣相沉積（PVD）製程形成。
接下來，如第1D圖所示，根據本揭露的一些實施例，在半導體晶粒120以及內連線結構110之間形成底部填充層（underfill layer）130。底部填充層130圍繞並且保護導電連接器128。在一些實施例中，底部填充層130與導電連接器128直接接觸。
在一些實施例中，底部填充層130由聚合物材料製成、或包括聚合物材料。底部填充層130可以包括環氧基樹脂（epoxy-based resin）。在一些實施例中，底部填充層130包括分散在環氧基樹脂中的填充劑。
在一些實施例中，底部填充層130的形成包括注入（injecting）製程、旋塗（spin-on）製程、分配（dispensing）製程、膜層積層（film lamination）製程、施加（application）製程、一個或複數個其他可應用製程、或其組合。在一些實施例中，在底部填充層130的形成期間使用熱固化（thermal curing）製程。
之後，在底部填充層130上方形成封裝層140。在底部填充層130以及封裝層140之間存在界面，此界面低於半導體晶粒120的頂表面。封裝層140圍繞並保護半導體晶粒120。在一些實施例中，封裝層140與半導體晶粒120的一部分直接接觸。
封裝層140由模制化合物材料（molding compound material）製成。模制化合物材料可包括聚合物材料，像是具有填充劑分散在其中的環氧基樹脂。在一些實施例中，將液態模制化合物材料施加在半導體晶粒120上方。液態模制化合物材料可流入半導體晶粒120之間的空間中。然後，使用熱處理以固化液態模制化合物並使其轉型進入封裝層140。
之後，如第1E圖所示，根據本揭露的一些實施例，去除封裝層140的一部分。結果，半導體晶粒120的頂表面被暴露。半導體晶粒120的頂表面與封裝層136的頂表面實質上齊平。在適用的情況下，術語「實質上」也可以指90％或更高，例如95％或更高，尤其是99％或更高，包括100％。
在一些實施例中，使用平坦化製程將封裝層140薄化。平坦化製程可以包括化學機械研磨（chemical mechanical polishing, CMP）製程、磨光（grinding）製程、蝕刻製程，另一種適用製程、或其組合。
隨後，將封裝層140附加到承載基板142。在一些實施例中，承載基板142被使用作為臨時基板。臨時基板在隨後的處理操作中提供機構以及結構支撐，例如稍後將更詳細描述的那些操作。承載基板142由半導體材料、陶瓷材料、聚合物材料、金屬材料、另一種合適的材料、或其組合。在一些實施例中，承載基板142是玻璃基板。在一些其他實施例中，承載基板142是半導體基板，例如矽晶圓。
之後，使用承載基板142作為支撐將第一基板102薄化。在一些實施例中，從第二表面102b薄化第一基板102，直到暴露出導電結構104。在一些實施例中，導電結構104被暴露並穿透薄化的第一基板102。結果，在第一基板102中形成了通導孔結構144。在一些實施例中，通導孔結構144是矽通孔（through substrate via, TSV）。在一些其他實施例中，通導孔結構144可以被稱為通矽導孔。
之後，如第1F圖所示，根據本揭露的一些實施例，鈍化層150形成在第一基板102的第二表面102b下方，並且導電墊152形成在鈍化層150中。導電連接器154形成在導電墊152下方。導電連接器154藉由導電墊152電連接至通導孔結構144。
鈍化層150由聚苯並噁唑(poly(p-phenylene-2,6-benzoxazole), PBO)、苯環丁烯（benzocyclobutene, BCB）、聚矽氧（silicone）、丙烯酸酯（acrylate）、矽氧烷（siloxane），另一種合適的材料、或其組合製成。在一些其他實施例中，鈍化層150由非有機材料製成。非有機材料包括氧化矽、未摻雜的矽酸鹽玻璃、氮氧化矽、氮化矽、碳化矽、另一種合適的材料、或其組合。在一些實施例中，鈍化層150藉由沉積製程形成，像是物理氣相沉積製程（PVD）、化學氣相沉積（CVD）製程、或另一種適用製程。
導電墊152由金屬材料製成，例如銅（Cu）、銅合金、鋁（Al）、鋁合金、鎢（W）、鎢合金、鈦（Ti）、鈦合金、鉭（Ta ）、或鉭合金。導電連接器154由金屬層製成，例如銅、銅合金、鎳、鎳合金、鋁、鋁合金、錫、錫合金、鉛、鉛合金、銀、銀合金、或其組合。在一些實施例中，導電連接器154藉由鍍層製程形成，像是電化學鍍層製程或化學鍍製程。
接下來，如第1G圖所示，根據本揭露的一些實施例，去除承載基板142以形成晶粒結構10，並且藉由導電連接器154在第二基板160上方形成晶粒結構10。第二基板160具有第一表面160a以及第二表面160b。晶粒結構10在第二基板160的第一表面160a上方形成。
之後，如第1H圖所示，根據本揭露的一些實施例，封裝層164圍繞並保護晶粒結構10，並且在第二基板160的第一表面160a上方形成環形結構166。環形結構166用於保護晶粒結構10並防止晶粒結構10彎曲。
環形結構166提供足夠的支撐功能以及翹曲控制。在一些實施例中，環形結構166包括支撐材料，例如聚合物、金屬、陶瓷、或其組合。
之後，如第1I圖所示，根據本揭露的一些實施例，將晶粒結構10上下顛倒，在第二基板160中形成複數個導電墊170，並且在導電墊170上方形成複數個電連接器172。更具體地說，電連接器172在第二基板160的第二表面160b上形成。
之後，如第1J圖所示，根據本揭露的一些實施例，在第二基板160的外圍區域中形成第一突出結構178。第一突出結構178圍繞電連接器172。
第一突出結構178用於提供第二基板160機構以及結構支撐。此外，第一突出結構178用於控制電連接器172的高度。
第一突出結構178由聚合物、金屬、陶瓷、或其組合製成。在一些實施例中，聚合物是聚甲基丙烯酸甲酯（poly(methyl methacrylate), PMMA）、具有填充劑分散在其中的環氧基樹脂。填充劑可包括絕緣纖維、絕緣顆粒、其他合適的元素、或其組合。在一些實施例中，聚合物的玻璃轉化點（glass transition point, Tg）在約攝氏200度至約攝氏250度的範圍內。在一些實施例中，金屬是銅（Cu）、銅合金、鋁（Al）、鋁合金、鎢（W）、鎢合金、鈦（Ti）、鈦合金、鉭（Ta）、或鉭合金。
第一突出結構178藉由沉積製程以及固化製程形成。在一些實施例中，沉積製程包括印刷、化學氣相沉積（CVD）製程、物理氣相沉積（PVD）製程、或另一種適用的製程。在一些實施例中，當第一突出結構178由聚合物製成時，固化製程在約攝氏120度至約攝氏200度的溫度範圍內進行。在一些實施例中，固化製程進行約0.5小時至約2小時範圍內的一段時間。
如第1J圖所示，第一突出結構178具有第一高度H 1。每個電連接器172具有原始高度H 1’。在一些實施例中，原始高度H 1’高於第一高度H 1。由於每個電連接器172可以具有不同的高度，並且電連接器172的接合表面可以處於相同的水平。為了減少接合表面的非平面程度（degree of non-planarity），藉由加壓製程20來調節電連接器172的高度。
接下來，如第1K圖所示，根據本揭露的一些實施例，藉由模制裝置18在電連接器172以及第一突出結構178上執行加壓製程20。
在一些實施例中，加壓製程20以每個晶粒結構10在大約500Kg至大約5000kg的範圍內的力操作。在一些實施例中，加壓製程20在大約攝氏30度至大約攝氏150度的溫度範圍內操作。
在加壓製程20之後，電連接器172以及第一突出結構178中的每一個為相同的高度，例如，第一高度H 1。在一些實施例中，第一高度H 1在大約0.2mm至大約0.8mm的範圍內。電連接器172具有實質平坦的頂表面。在適用的情況下，術語「實質上」也可以指90％或更高，例如95％或更高，尤其是99％或更高，包括100％。
之後，如第1L圖所示，根據本揭露的一些實施例，在加壓製程20之後，第三基板180提供有第二突出結構182，並且第二突出結構182面向第一突出結構178。與第一突出結構178相似，第二突出結構182也用作機構以及結構支撐。
第一突出結構178以及第二突出結構182被配置使用作為對準標記。在將第二基板160接合到第三基板180之後，第一突出結構178不與第二突出結構182重疊。在將第二基板160接合到第三基板180之前，在第二基板160的第二表面160b下方的電連接器178應與形成在第三基板180的第一表面180a上的對應的電連接器190對準。然而，在一些實施例中，電連接器178可能不與對應的電連接器190對準，並且因此降低第二基板160對於第三基板180的接合可靠度。
為了防止未對準問題，在第二基板160以及第三基板180上分別形成第一突出結構178以及第二突出結構182。在將第二基板160接合到第三基板180期間，藉由檢測對準標記（例如，第一突出結構178以及第二突出結構182）的位置來控制電連接器178以及電連接器190之間的對準。因此，藉由形成第一突出結構178以及第二突出結構182來改善對準的準確度。
第二突出結構182由聚合物、金屬、陶瓷、或其組合製成。在一些實施例中，第一突出結構178以及第二突出結構182由不同的材料製成。第三基板180是印刷電路板（printed circuit board, PCB）、陶瓷基板、或另一種合適的封裝基板。在一些實施例中，第一突出結構178以及第二突出結構182兩者為相同的高度H 1。
隨後，如第1M圖所示，根據本揭露的一些實施例，第二基板160接合到第三基板180。更具體地說，每個電連接器178藉由回流（reflow）製程連接到對應的每個電連接器190，以形成電連接器192。
在將第二基板160接合到第三基板180之後，第一突出結構178不與第二突出結構182重疊。第一突出結構178比第二突出結構更靠近電連接器172中的一個。在一些實施例中，第一突出結構178的外側壁與環形結構166的外側壁實質上對準。
由於第一突出結構178被配置為提供第二基板160機構以及結構支撐，所以可以減少第二基板160的翹曲。此外，第一突出結構178被配置為當在電連接器172上執行加壓製程20時控制電連接器172的高度。藉由形成第一突出結構178以及第二突出結構182，當第二基板160接合到第三基板180上時，減少了未對準的問題。因此，改善了封裝結構100a的接合可靠度。
第1M’圖示出了根據本揭露的一些實施例的封裝結構100b的剖面圖。除了在第三結構180上方並在第二突出結構182旁邊初始形成第三突出結構184之外，封裝結構100b與第1M圖所示的封裝結構100a相似或相同。用於形成封裝結構100c的製程以及材料可以與用於形成封裝結構100a的製程以及材料相似或相同，在此不再贅述。
在將第二基板160接合到第三基板180之後，第一突出結構178在第二突出結構182以及第三突出結構184之間。
第二突出結構182以及第三突出結構184之間的空間用於設置第一突出結構178。第一突出結構178、第二突出結構182以及第三突出結構184使用作為對準標記。在第一突出結構178以及第二突出結構182之間存在第一空間S 1，並且在第一突出結構178以及第三突出結構184之間存在第二空間S 2。在一些實施例中，第一空間S 1實質上與第二空間S 2相等。如果第一空間S 1或第二空間S 2不在特定範圍內，則電連接器172可能不與對應的電連接器190對準。因此，第二基板160以及第三基板180之間的接合強度由於未對準而降低。
在一些實施例中，第一空間S 1在大約0.05mm至大約0.5mm的範圍內。在一些實施例中，第二空間S 2在大約0.05mm至大約0.5mm的範圍內。當第一空間S 1以及第二空間S 2在上述範圍內時，改善了第二基板160以及第三基板180之間的對準的準確度。
第2A圖示出了根據本揭露的一些實施例的第1H圖中的環形結構166的俯視圖。當從俯視觀察時，環形結構166具有矩形形狀並且圍繞晶粒結構10。
第2B圖示出了根據本揭露的一些實施例的第1K圖中的第一突出結構178的俯視圖。第1L圖示出了沿第2B圖的線段A-A’截取的第二基板160的剖面圖。
當從俯視觀察時，第一突出結構178具有四個子部分。當從俯視觀察時，四個子部分中的每一個都具有L形。第一突出結構178的每個子部分位於第一基板160的角落。在一些實施例中，第一突出結構178的每個子部分具有在大約0.1mm至大約1mm的範圍內的第一寬度W 1。在一些實施例中，第一突出結構178的每個子部分具有在大約1mm至大約5mm的範圍內的第一長度L 1。
由於在加壓製程20中對電連接器172進行加壓，因此電連接器172具有矩形形狀。
第2C圖示出了根據本揭露的一些實施例的第1L圖中的第二突出結構182的俯視圖。第1L圖示出了沿第2C圖的線段B-B’截取的第三基板180的剖面圖。
當從俯視觀察時，第二突出結構182具有四個子部分。第二突出結構182的每個子部分位於第三基板180的角落。在一些實施例中，第二突出結構182的每個子部分具有在大約0.1mm至大約1mm的範圍內的第二寬度W 2。在一些實施例中，第二突出結構182的每個子部分具有在大約1mm至大約5mm的範圍內的第二長度L 2。
第2C’圖示出了根據本揭露的一些實施例的第二突出結構182以及第三突出結構184的俯視圖。
與第二突出結構182相似，當從俯視觀察時，第三突出結構184也具有四個子部分。第三突出結構184的每個子部分位於第三基板180的角落。在一些實施例中，第三突出結構184的每個子部分具有在大約0.1mm至大約1mm的範圍內的第三寬度W 3。在一些實施例中，第三突出結構184的每個子部分具有在大約1mm至大約5mm的範圍內的第三長度L 3。
第3A圖至第3E圖示出了根據本揭露的一些實施例的形成封裝結構100c的各個階段的剖面圖。除了第二基板160向上翹曲或彎曲之外，封裝結構100c與第1M圖所示的封裝結構100a相似或相同。用於形成封裝結構100c的製程以及材料可以與用於形成封裝結構100a的製程以及材料相似或相同，在此不再贅述。
如第3A圖所示，第二基板160在熱製程之後呈現出翹曲。之後，在導電墊170上方形成助熔劑（flux）171。導電材料174在裝置22下方並且面對助熔劑171。由於第二基板160呈現出翹曲，所以將助熔劑171形成在第二基板160的非平面的頂表面上。
助熔劑171用於在回流製程期間抑制或防止在電連接器172的表面上生成氧化物形式。可以防止在隨後的回流製程期間由氧化物引起的接合缺陷。在一些實施例中，助熔劑171包括氯化物、氟化物、樹脂、或另一種適用的材料。
在一些實施例中，第二基板160的翹曲是由在封裝製程期間兩種不同的封裝材料（例如晶粒結構10以及第二基板160）之間的熱膨脹係數（coefficient of thermal expansion,  CTE）失配（mismatch）引起的。封裝製程可以是安裝晶粒結構10（第1G圖）或在第二基板160上方形成封裝層164（第1H圖）。
接下來，如第3B圖所示，根據本揭露的一些實施例，導電材料174被設置在對應的助熔劑171上以藉由回流製程形成複數個電連接器172。結果，電連接器172形成在第二基板160的非平面的第二表面160b上。在一些實施例中，電連接器172提供用於接合到第三基板180的凹形接合表面。在一些其他實施例中，電連接器172提供用於接合到第三基板180的凸形接合表面。
應注意的是，由於每個電連接器172具有相同的尺寸並且形成在第二基板160的非平面的第二表面160b上，所以每個電連接器172具有不同的高度（水平）。在一些實施例中，位於第二基板160的中央區域中的電連接器172低於位於第二基板160的外圍區域中的電連接器172。
在一些實施例中，電連接器172的最高點以及最低點之間存在距離G。如果距離G太大，則電連接器172的非平面會在隨後的組裝製程中產生故障。
之後，為了提供平坦的接合表面，如第3C圖所示，根據本揭露的一些實施例，藉由模制裝置18在電連接器172以及第一突出結構178上執行加壓製程20。
應注意的是，如第3C圖所示，第一突出結構178形成在第二基板160的傾斜表面上。第一突出結構178具有平坦的頂表面以及傾斜的底表面。
接下來，如第3D圖所示，根據本揭露的一些實施例，模制裝置18被移除，並且電連接器172提供平坦的接合表面。電連接器172的非平面程度藉由加壓製程20而減小。電連接器172的一部分在第一區域11（例如，外圍區域）中被加壓，並且被加壓的電連接器172具有實質平坦的頂表面。電連接器172的另一部分在第二區域12（例如，中央區域）中未被加壓，並且未被加壓的電連接器172具有彎曲的頂表面。
第一突出結構178具有第一高度H 1。在第一區域11（例如，外圍區域）中被加壓的電連接器172具有第二高度H 2以及第二寬度D 2，並且在第二區域（例如，中央區域）中的未被加壓的電連接器172具有第三高度H 3以及第三寬度D 3。在一些實施例中，第一高度H 1小於第二高度H 2，並且第二高度H 2小於第三高度H 3。在一些實施例中，第二寬度D 2大於第三寬度D 3。
之後，如第3E圖所示，根據本揭露的一些實施例，第三基板180提供有第二突出結構182，並且第二基板160接合到第三基板180。
由於第二基板160可能呈現翹曲，因此如果在加壓製程20中未對電連接器172進行加壓，則會產生電連接器172的接合表面的非平面性。結果，電連接器172的一部分可能不與第三基板180接觸，並且第二基板160以及第三基板180之間的接合可靠度降低。為了補償翹曲，在將第二基板160接合至第三基板180之前對電連接器172進行加壓。因此，電連接器172的接合表面的共面性（co-planarity）被改善，並且封裝結構100c的接合可靠度被改善。
第3E’圖示出了根據本揭露的一些實施例的封裝結構100d的剖面圖。除了在第三基板180上方並在第二突出結構182旁邊初始形成第三突出結構184之外，封裝結構100d與第3E圖所示的封裝結構100c相似或相同。用於形成封裝結構100d的製程以及材料可以與用於形成封裝結構100c的製程以及材料相似或相同，在此不再贅述。
如第3E’圖所示，第一突出結構178在第二突出結構182以及第三突出結構184之間。第二突出結構182具有第四高度H 4，第三突出結構184具有第五高度H 5。在一些實施例中，第五高度H 5大於第一高度H 1，並且第一高度H 1大於第四高度H 4。
第4A圖示出了根據本揭露的一些實施例的第3D圖中的第一突出結構178的俯視圖。
當從俯視觀察時，第一突出結構178具有四個子部分。當從俯視觀察時，四個子部分中的每一個都具有L形。第一突出結構178的每個子部分位於第一基板160的角落。在一些實施例中，第一突出結構178的每個子部分具有在大約0.1mm至大約1mm的範圍內的第一寬度W 1。在一些實施例中，第一突出結構178的每個子部分具有在大約1mm至大約5mm的範圍內的第一長度L 1。
由於在加壓製程20中對電連接器172進行加壓，因此第一區域中的電連接器172具有矩形形狀。由於未對在第二區域中的電連接器172進行加壓，因此在第二區域中的電連接器172具有圓形形狀。
第4B圖示出了根據本揭露的一些實施例的第3E圖中的第二突出結構182的俯視圖。
當從俯視觀察時，第二突出結構182具有四個子部分。當從俯視觀察時，四個子部分中的每一個都具有L形。第二突出結構182的每個子部分位於第三基板180的角落。在一些實施例中，第二突出結構182的每個子部分具有在大約0.1mm至大約1mm的範圍內的第二寬度W 2。在一些實施例中，第二突出結構182的每個子部分具有在大約1mm至大約5mm的範圍內的第二長度L 2。
第4B’圖示出了根據本揭露的一些實施例的第二突出結構182以及第三突出結構184的俯視圖。
與第二突出結構182相似，當從俯視觀察時，第三突出結構184也具有四個子部分。第三突出結構184的每個子部分位於第三基板180的角落。
第5圖示出了根據本揭露的一些實施例的封裝結構100e的剖面圖。除了在第二基板160的第一表面160a上方形成罩蓋結構190之外，封裝結構100e與第1M圖所示的封裝結構100a相似或相同。用於形成封裝結構100e的製程以及材料可以與用於形成封裝結構100a的製程以及材料相似或相同，在此不再贅述。
如第5圖所示，罩蓋結構190圍繞晶粒結構10。因此，從半導體晶粒120產生的熱量可以散逸到罩蓋結構172，然後散逸到外部環境。第一突出結構178在罩蓋結構190的正下方。罩蓋結構190的外側壁與第一突出結構178的外側壁對準。
第6圖示出了根據本揭露的一些實施例的封裝結構100f的剖面圖。除了在第二基板160的第一表面160a上方形成罩蓋結構190以及在兩個相鄰的電連接器192之間形成第四突出結構186之外，封裝結構100f與第1M’圖所示的封裝結構100a相似或相同。在一些實施例中，可以在第二基板160下方初始形成第四突出結構186，然後接合到第三基板180。在一些其他實施例中，可以在第三基板180上初始形成第四突出結構186，然後接合到第二基板160。
第7圖示出了根據本揭露的一些實施例的封裝結構100g的剖面圖。除了在第二基板160的第一表面160a上方形成罩蓋結構190之外，封裝結構100g與第3E圖所示的封裝結構100c相似或相同。用於形成封裝結構100g的製程以及材料可以與用於形成封裝結構100c的製程以及材料相似或相同，在此不再贅述。
第8圖示出了根據本揭露的一些實施例的封裝結構100h的剖面圖。除了在第二基板160的第一表面160a上方形成罩蓋結構190，並且在兩個相鄰的電連接器192之間形成第四突出結構186之外，封裝結構100h與第3E’圖所示的封裝結構100d相似或相同。用於形成封裝結構100h的製程以及材料可以與用於形成封裝結構100d的結構相似或相同，在此不再贅述。
在一些實施例中，可以在第二基板160下方初始形成第四突出結構186，然後接合到第三基板180。在一些其他實施例中，可以在第三基板180上初始形成第四突出結構186，然後接合到第二基板160上。在一些實施例中，第四突出結構186的第六高度H 6大於第三突出結構184的第五高度H 5。
封裝結構100a、100b、100c、100d、100e、100f、100g、100h包括形成在第二基板160的第一表面160a上方的晶粒結構10。第一突出結構178形成在第二基板160的第二表面160b下方，並且鄰接於電連接器172。第二突出結構182形成在第三基板180上方。第一突出結構178以及第二突出結構182使用作為支撐以及對準標記。藉由使用第一突出結構178作為支撐，減少了第二基板160的翹曲。藉由使用第一突出結構178以及第二突出結構182作為對準標記，減少了第二基板160以及第三基板180之間的未對準。此外，藉由加壓製程20降低了電連接器172的非平面程度，並且第一突出結構178被配置為當在電連接器172上執行加壓製程20時控制電連接器172的高度。
提供了用於形成封裝結構的實施例及其形成方法。封裝結構包括形成在第二基板的第一表面上方的晶粒結構，以及形成在第二基板的第二表面下方的電連接器。第一突出結構以及電連接器形成在第二基板下方。第二突出結構形成在第三基板上方。第一突出結構以及第二突出結構使用作為支撐、高度控制器、以及對準標記。因此，改善了封裝結構的接合可靠度以及性能。
在一些實施例中，提供了一種形成封裝結構的方法。方法包括在第一基板的第一表面上方形成晶粒結構，在第一基板的第二表面下方形成複數個電連接器。方法也包括在第一基板的第二表面下方形成第一突出結構，並且電連接器被第一突出結構圍繞。此方法更包括在第二基板上方形成第二突出結構，以及將第一基板接合至第二基板。電連接器被第二突出結構圍繞，並且第一突出結構不與第二突出結構重疊。在一些實施例中，方法更包括在將第一基板接合到第二基板之前，從第一基板的第二表面加壓複數個電連接器的一部分，使得電連接器的部分具有實質底部平坦的表面。在一些實施例中，方法更包括在第一基板的第一表面上方形成環形結構或罩蓋結構，其中晶粒結構被環形結構或罩蓋結構圍繞。在一些實施例中，第一突出結構在環形結構或罩蓋結構的正下方。在一些實施例中，第一突出結構以及第二突出結構為相同的高度。在一些實施例中，第一突出結構以及第二突出結構皆由聚合物材料或金屬所製成。在一些實施例中，當從俯視觀察時，第一突出結構具有L形。在一些實施例中，當從俯視觀察時，第一突出結構具有四個子部分，並且子部分的每一個位於第一基板的角落。在一些實施例中，晶粒結構包括複數個矽通孔、內連線結構、以及晶粒。複數個矽通孔在第三基板中形成，內連線結構在矽通孔上方形成，晶粒在內連線結構上方形成。
在一些實施例中，提供了一種形成封裝結構的方法。方法包括在第一基板的第一表面上方形成晶粒結構，在第一基板的第二表面下方形成複數個電連接器。方法也包括在電連接器旁邊形成第一突出結構，從第一基板的第二表面加壓第一區域中的複數個電連接器的一部分，使得第一區域中的電連接器的每一個具有實質底部平坦的表面。方法更包括在第二基板上方形成第二突出結構以及第三突出結構，並且第二突出結構以及第三突出結構為不同的高度。方法包括將第一基板接合至第二基板，並且第一突出結構位於第二突出結構以及該第三突出結構之間。在一些實施例中，晶粒結構包括複數個矽通孔、內連線結構、以及晶粒。複數個矽通孔在第三基板中形成，內連線結構在矽通孔上方形成，晶粒在內連線結構上方形成。在一些實施例中，不加壓第二區域中的複數個電連接器的另一部分，並且第一區域中的電連接器中的一個具有第一高度，第一高度小於第二區域中的電連接器中的一個的第二高度。在一些實施例中，第一區域中的電連接器中的一個具有第一寬度，第一寬度大於第二區域中的電連接器中的一個的第二寬度。在一些實施例中，方法更包括在第一基板的第一表面上方形成環形結構或罩蓋結構，其中封裝結構被環形結構或罩蓋結構圍繞，並且第一突出結構在環形結構或罩蓋結構的正下方。在一些實施例中，環形結構或罩蓋結構的外側壁與第一突出結構的外側壁對齊。
在一些實施例中，提供了一種形成封裝結構的方法。方法包括在第一基板上方形成晶粒結構，並且在第一基板下方形成複數個電連接器。方法也包括在第一基板下方形成第一支撐結構，並且第一支撐結構具有第一高度，方法更包括對電連接器執行加壓製程，使得電連接器包括第一組被加壓電連接器以及第二組未被加壓電連接器。方法更包括使用電連接器將第一基板接合到第二基板，並且第一組被加壓電連接器中的一個具有第二高度。第二組未被加壓電連接器中的一個具有第三高度。第一高度小於第二高度，並且第二高度小於第三高度。在一些實施例中，方法更包括在將第一基板接合到第二基板之前，在第二基板上方形成第二突出結構，其中在將第一基板接合到第二基板之後，第二突出結構在第一基板以及第二基板之間。在一些實施例中，方法更包括在將第一基板接合到第二基板之前，在第二基板上方形成第三突出結構，其中第二突出結構在第一突出結構以及第三突出結構之間。在一些實施例中，第一組被加壓電連接器中的一個具有第二寬度，第二組未被加壓電連接器中的一個具有第三寬度，並且第二寬度大於第三寬度。在一些實施例中，方法更包括在第一基板的第一表面上方形成環形結構或罩蓋結構，其中晶粒結構被環形結構或罩蓋結構圍繞，並且第一突出結構在環形結構或罩蓋結構的正下方。
前面概述數個實施例之特徵，使得本技術領域中具有通常知識者可更好地理解本揭露之各方面。本技術領域中具有通常知識者應理解的是，可輕易地使用本揭露作為設計或修改其他製程以及結構的基礎，以實現在此介紹的實施例之相同目的及/或達到相同優點。本技術領域中具有通常知識者亦應理解的是，這樣的等效配置並不背離本揭露之精神以及範疇，且在不背離本揭露之精神以及範疇的情形下，可對本揭露進行各種改變、替換以及更改。
10:晶粒結構 11:第一區域 12:第二區域 18:模制裝置 20:加壓製程 22:裝置 100a,100b,100c,100d,100e,100g,100h:封裝結構 102:基板/第一基板 102a,160a,180a:第一表面 102b,160b,180b:第二表面 104:導電結構 106,124:導電層 108:介電層 110,122:內連線結構 112,126,152,170:導電墊 120:半導體晶粒 121:基板 128,154:導電連接器 130:底部填充層 140,164:封裝層 142:承載基板 150:鈍化層 160:第二基板 166:環形結構 171:助熔劑 172,190,192:電連接器 174:導電材料 178:第一突出結構 180:第三基板 182:第二突出結構 184:第三突出結構 D 1:第一寬度 D 2:第二寬度 D 3:第三寬度 G:距離 H 1:第一高度 H 1’:原始高度 H 2:第二高度 H 3:第三高度 H 4:第四高度 H 5:第五高度 L 1:第一長度 L 2:第二長度 L 3:第三長度 S 1:第一空間 S 2:第一空間 W 1:第一寬度 W 2:第二寬度 W 3:第三寬度
以下將配合所附圖式詳述本揭露之實施例。應注意的是，依據在業界的標準做法，多種特徵並未按照比例繪示且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。 第1A圖至第1M圖示出了根據本揭露的一些實施例的形成封裝結構的各個階段的剖面圖。 第1M’圖示出了根據本揭露的一些實施例的封裝結構的剖面圖。 第2A圖示出了根據本揭露的一些實施例的環形結構的俯視圖。 第2B圖示出了根據本揭露的一些實施例的第1K圖中的第一突出結構的俯視圖。 第2C圖示出了根據本揭露的一些實施例的第1L圖中的第二突出結構的俯視圖。 第2C’圖示出了根據本揭露的一些實施例的第二突出結構以及第三突出結構的俯視圖。 第3A圖至第3E圖示出了根據本揭露的一些實施例的形成封裝結構的各個階段的剖面圖。 第3E’圖示出了根據本揭露的一些實施例的封裝結構的剖面圖。 第4A圖示出了根據本揭露的一些實施例的第3D圖中的第一突出結構的俯視圖。 第4B圖示出了根據本揭露的一些實施例的第3E圖中的第二突出結構的俯視圖。 第4B’圖示出了根據本揭露的一些實施例的第二突出結構以及第三突出結構的俯視圖。 第5圖示出了根據本揭露的一些實施例的封裝結構的剖面圖。 第6圖示出了根據本揭露的一些實施例的封裝結構的剖面圖。 第7圖示出了根據本揭露的一些實施例的封裝結構的剖面圖。 第8圖示出了根據本揭露的一些實施例的封裝結構的剖面圖。
無
100a:封裝結構 102:基板/第一基板 104:導電結構 106,124:導電層 108:介電層 112,126,152:導電墊 121:基板 122:內連線結構 128,154:導電連接器 150:鈍化層 160:第二基板 164:封裝層 166:環形結構 178:第一突出結構 180:第三基板 180a:第一表面 180b:第二表面 182:第二突出結構 192:電連接器 H 1:第一高度

Claims (10)

  1. 一種形成封裝結構的方法，包括：在一第一基板的一第一表面上方形成一晶粒結構；在該第一基板的一第二表面下方形成複數個電連接器；在該第一基板的該第二表面下方形成一第一突出結構，其中該等電連接器被該第一突出結構圍繞；在一第二基板上方形成一第二突出結構；以及將該第一基板接合至該第二基板，其中該等電連接器被該第二突出結構圍繞，並且該第一突出結構不與該第二突出結構重疊。
  2. 如請求項1所述的形成封裝結構的方法，更包括：在將該第一基板接合到該第二基板之前，從該第一基板的該第二表面加壓複數個電連接器的一部分，使得該等電連接器的該部分具有一實質底部平坦的表面。
  3. 如請求項1所述的形成封裝結構的方法，更包括：在該第一基板的該第一表面上方形成一環形結構或一罩蓋結構，其中該晶粒結構被該環形結構或該罩蓋結構圍繞。
  4. 如請求項1所述的形成封裝結構的方法，其中當從俯視觀察時，該第一突出結構具有L形。
  5. 如請求項1所述的形成封裝結構的方法，其中當從俯視觀察時，該第一突出結構具有四個子部分，並且該等子部分的每一個位於該第一基板的角落。
  6. 一種形成封裝結構的方法，包括：在一第一基板的一第一表面上方形成一晶粒結構；在該第一基板的一第二表面下方形成複數個電連接器； 在該等電連接器旁邊形成一第一突出結構；從該第一基板的該第二表面加壓一第一區域中的複數個電連接器的一部分，使得該第一區域中的該等電連接器的每一個具有一實質底部平坦的表面；在一第二基板上方形成一第二突出結構以及一第三突出結構，其中該第二突出結構以及該第三突出結構為不同的高度；以及將該第一基板接合至該第二基板，其中該第一突出結構位於該第二突出結構以及該第三突出結構之間。
  7. 如請求項6所述的形成封裝結構的方法，其中該晶粒結構包括：複數個矽通孔，在一第三基板中形成；一內連線結構，在該等矽通孔上方形成；以及一晶粒，在該內連線結構上方形成。
  8. 一種形成封裝結構的方法，包括：在一第一基板上方形成一晶粒結構；在該第一基板下方形成複數個電連接器；在該第一基板下方形成一第一支撐結構，其中該第一支撐結構具有一第一高度；對該等電連接器執行一加壓製程，使得該電連接器包括一第一組被加壓電連接器以及一第二組未被加壓電連接器；以及使用該等電連接器將該第一基板接合到一第二基板，其中該第一組被加壓電連接器中的一個具有一第二高度，該第二組未被加壓電連接器中的一個具有一第三高度，該第一高度小於該第二高度，並且該第二高度小於該第三高度。
  9. 如請求項8所述的形成封裝結構的方法，更包括：在將該第一基板接合到該第二基板之前，在該第二基板上方形成一第二突出 結構，其中在將該第一基板接合到該第二基板之後，該第二突出結構在該第一基板以及該第二基板之間。
  10. 如請求項9所述的形成封裝結構的方法，更包括：在將該第一基板接合到該第二基板之前，在該第二基板上方形成一第三突出結構，其中該第二突出結構在該第一突出結構以及該第三突出結構之間。
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