TW202347679A - 積體電路封裝體及其形成方法 - Google Patents
積體電路封裝體及其形成方法 Download PDFInfo
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- TW202347679A TW202347679A TW112100991A TW112100991A TW202347679A TW 202347679 A TW202347679 A TW 202347679A TW 112100991 A TW112100991 A TW 112100991A TW 112100991 A TW112100991 A TW 112100991A TW 202347679 A TW202347679 A TW 202347679A
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Abstract
一個實施例是一種包括封裝組件的裝置,所述封裝組件包括積體電路晶粒及連接至積體電路晶粒的多個導電連接件,導電連接件設置於封裝組件的第一側處。所述裝置亦包括位於封裝組件的第二側上的金屬層,第二側與第一側相對。所述裝置亦包括位於金屬層上的熱介面材料。所述裝置亦包括位於熱介面材料上的蓋。所述裝置亦包括位於封裝組件及熱介面材料的側壁上的保持結構。所述裝置亦包括連接至導電連接件的封裝基底,蓋黏合至封裝基底。
Description
由於各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度的不斷提高,半導體行業已經歷快速發展。在很大程度上,積體密度的提高源於最小特徵大小(minimum feature size)的迭代減小,此使得能夠將更多的組件整合至給定的面積中。隨著對日益縮小的電子裝置的需求的增長,出現了對更小且更具創造性的半導體晶粒封裝技術的需要。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本揭露。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於……之下(beneath)」、「位於……下方(below)」、「下部的(lower)」、「位於……上方(above)」、「上部的(upper)」及類似用語等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性闡述語可同樣相應地進行解釋。
根據各種實施例,藉由將多個積體電路晶粒(integrated circuit die)封裝於晶圓中來形成多個積體電路封裝體(integrated circuit package)。對晶圓進行單體化以形成多個中間封裝組件(intermediate package component)。然後,將中間封裝組件貼合至封裝基底(package substrate),以形成積體電路封裝體。在一些實施例中,在中間封裝組件貼合至封裝基底之後,將散熱結構(heat dissipation structure)貼合至中間封裝組件,且所述散熱結構可包含銦。可在封裝基底上相鄰於中間封裝組件及散熱結構來形成保持結構(retaining structure)(例如,保持壁(retaining wall))。然後,可將蓋(lid)貼合於中間封裝組件及保持結構之上,隨後進行熱夾持(heat clamping)及/或回焊製程(reflow process)以對蓋及/或散熱結構進行貼合。由於具有保持結構,因此散熱結構的金屬(例如,銦)在封裝體的熱夾持、回焊或正常操作期間的任何後續滲出或回流受到遏制。此種遏制會防止金屬溢出而使封裝組件短路(shorting),且會防止在散熱結構中形成空隙(void),此可改善封裝體的可靠性及效能。
圖1是積體電路晶粒50的剖視圖。在隨後的處理中,將對多個積體電路晶粒50進行封裝以形成多個積體電路封裝體。每一積體電路晶粒50可為邏輯裝置(例如,中央處理單元(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、微控制器等)、記憶體裝置(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒等)、電源管理裝置(例如,電源管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)裝置、感測器裝置、微機電系統(micro-electro-mechanical-system,MEMS)裝置、訊號處理裝置(例如,數位訊號處理(digital signal processing,DSP)晶粒)、前端裝置(例如,類比前端(analog front-end,AFE)晶粒)、類似裝置或其組合(例如,系統晶片(system-on-a-chip,SoC)晶粒)。可將積體電路晶粒50形成於晶圓中,所述晶圓可包括在隨後的步驟中被單體化以形成多個積體電路晶粒50的多個不同晶粒區。積體電路晶粒50包括半導體基底(semiconductor substrate)52、內連線結構(interconnect structure)54、多個晶粒連接件(die connector)56及介電層(dielectric layer)58。
半導體基底52可為經摻雜或未經摻雜的矽基底,或者可為絕緣體上半導體(semiconductor-on-insulator,SOI)基底的主動層(active layer)。半導體基底52可包含其他半導體材料(例如鍺);化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦);合金半導體(包括矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷砷化鎵銦);或者其組合。亦可使用其他基底,例如多層式基底(multi-layered substrate)或梯度基底(gradient substrate)。半導體基底52具有主動表面(active surface)(例如,面朝上的表面)及非主動表面(inactive surface)(例如,面朝下的表面)。半導體基底52的主動表面處具有多個裝置。所述裝置可為主動裝置(例如,電晶體、二極體等)、電容器、電阻器等。非主動表面可不具有裝置。
內連線結構54位於半導體基底52的主動表面之上,且用於對半導體基底52的裝置進行電性連接以形成積體電路。內連線結構54可包括一或多個介電層以及位於介電層中的多個相應金屬化層。用於介電層的可接受的介電材料包括:氧化物,例如氧化矽或氧化鋁;氮化物,例如氮化矽;碳化物,例如碳化矽;類似材料;或者其組合,例如氮氧化矽、碳氧化矽、碳氮化矽、碳氮氧化矽或類似材料。亦可使用其他介電材料,例如聚合物,所述聚合物為例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide,PI)、苯並環丁烯(benzocyclobutene,BCB)系聚合物或類似聚合物。金屬化層可包括多個導通孔(conductive via)及/或多個導線(conductive line)以對半導體基底52的裝置進行內連。金屬化層可由例如金屬(例如銅、鈷、鋁、金、其組合或類似金屬)等導電材料形成。內連線結構54可藉由例如單鑲嵌製程(single damascene process)、雙鑲嵌製程(dual damascene process)或類似製程等鑲嵌製程來形成。
積體電路晶粒50的前側50F處具有晶粒連接件56。晶粒連接件56可為與外部進行連接的導電柱、接墊或類似元件。晶粒連接件56位於內連線結構54中及/或位於內連線結構54上。舉例而言,晶粒連接件56可為內連線結構54的上部金屬化層的一部分。晶粒連接件56可由金屬(例如,銅、鋁或類似金屬)形成,且可藉由例如鍍覆(plating)或類似製程來形成。
可選地,在積體電路晶粒50的形成期間,可在晶粒連接件56上設置多個焊料區(solder region)(未單獨示出)。焊料區可用於對積體電路晶粒50實行晶片探針(chip probe,CP)測試。舉例而言,焊料區可為用於將晶片探針附接至晶粒連接件56的焊料球、焊料凸塊或類似結構。可對積體電路晶粒50實行晶片探針測試,以確定積體電路晶粒50是否是已知良好晶粒(known good die,KGD)。因此,只有(其為KGD的)積體電路晶粒50經歷隨後的處理而被封裝,而未通過晶片探針測試的晶粒不被封裝。在測試之後,焊料區可在隨後的處理步驟中被移除。
積體電路晶粒50的前側50F處具有介電層58。介電層58位於內連線結構54中及/或位於內連線結構54上。舉例而言,介電層58可為內連線結構54的上部介電層。介電層58在側向上包封晶粒連接件56。介電層58可為氧化物、氮化物、碳化物、聚合物、類似材料或其組合。介電層58可例如藉由旋轉塗佈(spin coating)、疊層(lamination)、化學氣相沈積(chemical vapor deposition,CVD)或類似製程來形成。最初,介電層58可掩埋晶粒連接件56,進而使得介電層58的頂表面位於晶粒連接件56的頂表面上方。在積體電路晶粒50的形成期間,晶粒連接件56藉由介電層58而被暴露出。暴露出晶粒連接件56可移除可能存在於晶粒連接件56上的任何焊料區。可對各個層應用移除製程,以移除位於晶粒連接件56之上的過量材料。移除製程可為平坦化製程,例如化學機械研磨(chemical mechanical polish,CMP)、回蝕(etch-back)、其組合或類似製程。在平坦化製程之後,晶粒連接件56的頂表面與介電層58的頂表面實質上共面(在製程變化內),進而使得其彼此齊平。晶粒連接件56及介電層58在積體電路晶粒50的前側50F處被暴露出。
在一些實施例中,積體電路晶粒50是包括多個半導體基底52的堆疊裝置。舉例而言,積體電路晶粒50可為包括多個記憶體晶粒的記憶體裝置,例如混合記憶體立方(hybrid memory cube,HMC)裝置、高頻寬記憶體(high bandwidth memory,HBM)裝置或類似裝置。在此種實施例中,積體電路晶粒50包括藉由例如矽穿孔等多個基底穿孔(through-substrate via,TSV)進行內連的多個半導體基底52。半導體基底52中的每一者可(或可不)具有單獨的內連線結構54。
圖2至圖14是根據一些實施例的積體電路封裝體(又稱封裝體)200的製造中的中間階段的示意圖。圖2至圖13是用於形成包括中介層(interposer)的封裝組件210(例如用於基底上晶圓上晶片(chip-on-wafer-on-substrate,CoWoS
®)裝置的封裝組件)的製程的剖視圖及平面圖。封裝組件210可為晶圓上晶片(chip-on-wafer,CoW)封裝組件。
將藉由最初對多個積體電路晶粒50進行封裝以在晶圓110中形成封裝組件210來形成積體電路封裝體200(參見圖13)。示出晶圓110的一個封裝區100A,且對積體電路晶粒50進行封裝以在晶圓110的封裝區100A中的每一者中形成封裝組件210。應理解,可同時處理任意數量的封裝區,以形成任意數量的封裝組件。將對晶圓110的封裝區100A進行單體化以形成封裝組件210。將會將封裝組件210貼合至封裝基底220(參見例如圖8或圖16)。然後,將在封裝組件210及封裝基底220上形成散熱結構(包括背側金屬212/焊劑214/蓋230/熱介面材料232/焊劑234/背側金屬236),以完成積體電路封裝體200的形成(參見例如圖13、圖15或圖18)。
在圖2中,獲得或形成晶圓110。晶圓110包括位於封裝區100A中的多個裝置,封裝區100A將在隨後的處理中被單體化以包括於封裝組件210中。晶圓110中的裝置可為中介層、積體電路晶粒或類似裝置。在一些實施例中,在晶圓110中形成中介層102,中介層102包括基底112、內連線結構114及多個導通孔120。
基底112可為塊狀半導體基底(bulk semiconductor substrate)、絕緣體上半導體(SOI)基底、多層式半導體基底或類似基底。基底112可包含:半導體材料,例如矽、鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷砷化鎵銦;或者其組合。亦可使用其他基底,例如多層式基底或梯度基底。基底112可為經摻雜的或未經摻雜的。在晶圓110中形成中介層的實施例中,儘管中介層可包括形成於基底112的前表面(例如,圖2中面對上的表面)中及/或形成於基底112的前表面上的被動裝置,然而基底112中一般不包括主動裝置。在晶圓110中形成積體電路裝置的實施例中,可在基底112的前表面中及/或在基底112的前表面上形成例如電晶體、電容器、電阻器、二極體及類似裝置等主動裝置。
內連線結構114位於基底112的前表面之上,且用於對基底112的裝置(若有的話)進行電性連接。內連線結構114可包括一或多個介電層以及位於所述介電層中的多個相應金屬化層。用於介電層的可接受的介電材料包括:氧化物,例如氧化矽或氧化鋁;氮化物,例如氮化矽;碳化物,例如碳化矽;類似材料;或者其組合,例如氮氧化矽、碳氧化矽、碳氮化矽、碳氮氧化矽或類似材料。亦可使用其他介電材料,例如聚合物,所述聚合物為例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)系聚合物或類似聚合物。金屬化層可包括多個導通孔及/或多個導線以將任何裝置內連於一起及/或將任何裝置內連至外部裝置。金屬化層可由例如金屬(例如銅、鈷、鋁、金、其組合或類似材料)等導電材料形成。可藉由例如單鑲嵌製程、雙鑲嵌製程或類似製程等鑲嵌製程來形成內連線結構114。
在一些實施例中,晶圓110的前側處具有多個晶粒連接件116及介電層118。具體而言,晶圓110可包括與針對圖1闡述的積體電路晶粒50的晶粒連接件及介電層相似的晶粒連接件116及介電層118。舉例而言,晶粒連接件116及介電層118可為內連線結構114的上部金屬化層的一部分。
導通孔120延伸至內連線結構114及/或基底112中。導通孔120電性連接至內連線結構114的金屬化層。導通孔120有時亦被稱為基底穿孔(TSV)。作為形成導通孔120的實例,可藉由例如蝕刻、銑切(milling)、雷射技術、其組合及/或類似製程在內連線結構114及/或基底112中形成多個凹陷(recess)。可例如利用氧化技術來在凹陷中形成薄的介電材料。可例如藉由CVD、原子層沈積(atomic layer deposition,ALD)、物理氣相沈積(physical vapor deposition,PVD)、熱氧化、其組合及/或類似製程來在凹陷中共形地沈積薄的障壁層。障壁層可由氧化物、氮化物、碳化物、其組合或類似材料形成。可在障壁層之上及在凹陷中沈積導電材料。可藉由電化學鍍覆製程(electro-chemical plating process)、CVD、ALD、PVD、其組合及/或類似製程來形成導電材料。導電材料的實例為銅、鎢、鋁、銀、金、其組合及/或類似材料。藉由例如CMP而自內連線結構114或基底112的表面移除過量的導電材料及障壁層。障壁層的其餘部分及導電材料的其餘部分形成導通孔120。
在圖3中,將積體電路晶粒50(例如,第一積體電路晶粒50A及多個第二積體電路晶粒50B)貼合至晶圓110。在所示實施例中,彼此相鄰地放置多個積體電路晶粒50(包括第一積體電路晶粒50A及第二積體電路晶粒50B),其中第一積體電路晶粒50A位於第二積體電路晶粒50B之間。在一些實施例中,第一積體電路晶粒50A是邏輯裝置(例如CPU、GPU或類似裝置),而第二積體電路晶粒50B是記憶體裝置(例如DRAM晶粒、HMC模組、HBM模組或類似裝置)。在一些實施例中,第一積體電路晶粒50A是與第二積體電路晶粒50B相同類型的裝置(例如,SoC)。
在所示實施例中,利用多個焊料接合件(solder bonds)(例如利用導電連接件132)將積體電路晶粒50貼合至晶圓110。可使用例如拾取及放置工具(pick-and-place tool)將積體電路晶粒50放置於內連線結構114上。導電連接件132可由例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等可回焊的導電材料形成。在一些實施例中,藉由最初透過例如蒸鍍、電鍍、印刷、焊料轉移、植球或類似方法等方法形成焊料層來形成導電連接件132。一旦已在所述結構上形成焊料層,便可實行回焊以便將導電連接件132造型呈所期望的凸塊形狀。將積體電路晶粒50貼合至晶圓110可包括將積體電路晶粒50放置於晶圓110上以及對導電連接件132進行回焊。導電連接件132在晶圓110的對應晶粒連接件116與積體電路晶粒50的晶粒連接件56之間形成多個接頭(joint),從而將中介層102電性連接至積體電路晶粒50。
可在導電連接件132周圍以及晶圓110與積體電路晶粒50之間形成底部填充劑(underfill)134。底部填充劑134可減小應力並保護由導電連接件132的回焊產生的接頭。底部填充劑134可由例如模製化合物(molding compound)、環氧樹脂或類似材料等底部填充材料形成。可在將積體電路晶粒50貼合至晶圓110之後藉由毛細流動製程(capillary flow process)來形成底部填充劑134,或者可在將積體電路晶粒50貼合至晶圓110之前藉由適合的沈積方法來形成底部填充劑134。可以液體或半液體形式施加底部填充劑134,且隨後對底部填充劑134進行固化。
在其他實施例中(未單獨示出),利用直接接合件(direct bond)將積體電路晶粒50貼合至晶圓110。舉例而言,可使用金屬對金屬接合(metal to metal bonding)及介電質對介電質接合(dielectric to dielectric bonding)、熔融接合(fusion bonding)、介電質接合、金屬接合或類似接合方式來在不使用黏合劑或焊料的情況下對積體電路晶粒50及晶圓110的對應介電層58、介電層118及/或晶粒連接件56、晶粒連接件116進行直接接合。當使用直接接合時,可省略底部填充劑134。此外,可使用接合技術的混合形式,例如,可藉由焊料接合件將一些積體電路晶粒50貼合至晶圓110,且可藉由直接接合件將其他積體電路晶粒50貼合至晶圓110。
在圖4中,在積體電路晶粒50上及積體電路晶粒50周圍形成包封體(encapsulant)136。在形成之後,包封體136包封積體電路晶粒50以及底部填充劑134(若存在)或導電連接件132。包封體136可為模製化合物、環氧樹脂或類似材料。可藉由壓縮模製(compression molding)、轉移模製(transfer molding)或類似製程來施加包封體136,且在晶圓110之上形成包封體136,進而使得積體電路晶粒50被掩埋或覆蓋。可以液體或半液體形式施加包封體136,且隨後對包封體136進行固化。可對包封體136進行薄化,以暴露出積體電路晶粒50。薄化製程可為磨製製程(grinding process)、化學機械研磨(CMP)、回蝕、其組合或類似製程。在薄化製程之後,積體電路晶粒50的頂表面與包封體136的頂表面共面(在製程變化內),進而使得其彼此齊平。實行所述薄化,直至已移除所期望量的積體電路晶粒50及/或包封體136為止。
在圖5中,對基底112進行薄化以暴露出導通孔120。可藉由例如磨製製程、化學機械研磨(CMP)、回蝕、其組合或類似製程等薄化製程來達成導通孔120的暴露。在一些實施例(未單獨示出)中,用於暴露出導通孔120的薄化製程包括CMP,且由於在CMP期間發生的下陷(dishing),導通孔120在晶圓110的背側處突出。在此種實施例中,可在基底112的背表面上可選地形成環繞導通孔120的突出部分的絕緣層(未單獨示出)。所述絕緣層可由例如氮化矽、氧化矽、氮氧化矽或類似材料等含矽絕緣體形成,且可藉由例如旋轉塗佈、CVD、電漿增強型CVD(plasma-enhanced CVD,PECVD)、高密度電漿CVD(high density plasma CVD,HDP-CVD)或類似製程等適合的沈積方法來形成所述絕緣層。在對基底112進行薄化之後,導通孔120的被暴露出的表面與絕緣層(若存在)或基底112的被暴露出的表面共面(在製程變化內),進而使得其彼此齊平,且在晶圓110的背側處被暴露出。
在圖6中,在導通孔120的被暴露出的表面及基底112的被暴露出的表面上形成多個凸塊下金屬(under bump metallurgy,UBM)146。作為在此實施例中形成凸塊下金屬146的實例,在導通孔120的被暴露出的表面及基底112的被暴露出的表面之上形成晶種層(seed layer)(未單獨示出)。在一些實施例中,晶種層是金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。可利用例如PVD或類似製程來形成晶種層。然後,在晶種層上形成光阻並對光阻進行圖案化。可藉由旋轉塗佈或類似製程來形成光阻,且可將光阻暴露於光以進行圖案化。光阻的圖案對應於凸塊下金屬146。所述圖案化會形成穿過光阻的多個開口以暴露出晶種層。然後,在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆(例如電鍍或無電鍍覆)或類似製程來形成導電材料。導電材料可包括金屬,例如銅、鈦、鎢、鋁或類似金屬。然後,移除光阻以及晶種層的上面未形成導電材料的部分。可藉由例如使用氧電漿或類似材料的可接受的灰化製程(ashing process)或剝離製程(stripping process)來移除光阻。一旦光阻被移除,便例如利用可接受的蝕刻製程來移除晶種層的被暴露出的部分。晶種層的其餘部分以及導電材料形成凸塊下金屬146。
此外,在凸塊下金屬146上形成多個導電連接件148。導電連接件148可為球柵陣列(ball grid array,BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊或類似元件。導電連接件148可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中,藉由最初透過蒸鍍、電鍍、印刷、焊料轉移、植球或類似製程形成焊料層來形成導電連接件148。一旦已在所述結構上形成焊料層,便可實行回焊,以便將材料造型呈所期望的凸塊形狀。在另一實施例中,導電連接件148包括藉由濺鍍(sputtering)、印刷、電鍍、無電鍍覆、CVD或類似製程而形成的金屬柱(例如銅柱)。金屬柱可不含焊料,且可具有實質上垂直的側壁。在一些實施例中,在金屬柱的頂部上形成金屬頂蓋層(metal cap layer)。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可藉由鍍覆製程來形成金屬頂蓋層。
在圖7中,沿封裝組件210的背側表面形成背側金屬(back-side metal)212。背側金屬212由一或多個層形成。背側金屬212可包括每一層具有不同組成物及功能性的多個層,例如黏合層(adhesion layer)、擴散阻擋層(diffusion blocking layer)及抗氧化層(anti-oxidation layer)。在一些實施例中,所述層中的至少一者由具有高導熱率(thermal conductivity)的材料形成。背側金屬212的所述一或多個層可由可藉由PVD製程(例如濺鍍或蒸鍍)、鍍覆製程(例如無電鍍覆或電鍍)、印刷製程(例如噴墨印刷)或類似製程來共形地形成的金屬或金屬氮化物(例如鋁、鈦、氮化鈦、鎳、鎳釩、銀、金、銅、其組合或類似材料)形成。隨後將對背側金屬212進行單體化,以使得每一封裝組件210包括背側金屬212的一部分。
儘管背側金屬212被示出為在導電連接件148之後形成,然而在一些實施例中,背側金屬212可在導電連接件148之前形成。
此外,藉由沿例如位於封裝區100A周圍的切割道區(scribe line region)進行剖切來實行單體化製程。單體化製程可包括鋸切(sawing)、切割(dicing)或類似製程。舉例而言,單體化製程可包括對包封體136、內連線結構114及基底112進行鋸切。單體化製程自相鄰的封裝區單體化出封裝區100A。所得的經單體化的封裝組件210來自封裝區100A。單體化製程自晶圓110的經單體化部分形成中介層102。作為單體化製程的結果,中介層102的外側壁、背側金屬212的外側壁及包封體136的外側壁在側向上相連(在製程變化內)。
圖8、圖9A、圖9B、圖10、圖11、圖12、圖13、圖14示出實施例封裝體的製造中的各種附加步驟。將會將包括散熱結構的封裝組件210貼合至封裝基底220(參見圖13),從而完成積體電路封裝體200的形成。示出單一的封裝組件210、單一的封裝基底220及單一的積體電路封裝體200。應理解,可同時處理多個封裝組件以形成多個積體電路封裝體200。
在圖8中,使用導電連接件148將封裝組件210貼合至封裝基底220。封裝基底220包括基底芯體(substrate core)222,基底芯體222可由例如矽、鍺、金剛石或類似材料等半導體材料製成。作為另外一種選擇,亦可使用化合物材料(例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷砷化鎵、磷化鎵銦、其組合或類似材料)。另外,基底芯體222可為SOI基底。一般而言,SOI基底包括由半導體材料(例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon-germanium on insulator,SGOI)或其組合)形成的層。在另一實施例中,基底芯體222是絕緣芯體(例如玻璃纖維加強型樹脂芯體)。一種實例性芯體材料是玻璃纖維樹脂(例如弗朗克功能調節劑4(Frankel’s function regulator-4,FR4))。芯體材料的替代品包括雙馬來醯亞胺-三嗪(bismaleimide-triazine,BT)樹脂,或者作為另外一種選擇包括其他印刷電路板(printed circuit board,PCB)材料或膜。可對基底芯體222使用例如味之素構成膜(Ajinomoto build-up film,ABF)等構成膜或者其他疊層體。
基底芯體222可包括主動裝置及被動裝置(未單獨示出)。可使用例如電晶體、電容器、電阻器、其組合及類似裝置等裝置來產生所述系統的設計的結構要求及功能要求。可使用任何適合的方法來形成所述裝置。
基底芯體222亦可包括多個金屬化層及多個通孔以及位於金屬化層及通孔之上的多個接合接墊(bond pad)224。可在主動裝置及被動裝置之上形成金屬化層,並將金屬化層設計成對各種裝置進行連接以形成功能電路系統。金屬化層可由介電材料(例如,低介電常數(low-k)介電材料)與導電材料(例如,銅)的交替層形成,其中通孔對由導電材料形成的層進行內連,且可藉由任何適合的製程(例如,沈積、鑲嵌或類似製程)形成。在一些實施例中,基底芯體222實質上不具有主動裝置及被動裝置。
對導電連接件148進行回焊以將凸塊下金屬146貼合至接合接墊224。導電連接件148將包括內連線結構114的封裝組件210連接至包括基底芯體222的金屬化層的封裝基底220。因此,封裝基底220電性連接至積體電路晶粒50。在一些實施例中,可在將多個被動裝置(例如,表面安裝裝置(surface mount device,SMD),未單獨示出)安裝於封裝基底220上之前將所述被動裝置貼合至封裝組件210(例如,接合至凸塊下金屬146)。在此種實施例中,被動裝置可與導電連接件148接合至封裝組件210的同一表面。在一些實施例中,可將多個被動裝置226(例如,SMD)貼合至封裝基底220,例如,貼合至接合接墊224。
在一些實施例中,在封裝組件210與封裝基底220之間形成環繞導電連接件148的底部填充劑228。可在貼合封裝組件210之後藉由毛細流動製程來形成底部填充劑228,或者可在貼合封裝組件210之前藉由任何適合的沈積方法來形成底部填充劑228。底部填充劑228可為自封裝基底220延伸至基底112的連續材料。
儘管未示出,封裝基底220可具有多個導電連接件,所述導電連接件形成於封裝基底220的與封裝組件210相對的一側(圖8中的底側)上的多個接合接墊上。
在圖9A及圖9B中,利用焊劑(flux)214來對背側金屬212進行塗佈。在一些實施例中,焊劑214是免清潔焊劑(no-clean flux)。可將焊劑214噴射至背側金屬212上。如圖9B所示平面圖中所示,焊劑214實質上覆蓋背側金屬212(在製程變化內)。在另一實施例中,焊劑214不實質上覆蓋背側金屬212。
在圖10中,使用例如拾取及放置工具將熱介面材料(thermal interface material,TIM)232放置於封裝組件210上。在一些實施例中,將熱介面材料232形成於單獨的結構(例如,晶圓或載體)上,且然後放置於封裝組件210上。熱介面材料232包含銦、銀、錫、類似材料或其合金。熱介面材料232可具有處於10微米至1000微米範圍內(例如100微米)的厚度T
1。在一些實施例中,熱介面材料232厚於背側金屬212。在一些實施例中,熱介面材料232具有與封裝組件210相同的寬度。在一些實施例中,熱介面材料232可具有與封裝組件210相同的面積(在平面圖中)。在其他實施例中,熱介面材料232及封裝組件210的寬度及面積可不同(參見例如圖15)。
在圖11中,利用焊劑234對熱介面材料232進行塗佈。在一些實施例中,焊劑234是免清潔焊劑。可將焊劑234噴射至熱介面材料232上。相似於焊劑214,焊劑234實質上覆蓋熱介面材料232(在製程變化內)。在另一實施例中,焊劑234不實質上覆蓋熱介面材料232。
在圖12A及圖12B中,在封裝基底220上形成黏合劑(adhesive)216及保持結構(retaining structure)218。黏合劑216用於隨後將蓋(lid)230(參見圖13)黏合至封裝基底220。保持結構218用於保持熱介面材料232的任何隨後的滲出或回流,以防止熱介面材料232到達例如被動裝置226。黏合劑216可為熱介面材料(TIM)、晶粒貼合膜(die attach film,DAF)或類似材料,且可分配於封裝基底上。舉例而言,黏合劑216可為具有聚合材料及填料的凝膠(gel)。凝膠的聚合材料可為PI、PBO、環氧樹脂系(epoxy-based)聚合物、氧化矽系(silica-based)聚合物、丙烯酸系(acrylic-based)聚合物、類似材料或其組合。凝膠的填料可包括鋁、銅、錫、氮化硼、類似材料或其組合。
在一些實施例中,保持結構218可與黏合劑216同時形成且可由與黏合劑216相同的材料形成。在一些實施例中,保持結構218可由不同於黏合劑216的材料形成。可將保持結構218分配於封裝基底220、底部填充劑228及/或封裝組件210上。在一些實施例中,將保持結構218形成於封裝組件210的側壁上以及熱介面材料232的側壁及頂表面上。在一些實施例中,將保持結構218與封裝組件210(參見例如圖16至圖19)間隔開。可將保持結構218形成於底部填充劑228上。在一些實施例中,保持結構218在封裝組件210外部完全地覆蓋底部填充劑228,而在其他實施例中,保持結構218僅部分地覆蓋底部填充劑228。
在一些實施例中,將保持結構218形成為具有較熱介面材料232的頂表面高的頂表面,而在其他實施例中,將保持結構218的頂表面形成為低於熱介面材料232的頂表面。如見於圖12B中,保持結構218可環繞封裝組件210,且可沿封裝基底220的邊緣形成黏合劑216。
儘管保持結構218被示出為具有平坦且平行的側壁,然而本揭露不限於保持結構218的所示形狀。舉例而言,保持結構218可具有彎曲的側壁、彎折的側壁、傾斜的側壁及/或不平行的側壁。
在圖13中,將具有可選的背側金屬236的蓋230貼合至熱介面材料232及封裝基底220。蓋230可為導熱蓋(thermal lid)、散熱器(heatsink)或類似元件。在所示實施例中,蓋230是亦貼合至封裝基底220的導熱蓋。導熱蓋的底部中具有凹陷,以使得導熱蓋可覆蓋封裝組件210及熱介面材料232。在蓋230是導熱蓋的一些實施例中,導熱蓋亦可覆蓋被動裝置226。如圖13中所示,保持結構218可實體地接觸蓋230。保持結構218將防止熱介面材料232的材料隨後滲出至封裝基底220上及/或被動裝置226上。
蓋230可由例如金屬(例如銅、鎳、銦、鋼、鐵或類似金屬)等具有高導熱率的材料形成。在一些實施例中,蓋230由銅、鎳及銦形成。蓋230保護封裝組件210並形成熱路徑(thermal pathway)以自封裝組件210的各種組件(例如,積體電路晶粒50)傳導熱量。蓋230藉由熱介面材料232及可選的背側金屬236熱耦合至封裝組件210的背側表面,例如背側金屬212的背側表面。背側金屬236可相似於以上闡述的背側金屬212,且本文中不再對其予以贅述。可在貼合蓋230之前,在焊劑234上或在蓋230上形成背側金屬236。
在一些實施例中,在多步驟製程中貼合蓋230並接合熱介面材料232。在多步驟製程之後,熱介面材料232可在被放置於封裝組件210上之後具有小於厚度T
1的厚度T
2。在第一製程步驟中,利用熱夾持製程將蓋230貼合至熱介面材料232及封裝基底220。在一些實施例中,熱夾持製程涉及在向蓋230及/或封裝基底220施加力的同時對所述結構進行加熱。在熱夾持製程中,加熱溫度小於熱介面材料232的金屬的熔化溫度。舉例而言,若熱介面材料232由熔化溫度為156.6℃的銦製成,則熱夾持製程的加熱溫度將保持在156.6℃以下。
在第二製程步驟中,將熱介面材料232與背側金屬212/236及蓋230接合或連接。第二製程步驟涉及將所述結構加熱至較熱介面材料232的金屬的熔化溫度大的溫度。舉例而言,若熱介面材料232由熔化溫度為156.6℃的銦製成,則熱夾持製程的加熱溫度將達到156.6℃以上。在一些實施例中,此第二製程步驟亦涉及熱夾持製程,包括在向蓋230及/或封裝基底220施加力的同時對所述結構進行加熱。在一些實施例中,貼合蓋230並接合熱介面材料232的多步驟製程的所有步驟在同一處理腔室中實行,而不會破壞所述腔室的環境(ambient)。
由於具有保持結構218,因此熱介面材料232的金屬(例如,銦)在封裝體的熱夾持、回焊或正常操作期間的任何後續滲出或回流受到遏制。此種遏制會防止金屬溢出而使封裝組件短路,且會防止在熱介面材料232中形成空隙,此可改善封裝體的可靠性及效能。
亦可包括其他特徵及製程。舉例而言,可包括測試結構以幫助對三維(three-dimensional,3D)封裝體或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或基底上形成的測試接墊(test pad),以便能夠對3D封裝體或3DIC進行測試、對探針及/或探針卡(probe card)進行使用以及進行類似操作。可對中間結構以及最終結構實行驗證測試。另外,可將本文中所揭露的結構及方法與包含對已知良好晶粒進行中間驗證的測試方法結合使用,以提高良率(yield)並降低成本。
圖14示出對封裝體200進行夾持固化(clamp curing)的可選步驟。在一些實施例中,夾持固化製程可代替圖13中的上述多步驟製程的第二步驟。如圖14中所示,將封裝體200放置於夾具(clamp)250內,且可對封裝體200施加熱量。在一些實施例中,夾持固化製程涉及將所述結構加熱至較熱介面材料232的金屬的熔化溫度大的溫度。舉例而言,若熱介面材料232由熔化溫度為156.6℃的銦製成,則熱夾持製程的加熱溫度將達到156.6℃以上。在一些實施例中,此第二製程步驟亦涉及熱夾持製程,包括在向蓋230及/或封裝基底220施加力的同時對所述結構進行加熱。
圖15示出根據一些其他實施例的積體電路封裝體200的剖視圖。除了熱介面材料232的寬度小於封裝組件210且保持結構218延伸以上覆於包封體136及背側金屬212的頂表面之上以外,此實施例相似於圖1至圖14中闡述的實施例。在一些實施例中,熱介面材料232可被形成為具有較封裝組件210的寬度W
1小的寬度W
2。
圖16至圖19是根據一些其他實施例的積體電路封裝體200的製造的中間階段的示意圖。除了保持結構218不接觸封裝組件210但與封裝組件210間隔開以外,此實施例相似於針對圖1至圖14闡述的實施例。在貼合蓋230之後,保持結構218與封裝組件210之間的空間可形成空隙。此空隙可容納熱介面材料232的經回流的金屬。
圖16處於與圖11相似的處理點,且本文中不再對達成此處理階段予以贅述。
在圖17A及圖17B中,在封裝基底220上形成保持結構218及黏合劑216。保持結構218及黏合劑216的材料及製程可相似於以上在圖12A及圖12B中闡述的材料及製程。
在此實施例中,保持結構218與封裝組件210間隔開。儘管保持結構218被示出為具有較熱介面材料232的頂表面高的頂表面,然而在其他實施例中,保持結構218的頂表面可低於熱介面材料232的頂表面。相似於圖12B的闡述,在圖17B中,保持結構218可環繞封裝組件210,且可沿封裝基底220的邊緣形成黏合劑216。
在圖18中,將具有可選的背側金屬236的蓋230貼合至熱介面材料232及封裝基底220。保持結構218在封裝組件210與保持結構218之間形成空隙238。如圖18中所示,保持結構218可實體地接觸蓋230,進而使得蓋230形成空隙238的表面。在熱介面材料232的金屬熔化之後,由保持結構218形成的空隙238將容納熱介面材料232的材料(例如,參見圖19)。
在圖19中,圖18的結構經歷以上在圖13中闡述的多步驟貼合及接合製程,從而導致熱介面材料232的溢出(overflow)232’至封裝組件210及底部填充劑228的各側上以及封裝基底220上。儘管圖19示出溢出232’實質上填充空隙238,然而在一些實施例中,空隙238僅被部分地填充。
藉由具有由保持結構218形成的空隙238,熱介面材料232的金屬(例如,銦)在封裝體的熱夾持、回焊或正常操作期間的任何後續滲出或回流受到遏制。此種遏制會防止金屬溢出而使封裝組件短路,且會防止在熱介面材料232中形成空隙,此可改善封裝體的可靠性及效能。
實施例可達成優點。在一些實施例中,在封裝組件貼合至封裝基底之後,將散熱結構貼合至封裝組件。可在封裝基底上相鄰於封裝組件及散熱結構來形成保持結構(例如,保持壁)。然後,可將蓋貼合於散熱結構及保持結構之上,隨後進行熱夾持及/或回焊製程以對蓋及/或散熱結構進行貼合。由於具有保持結構,因此散熱結構的金屬(例如,銦)在封裝的熱夾持、回焊或正常操作期間的任何後續滲出或回流受到遏制。此種遏制會防止金屬溢出而使封裝組件短路,且會防止在散熱結構中形成空隙,此可改善封裝體的可靠性及效能。
在實施例中,一種裝置包括封裝組件,所述封裝組件包括積體電路晶粒及連接至積體電路晶粒的多個導電連接件,所述多個導電連接件設置於封裝組件的第一側處。所述裝置亦包括位於封裝組件的第二側上的金屬層,第二側與第一側相對。所述裝置亦包括位於金屬層上的熱介面材料。所述裝置亦包括位於熱介面材料上的蓋。所述裝置亦包括位於封裝組件及熱介面材料的側壁上的保持結構。所述裝置亦包括連接至導電連接件的封裝基底,蓋黏合至封裝基底。
實施例可包括以下特徵中的一或多者。在所述裝置中,保持結構在封裝組件的頂表面之上延伸。熱介面材料由銦製成。保持結構實體地接觸蓋。熱介面材料厚於背側金屬層。所述裝置更包括位於封裝基底與封裝組件之間的底部填充劑,保持結構實體地接觸底部填充劑。封裝組件是晶圓上晶片封裝組件。保持結構包含聚合材料及填料材料。所述裝置更包括將蓋黏合至封裝基底的黏合劑,所述黏合劑與保持結構具有相同的材料組成。
在實施例中,一種方法包括將積體電路晶粒封裝於晶圓的封裝區中。所述方法亦包括在積體電路晶粒的背側上沈積背側金屬層。所述方法亦包括自晶圓單體化出封裝區以形成封裝組件。所述方法亦包括在單體化出封裝區之後,將封裝組件連接至封裝基底。所述方法亦包括在背側金屬層上放置熱介面材料。所述方法亦包括相鄰於封裝組件及熱介面材料來分配保持結構。所述方法亦包括將蓋貼合至封裝基底,蓋耦合至熱介面材料。所述方法亦包括實行接合製程以將熱介面材料接合至背側金屬層及蓋,接合製程是在大於熱介面材料的熔點的溫度下實行。
實施例可包括以下特徵中的一或多者。在所述方法中,保持結構實體地接觸封裝組件。保持結構與封裝組件間隔開。在實行接合製程之後,熱介面材料的溢出部分在封裝組件的側壁上延伸。在實行接合製程之後,熱介面材料的溢出部分在底部填充劑的側壁上延伸。保持結構實體地接觸蓋。所述方法更包括在背側金屬層上放置熱介面材料之後且在將蓋貼合至封裝基底之前,在封裝基底的頂表面上分配黏合層,所述黏合層將蓋黏合至封裝基底。黏合層與保持結構具有相同的材料組成。
在實施例中,一種方法包括在晶圓的封裝區中將多個積體電路晶粒接合至所述晶圓。所述方法亦包括利用模製化合物對所述多個積體電路晶粒進行包封。所述方法亦包括在模製化合物以及所述多個積體電路晶粒的背側上形成背側金屬層。所述方法亦包括自晶圓單體化出封裝區以形成封裝組件。所述方法亦包括將封裝組件接合至封裝基底。所述方法亦包括在經接合的封裝組件的積體電路晶粒的背側上沈積第一焊劑。所述方法亦包括將熱介面材料貼合至第一焊劑,熱介面材料包含銦。所述方法亦包括相鄰於封裝組件及熱介面材料來形成保持結構。所述方法亦包括將蓋貼合至封裝基底,熱介面材料及保持結構耦合至蓋。
實施例可包括以下特徵中的一或多者。所述方法更包括實行接合製程以將熱介面材料接合至背側金屬層及蓋,接合製程是在大於熱介面材料的熔點的溫度下實行,其中在實行接合製程之後,熱介面材料的溢出部分在封裝組件的側壁上延伸。保持結構實體地接觸封裝組件。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各態樣。熟習此項技術者應理解,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,此種等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
50:積體電路晶粒
50A:第一積體電路晶粒
50B:第二積體電路晶粒
50F:前側
52:半導體基底
54、114:內連線結構
56、116:晶粒連接件
58、118:介電層
100A:封裝區
102:中介層
110:晶圓
112:基底
120:導通孔
132、148:導電連接件
134、228:底部填充劑
136:包封體
146:凸塊下金屬
200:積體電路封裝體/封裝體
210:封裝組件
212、236:背側金屬
214、234:焊劑
216:黏合劑
218:保持結構
220:封裝基底
222:基底芯體
224:接合接墊
226:被動裝置
230:蓋
232:熱介面材料
232’:溢出
238:空隙
250:夾具
T
1、T
2:厚度
W
1、W
2:寬度
X、Z:方向
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1是積體電路晶粒的剖視圖。
圖2至圖14是根據一些實施例的積體電路封裝體的製造中的中間階段的示意圖。
圖15是根據一些實施例的積體電路封裝體的剖視圖。
圖16至圖19是根據一些實施例的積體電路封裝體的製造中的中間階段的示意圖。
56、116:晶粒連接件
114:內連線結構
118:介電層
132、148:導電連接件
134、228:底部填充劑
136:包封體
146:凸塊下金屬
200:積體電路封裝體/封裝體
210:封裝組件
212、236:背側金屬
214、234:焊劑
216:黏合劑
218:保持結構
220:封裝基底
222:基底芯體
224:接合接墊
226:被動裝置
230:蓋
232:熱介面材料
W1、W2:寬度
X、Z:方向
Claims (20)
- 一種裝置,包括: 封裝組件,包括積體電路晶粒及連接至所述積體電路晶粒的多個導電連接件,所述多個導電連接件設置於所述封裝組件的第一側處; 金屬層,位於所述封裝組件的第二側上,所述第二側與所述第一側相對; 熱介面材料,位於所述金屬層上; 蓋,位於所述熱介面材料上; 保持結構,位於所述封裝組件及所述熱介面材料的側壁上;以及 封裝基底,連接至所述多個導電連接件,所述蓋黏合至所述封裝基底。
- 如請求項1所述的裝置,其中所述保持結構在所述封裝組件的頂表面之上延伸。
- 如請求項1所述的裝置,其中所述熱介面材料由銦製成。
- 如請求項1所述的裝置,其中所述保持結構實體地接觸所述蓋。
- 如請求項1所述的裝置,其中所述熱介面材料厚於所述金屬層。
- 如請求項1所述的裝置,更包括: 底部填充劑,位於所述封裝基底與所述封裝組件之間,所述保持結構實體地接觸所述底部填充劑。
- 如請求項1所述的裝置,其中所述封裝組件是晶圓上晶片封裝組件。
- 如請求項1所述的裝置,其中所述保持結構包含聚合材料及填料材料。
- 如請求項1所述的裝置,更包括: 黏合劑,將所述蓋黏合至所述封裝基底,所述黏合劑與所述保持結構具有相同的材料組成。
- 一種方法,包括: 將積體電路晶粒封裝於晶圓的封裝區中; 在所述積體電路晶粒的背側上沈積背側金屬層; 自所述晶圓單體化出所述封裝區以形成封裝組件; 在單體化出所述封裝區之後,將所述封裝組件連接至封裝基底; 在所述背側金屬層上放置熱介面材料; 相鄰於所述封裝組件及所述熱介面材料來分配保持結構; 將蓋貼合至所述封裝基底,所述蓋耦合至所述熱介面材料;以及 實行接合製程以將所述熱介面材料接合至所述背側金屬層及所述蓋,所述接合製程是在大於所述熱介面材料的熔點的溫度下實行。
- 如請求項10所述的方法,其中所述保持結構實體地接觸所述封裝組件。
- 如請求項10所述的方法,其中所述保持結構與所述封裝組件間隔開。
- 如請求項12所述的方法,其中在實行所述接合製程之後,所述熱介面材料的溢出部分在所述封裝組件的側壁上延伸。
- 如請求項12所述的方法,更包括: 在所述封裝基底與所述封裝組件之間形成底部填充劑,其中在實行所述接合製程之後,所述熱介面材料的溢出部分在所述底部填充劑的側壁上延伸。
- 如請求項10所述的方法,其中所述保持結構實體地接觸所述蓋。
- 如請求項10所述的方法,更包括: 在所述背側金屬層上放置所述熱介面材料之後且在將所述蓋貼合至所述封裝基底之前,在所述封裝基底的頂表面上分配黏合層,所述黏合層將所述蓋黏合至所述封裝基底。
- 如請求項16所述的方法,其中所述黏合層與所述保持結構具有相同的材料組成。
- 一種方法,包括: 在晶圓的封裝區中將多個積體電路晶粒接合至所述晶圓; 利用模製化合物對所述多個積體電路晶粒進行包封; 在所述模製化合物以及所述多個積體電路晶粒的背側上形成背側金屬層; 自所述晶圓單體化出所述封裝區以形成封裝組件; 將所述封裝組件接合至封裝基底; 在經接合的所述封裝組件的所述多個積體電路晶粒的所述背側上沈積第一焊劑; 將熱介面材料貼合至所述第一焊劑,所述熱介面材料包含銦; 相鄰於所述封裝組件及所述熱介面材料來形成保持結構;以及 將蓋貼合至所述封裝基底,所述熱介面材料及所述保持結構耦合至所述蓋。
- 如請求項18所述的方法,更包括: 實行接合製程以將所述熱介面材料接合至所述背側金屬層及所述蓋,所述接合製程是在大於所述熱介面材料的熔點的溫度下實行,其中在實行所述接合製程之後,所述熱介面材料的溢出部分在所述封裝組件的側壁上延伸。
- 如請求項18所述的方法,其中所述保持結構實體地接觸所述封裝組件。
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US17/891,634 US20230378017A1 (en) | 2022-05-17 | 2022-08-19 | Integrated circuit packages and methods of forming the same |
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