SG11201901194SA - Wafer-level package with enhanced performance - Google Patents

Wafer-level package with enhanced performance

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Publication number
SG11201901194SA
SG11201901194SA SG11201901194SA SG11201901194SA SG11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA
Authority
SG
Singapore
Prior art keywords
die
thinned
wafer
mold compound
international
Prior art date
Application number
SG11201901194SA
Inventor
Julio Costa
Jan Vandemeer
Jonathan Hammond
Merrill Hatcher
Jon Chadwick
Original Assignee
Qorvo Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US201662374439P priority Critical
Priority to US201662374332P priority
Priority to US201662374318P priority
Application filed by Qorvo Us Inc filed Critical Qorvo Us Inc
Priority to PCT/US2017/046758 priority patent/WO2018031995A1/en
Publication of SG11201901194SA publication Critical patent/SG11201901194SA/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
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    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
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    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
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    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01L2924/1901Structure
    • H01L2924/19011Structure including integrated passive components
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    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

APPLYA THIRD DIELECTRIC LAYER AT THE BOTTOM SURFACE OF THE MULTILAYER REDISTRUBUTION STRUCTURE THIN DOWN THE FIRST MOLD COMPOUND TO EXPOSE THE SUBSTRATES OF THE DIE AND THE MEMS DIE REMOVE SUBSTANRALY THE SUBSTRATES OF THE SOI DIE AND THE MEMS DIE TO PROVIDE AN ETCHED PRECUSOR PACKAGE, WHICH INCLUDES A THINNED SOI DIE WITH A FIRST CAVITY AND A THINNED MEMS DIE WITH A SECOND CAVITY ATTACH THE ETCHED PRECUSOR PACKAGE TO A RIGID CARRIER MAN ADHESIVE MATERIAL. WHERE THE BOTTOM SURFACE OF THE THIRD DIELECTRIC LAYER IS IN CONTACT WITH THE ADHESIVE MATERIAL APPLY A SECOND MOLD COMPOUND TO SUBSTANTIALLY FILL THE FIRST AND SECOND CAVITIES (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 15 February 2018 (15.02.2018) WIP0 I PCT olimion °nolo III 01110l (10) International Publication Number WO 2018/031995 Al (51) International Patent Classification: H01L 23/31 (2006.01) H01L 21/60 (2006.01) H01L 21/56 (2006.01) (21) International Application Number: PCT/US2017/046758 (22) International Filing Date: 14 August 2017 (14.08.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/374,318 12 August 2016 (12.08.2016) US 62/374,332 12 August 2016 (12.08.2016) US 62/374,439 12 August 2016 (12.08.2016) US (71) Applicant: QORVO US, INC. [US/US]; 7628 Thomdike Road, Greensboro, North Carolina 27409 (US). (72) Inventors: COSTA, Julio, C.; 6601 Ashton Park Drive, Oak Ridge, North Carolina 27310 (US). VANDEMEER, Jan, Edward; 279 Weatherfield Lane, Kemersville, North Carolina 27284 (US). HAMMOND, Jonathan, Hale; 5808 Autumn Gate Drive, Oak Ridge, North Carolina 27310 (US). HATCHER, Merrill, Albert, Jr.; 5607 Old Fox Trail, Greensboro, North Carolina 27407 (US). CHAD- WICK, Jon; 1907 Efland Drive, Greensboro, North Caroli- na 27408 (US). (74) Agent: WITHROW, Benjamin, S.; WITHROW & TER- RANOVA, P.L.L.C., 106 Pinedale Springs Way, Cary, North Carolina 27511 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, (54) Title: WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE (57) : The present disclosure relates to a packaging process to en- 00 Nance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die 102 (14) having a first device layer (20), a multilayer redistribution structure (52), a first mold compound (42), and a second mold compound (74). The multi- 104 layer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects con- necting the first device layer to the package contacts. The first mold com- 1 pound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to de- fine a cavity (66) within the first mold compound and over the first thinned 1613 die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die. 110 I 112 I 116 118 CURE THE SECOND MOLD COMPOUND PLANARIZE A TOP SURFACE OF THE SECOND MOLD , XIMPOUND W O 20 18/03 1995 Al DETACH THE RIGID CARRIER FROM THE THIRD DIELECTRIC LAYER COMPLETE A WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE MARK. DICE. AND SINGULATE THE WAFER-LEVEL PACKAGE FIG. 9 [Continued on next page] WO 2018/031995 Al D ill TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: with international search report (Art. 21(3)) with amended claims (Art. 19(1))
SG11201901194SA 2016-08-12 2017-08-14 Wafer-level package with enhanced performance SG11201901194SA (en)

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Application Number Priority Date Filing Date Title
US201662374439P true 2016-08-12 2016-08-12
US201662374332P true 2016-08-12 2016-08-12
US201662374318P true 2016-08-12 2016-08-12
PCT/US2017/046758 WO2018031995A1 (en) 2016-08-12 2017-08-14 Wafer-level package with enhanced performance

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US (2) US10109550B2 (en)
EP (1) EP3497717A1 (en)
JP (1) JP2019525488A (en)
CN (1) CN109844938A (en)
SG (1) SG11201901194SA (en)
WO (1) WO2018031995A1 (en)

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US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
JP2019525487A (en) * 2016-08-12 2019-09-05 コーボ ユーエス,インコーポレイティド Wafer level package with improved performance
EP3497717A1 (en) 2016-08-12 2019-06-19 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies

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US10804179B2 (en) 2020-10-13
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WO2018031995A1 (en) 2018-02-15
US20190057922A1 (en) 2019-02-21
JP2019525488A (en) 2019-09-05
EP3497717A1 (en) 2019-06-19
US20180047653A1 (en) 2018-02-15

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