TW201917859A - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

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Publication number
TW201917859A
TW201917859A TW107114013A TW107114013A TW201917859A TW 201917859 A TW201917859 A TW 201917859A TW 107114013 A TW107114013 A TW 107114013A TW 107114013 A TW107114013 A TW 107114013A TW 201917859 A TW201917859 A TW 201917859A
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Taiwan
Prior art keywords
layer
interconnect structure
substrate
optical
semiconductor package
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TW107114013A
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English (en)
Inventor
王垂堂
張智傑
廖祐廣
夏興國
張智援
謝政憲
余振華
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台灣積體電路製造股份有限公司
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Publication of TW201917859A publication Critical patent/TW201917859A/zh

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Abstract

根據本發明的一些實施例，一種半導體封裝包含：一互連結構，其具有一第一表面及與該第一表面相對之一第二表面；至少一個光學晶片，其在該互連結構之該第一表面上方且電耦合至該互連結構；一絕緣層，其接觸該互連結構之該第二表面；及一模塑料，其在該互連結構之該第一表面上方。該絕緣層包含面向該互連結構之該第二表面之一第三表面及與該第三表面相對之一第四表面。藉由該模塑料覆蓋該光學晶片之至少一邊緣。

Description

半導體封裝及其製作方法
本發明實施例係有關半導體封裝及其製作方法。
先進電子技術之需求需要使電子產品更輕、更薄、更快且更智慧，同時使其等更友好、強大、可靠、穩健及便宜。因此，電子封裝之趨勢係開發高度整合之封裝結構。多晶片模組(MCM)封裝可整合具有不同功能之晶片，諸如微處理器、記憶體、邏輯元件、光學IC及電容器，且取代將個別封裝放置於一個電路板上之先前技術。因此，減小封裝大小且改良記憶體裝置之可靠性。
根據本發明的一實施例，一種半導體封裝包括：一互連結構，其包括一第一表面及與該第一表面相對之一第二表面；至少一個光學晶片，其在該互連結構之該第一表面上方且電耦合至該互連結構；一絕緣層，其接觸該互連結構之該第二表面，其中該絕緣層包括面向該互連結構之該第二表面之一第三表面及與該第三表面相對之一第四表面；及一模塑料，其在該互連結構之該第一表面上方，其中藉由該模塑料覆蓋該光學晶片之至少一邊緣。 根據本發明的一實施例，一種半導體封裝包括：一互連結構，其包括一第一表面及與該第一表面相對之一第二表面；一絕緣層，其接觸該互連結構之該第二表面，其中該絕緣層包括面向該互連結構之該第二表面之一第三表面及與該第三表面相對之一第四表面；及至少一個光學晶片，其在該絕緣層之該第四表面上方且電耦合至該互連結構；及一模塑料，其在該互連結構之該第一表面上方。 根據本發明的一實施例，一種用於製作一半導體封裝之方法包括：提供包括一第一側及與該第一側相對之一第二側之一基板，該基板包括該第一側處之至少一個絕緣層及該絕緣層上方之一互連結構；自該第二側薄化該基板；在該基板上方放置至少一個光學晶片；在該互連結構上方放置一模塑料；及在該第二側處該基板上方形成複數個導電層，其中該等導電層電耦合至該互連結構。
下列揭露提供用於實施所提供標的物之不同構件之許多不同實施例或實例。在下文描述元件及配置之特定實例以簡化本揭露。當然，此等僅為實例且並不意欲為限制性的。例如，在以下描述中，一第一構件形成在一第二構件上方或上可包含其中第一構件及第二構件經形成直接接觸之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件及第二構件可未直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係用於簡單及清楚之目的，且本身並不指示所論述之各種實施例及/或組態之間的一關係。 此外，為便於描述，諸如「在…下方」、「在…下」、「下」、「在…上方」、「上」、「在…上」及類似物之空間相對術語可在本文中用於易於描述一個元件或構件與圖中繪示之另一(些)元件或構件之關係。除圖中描繪之定向外，空間相對術語亦意欲涵蓋在使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或呈其他定向)且因此同樣可解釋本文中使用之空間相對描述符。 如在本文中使用，諸如「第一」、「第二」及「第三」之術語描述各種元件、組件、區域、層及/或區段，但此等元件、組件、區域、層及/或區段不應受限於此等術語。此等術語僅可用於區分一個元件、組件、區域、層或區段與另一元件、組件、區域、層或區段。諸如「第一」、「第二」及「第三」之術語在本文中使用時並不暗示一序列或順序，除非由背景內容明確指示。 如在本文中使用，術語「大約」、「實質上」、「實質」及「約」用於描述及說明小變化。當結合一事件或狀況使用時，該等術語可係指其中確切地發生該事件或狀況之例項以及其中非常近似地發生該事件或狀況之例項。例如，當結合一數值使用時，該等術語可係指小於或等於該數值之±10%之一變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%。例如，若兩個數值之間的差小於或等於該等值之一平均值之±10%，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%，則該等值可被視為「實質上」相同或相等。例如，「實質上」平行可係指相對於0°小於或等於±10°之一角度變化範圍，諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°。例如，「實質上」垂直可係指相對於90°小於或等於±10°之一角度變化範圍，諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°。 亦可包含其他構件及製程。例如，可包含測試結構以協助3D封裝或3DIC裝置之驗證測試。測試結構可包含例如形成於一重佈層中或一基板上之測試墊，其允許測試3D封裝或3DIC、使用探針及/或探針卡及類似物。可對中間結構以及最終結構執行驗證測試。另外，本文中揭示之結構及方法可結合併入已知良好晶粒之中間驗證之測試方法使用以增大良率且降低成本。 在一項實施例中，矽光子收發器包含光電子收發器及光源，其等能夠將光學訊號垂直傳送至光子台之表面及自光子台之表面垂直傳送光學訊號，光子台通常包含一互連結構、一矽插入器及形成於插入器中之貫穿基板通路(本文中稱為TSV)。如在此項技術中已知，TSV (在矽基板/晶圓之情況中，其亦通常被稱為貫穿矽通路)係自一個側延伸塊體矽插入器之整個厚度至另一側之垂直電連接。然而，包含TSV之矽插入器經受高成本及較低處理能力，因為製作具有TSV之插入器係一複雜製程。此外，矽光子收發器經受歸因於長TSV訊號路徑之電損耗。另外，光學損耗作為易於傳播至插入器之底部處之塊體矽中之光而存在。 此外，發現諸如雷射晶片、耦合器及光纖之光學元件全部安裝於封裝之模塑料上。因此，需要嵌入模塑料中之一矽間隔件，藉此允許光通過。因此，封裝可經受歸因於此配置之增大光學路徑。更重要的是，光子封裝並非一平面封裝，其較不適於後續製作操作。 現將參考附圖描述本揭露之一或多個實施方案，其中相同參考數字用於指貫穿全文之相同元件，且其中所繪示結構不必按比例繪製。如在本文中使用，術語「晶粒」及「晶片」貫穿說明書可互換。 本文中使用之術語「晶圓」及「基板」包含具有一曝露表面之任何結構，根據本揭露將一層沉積於該曝露表面上例如以形成諸如一重佈層(RDL)之電路結構。術語基板被理解為包含半導體晶圓，但不限於此。術語基板亦用於指處理期間之半導體結構且可包含已製作於其上之其他層。 術語「圖案化」或「經圖案化」在本揭露中用於描述將一預定圖案形成於一表面上之一操作。圖案化操作包含各種步驟及製程且根據本揭露之構件而變化。在一些實施例中，一圖案化操作經調適以圖案化一現有膜或層。圖案化操作包含在現有膜或層上形成一遮罩且使用一蝕刻或其他移除製程移除未遮罩膜或層。遮罩係光阻劑或硬遮罩。在一些實施例中，圖案化操作經調適以在一表面上直接形成一圖案化層。圖案化操作包含：在表面上形成一光敏膜；進行一光微影製程及一顯影製程。剩餘光敏膜被保留且整合至半導體裝置中。 圖1係表示根據本揭露之一些實施例之用於製作一半導體封裝10之一方法之一流程圖。用於製作半導體封裝10之方法包含一操作102：提供包含一第一側及與第一側相對之一第二側之一基板，該基板包含第一側處之至少一個絕緣層及形成於絕緣層上方之一互連結構；一操作104：自第二側薄化基板；一操作106：在互連結構上方放置至少一個光學晶片；一操作108：在互連結構上方放置一模塑料；及一操作110：在該第二側處該基板上方形成複數個導電層，其中導電層電耦合至互連結構。將根據一或多項實施例進一步描述用於製作半導體封裝10之方法。圖2係表示根據本揭露之一些實施例之用於製作一半導體封裝11之一方法之一流程圖。用於製作半導體封裝11之方法包含一操作112：提供包含一第一側及與第一側相對之一第二側之一基板，該基板包含第一側處之至少一個絕緣層及形成於絕緣層上方之一互連結構；一操作114：自第二側薄化基板；一操作116：在互連結構上方放置一模塑料；一操作118：在該第二側處該基板上方形成複數個導電層，導電層經電耦合至互連結構；及一操作120：在該第二側處該基板上方放置至少一個光學晶片。將根據一或多項實施例進一步描述用於形成半導體封裝11之方法。 圖3係表示根據本揭露之一些實施例之用於製作一半導體封裝20之一方法之一流程圖。用於製作半導體封裝20之方法包含一操作202：提供包含一第一側及與第一側相對之一第二側之一基板，該基板包含第一側處之至少一個絕緣層及形成於絕緣層上方之一互連結構；一操作204：在互連結構上方放置至少一個光學晶片；一操作206：在互連結構上方放置一模塑料；一操作208：自第二側薄化基板；及一操作210：在該第二側處該基板上方形成複數個導電層，導電層經電耦合至互連結構。將根據一或多項實施例進一步描述用於製作半導體封裝20之方法。 圖4A至圖4M繪示在一些實施例中根據本揭露之態樣建構之各種製作階段之一半導體封裝30之剖面圖。 參考圖4A，根據操作102提供一基板300。基板300包含一第一側300a及與第一側300a相對之一第二側300b。在本揭露之一些實施例中，基板300可包含一矽基板，但是可在各種實施例中利用其他半導體基板，諸如矽鍺基板或III-V族化合物基板。在本揭露之一些實施例中，基板300包含一絕緣體上覆矽(SOI)基板。在本揭露之一些實施例中，基板300包含形成於第一側300a處之一絕緣體層304上之一半導體層306且半導體層306可包含例如但不限於矽。絕緣體層304可為例如埋藏氧化物(BOX)層或氧化矽層。將絕緣體層304設置於一塊體結構302 (通常矽或玻璃基板)上。亦可使用其他物質，諸如多層或梯度基板。在本揭露之一些實施例中，可執行各種操作以在半導體層306中形成諸如調變器、波導、偵測器、光柵及/或耦合器之光學裝置。因此，半導體層306可被稱為一光學裝置層306。換言之，光學裝置層306包含調變器、波導、偵測器、光柵或耦合器。在本揭露之一些實施例中，可視需要形成除光學裝置外之裝置。另外，可在絕緣體層304上方形成包含(若干)絕緣材料之一介電層308以提供保護且形成一平坦表面以供隨後操作。 仍參考圖4A，在基板300上方第一側300a處形成一互連結構320。因此，將光學裝置層306夾置於至少一個絕緣體層304與互連結構320之間。互連結構320包含一第一表面320a及與第一表面320a相對之一第二表面320b，且互連結構320之第二表面320b面向基板300及光學裝置層306中之介電層308。互連結構320可包含一或多個重佈層(RDL)，且RDL可包含具有形成於其中之導電線324之一介電層322之一層。可在一後段製程(BEOL)中形成RDL，但不限於此。介電層322可包含例如但不限於聚合物材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)及類似物，或可由普遍已知介電材料形成，諸如旋塗玻璃、氧化矽(SiO)、氮氧化矽(SiON)或由諸如旋塗之任何適合方法形成之類似物。導電線324可包含一金屬，諸如銅(Cu)、銀(Ag)、鋁(Al)、鎳(Ni)、其等之組合或類似物。互連結構320可經電耦合至光學裝置層306中之光學裝置或其他裝置。 參考圖4B及圖4C，接著翻轉基板300及互連結構320且透過一黏著材料331 (諸如膠帶、晶粒附著膜(DAF)或類似物)將其等附接至第一側300a處之一載體基板330。此後，根據操作104自第二側300b薄化基板300。一般言之，薄化可為例如但不限於蝕刻、研磨或平坦化操作(例如，化學機械拋光(CMP))。在本揭露之一些實施例中，藉由自第二側300b薄化基板300而移除基板300之塊體結構302。在本揭露之一些實施例中，可在基板300上第二側300b處保留塊體結構302且剩餘塊體結構302 (如在圖8中展示)包含小於約50微米(μm)之一厚度。在一些實施例中，介電層308及包含絕緣體層304及半導體層306之經薄化基板(具有或不具有塊體結構302)被稱為接觸第二表面320b之一絕緣層310，且絕緣層310包含小於約50 μm之一厚度。如在圖4C中展示，絕緣層310包含面向互連結構320之第二表面320b之一第三表面310a及與第三表面310a相對之一第四表面310b。 參考圖4D，接著自載體基板330卸離絕緣層310及互連結構320且透過另一黏著材料333 (諸如膠帶、DAF或類似物)將其等附接至第二側300b處之另一載體基板332，且接著移除載體基板330及黏著材料331。如在圖4D中展示，根據操作106在互連結構320之第一表面320a上方放置至少一個光學晶片340。在本揭露之一些實施例中，光學晶片340可包含具有一光源(諸如例如但不限於一半導體雷射或一發光二極體)之一總成。光學晶片340透過導電結構342電耦合至互連結構320。另外，可使用一底膠填充344囊封導電結構342以進行保護。在一些實施例中，導電結構342包含具有低於10 μm (例如3 μm至5 μm)之一凸塊高度之一微凸塊。底膠材料344可包含例如但不限於光學環氧樹脂。此外，透過一光學膠將一間隔件350附裝至互連結構320之第一表面320a。間隔件350對一預定波長範圍之一電磁波透明。在本揭露之一些實施例中，間隔件350可包含矽或玻璃，但不限於此。另外，可在間隔件350之一頂表面上方形成一保護層352以用於保護。在本揭露之一些實施例中，保護層352可包含DAF，但不限於此。 仍參考圖4D，在本揭露之一些實施例中，在互連結構320之第一表面320a上方放置一裝置晶片360。裝置晶片360可為一電子積體電路(EIC)晶片。在本揭露之一些實施例中，裝置晶片360可提供半導體封裝30之所需電子功能。裝置晶片360透過導電結構362電耦合至互連結構320。另外，可使用一底膠填充364囊封導電結構362以進行保護。 參考圖4E，根據操作108在互連結構320之第一表面320a上方放置一模塑料370。如在圖4E中展示，在模塑料370中模製光學晶片340、間隔件350及裝置晶片360。模塑料370可為一單層膜或一複合堆疊。應用模塑料370以保護光學晶片340、間隔件350及裝置晶片360且提供機械剛度且增強半導體封裝30之機械強度。模塑料370可包含任何適合材料，諸如環氧樹脂、成型底膠填充或類似物。用於形成模塑料370之適合方法可包含壓縮成型、轉移成型、液體囊封劑成型或類似物。例如，可將模塑料370以液體形式施配於晶片340/360與間隔件350之間。隨後，執行一固化製程以固化模塑料370。模塑料370之填充可溢流於晶片340/360及間隔件350上方，使得模塑料370覆蓋晶片340/360及間隔件350之頂表面。在本揭露之一些實施例中，因此執行一薄化操作以曝露保護層352之至少一頂表面。此薄化操作可採用一機械研磨製程、一化學拋光製程、一蝕刻製程、其等之組合或類似物。因此，藉由模塑料370覆蓋光學晶片340之至少一邊緣。 參考圖4F及圖4G，接著使半導體封裝30翻轉，自載體基板332卸離且透過一黏著材料335 (諸如膠帶、DAF或類似物)附接至第一側300a處之另一載體基板334，且接著移除載體基板332及黏著材料333。隨後，在第二側300b處之絕緣層310上形成一光阻劑336。如在圖4G中展示，接著圖案化光阻劑336以界定將描述之外部終端之位置。隨後，圖案化絕緣層310 (包含絕緣體304、光學裝置層306及介電層308)以曝露第二表面320b處之互連結構320之部分。 參考圖4H及圖4I，移除圖案化光阻劑336且接著保形地形成聚合物層380以覆蓋絕緣層310及互連結構320之曝露部分。聚合物層380包含聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗焊劑(SR)、ABF膜及類似物。在聚合物層380上形成另一光阻劑337且圖案化光阻劑337。隨後，圖案化聚合物層380以曝露第二表面320b處之互連結構320之部分。在一些實施例中，在圖4H至圖4I中展示之操作係選用的。 參考圖4J及圖4K，接著移除圖案化光阻劑337且接著在絕緣層310、聚合物層380及互連結構320之曝露部分上方形成一導電材料382。導電材料382可藉由例如但不限於物理氣相沉積(PVD)、CVD、電鍍、無電式電鍍或其等之任何組合製成。在一些實施例中，形成導電材料382之製程可包含用於在導電材料382之表面上形成ENIG或Im-Sn材料之一無電式鎳浸金(ENIG)製程或浸錫(Im-Sn)製程。在本揭露之一些實施例中，導電材料382可包含一擴散阻障層及一晶種層(未展示)。在一些實施例中，擴散阻障層亦可用作一黏著層(或一膠合層)。擴散阻障層可由氮化鉭(TaN)形成，但是其亦可由其他材料形成，諸如氮化鈦(TiN)、鉭(Ta)、鈦(Ti)或類似物。晶種層可為形成於擴散阻障層上之Cu晶種層。Cu晶種層可由Cu或包含Ag、Ni、鉻(Cr)、錫(Sn)、金(Au)及其等之組合之Cu合金之一者形成。此後，如在圖4J中展示般在導電材料382上形成另一光阻劑338，且如在圖4K中展示般圖案化光阻劑338。接著，使用充當一遮罩之圖案化光阻劑338移除導電材料382之部分。因此，根據操作110在第二側300b處基板上方形成複數個導電層384。換言之，在絕緣層310之第四表面310b上方形成導電層384。導電層384充當凸塊下金屬(UBM)層。如在圖4K中展示，導電層384經電耦合至互連結構320。 如在圖4K中展示，由於絕緣層310之厚度小於50 μm，故導電層384能夠提供自絕緣層310之第一側300a至第二側300b之垂直電連接。換言之，使用導電層384取代習知用於提供垂直電連接之TSV。 參考圖4L及圖4M，移除圖案化光阻劑338。形成複數個外部終端386使之與導電層384接觸。外部終端386可包含焊球、金屬墊、金屬柱及/或其等之組合，且可由Au、Ag、Ni、Al、鎢(W)及/或其等之合金形成。接著移除黏著材料335及載體基板334且翻轉半導體封裝30。如在圖4M中展示，移除間隔件350之頂表面上方之保護層352且透過例如但不限於光學膠將一光纖或其他外部光學耦合裝置356附裝至間隔件350之頂表面。光纖356經組態以傳輸預定波長範圍之電磁波。 如在圖4M中展示，光學晶片340放置於互連結構320及絕緣層310上。由於具有或不具有塊體結構之絕緣層310 (包含介電層308、光學裝置306及絕緣體層304)之厚度減小至50 μm或更小，故縮短通過絕緣層310中之垂直電連接之電路徑長度。因此，減小電損耗。另外，基板300經足夠薄化，使得導電層384可充當一鏡。在本揭露之一些實施例中，光學晶片340之光學發射路徑以投影方式與導電層384重疊，使得可藉由導電層384反射光。因此，可進一步減小光學損耗且可改良光學耦合效率。在本揭露之一些實施例中，薄化基板300至僅整個或部分絕緣層310保留於基板300之第二側300b上，此亦減小由塊體結構302內之光學導引引起之光學損耗。 圖5係在一些實施例中根據本揭露之態樣之一半導體封裝32之一剖面圖。因此，為清楚及簡單起見，由相同參考數字識別圖4A至圖4M及圖5中之類似構件。可執行用於製作半導體封裝10之方法以形成半導體封裝32且為了簡潔而省略該等細節。如在圖5中展示，在本揭露之一些實施例中，透過一光學膠將光纖或其他外部光學耦合裝置356附裝至互連結構320及絕緣層310之側表面。且在絕緣層310中之光學裝置層306中相鄰於光纖或其他外部光學耦合裝置356形成至少一個邊緣耦合器358。 根據上述實施例，在模塑料370中模製光學晶片340，因此改良半導體封裝30及32之平面度。 圖6A至圖6B繪示在一些實施例中根據本揭露之態樣建構之各種製作階段之一半導體封裝40之剖面圖。 參考圖6A至圖6B，應理解，圖4A至圖4M及圖6A至圖6B中之類似構件可包含類似材料，因此為了簡潔而省略該等細節。且可執行用於形成半導體封裝11之方法以形成半導體封裝40。參考圖6A，根據操作112提供一基板(未展示)。基板包含一第一側400a及與第一側400a相對之一第二側400b。在本揭露之一些實施例中，基板可包含一SOI基板。在本揭露之一些實施例中，基板400可包含形成於第一側400a處之一絕緣體層404上之一半導體層406且絕緣體層404經設置於一塊體結構402上(如在圖8中展示)。在本揭露之一些實施例中，可執行各種操作以在半導體層406中形成諸如調變器、波導、偵測器、光柵及/或耦合器之光學裝置。因此，半導體層406可被稱為一光學裝置層406。換言之，光學裝置層406包含調變器、波導、偵測器、光柵或耦合器。在本揭露之一些實施例中，可視需要形成除光學裝置外之裝置。另外，可在絕緣體層404上形成一介電層408以提供保護且形成一平坦表面以供隨後操作。 仍參考圖6A，在第一側400a處基板上方形成一互連結構420。因此，將光學裝置層406夾置於至少一個絕緣體層404與互連結構420之間。互連結構420包含一第一表面420a及與第一表面420a相對之一第二表面420b，且互連結構420之第二表面420b面向基板及光學裝置層406中之介電層408。互連結構420可包含一或多個重佈層(RDL)，且RDL可包含具有形成於其中之導電線424之一介電層422之一層。如上文提及，可在一後段製程(BEOL)中形成RDL，但不限於此。 仍參考圖6A，接著翻轉基板及互連結構420且透過一黏著材料(未展示)將其等附接至第一側400a處之一載體基板(未展示)。此後，根據操作114自第二側400b薄化基板。在本揭露之一些實施例中，藉由自第二側400b薄化基板而移除基板之塊體結構。在本揭露之一些實施例中，塊體結構可保留在基板上第二側400b處且剩餘餘塊體結構402 (如在圖8中展示)包含小於約50 μm之一厚度。在一些實施例中，換言之，介電層408及包含絕緣體層404及半導體層406之經薄化基板(具有或不具有塊體結構)被稱為一絕緣層410，且絕緣層410包含小於約50 μm之一厚度。如在圖6A中展示，絕緣層410包含面向互連結構420之第二表面420b之一第三表面410a及與第三表面410a相對之一第四表面410b。 仍參考圖6A，接著藉由另一黏著材料(未展示)將絕緣層410及互連結構420附接至第二側處之另一載體基板(未展示)。且自基板之第一側400a移除上述載體基板及黏著材料。如在圖6A中展示，至少一個裝置晶片460放置於互連結構420之第一表面420a上方。裝置晶片460可為一電子積體電路(EIC)晶片。在本揭露之一些實施例中，裝置晶片460可提供半導體封裝40之所需電子功能。裝置晶片460透過導電結構462電耦合至互連結構420。另外，可使用一底膠填充464囊封導電結構462以進行保護。 仍參考圖6A，根據操作116在互連結構420之第一表面420a上方放置一模塑料470。如在圖6A中展示，在模塑料470中模製裝置晶片460。隨後，接著翻轉半導體封裝40且透過一黏著材料(未展示)將其附接至第一側400a處之另一載體基板(未展示)。接著，圖案化絕緣層410 (包含絕緣體404、光學裝置層406及介電層408)以曝露第二表面420b處之互連結構420之部分。接著保形地形成一聚合物層480以覆蓋絕緣層410及互連結構420之曝露部分。隨後，圖案化聚合物層480以曝露第二表面420b處之互連結構420之部分。 仍參考圖6A，在聚合物480上方形成一導電材料且接著圖案化導電材料。因此，根據操作118在第二側400b處基板上方形成複數個導電層484。換言之，在絕緣層410之第四表面410b上方形成導電層484。導電層484充當UBM層。接著形成複數個外部終端486使之與導電層484接觸。 如上文提及，由於絕緣層410之厚度小於50 μm，故導電層484能夠提供自絕緣層410之第一側400a至第二側400b之垂直電連接。換言之，使用導電層484取代習知用於提供垂直電連接之TSV。 參考圖6B，接著根據操作120在第二側400b處基板上方放置一光學晶片440。換言之，在絕緣層410之第四表面410b上方放置光學晶片440。光學晶片440透過如在圖6B中展示之導電層484電耦合至互連結構420。此外，可透過一底膠材料444將光學晶片440附裝至基板。如在圖6B中展示，在本揭露之一些實施例中，透過一光學膠(未展示)將一光纖或其他外部光學耦合裝置456附裝至互連結構420及絕緣層410之側表面。且在絕緣層410中之光學裝置層406中相鄰於光纖456形成至少一個邊緣耦合器438。 圖7係在一些實施例中根據本揭露之態樣之一半導體封裝42之一剖面圖。因此，為清楚及簡單起見，由相同參考數字識別圖6A至圖6B及圖7中之類似構件。可執行用於製作半導體封裝11之方法以形成半導體封裝42。如在圖7中展示，在本揭露之一些實施例中，在執行操作116之前透過一光學膠將一間隔件450附裝至互連結構420之第一表面420a。間隔件450對一預定波長範圍之一電磁波透明。在本揭露之一些實施例中，間隔件450可包含矽或玻璃，但不限於此。且在操作120之後透過例如但不限於一光學膠將一光纖或其他外部光學耦合裝置456附裝至間隔件450之頂表面。光纖或其他外部光學耦合裝置456經組態以傳輸預定波長範圍之電磁波。因此，可進一步改良光學耦合效率。 圖8係在一些實施例中根據本揭露之態樣之一半導體封裝44之一剖面圖。因此，為清楚及簡單起見，由相同參考數字識別圖6A至圖6B及圖8中之類似構件。可執行用於製作半導體封裝11之方法以形成半導體封裝44。如在圖8中展示，在本揭露之一些實施例中，塊體結構402可保留在基板400上第二側400b處且剩餘塊體結構402包含小於約50 μm之一厚度。 根據上述實施例，光學晶片440經放置於第二側400b處，而裝置晶片460處在第一側400b。換言之，光學晶片440及裝置晶片460經放置於半導體封裝40/42/44之相對側處。如在圖6A至圖8中展示，儘管未將光學晶片440模製在模塑料470中，但將光學晶片440放置於其中放置導電層484及外部終端486之第二側400b處，因此仍改良半導體封裝40/42/44之平面度。 圖9A至圖9G繪示根據一些實施例中在本揭露之態樣建構之各種製作階段之一半導體封裝50之剖面圖。應理解，圖4A至圖4M及圖9A至圖9G中之類似構件可包含類似材料，因此為了簡潔而省略該等細節。可執行用於製作半導體封裝20之方法以形成半導體封裝50且為了簡潔而省略該等細節。 參考圖9A，根據操作202提供一基板500。基板500包含一第一側500a及與第一側500a相對之一第二側500b。在本揭露之一些實施例中，基板500包含形成於第一側500a處之一絕緣體層504上之一半導體層506。絕緣體層504經設置於一塊體結構502 (通常一矽或玻璃基板)上。亦可使用其他物質，諸如多層或梯度基板。在本揭露之一些實施例中，可執行各種操作以在半導體層506中形成諸如調變器、波導、偵測器、光柵及/或耦合器之光學裝置。因此，半導體層506可被稱為一光學裝置層506。換言之，光學裝置層506包含調變器、波導、偵測器、光柵或耦合器。在本揭露之一些實施例中，可視需要形成除光學裝置外之裝置。另外，可在絕緣體層504上方形成包含(若干)絕緣材料之一介電層508以提供保護且形成一平坦表面以供隨後操作。在一些實施例中，可在絕緣層508、半導體層506、絕緣體層504及塊體結構502中形成複數個開口512，如在圖9A中展示。 參考圖9B，在開口512中形成複數個連接器514。在一些實施例中，連接器514填充開口512，但本揭露不限於此。參考圖9C，根據操作202在第一側500a處基板500上方形成一互連結構520。因此，將光學裝置層506夾置於至少一個絕緣體層504與互連結構520之間。互連結構520包含一第一表面520a及與第一表面520a相對之一第二表面520b，且互連結構520之第二表面520b面向基板500及光學裝置層506中之介電層508。互連結構520可包含一或多個RDL，且RDL可包含具有形成於其中之導電線524之一介電層522之一層。互連結構520可電耦合至光學裝置層506中之光學裝置或其他裝置。在一些實施例中，互連結構520經電耦合至連接器514。 參考圖9D，根據操作204在互連結構520之第一表面520a上方放置至少一個光學晶片540。在本揭露之一些實施例中，光學晶片540可包含具有一光源(諸如例如但不限於一半導體雷射或一發光二極體)之一總成。光學晶片540透過導電結構542電耦合至互連結構520。另外，可使用一底膠填充544囊封導電結構542以進行保護。此外，透過一光學膠將一間隔件550附裝至互連結構520之第一表面520a。間隔件550對一預定波長範圍之一電磁波透明。另外，可在間隔件550之一頂表面上方形成一保護層552以用於保護。在本揭露之一些實施例中，保護層552可包含DAF，但不限於此。在本揭露之一些實施例中，在互連結構520之第一表面520a上方放置一裝置晶片560。裝置晶片560可為一電子積體電路(EIC)晶片。在本揭露之一些實施例中，裝置晶片560可提供半導體封裝50之所需電子功能。裝置晶片560透過導電結構562電耦合至互連結構520。另外，可使用一底膠填充564囊封導電結構562以進行保護。 仍參考圖9D，根據操作206在互連結構520之第一表面520a上方放置一模塑料570。如在圖9D中展示，在模塑料570中模製光學晶片540、間隔件550及裝置晶片560。模塑料570可為一單層膜或一複合堆疊。應用模塑料570以保護光學晶片540、間隔件550及裝置晶片560且提供機械剛度且增強半導體封裝50之機械強度。在本揭露之一些實施例中，藉由模塑料570覆蓋光學晶片540之至少一邊緣。 參考圖9E，接著翻轉基板500且透過一黏著材料531將其附接至第一側500a處之一載體基板530。此後，根據操作208自第二側500b薄化基板500以曝露連接器514。在本揭露之一些實施例中，藉由自第二側500b薄化基板500而移除基板500之塊體結構502。在本揭露之一些實施例中，塊體結構502可保留在第二側500b處基板500上且剩餘塊體結構502包含小於約50 μm之一厚度，如在圖9E中展示。在一些實施例中，介電層508及包含絕緣體層504及半導體層506之經薄化基板500 (具有或不具有塊體結構502)被稱為一絕緣層510，且絕緣層510包含小於約50 μm之一厚度。如在圖9E中展示，絕緣層510包含面向互連結構520之第二表面520b之一第三表面510a及與第三表面510a相對之一第四表面510b。 參考圖9F，形成一聚合物層580以覆蓋絕緣層510及曝露連接器514之部分。隨後，圖案化聚合物層580以自第四表面510b曝露連接器514。在一些實施例中，在圖9F中展示之操作係選用的。接著，在絕緣層510、聚合物層580及曝露連接器514上方形成一導電材料582。在本揭露之一些實施例中，導電材料582可包含一擴散阻障層及一晶種層(未展示)。 參考圖9G，在導電材料582上形成另一圖案化光阻劑(未展示)。接著，使用充當一遮罩之圖案化光阻劑移除導電材料582之部分。因此，根據操作210在第二側500b處基板上方形成複數個導電層584。換言之，在絕緣層510之第四表面510b上方形成導電層584。導電層584充當UBM層。如在圖9G中展示，透過連接器514將導電層584電耦合至互連結構520。 仍參考圖9G，移除圖案化光阻劑，且形成複數個外部終端586使之與導電層584接觸。外部終端586可包含焊球、金屬墊、金屬柱及/或其等之組合。儘管未展示，但熟習此項技術者將容易地認識到，接著移除黏著材料531及載體基板530，且翻轉半導體封裝50。此外，移除間隔件550之頂表面上方之保護層552且可透過例如但不限於一光學膠將一光纖或其他外部光學耦合裝置(未展示)附裝至間隔件550之頂表面。如上文提及，光纖經組態以傳輸預定波長範圍之電磁波。此外，熟習此項技術者將理解，在一些實施例中，可透過如前述提及且在圖5中展示之一光學膠(未展示)將光纖或其他外部光學耦合裝置附裝至互連結構520及絕緣層510之側表面。且如前述及圖5中展示般在絕緣層510中之光學裝置層506中相鄰於光纖或其他外部光學耦合裝置形成至少一個邊緣耦合器(未展示)。 根據上述實施例，在模塑料570中模製光學晶片540，因此改良半導體封裝50之平面度。在一些實施例中，剩餘塊體結構502提供較強機械強度。在一些實施例中，可將光學晶片540放置於第二側500b處基板500上方。換言之，將光學晶片540放置於絕緣層510之第四表面510b上方。在該等實施例中，光學晶片540透過導電層584及連接器514電耦合至互連結構520。 在本揭露中，具有或不具有塊體結構之絕緣層(包含絕緣體層、光學裝置層及介電層)充當無TSV之結構，使得在不具有TSV之情況下將導電層電耦合至互連結構。即，導電層提供自絕緣層之第一側至第二側之垂直電連接。因此，歸因於TSV訊號路徑(其可為超過100 μm)之消除而縮短路由路徑。因此，減小電損耗且改良電效能。因此簡化用於形成半導體封裝之製作方法。更重要的是，由於光學晶片模製在模塑料內或放置於其中放置導電層及外部終端之側處，故改良半導體封裝之平面度。 在一些實施例中，提供一種半導體封裝。該半導體封裝包含：一互連結構，其具有一第一表面及與該第一表面相對之一第二表面；至少一個光學晶片，其在該互連結構之該第一表面上方且電耦合至該互連結構；一絕緣層，其接觸該互連結構之該第二表面；及一模塑料，其在該互連結構之該第一表面上方。該絕緣層包含面向該互連結構之該第二表面之一第三表面及與該第三表面相對之一第四表面。藉由該模塑料覆蓋該光學晶片之至少一邊緣。 在一些實施例中，提供一種半導體封裝。該半導體封裝包含：一互連結構，其具有一第一表面及與該第一表面相對之一第二表面；一絕緣層，其接觸該互連結構之該第二表面，其中該絕緣層具有面向該互連結構之該第二表面之一第三表面及與該第三表面相對之一第四表面；至少一個光學晶片，其在該絕緣層之該第四表面上方且電耦合至該互連結構；及一模塑料，其在該互連結構之該第一表面上方。 在一些實施例中，提供一種用於製作一半導體封裝之方法。該方法包含：提供包括一第一側及與該第一側相對之一第二側之一基板，該基板包括該第一側處之至少一個絕緣層及該絕緣層上方之一互連結構；自該第二側薄化該基板；在該基板上方放置至少一個光學晶片；在該互連結構上方放置一模塑料；及在該第二側處該基板上方形成複數個導電層。該等導電層經電耦合至該互連結構。 前文概述若干實施例之特徵，使得熟習此項技術者可更好理解本揭露之態樣。熟習此項技術者應瞭解，其等可容易地使用本揭露作為設計或修改用於實行本文中介紹之實施例之相同目的及/或達成相同優點之其他製程及結構之一基礎。熟習此項技術者亦應認識到，此等等效構造並不脫離本揭露之精神及範疇，且其等可在不脫離本揭露之精神及範疇之情況下在本文中做出各種改變、替代及更改。
10‧‧‧半導體封裝
11‧‧‧半導體封裝
20‧‧‧半導體封裝
30‧‧‧半導體封裝
32‧‧‧半導體封裝
40‧‧‧半導體封裝
42‧‧‧半導體封裝
44‧‧‧半導體封裝
50‧‧‧半導體封裝
102‧‧‧操作
104‧‧‧操作
106‧‧‧操作
108‧‧‧操作
110‧‧‧操作
112‧‧‧操作
114‧‧‧操作
116‧‧‧操作
118‧‧‧操作
120‧‧‧操作
202‧‧‧操作
204‧‧‧操作
206‧‧‧操作
208‧‧‧操作
210‧‧‧操作
300‧‧‧基板
300a‧‧‧第一側
300b‧‧‧第二側
302‧‧‧塊體結構
304‧‧‧絕緣體層
306‧‧‧半導體層/光學裝置層
308‧‧‧介電層
310‧‧‧絕緣層
310a‧‧‧第三表面
310b‧‧‧第四表面
320‧‧‧互連結構
320a‧‧‧第一表面
320b‧‧‧第二表面
322‧‧‧介電層
324‧‧‧導電線
330‧‧‧載體基板
331‧‧‧黏著材料
332‧‧‧載體基板
333‧‧‧黏著材料
334‧‧‧載體基板
335‧‧‧黏著材料
336‧‧‧光阻劑
337‧‧‧光阻劑
338‧‧‧光阻劑
340‧‧‧光學晶片
342‧‧‧導電結構
344‧‧‧底膠填充/底膠材料
350‧‧‧間隔件
352‧‧‧保護層
356‧‧‧光纖/外部光學耦合裝置
358‧‧‧邊緣耦合器
360‧‧‧裝置晶片
362‧‧‧導電結構
364‧‧‧底膠填充
370‧‧‧模塑料
380‧‧‧聚合物層
382‧‧‧導電材料
384‧‧‧導電層
386‧‧‧外部終端
400a‧‧‧第一側
400b‧‧‧第二側
402‧‧‧塊體結構
404‧‧‧絕緣體層
406‧‧‧半導體層/光學裝置層
408‧‧‧介電層
410‧‧‧絕緣層
410a‧‧‧第三表面
410b‧‧‧第四表面
420‧‧‧互連結構
420a‧‧‧第一表面
420b‧‧‧第二表面
422‧‧‧介電層
424‧‧‧導電線
440‧‧‧光學晶片
444‧‧‧底膠材料
450‧‧‧間隔件
456‧‧‧外部光學耦合裝置
460‧‧‧裝置晶片
462‧‧‧導電結構
464‧‧‧底膠填充
470‧‧‧模塑料
480‧‧‧聚合物層
484‧‧‧導電層
486‧‧‧外部終端
500‧‧‧基板
500a‧‧‧第一側
500b‧‧‧第二側
502‧‧‧塊體結構
504‧‧‧絕緣體層
506‧‧‧半導體層/光學裝置層
508‧‧‧介電層
510‧‧‧絕緣層
510a‧‧‧第三表面
510b‧‧‧第四表面
512‧‧‧開口
514‧‧‧連接器
520‧‧‧互連結構
520a‧‧‧第一表面
520b‧‧‧第二表面
522‧‧‧介電層
524‧‧‧導電線
530‧‧‧載體基板
531‧‧‧黏著材料
540‧‧‧光學晶片
542‧‧‧導電結構
544‧‧‧底膠填充
550‧‧‧間隔件
552‧‧‧保護層
560‧‧‧裝置晶片
562‧‧‧導電結構
564‧‧‧底膠填充
570‧‧‧模塑料
580‧‧‧聚合物層
582‧‧‧導電材料
584‧‧‧導電層
586‧‧‧外部終端
當結合附圖閱讀時，自以下實施方式更好理解本揭露之態樣。應注意，根據行業中之標準實踐，各種構件不按比例繪製。實際上，為清晰論述，各種構件之尺寸可任意增大或減小。 圖1係表示根據本揭露之一些實施例之用於製作一半導體封裝之一方法之一流程圖。 圖2係表示根據本揭露之一些實施例之用於製作一半導體封裝之一方法之一流程圖。 圖3係表示根據本揭露之一些實施例之用於製作一半導體封裝之一方法之一流程圖。 圖4A至圖4M繪示在一或多項實施例中根據本揭露之態樣建構之各種製作階段之一半導體封裝之剖面圖。 圖5係在一些實施例中根據本揭露之其他態樣之一半導體封裝之一剖面圖。 圖6A至圖6B繪示在一或多項實施例中根據本揭露之態樣建構之各種製作階段之一半導體封裝之剖面圖。 圖7係在一些實施例中根據本揭露之其他態樣之一半導體封裝之一剖面圖。 圖8係在一些實施例中根據本揭露之其他態樣之一半導體封裝之一剖面圖。 圖9A至圖9G繪示在一或多項實施例中根據本揭露之態樣建構之各種製作階段之一半導體封裝之剖面圖。

Claims (1)

  1. 一種半導體封裝，其包括： 一互連結構，其包括一第一表面及與該第一表面相對之一第二表面； 至少一個光學晶片，其在該互連結構之該第一表面上方且電耦合至該互連結構； 一絕緣層，其接觸該互連結構之該第二表面，其中該絕緣層包括面向該互連結構之該第二表面之一第三表面及與該第三表面相對之一第四表面；及 一模塑料，其在該互連結構之該第一表面上方， 其中藉由該模塑料覆蓋該光學晶片之至少一邊緣。
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US20190131267A1 (en) 2019-05-02
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US10665560B2 (en) 2020-05-26
US20200286845A1 (en) 2020-09-10

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