TW201906115A - 積體扇出式封裝及其形成方法 - Google Patents

積體扇出式封裝及其形成方法 Download PDF

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Publication number
TW201906115A
TW201906115A TW106126421A TW106126421A TW201906115A TW 201906115 A TW201906115 A TW 201906115A TW 106126421 A TW106126421 A TW 106126421A TW 106126421 A TW106126421 A TW 106126421A TW 201906115 A TW201906115 A TW 201906115A
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Taiwan
Prior art keywords
layer
die
integrated fan
molding
material layer
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TW106126421A
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English (en)
Inventor
陳威宇
蘇安治
葉德強
黃立賢
葉名世
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台灣積體電路製造股份有限公司
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Publication of TW201906115A publication Critical patent/TW201906115A/zh

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Abstract

本發明實施例揭露積體扇出式封裝及其形成方法。一種積體扇出式封裝包括：第一晶粒、至少一個積體扇出式穿孔以及模塑層。所述至少一個積體扇出式穿孔位於所述第一晶粒旁邊且包括晶種層及金屬層。所述模塑層包封所述至少一個積體扇出式穿孔及所述第一晶粒。此外，所述晶種層環繞所述金屬層的側壁且位於所述金屬層與所述模塑層之間。

Description

積體扇出式封裝及其形成方法
本發明實施例是有關於一種封裝及其形成方法，且特別是有關於一種積體扇出式封裝及其形成方法。
近年來，由於各種電子元件（例如，晶體管、二極管、電阻器、電容器等）的積體密度的持續提高，半導體產業經歷了快速成長。在大多數情况下，積體密度的此種提高源自於最小特徵尺寸的連續縮减，此使得能夠在給定區域中整合更多元件。
這些較小的電子元件也需要與先前的封裝相比占據較小區域的較小的封裝。半導體的封裝類型的實例包括方形扁平封裝（quad flat package，QFP）、針格陣列（pin grid array，PGA）封裝、球格陣列（ball grid array，BGA）封裝、覆晶封裝（flip chip，FC）、三維積體電路（three-dimensional integrated circuit，3DIC）、晶圓級封裝（wafer level package，WLP）、及疊層封裝（package on package，PoP）裝置等。目前，積體扇出式封裝因其緻密性（compactness）而變得越來越受歡迎。然而，存在許多與積體扇出式封裝相關的挑戰。
本發明實施例的一種積體扇出式封裝包括第一晶粒、至少一個積體扇出式穿孔以及模塑層。至少一個積體扇出式穿孔位於所述第一晶粒旁邊且包括晶種層及金屬層。模塑層包封所述至少一個積體扇出式穿孔及所述第一晶粒。所述晶種層環繞所述金屬層的側壁且位於所述金屬層與所述模塑層之間。
本發明實施例的一種形成積體扇出式封裝的方法包括下列操作。將第一晶粒放置在載體上。在所述第一晶粒上形成模塑層，其中在所述模塑層中形成至少一個第一開口且所述第一開口不穿透所述模塑層。在所述第一開口的表面上形成晶種材料層及金屬材料層。
本發明實施例的一種形成積體扇出式封裝的方法包括下列操作。提供載體，在所述載體上具有晶粒貼合膜。將第一晶粒放置在所述晶粒貼合膜上。在所述第一晶粒之上形成模塑層，其中在所述模塑層中形成至少一個第一開口，且所述第一開口穿透所述模塑層並與所述晶粒貼合膜實體接觸。在所述第一開口的表面上形成晶種材料層及金屬材料層。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及設置的具體實例的目的在於以簡化方式傳達本揭露內容。當然，這些僅爲實例且不旨在進行限制。舉例來說，以下說明中將第二特徵形成在第一特徵“之上”或第一特徵“上”可包括其中第二特徵及第一特徵被形成爲直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成有附加特徵、進而使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。此外，在本揭露內容的各種實例中，可使用相同的參考編號及/或字母來指代相同或類似的部件。對參考編號的重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“位於…上（on）”、“位於…之上（over）”、“上方（above）”、及“上部的（upper）”等空間相對性用語以便於闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
上述內容還可包括其他特徵及製程。舉例來說，可包括測試結構以幫助進行三維（3D）封裝或三維積體電路（3DIC）裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊，所述測試墊使得能夠測試3D封裝或3DIC、使用探針（probe）及/或探針卡（probe card）等。可對中間結構及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可接合包含對已知良好晶粒的中間驗證的測試方法論一起使用，以提高産率（yield）及降低成本。
圖1A至圖1J是一種根據一些實施例形成積體扇出式封裝的方法的剖視圖。
參照圖1A，提供一個或多個第一晶粒100。在一些實施例中，第一晶粒100中的每一個包括基底102、一個或多個連接件104以及鈍化層106。基底102包括，但不限於，例如經摻雜或未經摻雜的塊狀矽、或絕緣體上半導體（semiconductor-on-insulator，SOI）基底的主動層。連接件104形成在第一晶粒100的位於連接件104之下的墊或互連結構（圖中未示出）之上並電性連接到所述墊或互連結構。在一些實施例中，連接件104被形成爲第一晶粒100的頂部。連接件104從第一晶粒100的其餘部分或下部突出。在說明通篇中，第一晶粒100的存在連接件104的側被稱爲前側或第一側。連接件104可以是電性連接件、虛設連接件、或是電性連接件與虛設連接件兩者。連接件104可包括焊料凸塊、金凸塊、銅柱等，且是由置球製程（ball drop process）或電鍍製程形成。鈍化層106形成在第一晶粒100之上以覆蓋連接件104的頂部及側壁，並填充連接件104之間的間隙。在一些實施例中，鈍化層106包含感光性材料，例如聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）、或其組合等，所述材料可利用光阻罩幕容易地進行圖案化。在替代實施例中，鈍化層106包含氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）、或其組合等。
在一些實施例中，第一晶粒100形成在晶圓臺（wafer stage）中。在形成鈍化層106之後，在第一晶粒100的背側或第二側之上形成黏合層或毯覆式晶粒貼合膜（blanket die attach film）。然後利用鋸片或雷射切割工具沿切割區執行單體化製程，以使第一晶粒100彼此分離，且因此提供在其背側上具有晶粒貼合膜DAF的第一晶粒100。
繼續參照圖1A，將一個或多個第一晶粒100放置在載體C上。在一些實施例中，在選取第一晶粒100並在將第一晶粒100放置在載體C上之前，在第一晶粒100的背側或第二側上形成晶粒貼合膜DAF。載體C設置有剝離層DB及形成在剝離層DB上的介電層DI。載體C可以是坯料（blank）玻璃載體、坯料陶瓷載體等。剝離層DB可由例如紫外（UV）膠、光熱轉換（light-to-heat conversion，LTHC）膠等黏合劑形成，但也可使用其他類型的黏合劑。在一些實施例中，剝離層DB可在光的熱量下分解，從而使載體C從形成在其上面的結構分離。介電層DI形成在剝離層DB之上。在一些實施例中，介電層DI是聚合物層。聚合物包含例如聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）、味之素增層膜（Ajinomoto Buildup Film，ABF）、或阻焊膜（Solder Resist film，SR）等。介電層DI是藉由例如旋轉塗布、疊層、或沉積等適當的製造技術而形成。在一些實施例中，第一晶粒100中的每一個貼合到介電層DI，其中在第一晶粒100與介電層DI之間設置有晶粒貼合膜DAF。在替代實施例中，可省略形成介電層DI的操作，且第一晶粒100中的每一個貼合到剝離層DB，其中在第一晶粒100與剝離層DB之間設置有晶粒貼合膜DAF。
之後，在第一晶粒100之上形成預模塑層107。具體來說，預模塑層107形成在介電層DI的頂面上，並包封第一晶粒100的頂部及側壁。在一些實施例中，預模塑層107包含模塑化合物、模塑底部填充、樹脂等，例如環氧樹脂。預模塑層107可藉由例如旋轉塗布、疊層、或沉積等適當的製造技術而形成。在一些實施例中，預模塑層107包含感光性材料，例如聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）、或其組合等。在替代實施例中，模塑層108包含氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜硼的磷矽酸鹽玻璃（BPSG）、或其組合等。
參照圖1B及圖1C，對預模塑層107進行模塑，以形成其中具有一個或多個第一開口O1的模塑層108。在一些實施例中，第一開口O1不穿透模塑層108。在一些實施例中，將模塑機器的模具M按壓抵靠模塑層108，以在模塑層108中界定多個第一開口O1，如圖1B所示。模具M包括模具箱（mold chest）及從模具箱的接觸表面突出的多個模具銷（mold pin）。模具銷的形狀對應於隨後形成的積體扇出式穿孔（TIV）的形狀。在一些實施例中，模具M的模具銷具有傾斜的側壁。舉例來說，模具銷中的每一個的橫截面積朝遠離模具M的模具箱的方向逐漸減小。在替代實施例中，模具M的模具銷具有垂直於模具箱的接觸表面的實質上垂直的側壁。在一些實施例中，模具銷的高度小於模塑層108的高度，因此所形成的第一開口O1不穿透模塑層108。在模塑層108中形成第一開口O1之後，抬起模具M，如圖1C所示。具體來說，第一開口O1從第一晶粒100的前側向背側延伸進入模塑層108中。在一些實施例中，第一開口O1具有傾斜的側壁。舉例來說，第一開口O1中的每一個的橫截面積朝第一晶粒100的背側或第二側逐漸減小。在替代實施例中，第一開口O1具有垂直於模塑層108的前表面的實質上垂直的側壁。
在一些實施例中，在圖1B所示的步驟期間，對模具M以及模塑層108進行加熱一段時間，以使模塑層108半固化。在抬起模具M之後，如圖1C所示，對半固化的模塑層108進行加熱另一段時間，以使材料層108充分固化。
參照圖1D，在第一開口O1的表面上形成膠材料層109、晶種材料層110以及金屬材料層112。具體來說，膠材料層109、晶種材料層110以及金屬材料層112依序形成在模塑層108之上並覆蓋第一開口O1的整個表面。在一些實施例中，膠材料層109有助於將模塑層108黏合到隨後形成的晶種材料層110。膠材料層109可包含鈦系材料或鉭系材料，例如鈦、氮化鈦、鉭、氮化鉭、或其組合等，並可藉由例如物理氣相沉積（PVD）、化學氣相沉積（CVD）、濺鍍等製程形成，但作爲另一選擇也可使用其他方法及材料。晶種材料層110可藉由PVD、CVD、濺鍍等來沉積，但作爲另一選擇也可使用其他方法。晶種材料層110可包含銅系材料（例如，銅、鈦銅合金等），但作爲另一選擇也可使用其他材料（例如，鎳、金）。金屬材料層112可包含銅系材料（例如，銅、銅系合金等），但作爲另一選擇也可利用另一適當材料，例如鎳、鈦、鋁等。金屬材料層112可藉由將銅電鍍到晶種材料層110上而形成，但作爲另一選擇也可利用用於形成金屬材料層112的任意適當的替代製程。在一些實施例中，膠材料層109、晶種材料層110以及金屬材料層112共同將第一開口O1完全填滿。
在一些實施例中，膠材料層109與模塑層108實體接觸，如圖1D所示。在替代實施例中，可省略形成膠材料層109的操作，並將晶種材料層110直接形成在模塑層108上。
參照圖1E，從第一晶粒100的前側或第一側研磨模塑層108，直到暴露出第一晶粒100的連接件104。在一些實施例中，執行研磨製程以移除模塑層108的一部分以及鈍化層106的一部分。在研磨製程期間，同時移除膠材料層109的、晶種材料層110的以及金屬材料層112的位於第一開口O1外部的部分，以形成積體扇出式穿孔TIV。
參照圖1F，在第一晶粒100的第一側之上形成重佈線層結構114。在一些實施例中，重佈線層結構114電性連接到第一晶粒100的連接件104以及第一開口O1中的金屬材料層112。在通篇說明書中，重佈線層結構114也可被稱爲“前側重佈線層結構”。在一些實施例中，重佈線層結構114包括交替堆疊的多個聚合物層及多個重佈線層。聚合物層或重佈線層的數目不受本揭露內容的限制。在一些實施例中，最頂端的重佈線層也被稱爲用於安裝球的球下金屬（under-ball metallurgy，UBM）層。在一些實施例中，聚合物層中的每一層包含聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）、或其組合等。在一些實施例中，重佈線層中的每一層包含銅、鎳、鈦、或其組合等，且是藉由電鍍製程而形成。
之後，在重佈線層結構114之上形成球或凸塊116，並使球或凸塊116電性連接到重佈線層結構114。在一些實施例中，凸塊116是由具有低電阻率的導電性材料（例如，Sn、Pb、Ag、Cu、Ni、Bi、或其合金）製成，且是藉由例如蒸鍍、鍍覆、置球、或網版印刷等適當的製程而形成。
參照圖1G，剝離載體C。在一些實施例中，將具有第一晶粒100、模塑層108、重佈線層結構114以及凸塊116的載體C翻轉，剝離層DB在光的熱量下分解，然後載體C從第一晶粒100的背側或第二側分離。
參照圖1H及圖1I，從第一晶粒100的背側或第二側將第二晶粒200電性連接到或接合到第一晶粒100。在一些實施例中，第二晶粒200中的每一個包括存儲器裝置或適當的半導體裝置。如圖1H所示，從第一晶粒100的背側後第二側對模塑層108執行圖案化製程，以形成與第一開口O1對應的第二開口O2。在一些實施例中，在圖案化製程期間，同時移除部分的介電層DI、部分的膠材料層109以及部分的晶種材料層110。具體來說，第二開口O2穿透介電層DI、模塑層108、膠材料層109以及晶種材料層110，並暴露出第一開口O1中的金屬材料層112。在一些實施例中，所述圖案化製程包括雷射鑽孔製程。在一些實施例中，在雷射鑽孔製程之後，從第一晶粒100的背側或第二側執行處理，藉此移除由雷射鑽孔製程造成的殘餘物及/或被暴露出的膠材料層109或晶種材料層110（如果未被雷射鑽孔製程移除），以暴露出第一開口O1中的金屬材料層112。在一些實施例中，所述處理包括電漿清潔製程、乾蝕刻製程等。
在一些實施例中，第二開口O2具有傾斜的側壁。舉例來說，第二開口O2中的每一個的橫截面積朝第一晶粒100的背側或第二側逐漸減小。在替代實施例中，第二開口O2具有垂直於模塑層108的後表面的實質上垂直的側壁。
之後，在第一晶粒100的背側或第二側之上設置第二晶粒200。在一些實施例中，第二晶粒200中的每一個包括基底202、多個墊204以及多個凸塊206。第二晶粒200從第一晶粒100的背側電性連接到或接合到第一晶粒100，其中凸塊206填充到第二開口O2中。具體來說，第二晶粒200的凸塊206與介電層DI及模塑層108中的第二開口O2對齊並填充到第二開口O2中，且接合到積體扇出式穿孔TIV。在一些實施例中，積體扇出式穿孔TIV中的每一個包括膠層109a、晶種層110a以及金屬層112a。晶種層110a位於膠層109a與金屬層112a之間。
之後，形成底部填充層UF，以填充第一晶粒100與第二晶粒200之間的空間並環繞凸塊206。在一些實施例中，底部填充層UF包含模塑化合物（例如，環氧樹脂），並使用分配、注射、及/或噴塗而形成。
參照圖1J，執行單體化製程，以使積體扇出式封裝10（或在一些實施例中被稱爲PoP封裝）彼此分離。在一些實施例中，使用鋸片或雷射切割工具貫穿底部填充層UF、介電層DI、模塑層108以及重佈線層結構114的聚合物層，對半導體裝置進行單體化，以分離個別積體扇出式封裝10。
提供在將第二晶粒接合到第一晶粒之前執行雷射鑽孔製程的以上實施例是用於說明目的，且不應將其視爲限制本揭露內容。在替代實施例中，可省略雷射鑽孔製程以進一步簡化製程。
圖2A至圖2J是一種根據替代實施例形成積體扇出式封裝的方法的剖視圖。圖2A至圖2J所示的方法類似於圖1A至圖1J所示的方法。以下將進一步詳細地闡述所述實施例之間的區別。
參照圖2A，提供上面具有晶粒貼合膜DAF的載體C。具體來說，載體C設置有依序形成於其上面的剝離層DB、介電層DI以及晶粒貼合膜DAF。在一些實施例中，晶粒貼合膜DAF是覆蓋介電層DI的整個表面的毯覆式晶粒貼合膜。
參照圖2B，將一個或多個第一晶粒100放置在晶粒貼合膜DAF上。在一些實施例中，選取第一晶粒100並將第一晶粒100放置在位於載體C之上的晶粒貼合膜DAF上。之後，在第一晶粒100之上形成預模塑層107。具體來說，預模塑層107形成在晶粒貼合膜DAF的表面上並包封第一晶粒100的頂部及側壁。
參照圖2C及圖2D，對預模塑層107進行模塑，以形成其中具有一個或多個第一開口O1的模塑層108。在一些實施例中，第一開口O1穿透過模塑層108。在一些實施例中，將模塑機器的模具M按壓抵靠模塑層108，以在模塑層108中界定多個第一開口O1，如圖2C所示。模具M包括模具箱及從模具箱的表面突出的多個模具銷。在一些實施例中，模具銷的高度實質上等於或略大於模塑層108的高度，因此所形成的第一開口O1穿透模塑層108並與晶粒貼合膜DAF實體接觸。在模塑層108中形成第一開口O1之後，抬起模具M，如圖2D所示。
參照圖2E，在第一開口O1的表面上形成膠材料層109、晶種材料層110以及金屬材料層112。在一些實施例中，膠材料層109與模塑層108實體接觸，如圖2E所示。在替代實施例中，可省略形成膠材料層109的操作，並將晶種材料層110直接形成在模塑層108上。
參照圖2F，從第一晶粒100的前側或第一側研磨模塑層108，直到暴露出第一晶粒100的連接件104。
參照圖2G，在第一晶粒100的前側或第一側之上形成重佈線層結構114。之後，在重佈線層結構114之上形成凸塊116，並使凸塊116電性連接到重佈線層結構114。
參照圖2H，剝離載體C。在一些實施例中，剝離層DB在光的熱量下分解，然後載體C從第一晶粒100的背側或第二側分離。
之後，移除晶粒貼合膜DAF，以暴露出膠材料層109。在一些實施例中，移除操作包括執行乾蝕刻製程及濕蝕刻製程。在一些實施例中，在移除操作期間同時移除介電層DI。
然後，從第一晶粒100的背側或第二側執行處理，藉此移除被暴露出的膠材料層109及晶種材料層110，以暴露出第一開口O1中的金屬材料層112。在一些實施例中，所述處理包括電漿清潔製程、乾蝕刻製程等。
參照圖2I，從第一晶粒100的背側或第二側將第二晶粒200電性連接到或接合到第一晶粒100。具體來說，第二晶粒200利用凸塊206及積體扇出式穿孔TIV從第一晶粒100的背側接合到第一晶粒100。在一些實施例中，積體扇出式穿孔TIV中的每一個包括膠層109a、晶種層110a以及金屬層112a。晶種層110a位於膠層109a與金屬層112a之間。之後，形成底部填充層UF，以填充第一晶粒100與第二晶粒200之間的空間並環繞凸塊206。
參照圖2J，執行單體化製程以使積體扇出式封裝20（或在一些實施例中被稱爲PoP封裝）彼此分離。
以下參照圖1J及圖2J說明積體扇出式封裝的結構。積體扇出式封裝10/20包括第一晶粒100、至少一個積體扇出式穿孔TIV以及模塑層108。至少一個積體扇出式穿孔TIV位於第一晶粒100旁邊。在一些實施例中，積體扇出式穿孔TIV包括膠層109a、晶種層110a及金屬層112a。在替代實施例中，積體扇出式穿孔TIV包含晶種層110a及金屬層112a。在一些實施例中，膠層109a包含鈦系材料或鉭系材料，晶種層110a包含銅系材料，而金屬層112a包含銅系材料。模塑層108包封或環繞至少一個積體扇出式穿孔TIV的側壁及第一晶粒100的側壁。晶種層110a位於金屬層112a與模塑層108之間，並環繞金屬層112a的整個側壁。在一些實施例中，膠層109a位於晶種層110a與模塑層108之間並與晶種層110a及模塑層108實體接觸。在替代實施例中，晶種層110a位於金屬層112a與模塑層108之間，並與金屬層112a及模塑層108實體接觸。
在一些實施例中，模塑層108的表面不與至少一個積體扇出式穿孔TIV的表面齊平。在一些實施例中，模塑層108進一步覆蓋至少一個積體扇出式穿孔TIV的頂面的一部分，如圖1J所示。從另一個角度來看，模塑層108形成包圍積體扇出式穿孔TIV的邊緣部分的鈎狀結構，且可選的膠層109a及晶種層110a在積體扇出式穿孔TIV的邊緣部分附近具有轉折點。
在替代實施例中，模塑層108的表面與至少一個積體扇出式穿孔TIV的表面齊平，如圖2J所示。
積體扇出式封裝10/20進一步包括重佈線層結構114及第二晶粒200。重佈線層結構114位於第一晶粒100的前側或第一側且電性連接到第一晶粒100。第二晶粒200位於第一晶粒100的背側或第二側。第二晶粒200包括至少一個凸塊206，且經由至少一個積體扇出式穿孔TIV及至少一個凸塊206電性連接到或接合到第一晶粒100。在一些實施例中，至少一個凸塊206的一部分被模塑層108嵌置。具體來說，至少一個凸塊206延伸到模塑層108的一部分中，並電性連接到至少一個積體扇出式穿孔TIV的金屬層112a。在一些實施例中，至少一個積體扇出式穿孔TIV的橫截面積朝至少一個凸塊206逐漸減小。在替代實施例中，至少一個積體扇出式穿孔TIV的橫截面積實質上不變。
積體扇出式封裝10/20進一步包括底部填充層UF，所述底部填充層UF位於第一晶粒100與第二晶粒200之間及至少一個凸塊206周圍。在一些實施例中，晶粒貼合膜DAF位於第一晶粒100與底部填充層UF之間，如圖1J所示。可視情况在晶粒貼合膜DAF與底部填充層UF之間設置介電層DI。
在替代實施例中，在第一晶粒100與底部填充層UF之間不存在晶粒貼合膜，如圖2J所示。具體來說，底部填充層UF與模塑層108實體接觸，且在所述兩者之間不存在介電層。
鑒於以上內容，本揭露內容的TIV圖案（例如，如圖1E所示各自包括膠材料層109、晶種材料層110以及金屬材料層112的圖案）是藉由以下方式進行界定：利用具有TIV圖案銷的模具箱對模塑層進行模塑以在其中形成TIV開口圖案，然後在TIV開口中形成晶種層並鍍覆金屬層。藉由此種順序，可省略一些傳統操作，例如在鍍覆金屬層之前形成乾光阻膠膜條帶（dry resist film strip）的操作以及在鍍覆金屬層之後移除乾光阻膠膜條帶及位於下面的晶種層的操作。換句話說，在形成本揭露內容的TIV圖案期間不需要乾光阻膠膜。因此，顯著簡化了界定TIV圖案的製程，且大大減小了生産成本。
根據本揭露內容的一些實施例，一種積體扇出式封裝包括：第一晶粒、至少一個積體扇出式穿孔以及模塑層。所述至少一個積體扇出式穿孔位於所述第一晶粒旁邊且包括晶種層及金屬層。所述模塑層包封所述至少一個積體扇出式穿孔及所述第一晶粒。此外，所述晶種層環繞所述金屬層的側壁且位於所述金屬層與所述模塑層之間。
在本揭露內容的一些實施例中，所述至少一個集成扇出式穿孔進一步包括位於所述晶種層與所述模塑層之間的膠層。
在本揭露內容的一些實施例中，所述膠層包含鈦系材料或鉭系材料，且所述晶種層包含銅系材料。
在本揭露內容的一些實施例中，所述模塑層進一步覆蓋所述至少一個集成扇出式穿孔的表面的一部分。
在本揭露內容的一些實施例中，所述集成扇出式封裝進一步包括重佈線層結構以及第二晶粒。重佈線層結構位於所述第一晶粒的第一側且電性連接到所述第一晶粒。第二晶粒位於所述第一晶粒的與所述第一側相對的第二側，其中所述第二晶粒包括至少一個凸塊且經由所述至少一個集成扇出式穿孔及所述至少一個凸塊電性連接到所述第一晶粒。
在本揭露內容的一些實施例中，所述至少一個凸塊的一部分被所述模塑層嵌置。
在本揭露內容的一些實施例中，所述集成扇出式封裝進一步包括底部填充層，所述底部填充層位於所述第一晶粒與所述第二晶粒之間以及所述至少一個凸塊周圍，其中在所述第一晶粒與所述底部填充層之間具有晶粒貼合膜。
在本揭露內容的一些實施例中，所述集成扇出式封裝進一步包括底部填充層，所述底部填充層位於所述第一晶粒與所述第二晶粒之間以及所述至少一個凸塊周圍，其中在所述第一晶粒與所述底部填充層之間不存在晶粒貼合膜。
在本揭露內容的一些實施例中，所述底部填充層與所述模塑層實體接觸。
根據本揭露內容的替代實施例，一種形成積體扇出式封裝的方法包括以下操作。將第一晶粒放置在載體上。在所述第一晶粒上形成模塑層，其中在所述模塑層中形成至少一個第一開口且所述第一開口不穿透所述模塑層。在所述第一開口的表面上形成晶種材料層及金屬材料層。
在本揭露內容的一些實施例中，形成所述模塑層包括：在所述第一晶粒之上形成預模塑層；對所述預模塑層進行模塑，以形成其中具有所述至少一個第一開口的所述模塑層。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在形成所述晶種材料層及所述金屬材料層之後進一步包括：在所述第一晶粒的第一側之上形成重佈線層結構；剝離所述載體；以及將第二晶粒從所述第一晶粒的第二側接合到所述第一晶粒。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在形成所述晶種材料層及所述金屬材料層之後且在形成所述重佈線層結構之前進一步包括：從所述第一晶粒的所述第一側研磨所述模塑層，直到暴露出所述第一晶粒的至少一個連接件。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在剝離所述載體之後且在將所述第二晶粒接合到所述第一晶粒之前進一步包括：從所述第一晶粒的所述第二側對所述模塑層執行圖案化製程以形成與所述第一開口對應的第二開口，其中所述圖案化製程包括雷射鑽孔製程。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在形成所述晶種材料層及所述金屬材料層之前進一步包括在所述第一開口的所述表面上形成膠材料層。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在將所述第一晶粒放置在所述載體上之前進一步包括：在所述第一晶粒的所述第二側上形成晶粒貼合膜。
根據本揭露內容的另一些替代實施例，一種形成積體扇出式封裝的方法包括以下操作。提供載體，在所述載體上具有晶粒貼合膜。將第一晶粒放置在所述晶粒貼合膜上。在所述第一晶粒之上形成模塑層，其中在所述模塑層中形成至少一個第一開口，且所述第一開口穿透所述模塑層並與所述晶粒貼合膜實體接觸。在所述第一開口的表面上形成晶種材料層及金屬材料層。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在形成所述晶種材料層及所述金屬材料層之後，進一步包括：從所述第一晶粒的第一側研磨所述模塑層，直到暴露出所述第一晶粒的至少一個連接件；以及在所述第一晶粒的所述第一側上形成重佈線層結構。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法，進一步包括：移除所述晶粒貼合膜；從所述第一晶粒的第二側執行處理，直到暴露出所述第一開口中的所述金屬材料層，其中所述處理包括電漿清潔製程；以及將第二晶粒從所述第一晶粒的第二側接合到所述第一晶粒。
在本揭露內容的一些實施例中，所述形成集成扇出式封裝的方法在形成所述晶種材料層及所述金屬材料層之前，進一步包括：在所述第一開口的所述表面上形成膠材料層。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧積體扇出式封裝
20‧‧‧積體扇出式封裝
100‧‧‧第一晶粒
102‧‧‧基底
104‧‧‧連接件
106‧‧‧鈍化層
107‧‧‧預模塑層
108‧‧‧模塑層/材料層
109‧‧‧膠材料層
109a‧‧‧膠層
110‧‧‧晶種材料層
110a‧‧‧晶種層
112‧‧‧金屬材料層
112a‧‧‧金屬層
114‧‧‧重佈線層結構
116‧‧‧凸塊
200‧‧‧第二晶粒
202‧‧‧基底
204‧‧‧墊
206‧‧‧凸塊
C‧‧‧載體
DAF‧‧‧晶粒貼合膜
DB‧‧‧剝離層
DI‧‧‧介電層
M‧‧‧模具
O1‧‧‧第一開口
O2‧‧‧第二開口
TIV‧‧‧積體扇出式穿孔
UF‧‧‧底部填充層
圖1A至圖1J是一種根據一些實施例形成積體扇出式封裝的方法的剖視圖。 圖2A至圖2J是一種根據替代實施例形成積體扇出式封裝的方法的剖視圖。

Claims (1)

  1. 一種積體扇出式封裝，包括‧‧‧ 第一晶粒； 至少一個積體扇出式穿孔，位於所述第一晶粒旁邊且包括晶種層及金屬層；以及 模塑層，包封所述至少一個積體扇出式穿孔及所述第一晶粒， 其中所述晶種層環繞所述金屬層的側壁且位於所述金屬層與所述模塑層之間。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI756076B (zh) * 2019-03-04 2022-02-21 新加坡商Ｐｅｐ創新私人有限公司 晶片封裝結構

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
DE102018111389A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und Herstellungsverfahren
US11289426B2 (en) * 2018-06-15 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
CN109940285B (zh) * 2019-03-22 2020-10-16 苏州福唐智能科技有限公司 一种扇出形晶圆激光隐形切割方法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
KR20210082638A (ko) * 2019-12-26 2021-07-06 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
KR20210099244A (ko) * 2020-02-03 2021-08-12 삼성전자주식회사 반도체 장치 및 그의 제조 방법
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9500422B2 (en) * 2014-07-02 2016-11-22 Beretta Usa Corp. Gas operating system for small arms with spring loaded gas valve
US9449908B2 (en) * 2014-07-30 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package system and method
US9461192B2 (en) * 2014-12-16 2016-10-04 Sunpower Corporation Thick damage buffer for foil-based metallization of solar cells
TWI628757B (zh) * 2015-12-23 2018-07-01 力成科技股份有限公司 終極薄扇出型晶片封裝構造及其製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI756076B (zh) * 2019-03-04 2022-02-21 新加坡商Ｐｅｐ創新私人有限公司 晶片封裝結構

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