CN109103150A - 集成扇出式封装及其形成方法 - Google Patents
集成扇出式封装及其形成方法 Download PDFInfo
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- CN109103150A CN109103150A CN201710684019.6A CN201710684019A CN109103150A CN 109103150 A CN109103150 A CN 109103150A CN 201710684019 A CN201710684019 A CN 201710684019A CN 109103150 A CN109103150 A CN 109103150A
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- layer
- tube core
- fanned out
- integrated
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Abstract
本揭露实施例公开集成扇出式封装及其形成方法。一种集成扇出式封装包括:第一管芯、至少一个集成扇出式穿孔以及模制层。所述至少一个集成扇出式穿孔位于所述第一管芯旁边,且包括晶种层及金属层。所述模制层包封所述至少一个集成扇出式穿孔及所述第一管芯。此外,所述晶种层环绕所述金属层的侧壁,且位于所述金属层与所述模制层之间。
Description
技术领域
本揭露涉及集成扇出式封装及其形成方法。
背景技术
近年来,由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的持续提高,半导体行业经历了快速成长。在大多数情况下,集成密度的此种提高源自于最小特征大小的连续缩减,此使得能够在给定区域中集成更多组件。
这些较小的电子组件也需要与先前的封装相比占据较小区域的较小的封装。半导体的封装类型的实例包括方形扁平封装(quad flat package,QFP)、管脚网格阵列(pingrid array,PGA)封装、球网格阵列(ball grid array,BGA)封装、覆晶封装(flip chip,FC)、三维集成电路(three-dimensional integrated circuit,3DIC)、晶圆级封装(waferlevel package,WLP)及叠层封装(package on package,PoP)装置等。目前,集成扇出式封装因其致密性(compactness)而变得越来越受欢迎。然而,存在许多与集成扇出式封装相关的挑战。
发明内容
本揭露实施例的一种一种集成扇出式封装包括第一管芯、至少一个集成扇出式穿孔以及模制层。至少一个集成扇出式穿孔位于所述第一管芯旁边且包括晶种层及金属层。模制层包封所述至少一个集成扇出式穿孔及所述第一管芯。所述晶种层环绕所述金属层的侧壁且位于所述金属层与所述模制层之间。
本揭露实施例的一种形成集成扇出式封装的方法包括下列操作。将第一管芯放置在载体上。在所述第一管芯上形成模制层,其中在所述模制层中形成至少一个第一开口且所述第一开口不穿透所述模制层。在所述第一开口的表面上形成晶种材料层及金属材料层。
本揭露实施例的一种形成集成扇出式封装的方法包括下列操作。提供载体,在所述载体上具有管芯贴合膜。将第一管芯放置在所述管芯贴合膜上。在所述第一管芯之上形成模制层,其中在所述模制层中形成至少一个第一开口,且所述第一开口穿透所述模制层并与所述管芯贴合膜实体接触。在所述第一开口的表面上形成晶种材料层及金属材料层。
附图说明
图1A至图1J是一种根据一些实施例形成集成扇出式封装的方法的剖视图。
图2A至图2J是一种根据替代实施例形成集成扇出式封装的方法的剖视图。
[符号的说明]
10:集成扇出式封装
20:集成扇出式封装
100:第一管芯
102:衬底
104:连接件
106:钝化层
107:预模制层
108:模制层/材料层
109:胶材料层
109a:胶层
110:晶种材料层
110a:晶种层
112:金属材料层
112a:金属层
114:重布线层结构
116:凸块
200:第二管芯
202:衬底
204:垫
206:凸块
C:载体
DAF:管芯贴合膜
DB:剥离层
DI:介电层
M:模具
O1:第一开口
O2:第二开口
TIV:集成扇出式穿孔
UF:底部填充层
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及设置的具体实例的目的在于以简化方式传达本公开内容。当然,这些仅为实例且不旨在进行限制。举例来说,以下说明中将第二特征形成在第一特征“之上”或第一特征“上”可包括其中第二特征及第一特征被形成为直接接触的实施例,且也可包括其中第二特征与第一特征之间可形成有附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。此外,在本公开内容的各种实例中,可使用相同的参考编号及/或字母来指代相同或类似的部件。对参考编号的重复使用是出于简洁及清晰的目的,而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“位于…上(on)”、“位于…之上(over)”、“上方(above)”及“上部的(upper)”等空间相对性用语以便于阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向),且本文中所用的空间相对性描述语可同样相应地进行解释。
上述内容还可包括其他特征及工艺。举例来说,可包括测试结构以帮助进行三维(3D)封装或三维集成电路(3DIC)装置的验证测试。测试结构可包括例如形成于重布线层中或衬底上的测试垫,所述测试垫使得能够测试3D封装或3DIC、使用探针(probe)及/或探针卡(probe card)等。可对中间结构及最终结构执行验证测试。另外,本文中所公开的结构及方法可接合包含对已知良好管芯的中间验证的测试方法论一起使用,以提高产率(yield)及降低成本。
图1A至图1J是一种根据一些实施例形成集成扇出式封装的方法的剖视图。
参照图1A,提供一个或多个第一管芯100。在一些实施例中,第一管芯100中的每一个包括衬底102、一个或多个连接件104以及钝化层106。衬底102包括,但不限于,例如经掺杂或未经掺杂的块状硅或绝缘体上半导体(semiconductor-on-insulator,SOI)衬底的有源层。连接件104形成在第一管芯100的位于连接件104之下的垫,或互连结构(图中未示出)之上,并电连接到所述垫或互连结构。在一些实施例中,连接件104被形成为第一管芯100的顶部。连接件104从第一管芯100的其余部分或下部突出。在说明通篇中,第一管芯100的存在连接件104的侧被称为前侧或第一侧。连接件104可以是电连接件、虚设连接件或是电连接件与虚设连接件两者。连接件104可包括焊料凸块、金凸块、铜柱等,且是由置球工艺(ball drop process)或电镀工艺形成。钝化层106形成在第一管芯100之上以覆盖连接件104的顶部及侧壁,并填充连接件104之间的间隙。在一些实施例中,钝化层106包含感光性材料,例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)或其组合等,所述材料可利于以光刻掩模进行图案化。在替代实施例中,钝化层106包含氮化物(例如,氮化硅)、氧化物(例如,氧化硅)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicateglass,BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass,BPSG)或其组合等。
在一些实施例中,第一管芯100形成在晶圆台(wafer stage)中。在形成钝化层106之后,在第一管芯100的背侧或第二侧之上形成粘合层或毯覆式管芯贴合膜(blanket dieattach film)。然后利用锯片或激光切割工具沿切割区执行单体化工艺,以使第一管芯100彼此分离,且因此提供在其背侧上具有管芯贴合膜DAF的第一管芯100。
继续参照图1A,将一个或多个第一管芯100放置在载体C上。在一些实施例中,在选取第一管芯100并在将第一管芯100放置在载体C上之前,在第一管芯100的背侧或第二侧上形成管芯贴合膜DAF。载体C设置有剥离层DB及形成在剥离层DB上的介电层DI。载体C可以是坯料(blank)玻璃载体、坯料陶瓷载体等。剥离层DB可由例如紫外(UV)胶、光热转换(light-to-heat conversion,LTHC)胶等粘合剂形成,但也可使用其他类型的粘合剂。在一些实施例中,剥离层DB可在光的热量的作用下分解,从而使载体C从形成在其上面的结构分离。介电层DI形成在剥离层DB之上。在一些实施例中,介电层DI是聚合物层。聚合物包含例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、味之素增层膜(Ajinomoto Buildup Film,ABF)或阻焊膜(Solder Resist film,SR)等。介电层DI是通过例如旋转涂布、叠层或沉积等适当的制造技术而形成。在一些实施例中,第一管芯100中的每一个贴合到介电层DI,其中在第一管芯100与介电层DI之间设置有管芯贴合膜DAF。在替代实施例中,可省略形成介电层DI的操作,且第一管芯100中的每一个贴合到剥离层DB,其中在第一管芯100与剥离层DB之间设置有管芯贴合膜DAF。
之后,在第一管芯100之上形成预模制层107。具体来说,预模制层107形成在介电层DI的顶面上,并包封第一管芯100的顶部及侧壁。在一些实施例中,预模制层107包含模制化合物、模制底部填充、树脂等,例如环氧树脂。预模制层107可通过例如旋转涂布、叠层或沉积等适当的制造技术而形成。在一些实施例中,预模制层107包含感光性材料,例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)或其组合等。在替代实施例中,模制层108包含氮化物(例如,氮化硅)、氧化物(例如,氧化硅)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)或其组合等。
参照图1B及图1C,对预模制层107进行模制,以形成其中具有一个或多个第一开口O1的模制层108。在一些实施例中,第一开口O1不穿透模制层108。在一些实施例中,将模制机器的模具M按压抵靠模制层108,以在模制层108中界定多个第一开口O1,如图1B所示。模具M包括模具箱(mold chest)及从模具箱的接触表面突出的多个模具销(mold pin)。模具销的形状对应于随后形成的集成扇出式穿孔(TIV)的形状。在一些实施例中,模具M的模具销具有倾斜的侧壁。举例来说,模具销中的每一个的横截面积朝远离模具M的模具箱的方向逐渐减小。在替代实施例中,模具M的模具销具有垂直于模具箱的接触表面的实质上垂直的侧壁。在一些实施例中,模具销的高度小于模制层108的高度,因此所形成的第一开口O1不穿透模制层108。在模制层108中形成第一开口O1之后,抬起模具M,如图1C所示。具体来说,第一开口O1从第一管芯100的前侧向背侧延伸进入模制层108中。在一些实施例中,第一开口O1具有倾斜的侧壁。举例来说,第一开口O1中的每一个的横截面积朝第一管芯100的背侧或第二侧逐渐减小。在替代实施例中,第一开口O1具有垂直于模制层108的前表面的实质上垂直的侧壁。
在一些实施例中,在图1B所示的步骤期间,对模具M以及模制层108进行加热一段时间,以使模制层108半固化。在抬起模具M之后,如图1C所示,对半固化的模制层108进行加热另一段时间,以使材料层108充分固化。
参照图1D,在第一开口O1的表面上形成胶材料层109、晶种材料层110以及金属材料层112。具体来说,胶材料层109、晶种材料层110以及金属材料层112依序形成在模制层108之上,并覆盖第一开口O1的整个表面。在一些实施例中,胶材料层109有助于将模制层108粘合到随后形成的晶种材料层110。胶材料层109可包含钛系材料或钽系材料,例如钛、氮化钛、钽、氮化钽或其组合等,并可通过例如物理气相沉积(PVD)、化学气相沉积(CVD)、溅镀等工艺形成,但作为另一选择也可使用其他方法及材料。晶种材料层110可通过PVD、CVD、溅镀等来沉积,但作为另一选择也可使用其他方法。晶种材料层110可包含铜系材料(例如,铜、钛铜合金等),但作为另一选择也可使用其他材料(例如,镍、金)。金属材料层112可包含铜系材料(例如,铜、铜系合金等),但作为另一选择也可利用另一适当材料,例如镍、钛、铝等。金属材料层112可通过将铜电镀到晶种材料层110上而形成,但作为另一选择也可利用用于形成金属材料层112的任意适当的替代工艺。在一些实施例中,胶材料层109、晶种材料层110以及金属材料层112共同将第一开口O1完全填满。
在一些实施例中,胶材料层109与模制层108实体接触,如图1D所示。在替代实施例中,可省略形成胶材料层109的操作,并将晶种材料层110直接形成在模制层108上。
参照图1E,从第一管芯100的前侧或第一侧研磨模制层108,直到暴露出第一管芯100的连接件104。在一些实施例中,执行研磨工艺,以移除模制层108的一部分以及钝化层106的一部分。在研磨工艺期间,同时移除位于第一开口O1外部的部分胶材料层109、部分晶种材料层110的以及部分金属材料层112,以形成集成扇出式穿孔TIV。
参照图1F,在第一管芯100的第一侧之上形成重布线层结构114。在一些实施例中,重布线层结构114电连接到第一管芯100的连接件104以及第一开口O1中的金属材料层112。在通篇说明书中,重布线层结构114也可被称为“前侧重布线层结构”。在一些实施例中,重布线层结构114包括交替堆叠的多个聚合物层及多个重布线层。聚合物层或重布线层的数目不受本公开内容的限制。在一些实施例中,最顶端的重布线层也被称为用于安装球的球下金属(under-ball metallurgy,UBM)层。在一些实施例中,聚合物层中的每一层包含聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)或其组合等。在一些实施例中,重布线层中的每一层包含铜、镍、钛或其组合等,且是通过电镀工艺而形成。
之后,在重布线层结构114之上形成球或凸块116,并使球或凸块116电连接到重布线层结构114。在一些实施例中,凸块116是由具有低电阻率的导电性材料(例如,Sn、Pb、Ag、Cu、Ni、Bi或其合金)制成,且是通过例如蒸镀、镀覆、置球或网版印刷等适当的工艺而形成。
参照图1G,剥离载体C。在一些实施例中,将具有第一管芯100、模制层108、重布线层结构114以及凸块116的载体C翻转,剥离层DB在光的热量的作用下分解,然后载体C从第一管芯100的背侧或第二侧分离。
参照图1H及图1I,从第一管芯100的背侧或第二侧,将第二管芯200电连接到或接合到第一管芯100。在一些实施例中,第二管芯200中的每一个包括存储器装置或适当的半导体装置。如图1H所示,从第一管芯100的背侧或第二侧,对模制层108执行图案化工艺,以形成与第一开口O1对应的第二开口O2。在一些实施例中,在图案化工艺期间,同时移除部分的介电层DI、部分的胶材料层109以及部分的晶种材料层110。具体来说,第二开口O2穿透介电层DI、模制层108、胶材料层109以及晶种材料层110,并暴露出第一开口O1中的金属材料层112。在一些实施例中,所述图案化工艺包括激光钻孔工艺。在一些实施例中,在激光钻孔工艺之后,从第一管芯100的背侧或第二侧执行处理,借此移除由激光钻孔工艺造成的残余物及/或被暴露出的胶材料层109或晶种材料层110(如果未被激光钻孔工艺移除),以暴露出第一开口O1中的金属材料层112。在一些实施例中,所述处理包括等离子体清洁工艺、干蚀刻工艺等。
在一些实施例中,第二开口O2具有倾斜的侧壁。举例来说,第二开口O2中的每一个的横截面积朝第一管芯100的背侧或第二侧逐渐减小。在替代实施例中,第二开口O2具有垂直于模制层108的后表面的实质上垂直的侧壁。
之后,在第一管芯100的背侧或第二侧之上设置第二管芯200。在一些实施例中,第二管芯200中的每一个包括衬底202、多个垫204以及多个凸块206。第二管芯200从第一管芯100的背侧电连接到或接合到第一管芯100,其中凸块206填充到第二开口O2中。具体来说,第二管芯200的凸块206与介电层DI及模制层108中的第二开口O2对齐并填充到第二开口O2中,且接合到集成扇出式穿孔TIV。在一些实施例中,集成扇出式穿孔TIV中的每一个包括胶层109a、晶种层110a以及金属层112a。晶种层110a位于胶层109a与金属层112a之间。
之后,形成底部填充层UF,以填充第一管芯100与第二管芯200之间的空间并环绕凸块206。在一些实施例中,底部填充层UF包含模制化合物(例如,环氧树脂),并使用分配、注射及/或喷涂而形成。
参照图1J,执行单体化工艺,以使集成扇出式封装10(或在一些实施例中被称为PoP封装)彼此分离。在一些实施例中,使用锯片或激光切割工具贯穿底部填充层UF、介电层DI、模制层108以及重布线层结构114的聚合物层,对半导体装置进行单体化,以分离个别集成扇出式封装10。
提供在将第二管芯接合到第一管芯之前执行激光钻孔工艺的以上实施例是用于说明目的,且不应将其视为限制本公开内容。在替代实施例中,可省略激光钻孔工艺以进一步简化工艺。
图2A至图2J是一种根据替代实施例形成集成扇出式封装的方法的剖视图。图2A至图2J所示的方法类似于图1A至图1J所示的方法。以下将进一步详细地阐述所述实施例之间的区别。
参照图2A,提供上面具有管芯贴合膜DAF的载体C。具体来说,载体C设置有依序形成于其上面的剥离层DB、介电层DI以及管芯贴合膜DAF。在一些实施例中,管芯贴合膜DAF是覆盖介电层DI的整个表面的毯覆式管芯贴合膜。
参照图2B,将一个或多个第一管芯100放置在管芯贴合膜DAF上。在一些实施例中,选取第一管芯100并将第一管芯100放置在位于载体C之上的管芯贴合膜DAF上。之后,在第一管芯100之上形成预模制层107。具体来说,预模制层107形成在管芯贴合膜DAF的表面上并包封第一管芯100的顶部及侧壁。
参照图2C及图2D,对预模制层107进行模制,以形成其中具有一个或多个第一开口O1的模制层108。在一些实施例中,第一开口O1穿透过模制层108。在一些实施例中,将模制机器的模具M按压抵靠模制层108,以在模制层108中界定多个第一开口O1,如图2C所示。模具M包括模具箱及从模具箱的表面突出的多个模具销。在一些实施例中,模具销的高度实质上等于或略大于模制层108的高度,因此所形成的第一开口O1穿透模制层108并与管芯贴合膜DAF实体接触。在模制层108中形成第一开口O1之后,抬起模具M,如图2D所示。
参照图2E,在第一开口O1的表面上形成胶材料层109、晶种材料层110以及金属材料层112。在一些实施例中,胶材料层109与模制层108实体接触,如图2E所示。在替代实施例中,可省略形成胶材料层109的操作,而将晶种材料层110直接形成在模制层108上。
参照图2F,从第一管芯100的前侧或第一侧研磨模制层108,直到暴露出第一管芯100的连接件104。
参照图2G,在第一管芯100的前侧或第一侧之上形成重布线层结构114。之后,在重布线层结构114之上形成凸块116,并使凸块116电连接到重布线层结构114。
参照图2H,剥离载体C。在一些实施例中,剥离层DB在光的热量的作用下分解,然后载体C从第一管芯100的背侧或第二侧分离。
之后,移除管芯贴合膜DAF,以暴露出胶材料层109。在一些实施例中,移除操作包括执行干蚀刻工艺及湿蚀刻工艺。在一些实施例中,在移除操作期间同时移除介电层DI。
然后,从第一管芯100的背侧或第二侧执行处理,借此移除被暴露出的胶材料层109及晶种材料层110,以暴露出第一开口O1中的金属材料层112。在一些实施例中,所述处理包括等离子体清洁工艺、干蚀刻工艺等。
参照图2I,从第一管芯100的背侧或第二侧,将第二管芯200电连接到或接合到第一管芯100。具体来说,第二管芯200利用凸块206及集成扇出式穿孔TIV从第一管芯100的背侧接合到第一管芯100。在一些实施例中,集成扇出式穿孔TIV中的每一个包括胶层109a、晶种层110a以及金属层112a。晶种层110a位于胶层109a与金属层112a之间。之后,形成底部填充层UF,以填充第一管芯100与第二管芯200之间的空间并环绕凸块206。
参照图2J,执行单体化工艺,以使集成扇出式封装20(或在一些实施例中被称为PoP封装)彼此分离。
以下参照图1J及图2J说明集成扇出式封装的结构。集成扇出式封装10/20包括第一管芯100、至少一个集成扇出式穿孔TIV以及模制层108。至少一个集成扇出式穿孔TIV位于第一管芯100旁边。在一些实施例中,集成扇出式穿孔TIV包括胶层109a、晶种层110a及金属层112a。在替代实施例中,集成扇出式穿孔TIV包含晶种层110a及金属层112a。在一些实施例中,胶层109a包含钛系材料或钽系材料,晶种层110a包含铜系材料,而金属层112a包含铜系材料。模制层108包封或环绕至少一个集成扇出式穿孔TIV的侧壁及第一管芯100的侧壁。晶种层110a位于金属层112a与模制层108之间,并环绕金属层112a的整个侧壁。在一些实施例中,胶层109a位于晶种层110a与模制层108之间,并与晶种层110a及模制层108实体接触。在替代实施例中,晶种层110a位于金属层112a与模制层108之间,并与金属层112a及模制层108实体接触。
在一些实施例中,模制层108的表面不与至少一个集成扇出式穿孔TIV的表面齐平。在一些实施例中,模制层108进一步覆盖至少一个集成扇出式穿孔TIV的顶面的一部分,如图1J所示。从另一个角度来看,模制层108形成包围集成扇出式穿孔TIV的边缘部分的钩状结构,且可选的胶层109a及晶种层110a在集成扇出式穿孔TIV的边缘部分附近具有转折点。
在替代实施例中,模制层108的表面与至少一个集成扇出式穿孔TIV的表面齐平,如图2J所示。
集成扇出式封装10/20进一步包括重布线层结构114及第二管芯200。重布线层结构114位于第一管芯100的前侧或第一侧,且电连接到第一管芯100。第二管芯200位于第一管芯100的背侧或第二侧。第二管芯200包括至少一个凸块206,且经由至少一个集成扇出式穿孔TIV及至少一个凸块206电连接到或接合到第一管芯100。在一些实施例中,至少一个凸块206的一部分被模制层108嵌置。具体来说,至少一个凸块206延伸到模制层108的一部分中,并电连接到至少一个集成扇出式穿孔TIV的金属层112a。在一些实施例中,至少一个集成扇出式穿孔TIV的横截面积朝至少一个凸块206逐渐减小。在替代实施例中,至少一个集成扇出式穿孔TIV的横截面积实质上不变。
集成扇出式封装10/20进一步包括底部填充层UF,所述底部填充层UF位于第一管芯100与第二管芯200之间及至少一个凸块206周围。在一些实施例中,管芯贴合膜DAF位于第一管芯100与底部填充层UF之间,如图1J所示。可视情况在管芯贴合膜DAF与底部填充层UF之间设置介电层DI。
在替代实施例中,在第一管芯100与底部填充层UF之间不存在管芯贴合膜,如图2J所示。具体来说,底部填充层UF与模制层108实体接触,且在所述两者之间不存在介电层。
鉴于以上内容,本公开内容的TIV图案(例如,如图1E所示各自包括胶材料层109、晶种材料层110以及金属材料层112的图案)是通过以下方式进行界定:利用具有TIV图案销的模具箱对模制层进行模制,以在其中形成TIV开口图案,然后在TIV开口中形成晶种层并镀覆金属层。通过此种顺序,可省略一些传统操作,例如在镀覆金属层之前形成干光刻胶膜条带(dry resist film strip)的操作以及在镀覆金属层之后移除干光刻胶膜条带及位于下面的晶种层的操作。换句话说,在形成本公开内容的TIV图案期间不需要干光刻胶膜。因此,显著简化了界定TIV图案的工艺,且大大减小了生产成本。
根据本公开内容的一些实施例,一种集成扇出式封装包括:第一管芯、至少一个集成扇出式穿孔以及模制层。所述至少一个集成扇出式穿孔位于所述第一管芯旁边且包括晶种层及金属层。所述模制层包封所述至少一个集成扇出式穿孔及所述第一管芯。此外,所述晶种层环绕所述金属层的侧壁且位于所述金属层与所述模制层之间。
在本公开内容的一些实施例中,所述至少一个集成扇出式穿孔进一步包括位于所述晶种层与所述模制层之间的胶层。
在本公开内容的一些实施例中,所述胶层包含钛系材料或钽系材料,且所述晶种层包含铜系材料。
在本公开内容的一些实施例中,所述模制层进一步覆盖所述至少一个集成扇出式穿孔的表面的一部分。
在本公开内容的一些实施例中,所述集成扇出式封装进一步包括重布线层结构以及第二管芯。重布线层结构位于所述第一管芯的第一侧且电连接到所述第一管芯。第二管芯位于所述第一管芯的与所述第一侧相对的第二侧,其中所述第二管芯包括至少一个凸块且经由所述至少一个集成扇出式穿孔及所述至少一个凸块电连接到所述第一管芯。
在本公开内容的一些实施例中,所述至少一个凸块的一部分被所述模制层嵌置。
在本公开内容的一些实施例中,所述集成扇出式封装进一步包括底部填充层,所述底部填充层位于所述第一管芯与所述第二管芯之间以及所述至少一个凸块周围,其中在所述第一管芯与所述底部填充层之间具有管芯贴合膜。
在本公开内容的一些实施例中,所述集成扇出式封装进一步包括底部填充层,所述底部填充层位于所述第一管芯与所述第二管芯之间以及所述至少一个凸块周围,其中在所述第一管芯与所述底部填充层之间不存在管芯贴合膜。
在本公开内容的一些实施例中,所述底部填充层与所述模制层实体接触。
根据本公开内容的替代实施例,一种形成集成扇出式封装的方法包括以下操作。将第一管芯放置在载体上。在所述第一管芯上形成模制层,其中在所述模制层中形成至少一个第一开口且所述第一开口不穿透所述模制层。在所述第一开口的表面上形成晶种材料层及金属材料层。
在本公开内容的一些实施例中,形成所述模制层包括:在所述第一管芯之上形成预模制层;对所述预模制层进行模制,以形成其中具有所述至少一个第一开口的所述模制层。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在形成所述晶种材料层及所述金属材料层之后进一步包括:在所述第一管芯的第一侧之上形成重布线层结构;剥离所述载体;以及将第二管芯从所述第一管芯的第二侧接合到所述第一管芯。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在形成所述晶种材料层及所述金属材料层之后且在形成所述重布线层结构之前进一步包括:从所述第一管芯的所述第一侧研磨所述模制层,直到暴露出所述第一管芯的至少一个连接件。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在剥离所述载体之后且在将所述第二管芯接合到所述第一管芯之前进一步包括:从所述第一管芯的所述第二侧对所述模制层执行图案化工艺以形成与所述第一开口对应的第二开口,其中所述图案化工艺包括激光钻孔工艺。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在形成所述晶种材料层及所述金属材料层之前进一步包括在所述第一开口的所述表面上形成胶材料层。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在将所述第一管芯放置在所述载体上之前进一步包括:在所述第一管芯的所述第二侧上形成管芯贴合膜。
根据本公开内容的另一些替代实施例,一种形成集成扇出式封装的方法包括以下操作。提供载体,在所述载体上具有管芯贴合膜。将第一管芯放置在所述管芯贴合膜上。在所述第一管芯之上形成模制层,其中在所述模制层中形成至少一个第一开口,且所述第一开口穿透所述模制层并与所述管芯贴合膜实体接触。在所述第一开口的表面上形成晶种材料层及金属材料层。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在形成所述晶种材料层及所述金属材料层之后,进一步包括:从所述第一管芯的第一侧研磨所述模制层,直到暴露出所述第一管芯的至少一个连接件;以及在所述第一管芯的所述第一侧之上形成重布线层结构。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法,进一步包括:移除所述管芯贴合膜;从所述第一管芯的第二侧执行处理,直到暴露出所述第一开口中的所述金属材料层,其中所述处理包括等离子体清洁工艺;以及将第二管芯从所述第一管芯的第二侧接合到所述第一管芯。
在本公开内容的一些实施例中,所述形成集成扇出式封装的方法在形成所述晶种材料层及所述金属材料层之前进一步包括:在所述第一开口的所述表面上形成胶材料层。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知,其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明的精神及范围,而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (1)
1.一种集成扇出式封装,其特征在于,包括:
第一管芯;
至少一个集成扇出式穿孔,位于所述第一管芯旁边且包括晶种层及金属层;以及
模制层,包封所述至少一个集成扇出式穿孔及所述第一管芯,
其中所述晶种层环绕所述金属层的侧壁且位于所述金属层与所述模制层之间。
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US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US20130307153A1 (en) | 2012-05-18 | 2013-11-21 | International Business Machines Corporation | Interconnect with titanium-oxide diffusion barrier |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9500422B2 (en) * | 2014-07-02 | 2016-11-22 | Beretta Usa Corp. | Gas operating system for small arms with spring loaded gas valve |
US9449908B2 (en) * | 2014-07-30 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package system and method |
US9461192B2 (en) * | 2014-12-16 | 2016-10-04 | Sunpower Corporation | Thick damage buffer for foil-based metallization of solar cells |
TWI628757B (zh) * | 2015-12-23 | 2018-07-01 | 力成科技股份有限公司 | 終極薄扇出型晶片封裝構造及其製造方法 |
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TW201906115A (zh) | 2019-02-01 |
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