CN110707075A - 超高密度多芯片模组的三维扇出型封装结构与制备方法 - Google Patents
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Abstract
本发明涉及一种超高密度多芯片模组的三维扇出型封装结构,包括被第一塑封体塑封的器件芯片,器件芯片的引脚外露出第一塑封体,器件芯片靠近第一塑封体外围的引脚与第二塑封体内的金属互联柱连接,器件芯片靠近第一塑封体中心的引脚与第二塑封体内的互联芯片连接,互联芯片被第二塑封体完全包裹,金属互联柱外露出第二塑封体,第二塑封体远离第一塑封体的一侧设有和外露的金属互联柱适配的重新布线层,重新布线层远离第二塑封体的一侧设置锡球。本发明还公开了此种超高密度多芯片模组的三维扇出型封装结构的制备方法。采用本发明的设计方案,实现了对具有超精细引脚结构的高密度芯片进行扇出型集成封装的工艺结构。
Description
技术领域
本发明涉及半导体封装技术领域,具体涉及一种超高密度多芯片模组的三维扇出型封装结构及其制备方法。
背景技术
随着大数据(Big data)和人工智能(AI)时代的到来,应用于此类相关领域的芯片所要传输和高速交互处理的数据量非常巨大,该类芯片通常具有数量巨大的pad引脚(几百甚至上千个)、超精细的引脚大小和间距(只有几个微米),在把不同芯片之间的引脚进行互联时要求互联路径尽可能短从而实现低延时、低功耗,这就要求互联走线的精度要比较高(尽可能小的线宽、线距)才行。
另一方面,广泛使用的各种移动互联终端(例如手机或其它数据处理终端)又朝着小型化和多功能化的方向发展,如何将多个不同种类的高密度芯片集成封装在一起构成一个功能强大且体积功耗又比较小的模组,是芯片先进封装领域的一大挑战。
目前针对此类超高密度芯片的多芯片集成封装,由于封装基板(substrate或者PCB)的工艺精度较低,无法实现对仅有几个微米大小间距的引脚之间的引出与互联,或者存在互联路径较长的缺点,所以通常都是通过硅穿孔(TSV)、硅转接板(Si interposer)等方式进行,通过它们把各个芯片的超精细引脚进行引出和有效互联从而形成一个功能模块,但该技术的成本比较高。目前较为流行的扇出型封装技术,是采用在重构晶圆(reconwafer)上制作RDL重新布线层的方式来实现芯片的封装,为多芯片的集成封装提供了很好的平台,但是在目前现有的传统扇出型封装技术中(例如eWLB),RDL重新布线层通常是在重构晶圆上来制作完成,所以其布线精度有限,无法对超高密度芯片中大量的只有几个微米间距的非常精细的引脚进行互联(或者引脚之间的互联引线比较长,从而导致较高的延时和损耗等缺陷),或者由于布线精度有限从而使得封装体的面积较大,而且存在工序繁多、可靠性不高等一些问题。
发明内容
发明目的:本发明的目的在于解决现有的三维扇出型封装结构无法应用于超高密度多芯片模组的问题。
技术方案:为解决上述问题,本发明采用以下技术方案:
一种超高密度多芯片模组的三维扇出型封装结构,包括被第一塑封体塑封的器件芯片,器件芯片的引脚外露出第一塑封体,器件芯片靠近第一塑封体外围的引脚与第二塑封体内的金属互联柱连接,器件芯片靠近第一塑封体中心的引脚与第二塑封体内的互联芯片连接,互联芯片被第二塑封体完全包裹,金属互联柱外露出第二塑封体,第二塑封体远离第一塑封体的一侧设有和外露的金属互联柱适配的重新布线层,重新布线层远离第二塑封体的一侧设置锡球。
进一步地,互联芯片所引出的微铜柱外露出第二塑封体,且外露出的互联芯片微铜柱和外露出第一塑封体的器件芯片引脚适配连接。
进一步地,器件芯片每一个引脚都跟至少一个金属互联柱相连接。
一种超高密度多芯片模组的三维扇出型封装结构的制备方法,包括以下步骤:
1)在临时载片的上表面涂覆一层临时键合胶层;
2)在临时键合胶层上贴装需要进行互联和封装的器件芯片,器件芯片的器件面朝向临时键合胶层;
3)然后对贴装好的器件芯片进行塑封,形成第一塑封体;
4)对第一塑封体远离临时载片的一侧进行减薄,使器件芯片背部的引脚裸露出来;
5)对于器件芯片上靠近第一塑封体外围的引脚,在第一塑封体上使用光刻加上金属电镀的方法制作金属互联柱;
金属互联柱的高度通常为50~150um左右。
6)在器件芯片靠近第一塑封体中心的引脚处继续贴装互联芯片,互联芯片的引脚和器件芯片的引脚适配;
器件芯片上的引脚分为两类:一类是需要与其它芯片的引脚进行互联以实现特定功能,这类引脚通常分布在芯片的外围区域,增加了互联芯片的设计,使得引脚间进行互联时互联路径更短,以达到低功耗、低延时的目的;剩余的其它引脚是需要进行引出并成为模组的最终对外引脚的,故采用金属互联柱引出即可。
7)把互联芯片贴装在塑封有器件芯片的第一塑封体上之后,互联芯片的微铜柱与所要封装的器件芯片的引脚一一对应,形成互联;
8)对贴装好的互联芯片和制作好的金属互联柱进行塑封,形成第二塑封体;
9)对第二塑封体表面研磨,直至第二塑封体内的金属互联柱裸露出来;
10)使用常规的扇出工艺里面的重新布线方法制作重新布线层,把裸露出的金属互联柱引出到相应的位置形成焊盘或者形成互联;
11)在重新布线层的焊盘引出的金属衬垫处放置锡球;
12)采用激光或热剥离的办法将临时载片与其上的封装体分离,并去除临时键合胶。
进一步地,所述步骤6)中,互联芯片的制备具体包括以下步骤:
6.1)在Si硅晶圆上用化学气相沉积或者等离子化学气相沉积的方法沉积一层第一介电层;
第一介电层为无机介电层。
6.2)在第一介电层上面涂覆一层第一光刻胶层;
6.3)对第一光刻胶层进行曝光显影,在指定区域的第一光刻胶层上形成足够深的第一凹槽直至第一介电层裸露在第一光刻胶层的第一凹槽内;
6.4)在第一光刻胶层的第一凹槽处,使用等离子干法刻蚀或者湿法刻蚀的方法对裸露出来的第一介电层进行刻蚀形成第二凹槽;
6.5)使用干法或者湿法刻蚀的方法去除第一光刻胶层;
6.6)在第二凹槽内使用等离子体气相沉积加上电镀的方法沉积一层金属铜;
金属铜的厚度比第一介电层上第二凹槽凹槽的深度大。
6.7)使用化学机械抛光的方法对金属铜进行研磨,直至金属铜下方的第二凹槽区域以外的第一介电层裸露出来,研磨之后金属铜的上表面和第二凹槽以外区域的第一介电层上表面位于同一个水平面;
6.8)重复6.1~6.7,增加新的第一介电层,在对应于外露金属铜的位置构建新的凹槽,使得上下介电层互联;
根据实际需要,用相同的方法可以继续制作更多层的第一介电层和金属层以便实现线路间的互联。
6.9)在器件芯片表面沉积钝化层,用以保护已经制作完成的布线层,并在钝化层相应的位置进行光刻开孔,以使钝化层下方的金属铜裸露出来;
钝化层通常为SiN以及聚合物等有机介电材料。
6.10)在钝化层开孔处使用光刻加上电镀的工艺方法制作外露出钝化层的微铜柱。
进一步地,所述步骤6.6)中,在沉积铜之前,常常先沉积一层很薄的金属钛或者钛钨作为衬垫层以改善金属铜的粘附性。
进一步地,所述步骤9)中,金属互联柱的高度大于互联芯片的厚度,使得当金属互联柱裸露出来时互联芯片的上表面仍然在第二塑封体内。
互联芯片的厚度通常为40~130um,该厚度略小于金属互联柱的高度,互联芯片上面的微铜柱的间距可以做到几个微米甚至更小。
进一步地,所述步骤10)中,重新布线层的制备具体包括以下步骤:
10.1)在第二塑封体上使用旋涂的方法涂覆一层第二介电层,图中的为第二塑封体;
10.2)在第二介电层相应的位置处进行曝光和显影的光刻工艺,使第二介电层下方的金属互联柱裸露出来;
10.3)在第二介电层上使用物理气相沉积的方法沉积一层金属种子层;
10.4)在金属种子层上涂覆一层第二光刻胶层,并进行曝光和显影,在第二光刻胶层上开槽,把需要引出的引脚焊盘和布线区域的金属种子层裸露出来;
10.5)继续进行金属电镀工艺,在第二光刻胶层开槽的区域形成重新布线层;
10.6)采用湿法刻蚀的方法去除第二光刻胶层以及底部的金属种子层。
根据实际需要,如果需要更多层的重新布线层,可以重复10.1至10.6的工艺步骤。
有益效果:本发明与现有技术相比:
1)本发明实现了对具有超精细引脚结构(引脚大小与间距只有几个微米)的高密度芯片进行扇出型集成封装的工艺结构,弥补了目前常规的扇出型封装技术(如eWLB)在该方面的不足,扩展了扇出型封装技术的应用范围和领域;
2)对于具有超精细结构引脚的多芯片的集成封装,无需使用硅穿孔(TSV)、硅装接板(interposer)等高成本的复杂结构,提高了封装集成度,对于5G、AI等高密度芯片的应用场景尤为适合;
3)该封装方式简化了多芯片三维集成封装的工艺制程,提供了高密度芯片集成封装的新的结构和工艺方案。
附图说明
图1为本发明的结构示意图;
图2为本发明步骤1)结束后的结构示意图;
图3为本发明步骤2)结束后的结构示意图;
图4为本发明步骤3)结束后的结构示意图;
图5为本发明步骤4)结束后的结构示意图;
图6为本发明步骤5)结束后的结构示意图;
图7为本发明步骤6.1)结束后的结构示意图;
图8为本发明步骤6.2)结束后的结构示意图;
图9为本发明步骤6.3)结束后的结构示意图;
图10为本发明步骤6.4)结束后的结构示意图;
图11为本发明步骤6.5)结束后的结构示意图;
图12为本发明步骤6.6)结束后的结构示意图;
图13为本发明步骤6.7)结束后的结构示意图;
图14为本发明步骤6.8)结束后的结构示意图;
图15为本发明步骤6.9)结束后的结构示意图;
图16为本发明步骤6.10)结束后的结构示意图;
图17为本发明步骤7)结束后的结构示意图;
图18为本发明步骤8)结束后的结构示意图;
图19为本发明步骤9)结束后的结构示意图;
图20为本发明步骤10)结束后的结构示意图;
图21为本发明步骤10.1)结束后的结构示意图;
图22为本发明步骤10.2)结束后的结构示意图;
图23为本发明步骤10.3)结束后的结构示意图;
图24为本发明步骤10.4)结束后的结构示意图;
图25为本发明步骤10.5)结束后的结构示意图;
图26为本发明步骤10.6)结束后的结构示意图;
图27为本发明步骤11)结束后的结构示意图。
具体实施方式
下面结合附图和实施例对本发明进行进一步地说明。
实施例1
如图1所示,
一种超高密度多芯片模组的三维扇出型封装结构,包括被第一塑封体4塑封的器件芯片3,器件芯片3的引脚外露出第一塑封体4,器件芯片3靠近第一塑封体4外围的引脚与第二塑封体8内的金属互联柱6连接,器件芯片3靠近第一塑封体4中心的引脚与第二塑封体内8的互联芯片7连接,互联芯片7被第二塑封体8完全包裹,金属互联柱6外露出第二塑封体8,第二塑封体8远离第一塑封体4的一侧设有和外露的金属互联柱6适配的重新布线层9,重新布线层9远离第二塑封体8的一侧设置锡球10。
互联芯片7所引出的微铜柱707外露出第二塑封体8,且外露出的互联芯片7微铜柱和外露出第一塑封体4的器件芯片3引脚适配连接。
器件芯片3每一个引脚都跟至少一个金属互联柱6相连接。
实施例2
一种超高密度多芯片模组的三维扇出型封装结构的制备方法,包括以下步骤:
1)如图2所示,在临时载片1的上表面涂覆一层临时键合胶层2;
2)如图3所示,在临时键合胶层2上贴装需要进行互联和封装的器件芯片3,器件芯片3的器件面朝向临时键合胶层2;
3)如图4所示,然后对贴装好的器件芯片3进行塑封,形成第一塑封体4;
4)如图5所示,对第一塑封体4远离临时载片1的一侧进行减薄,使器件芯片3背部的引脚裸露出来;
5)如图6所示,对于器件芯片3上靠近第一塑封体4外围的引脚,在第一塑封体4上使用光刻加上金属电镀的方法制作金属互联柱6;
金属互联柱的高度通常为50~150um左右。
6)在器件芯片3靠近第一塑封体4中心的引脚处继续贴装互联芯片7,互联芯片7的引脚和器件芯片3的引脚适配;
器件芯片上的引脚分为两类:一类是需要与其它芯片的引脚进行互联以实现特定功能,这类引脚通常分布在芯片的外围区域,增加了互联芯片的设计,使得引脚间进行互联时互联路径更短,以达到低功耗、低延时的目的;剩余的其它引脚是需要进行引出并成为模组的最终对外引脚的,故采用金属互联柱引出即可。
互联芯片的制备具体包括以下步骤:
6.1)如图7所示,在Si硅晶圆上用化学气相沉积或者等离子化学气相沉积的方法沉积一层第一介电层701;
6.2)如图8所示,在第一介电层701上面涂覆一层第一光刻胶层702;
6.3)如图9所示,对第一光刻胶层702进行曝光显影,在指定区域的第一光刻胶层上形成足够深的第一凹槽直至第一介电层裸露在第一光刻胶的第一凹槽内;
6.4)如图10所示,在第一光刻胶层的第一凹槽处,使用等离子干法刻蚀或者湿法刻蚀的方法对裸露出来的第一介电层进行刻蚀形成第二凹槽;
6.5)如图11所示,使用干法或者湿法刻蚀的方法去除第一光刻胶层;
6.6)如图12所示,在第二凹槽内使用等离子体气相沉积加上电镀的方法沉积一层金属铜703;
在沉积铜之前,常常先沉积一层很薄的金属钛或者钛钨作为衬垫层以改善金属铜的粘附性。
金属铜的厚度比第一介电层上第二凹槽凹槽的深度大。
6.7)如图13所示,使用化学机械抛光的方法对金属铜703进行研磨,直至金属铜703下方的第二凹槽区域以外的第一介电层701裸露出来,研磨之后金属铜703的上表面和第二凹槽以外区域的第一介电层701上表面位于同一个水平面;
6.8)如图14所示,重复6.1~6.7,添加新的第一介电层,在对应于外露金属铜的位置构建新的凹槽,使得上下介电层互联;
根据实际需要,用相同的方法可以继续制作更多层的介电层和金属层以便实现线路间的互联。
6.9)如图15所示,在器件芯片表面沉积钝化层706,用以保护已经制作完成的布线层,并在钝化层706相应的位置进行光刻开孔,以使钝化层706下方的金属铜裸露出来;
钝化层通常为SiN以及聚合物等有机介电材料。
6.10)如图16所示,在钝化层706开孔处使用光刻加上电镀的工艺方法制作外露出钝化层706的微铜柱,图中采用标号707A,707B,707C和707D代表4个微铜柱,分别对应于器件芯片的引脚标号301A,301B,301C和301D。
7)如图17所示,把互联芯片7贴装在塑封有器件芯片3的第一塑封体4上之后,互联芯片7的微铜柱707与所要封装的器件芯片3的引脚一一对应,形成互联;
8)如图18所示,对贴装好的互联芯片7和制作好的金属互联柱6进行塑封,形成第二塑封体8;
9)如图19所示,对第二塑封体8表面研磨,直至第二塑封体8内的金属互联柱6裸露出来;
金属互联柱的高度大于互联芯片的厚度,使得当金属互联柱裸露出来时互联芯片的上表面仍然在第二塑封体内。
互联芯片的厚度通常为40~130um,该厚度略小于金属互联柱的高度,互联芯片上面的微铜柱的间距可以做到几个微米甚至更小。
10)如图20所示,使用常规的扇出工艺里面的重新布线方法制作重新布线层9,把裸露出的金属互联柱6引出到相应的位置形成焊盘或者形成互联;
重新布线层的制备具体包括以下步骤:
10.1)如图21所示,在第二塑封体8上使用旋涂的方法涂覆一层第二介电层901,图中的为第二塑封体8;
10.2)如图22所示,在第二介电层901相应的位置处进行曝光和显影的光刻工艺,使第二介电层901下方的金属互联柱6裸露出来;
10.3)如图23所示,在第二介电层901上使用物理气相沉积的方法沉积一层金属种子层902;
10.4)如图24所示,在金属种子层902上涂覆一层第二光刻胶层903,并进行曝光和显影,在第二光刻胶层903上开槽,把需要引出的引脚焊盘和布线区域的金属种子层902裸露出来;
10.5)如图25所示,继续进行金属电镀工艺,在第二光刻胶层903开槽的区域形成重新布线层9;
10.6)如图26所示,采用湿法刻蚀的方法去除第二光刻胶层903以及底部的金属种子层902。
根据实际需要,如果需要更多层的重新布线层,可以重复10.1至10.6的工艺步骤。
11)如图27所示,在重新布线层9的焊盘引出的金属衬垫处放置锡球10;
12)采用激光或热剥离的办法将临时载片1与其上的封装体分离,并去除临时键合胶2,得到成品,如图1所示。
Claims (8)
1.一种超高密度多芯片模组的三维扇出型封装结构,其特征在于:包括被第一塑封体塑封的器件芯片,器件芯片的引脚外露出第一塑封体,器件芯片靠近第一塑封体外围的引脚与第二塑封体内的金属互联柱连接,器件芯片靠近第一塑封体中心的引脚与第二塑封体内的互联芯片连接,互联芯片被第二塑封体完全包裹,金属互联柱外露出第二塑封体,第二塑封体远离第一塑封体的一侧设有和外露的金属互联柱适配的重新布线层,重新布线层远离第二塑封体的一侧设置锡球。
2.根据权利要求1所述的超高密度多芯片模组的三维扇出型封装结构,其特征在于:互联芯片所引出的微铜柱外露出第二塑封体,且外露出的互联芯片微铜柱和外露出第一塑封体的器件芯片引脚适配连接。
3.根据权利要求1所述的超高密度多芯片模组的三维扇出型封装结构,其特征在于:器件芯片每一个引脚都跟至少一个金属互联柱相连接。
4.一种如权利要求1所述的超高密度多芯片模组的三维扇出型封装结构的制备方法,其特征在于:包括以下步骤:
1)在临时载片的上表面涂覆一层临时键合胶层;
2)在临时键合胶层上贴装需要进行互联和封装的器件芯片,器件芯片的器件面朝向临时键合胶层;
3)然后对贴装好的器件芯片进行塑封,形成第一塑封体;
4)对第一塑封体远离临时载片的一侧进行减薄,使器件芯片背部的引脚裸露出来;
5)对于器件芯片上靠近第一塑封体外围的引脚,在第一塑封体上使用光刻加上金属电镀的方法制作金属互联柱;
6)在器件芯片靠近第一塑封体中心的引脚处继续贴装互联芯片,互联芯片的引脚和器件芯片的引脚适配;
7)把互联芯片贴装在塑封有器件芯片的第一塑封体上之后,互联芯片的微铜柱与所要封装的器件芯片的引脚一一对应,形成互联;
8)对贴装好的互联芯片和制作好的金属互联柱进行塑封,形成第二塑封体;
9)对第二塑封体表面研磨,直至第二塑封体内的金属互联柱裸露出来;
10)使用常规的扇出工艺里面的重新布线方法制作重新布线层,把裸露出的金属互联柱引出到相应的位置形成焊盘或者形成互联;
11)在重新布线层的焊盘引出的金属衬垫处放置锡球;
12)采用激光或热剥离的办法将临时载片与其上的封装体分离,并去除临时键合胶。
5.根据权利要求4所述的超高密度多芯片模组的三维扇出型封装结构的制备方法,其特征在于:所述步骤6)中,互联芯片的制备具体包括以下步骤:
6.1)在Si硅晶圆上用化学气相沉积或者等离子化学气相沉积的方法沉积一层第一介电层;
6.2)在第一介电层上面涂覆一层第一光刻胶层;
6.3)对第一光刻胶层进行曝光显影,在指定区域的第一光刻胶层上形成足够深的第一凹槽直至第一介电层裸露在第一光刻胶层的第一凹槽内;
6.4)在第一光刻胶层的第一凹槽处,使用等离子干法刻蚀或者湿法刻蚀的方法对裸露出来的第一介电层进行刻蚀形成第二凹槽;
6.5)使用干法或者湿法刻蚀的方法去除第一光刻胶层;
6.6)在第二凹槽内使用等离子体气相沉积加上电镀的方法沉积一层金属铜;
6.7)使用化学机械抛光的方法对金属铜进行研磨,直至金属铜下方的第二凹槽区域以外的第一介电层裸露出来,研磨之后金属铜的上表面和第二凹槽以外区域的第一介电层上表面位于同一个水平面;
6.8)重复6.1~6.7,增加新的第一介电层,在对应于外露金属铜的位置构建新的凹槽,使得上下介电层互联;
6.9)在器件芯片表面沉积钝化层,用以保护已经制作完成的布线层,并在钝化层相应的位置进行光刻开孔,以使钝化层下方的金属铜裸露出来;
6.10)在钝化层开孔处使用光刻加上电镀的工艺方法制作外露出钝化层的微铜柱。
6.根据权利要求5所述的超高密度多芯片模组的三维扇出型封装结构的制备方法,其特征在于:所述步骤6.6)中,在沉积铜之前,常常先沉积一层很薄的金属钛或者钛钨作为衬垫层以改善金属铜的粘附性。
7.根据权利要求4所述的超高密度多芯片模组的三维扇出型封装结构的制备方法,其特征在于:所述步骤9)中,金属互联柱的高度大于互联芯片的厚度,使得当金属互联柱裸露出来时互联芯片的上表面仍然在第二塑封体内。
8.根据权利要求4所述的超高密度多芯片模组的三维扇出型封装结构的制备方法,其特征在于:所述步骤10)中,重新布线层的制备具体包括以下步骤:
10.1)在第二塑封体上使用旋涂的方法涂覆一层第二介电层,图中的为第二塑封体;
10.2)在第二介电层相应的位置处进行曝光和显影的光刻工艺,使第二介电层下方的金属互联柱裸露出来;
10.3)在第二介电层上使用物理气相沉积的方法沉积一层金属种子层;
10.4)在金属种子层上涂覆一层第二光刻胶层,并进行曝光和显影,在第二光刻胶层上开槽,把需要引出的引脚焊盘和布线区域的金属种子层裸露出来;
10.5)继续进行金属电镀工艺,在第二光刻胶层开槽的区域形成重新布线层;
10.6)采用湿法刻蚀的方法去除第二光刻胶层以及底部的金属种子层。
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