WO2022012475A1 - 晶圆级封装方法以及封装结构 - Google Patents

晶圆级封装方法以及封装结构 Download PDF

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Publication number
WO2022012475A1
WO2022012475A1 PCT/CN2021/105827 CN2021105827W WO2022012475A1 WO 2022012475 A1 WO2022012475 A1 WO 2022012475A1 CN 2021105827 W CN2021105827 W CN 2021105827W WO 2022012475 A1 WO2022012475 A1 WO 2022012475A1
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Prior art keywords
chip
interconnect
interconnection
wafer
electrode
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PCT/CN2021/105827
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English (en)
French (fr)
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黄河
刘孟彬
向阳辉
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中芯集成电路（宁波）有限公司上海分公司
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Publication of WO2022012475A1 publication Critical patent/WO2022012475A1/zh

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Definitions

  • Embodiments of the present invention relate to the technical field of semiconductor packaging, and in particular, to a wafer-level packaging method and packaging structure.
  • advanced packaging methods mainly adopt the three-dimensional stacking mode of wafer-level system packaging (wafer level package system in package, WLPSIP), compared with the traditional system package, the wafer level system package is to complete the packaging integration process on the wafer, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, batch Sub-manufacturing and other advantages can significantly reduce workload and equipment requirements.
  • wafer level package system in package WLPSIP
  • the problem solved by the embodiments of the present invention is to provide a wafer-level packaging method and packaging structure, which can improve packaging compatibility and packaging reliability while realizing wafer-level packaging.
  • an embodiment of the present invention provides a wafer-level packaging method, including: providing a wafer formed with a plurality of first chips, the first chips include opposite first surfaces and second surfaces, the The first surface has first interconnect electrodes and external electrodes; a plurality of second chips and a plurality of interconnect chips are provided, the surfaces of the second chips have second interconnect electrodes, and the interconnect chips include opposite third surface and a fourth surface, an interconnect structure is formed in the interconnect chip, the third surface of the interconnect chip exposes a part of the interconnect structure; the second chip and the interconnect chip are bonded to on the first surface of the first chip; forming a first interconnect bump for realizing electrical connection between the first interconnect electrode and the second interconnect electrode, forming a second interconnect bump , used to realize the electrical connection between the external electrode and the interconnect structure.
  • an embodiment of the present invention provides a package structure, comprising: a substrate, wherein a first chip is formed in the substrate, the first chip includes a first surface and a second surface opposite to each other, and the first surface has a first chip. an interconnection electrode and an external electrode; a second chip is bonded to the first surface of the first chip, and the surface of the second chip has a second interconnection electrode; an interconnection chip is bonded to the first chip On a first surface of a chip, the interconnect chip includes a third surface and a fourth surface opposite to each other, an interconnect structure is formed in the interconnect chip, and the third surface of the interconnect chip exposes a portion of the interconnect chip. connection structure; first interconnection bump, electrically connecting the first interconnection electrode and the second interconnection electrode; second interconnection bump, electrically connecting the external electrode and the first interconnection structure.
  • the interconnection chip and the second chip are bonded on the surface of the first chip with the first interconnection electrode and the external electrode.
  • An interconnect structure is formed in the interconnect chip, the interconnect chip includes opposite third surfaces and a fourth surface, the third surface exposes a part of the interconnect structure, and forms a connection for electrically connecting the first interconnect electrode and the second interconnect electrode.
  • the first interconnect bump and the second interconnect bump for electrically connecting the external electrode and the external interconnect structure.
  • the packaging method according to the embodiment of the present invention can realize wafer level packaging, and the embodiment of the present invention
  • the lead terminal (for example, the I/O terminal) of the chip module composed of the first chip and the second chip can be led to the side of the wafer with the first interconnect electrode and the external electrode by interconnecting the chips, and the lead terminal can be connected to the chip module.
  • the embodiment of the present invention can not process the wafer (for example, backside thinning process or through silicon via interconnection process). ), thereby reducing the damage to the wafer and improving the packaging reliability, and making the packaging method suitable for the system integration of various wafers, thereby improving the packaging compatibility accordingly.
  • the second interconnection electrode and the first interconnection electrode face each other up and down to form a first cavity; an electroplating process is used.
  • the first interconnect bump is formed in the first cavity, and after the interconnect chip is bonded to the first chip, the interconnect structure and the external electrode face each other up and down to form a surrounding The second cavity; the second interconnection bump is formed in the second cavity by an electroplating process, and the embodiment of the present invention can achieve good filling in the first cavity and the second cavity through the electroplating process Therefore, the reliability of the electrical connection is improved, thereby improving the reliability of the packaging.
  • each of the second chips and each of the interconnected chips are individually bonded to the wafer in a chip-level manner, so that each second chip or each of the interconnected chips can be precisely bonded to the wafer. Even the chip is bonded to the preset position, thereby improving the reliability of the package.
  • 1 to 8 are schematic structural diagrams corresponding to each step in an embodiment of the wafer level packaging method of the present invention.
  • 9 to 13 are schematic structural diagrams corresponding to each step in another embodiment of the wafer level packaging method of the present invention.
  • 14 to 16 are schematic structural diagrams corresponding to each step in another embodiment of the wafer level packaging method of the present invention.
  • Wafer-level system packaging mainly includes two important processes of physical connection and electrical connection.
  • the most typical packaging method can be: 1) three-dimensionally stack the upper and lower bare chips on the substrate by curing glue, and use the wire bond process to wire the lead pads of the two bare chips to the substrate; 2 ) The upper and lower bare chips are three-dimensionally stacked on the substrate by curing glue, and wire The bonding process leads the lead pads of the upper bare chip to the lead pads of the lower bare chip, and then leads the lead pads of the lower bare chip to the substrate; 3) Through the bump welding prefabricated on the surface of the upper bare chip ) or prefabricated bump soldering on the lower bare chip surface to achieve flip-chip soldering, and use wire Bond the lead pads of the lower bare chip to the substrate; 4) Flip-chip bonding is realized by bump welding prefabricated on the surface of the upper bare chip or bump welding prefabricated on the surface of the lower bare chip, and using prefabricated bump welding on the surface of the lower bare chip A through
  • the bump flip-chip bonding process has been used more and more, especially the high-density system integration package based on the through-silicon via interconnection process and the micro-bump flip-chip bonding.
  • the TSV structure prefabricated in the lower bare chip will connect the lead pads of the lower bare chip to the backside of the lower bare chip, complex processes such as photolithography and deep hole etching are required, which is easy to cause damage to the lower bare chip. This results in a drop in yield and, moreover, an increase in cost.
  • an embodiment of the present invention provides a wafer-level packaging method, including: providing a wafer formed with a plurality of first chips, the first chips including opposite first surfaces and second surfaces, The first surface has first interconnect electrodes and external electrodes; a plurality of second chips and a plurality of interconnect chips are provided, the surfaces of the second chips have second interconnect electrodes, and the interconnect chips include opposite a third surface and a fourth surface, an interconnection structure is formed in the interconnection chip, the third surface of the interconnection chip exposes a part of the interconnection structure; the second chip and the interconnection chip are bonded on the first surface of the first chip; forming a first interconnection bump for realizing the electrical connection between the first interconnection electrode and the second interconnection electrode to form a second interconnection The bump is used to realize the electrical connection between the external electrode and the interconnect structure.
  • the packaging method according to the embodiment of the present invention can realize wafer-level packaging, and the embodiment of the present invention can connect the leading end (for example, the I/O end) of the chip module composed of the first chip and the second chip by interconnecting the chips.
  • Lead to the side of the wafer with the first interconnect electrode and the external electrode compared with the solution of leading the lead end to the side of the wafer facing away from the first interconnect electrode and the external electrode, the embodiments of the present invention follow Wafers can be left unprocessed (eg, backside thinning or through-silicon via interconnects), thereby reducing damage to the wafers, helping to improve packaging reliability, and making the packaging method applicable to a variety of System integration of wafers, correspondingly improve packaging compatibility.
  • 1 to 8 are schematic structural diagrams corresponding to each step in an embodiment of the wafer level packaging method of the present invention.
  • a first wafer 100 formed with a plurality of first chips 110 including opposing first surfaces 110a and second surfaces 110b, the first surface 110a having first interconnect electrodes 130 and externally connected electrode 120 .
  • the packaging method is used for realizing wafer-level system packaging, and the wafer 100 is used for bonding with the chip to be integrated in the subsequent process.
  • the wafer 100 is a device wafer (CMOS Wafer), which is fabricated by using an integrated circuit fabrication technology.
  • the wafer 100 includes a substrate.
  • the substrate is a silicon substrate.
  • the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator liner Bottom and other types of substrates.
  • the wafer 100 includes a front side of the wafer and a back side of the wafer, and the back side of the wafer refers to the bottom surface of the substrate in the wafer 100 .
  • a plurality of first chips 110 are formed in the wafer 100, the first surface 110a of the first chip 110 has the first interconnection electrode 130 and the external electrode 120, and at the edge of the first surface 110a, the first interconnection electrode 130 and the external electrodes 120 are exposed.
  • the first surface 110 a and the front surface of the wafer are the same surface, and the first interconnection electrodes 130 and the external electrodes 120 are both interconnection lead pads (Pads) of the first chip 110 , which are used to realize the connection between the first chip 110 and other chips. electrical connection.
  • the second chip is bonded on the first chip 110, and the first interconnection electrodes 130 are used to realize electrical connection with the second chip.
  • the external electrodes 120 are used to electrically lead out the chip module formed by the first chip 110 and the second chip.
  • the exposed positions of the first interconnection electrode 130 and the external electrode 120 are protected by a dielectric layer (not shown) to prevent short circuits, and during the fabrication process of the wafer 100 , the dielectric layer is etched to expose the The first interconnection electrodes 130 and the external electrodes 120, therefore, the surfaces of the first interconnection electrodes 130 and the external electrodes 120 are lower than the first surface 110a, that is, grooves are formed. It should also be noted that, for the convenience of illustration, this embodiment is described by taking as an example that three first chips 110 are formed in the wafer 100 . However, the number of the first chips 110 is not limited to three.
  • a plurality of second chips 200 and a plurality of interconnect chips 300 are provided, the surfaces of the second chips 200 have second interconnect electrodes 210, and the interconnect chips 300 include opposite third surfaces 300a and fourth surfaces 300b, An interconnection structure 305 is formed in the interconnection chip 300 , and a portion of the interconnection structure 305 is exposed on the third surface 300 a of the interconnection chip 300 .
  • the second chip 200 is used as a chip to be integrated in the wafer level system package.
  • the second chip 200 may be one or more of active elements, passive elements, micro-electromechanical systems, optical elements, and the like.
  • the second chip 200 may be a functional chip such as a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip.
  • a plurality of second chips 200 are integrated on the wafer 100, and the packaging integration process is completed on the wafer 100 to realize wafer-level packaging, thereby greatly reducing the area of the packaging structure, reducing the manufacturing cost, optimizing the electrical performance, Advantages such as batch manufacturing can significantly reduce workload and equipment requirements.
  • the number of the second chips 200 is the same as the number of the first chips 110 . In other embodiments, the numbers of the first chips and the second chips may also be different.
  • the second chip 200 is fabricated by using an integrated circuit fabrication technology, and the second chip 200 includes a substrate. For the description of the substrate of the second chip 200, reference may be made to the foregoing description of the first chip 110, and details are not repeated here.
  • the surface of the second chip 200 has a second interconnection electrode 210 , and at the edge of the surface of the second chip 200 , the second interconnection electrode 210 is exposed, and the second interconnection electrode 210 is an interconnection wire bond of the second chip 200 plate.
  • the second chip 200 includes a front side of the chip and a back side of the chip, and the second interconnect electrodes 210 are located on the front side of the chip, that is, the second interconnect electrodes 210 are exposed from the front side of the chip.
  • the backside of the chip refers to the bottom surface of the substrate in the second chip 200 .
  • the second chip 200 may have a surface structure similar to that of the first chip 110 , the exposed positions of the second interconnection electrodes 210 are protected by a dielectric layer (not marked) to prevent short circuits, and the second interconnection electrodes 210 are The surface is lower than the surface of the dielectric layer, that is, grooves are formed. It should also be noted that the interconnect chip 300 will be bonded on the first chip 110 later, so the size of the second chip 200 is smaller than the size of the first chip 110 , so as to reserve a space for the interconnect chip 300 .
  • the interconnect chip 300 is bonded to the first chip 100 and electrically connected to the external electrodes 120 , so as to lead out the electrical properties of the external electrodes 120 . Therefore, at least one surface of the interconnect chip 300 exposes part of the interconnect structure 305 , so that the interconnection structure 305 can be electrically connected with the external electrode 120 .
  • the leading end eg, the I/O end
  • the chip module formed by the first chip 110 and the second chip 200 can be led to the first interconnection electrode 130 and the external connection electrode 120 in the wafer 100 .
  • the wafer 100 can not be processed (for example, backside thinning or Through silicon via interconnection process), thereby reducing damage to the wafer 100 and improving packaging reliability, and making the packaging method suitable for system integration of various wafers 100, thereby improving packaging compatibility accordingly.
  • the semiconductor process is used to prepare the interconnect chip 300 to improve the process compatibility of the interconnect chip 300 preparation process, and to facilitate the formation of the interconnect chip 300 by a wafer-level preparation method, thereby improving the preparation efficiency.
  • a semiconductor substrate (not shown) is provided; a plurality of interconnect structures 305 are formed in the semiconductor substrate; after the interconnect structures 305 are formed, the semiconductor substrate is cut to obtain a plurality of discrete interconnect chips 300 .
  • the semiconductor substrate may be a silicon substrate.
  • the interconnection structure 305 penetrates the interconnection chip 300, and both ends of the interconnection structure 305 are exposed, wherein one end is used for electrical connection with the external electrode 120, and the other end is used for connection with other interconnection structures (eg, terminal) to achieve electrical connection.
  • the interconnect chip 300 includes opposite third surfaces 300a and fourth surfaces 300b, and the interconnect structure 305 includes plugs 320, interconnect lines 310 connected to the plugs 320, and pads 315, and the pads 315 are mutually The exposed portion of the third surface 300a of the chip 300 is connected.
  • the interconnect structure 305 includes interconnect lines 310 and pads 315 located on the third surface 300a, and plugs 320 embedded in the interconnect chip 300 from the fourth surface 300b, the plugs 320 and the interconnect lines 310 connected.
  • the third surface 300a exposes a part of the interconnection line 310 , and the part of the interconnection line 310 exposed by the third surface 300a serves as the bonding pad 315 .
  • the interconnect line 310 can function as a redistribution layer layer, RDL).
  • RDL redistribution layer layer
  • the plurality of external electrodes 120 can be connected by interconnecting wires 310 , and the electrical properties of the plurality of external electrodes 120 can be drawn out through a plug 320 .
  • the plug 320 is used to realize electrical connection with the lead terminal formed later.
  • the plug 320 has a certain height, which is beneficial to reduce the difficulty of forming the subsequent lead-out ends.
  • the material of the interconnection line 310 is aluminum.
  • the aluminum process is relatively simple and the process cost is low. Therefore, by selecting the aluminum interconnect layer, it is beneficial to reduce the process difficulty and process cost of the packaging process.
  • the interconnect lines can also be other applicable conductive materials.
  • the material of the plug 320 is copper.
  • the resistivity of copper is low, and by selecting copper material, it is beneficial to improve the electrical conductivity of the plug 320; moreover, the plug 320 is formed in the interconnection hole, and the filling of copper is good, thereby improving the plug 320 in the interconnection hole. quality of formation within.
  • the plug may also be of other applicable conductive materials.
  • the interconnect structure may also only include plugs penetrating through the interconnect chip, the plugs being correspondingly exposed portions of the third surface of the interconnect chip.
  • the interconnect structure includes interconnect lines and pads, the pads being exposed portions of the third surface of the interconnect chip.
  • the plugs 320 are formed. Specifically, the interconnection lines 310 located on the third surface 300a are formed; using the surface of the interconnection lines 310 facing the fourth surface 300b as an etching stop position, the interconnection chips 300 are etched from the fourth surface 300b to form interconnection holes ( Not shown); filling interconnection holes to form plugs 320 .
  • the interconnection line 310 first, it is easy to control the position where the etching stops during the process of forming the interconnection hole.
  • the interconnect lines may also be formed after the plugs are formed.
  • the thickness of the interconnect chip 300 is greater than or equal to the thickness of the second chip 200 .
  • both the second chip 200 and the interconnecting chip 300 are bonded to the first surface 110 a (as shown in FIG. 1 ) of the first chip 110 , and a covering of the second chip 200 and the interconnection are also formed on the wafer 100
  • the cover layer of the chip 300, the surface of the cover layer facing away from the wafer 100 exposes the fourth surface 300b of the interconnect chip 300, therefore, by making the thickness of the interconnect chip 300 greater than or equal to the thickness of the second chip 200, it is convenient for the cover layer to be exposed Simultaneously with the fourth surface 300b, the second chip 200 is buried therein.
  • the thickness difference between the interconnecting chip 300 and the second chip 200 is 0 ⁇ m to 100 ⁇ m.
  • the second chip 200 and the interconnect chip 300 are bonded on the first surface 110 a of the first chip 110 .
  • the system integration of the second chip 200 and the interconnecting chip 300 and the first wafer 100 is realized.
  • both the second chip 200 and the interconnecting chip 300 are bonded on the first surface 110 a so as to realize the electrical connection between the second chip 200 and the first chip 110 and the electrical connection between the interconnecting chip 300 and the first chip 110 .
  • the third surface 300 a of the interconnect chip 300 is bonded on the first chip 110 , so that the interconnect structure 305 exposed on the third surface 300 a faces the external electrode 120 , so as to facilitate the realization of the interconnect structure 305 and the external electrode 120 electrical connection.
  • the second interconnection electrode 210 and the first interconnection electrode 130 are opposed to each other up and down along the direction of the normal line of the first surface 110a to enclose the first cavity 10 and the first interconnection electrode 130 And the second interconnection electrode 210 is located in the first cavity 10 .
  • the first cavity 10 is used to provide a space for the subsequent formation of the first interconnection bump that electrically connects the first interconnection electrode 130 and the second interconnection electrode 210 .
  • the groove where the first interconnection electrode 130 is located and the groove where the second interconnection electrode is located are buckled to form the first cavity 10 , and the first cavity 10 is not airtight, so that the electroplating body can be filled into the first cavity 10 .
  • each second chip 200 is individually bonded on the wafer 100 in a chip-level manner, and the second chips 200 correspond to the first chips 110 one-to-one, so that each second chip 200 can be accurately bonded key to the preset position.
  • the optical alignment process is used to realize the bonding.
  • the surfaces of the second chip 200 and the first chip 110 have corresponding optical alignment marks. Therefore, the optical alignment process can be used to realize the bonding, which is beneficial to improve the Bonding accuracy.
  • the light source used in the optical alignment process includes an infrared light source or a visible light source.
  • the optical alignment process uses an infrared light source to further improve alignment accuracy.
  • the bonding can also be realized by means of mechanical alignment. For example, when the chip surface is not formed with alignment marks.
  • the interconnection structure 305 and the external electrode 120 face each other up and down to enclose the second cavity 20 , and the external electrode 120 and the interconnection structure 305 are located in the second cavity 20 .
  • the second cavity 20 is used to provide a space for the subsequent formation of second interconnect bumps that electrically connect the external electrodes 120 and the interconnect structure 305 .
  • the second cavity 20 is not airtight so that the electroplating body can be filled into the second cavity 20 .
  • each interconnect chip 300 is individually bonded on the wafer 100 in a chip-level manner, and the interconnect chips 300 correspond to the first chips 110 one-to-one, so that each interconnect chip 300 can be accurately bonded key to the preset position.
  • the bonding is achieved using an optical alignment process.
  • a plurality of interconnect chips may be bonded to the same first chip, so as to be electrically connected to the corresponding external electrodes respectively.
  • the second chip 200 and the interconnecting chip 300 are bonded to the first surface 110a by the adhesive layer 140, and the material of the adhesive layer 140 is a photosensitive material.
  • the adhesive layer 140 has a certain thickness, so that the unsealed first cavity 10 and the unsealed second cavity 20 can be formed.
  • the material of the adhesive layer 140 is a photosensitive material, so that the patterning can be realized by a photolithography process, thereby reducing the damage to the electrodes or interconnecting lines.
  • the low bonding temperature is beneficial to reduce the impact on the chip performance.
  • the process of adhesive bonding is simple.
  • the adhesive layer 140 may be a dry film.
  • other types of adhesive layers can also be used, for example, an adhesive film (Die Attach Film, DAF).
  • the adhesive layer 140 is formed on the exposed first surface 110a of the first interconnection electrode 130 and the external electrode 120, so that the adhesive layer 140 can be formed on the plurality of first chips 110 in the same step, and further Improve packaging efficiency.
  • the adhesive layer 140 exposes the first interconnection electrode 130 , the external electrode 120 , the second interconnection electrode 210 and the interconnection structure 305 , thereby forming the airtight first cavity 10 and the airtight second cavity 20 .
  • the thickness of the adhesive layer 140 should not be too small or too large. If the thickness is too small, the adhesive force of the adhesive layer 140 may be insufficient, thereby reducing the bonding strength of the second chip 200 or the interconnecting chip 300 and the wafer 100, and also easily causing the first cavity 10 or the second The height of the cavity 20 is too small, which increases the difficulty of filling the first cavity 10 or the second cavity 20 with the subsequent electroplating body; Conducive to the development of device miniaturization. Therefore, in this embodiment, the thickness of the adhesive layer 140 is 5 micrometers to 50 micrometers.
  • this embodiment takes adhesive bonding as an example for description.
  • other bonding methods may also be used to bond the second chip and the interconnecting chip to the wafer, for example, through silicon oxide - Bonding is achieved by fusion bonding of silicon oxide.
  • the dielectric layer used to realize the bonding is used as an adhesive layer, and the dielectric layer can be a silicon oxide layer.
  • a first interconnect bump 31 is formed for realizing electrical connection between the first interconnect electrode 130 and the second interconnect electrode 210
  • a second interconnect bump 32 is formed for realizing the external electrode 120 and the electrical connection between the interconnect structure 305 .
  • the first interconnection electrodes 130 and the second interconnection electrodes 210 are electrically connected through the first interconnection bumps 31 , thereby realizing the interconnection package of the second chip 200 and the wafer 100
  • the second interconnection bumps 32 are electrically connected to the external electrodes 120 and the interconnection structure 305, so as to realize the interconnection package of the interconnected chip 300 and the wafer 100, and lead out the electrical properties of the first chip 110, thereby preparing for the subsequent packaging process.
  • the electrical connection between the first chip 110 and other substrates eg, circuit boards
  • an electroplating process is performed, so that the electroplating body is filled into the first cavity 10 from the boundary of the second chip 200 , and the electroplating body in the first cavity 10 is connected to the first interconnection electrode 130 and the second interconnection electrode.
  • 210 are all in contact with each other, thereby forming the first interconnect bump 31 that electrically connects the first interconnect electrode 130 and the second interconnect electrode 210; similarly, the plating body is filled from the boundary of the interconnect chip 300 to the second cavity 20 , the plated body in the second cavity 20 is in contact with both the external electrode 120 and the external interconnection structure 305 , thereby forming a second interconnection bump 32 that electrically connects the external electrode 120 and the external interconnection structure 305 .
  • first interconnect bump 31 and the second interconnect bump 32 can be formed in the same process, thereby improving packaging efficiency.
  • the electroplating process is electroless electroplating (ie, electroless plating).
  • the bonded second chip 200 , the interconnecting chip 300 and the wafer 100 are placed in a solution containing metal ions (eg, electroless silver plating, nickel plating, copper plating, etc.)
  • metal ions eg, electroless silver plating, nickel plating, copper plating, etc.
  • the principle of reduction reaction is to use strong reducing agent to reduce metal ions to metal and deposit them on the surfaces of the first interconnection electrode 130, the second interconnection electrode 210, the external electrode 120 and the interconnection structure 305 to form a dense metal plating layer.
  • the metal plating layer fills the first cavity 10 and the second cavity 20, thereby forming the first interconnect bump 31 and the second interconnect bump 32, respectively.
  • the material of the first interconnect bump 31 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten and magnesium
  • the material of the second interconnect bump 32 includes copper, nickel, zinc , one or more of tin, silver, gold, tungsten and magnesium.
  • the third surface 300 a of the interconnect chip 300 is bonded to the first chip 110 , and therefore, the first interconnect bumps 32 are used to realize electrical connection between the external electrodes 120 and the interconnect lines 310 .
  • a bumping process may be used to form the first interconnection electrode on the second interconnection electrode or the first interconnection electrode.
  • an interconnection bump the second chip is welded to the first chip by a pressure welding process, so that the first interconnection electrode and the second interconnection electrode are electrically connected through the first interconnection bump; wherein, the pressure welding process is the The bonding process, or alternatively, the bonding process is performed after the bonding process.
  • a bump process may be used to form a second interconnect bump on the interconnect structure or the external electrode, and a pressure bonding process may be used to form the second interconnect bump.
  • the interconnect chip is welded to the first chip, so that the interconnect structure and the external electrode are electrically connected through the second interconnect bump; wherein, the bonding process is the bonding process, or the bonding is performed after the bonding process .
  • the method further includes: forming a covering second chip 200 , an interconnect chip 300 , and a first interconnect on the wafer 100
  • the bumps 31 and the cover layer 150 of the second interconnect bump 32 , and the cover layer 150 exposes the fourth surface 300 b of the interconnect chip 300 .
  • the capping layer 150 is used to insulate and protect the second chip 200 , the interconnect chip 300 , the first interconnect bump 31 and the second interconnect bump 32 . Therefore, the material of the cover layer 150 is an insulating material. In this embodiment, the material of the cover layer 150 includes one or both of a dielectric material and a molding material, wherein the dielectric material may be silicon oxide, silicon nitride or other dielectric materials.
  • the packaging method further includes: performing a planarization process on the cover layer 150 until the interconnecting chip 300 is exposed.
  • the cover layer 150 is a flat surface to facilitate the formation of the subsequent lead-out ends.
  • the capping layer above the interconnecting chips may be etched, thereby exposing the interconnecting chips.
  • a terminal 190 electrically connected to the interconnect structure 305 is formed on the top surface of the capping layer 150 .
  • the second chip 200 and the corresponding first chip 110 constitute a chip module
  • the lead terminal 190 is used as the input and output terminal of the chip module
  • the chip module can be bonded to other substrates (such as circuit boards) through the lead terminal 190 subsequently. .
  • the process of forming the chip module 190 includes a bump process. Compared with a wire bond process, this embodiment can implement wafer level packaging. Specifically, the chip module 190 includes the redistribution layer 160 connected to the interconnect structure 305 and the conductive bumps 180 on the redistribution layer 160 .
  • the steps of forming the input-output interconnect structure 190 include.
  • a redistribution layer 160 is formed on the top surface of the capping layer 150 , which is connected to the top end of the interconnect structure 305 (ie, the end exposed by the fourth surface 300 b ).
  • the redistribution layer 160 is used to redistribute the top of the interconnect structure 305 .
  • the material of the redistribution layer 160 is aluminum.
  • the redistribution layer may also be other applicable conductive materials.
  • the redistribution layer 160 may be formed by deposition and etching of corresponding materials.
  • the second chip 200 is covered by the cover layer 150, so as to realize the isolation of the rewiring layer 160 from the second chip 200.
  • the rewiring layer 160 may extend to the cover layer 150 above the second chip 200, so as to facilitate the The interconnect structure 305 is redistributed according to actual packaging requirements.
  • a passivation layer 170 covering the redistribution layer 160 is formed, and an opening 175 exposing the redistribution layer 160 is formed in the passivation layer 170 .
  • Openings 175 are used to provide spatial locations for the formation of conductive bumps.
  • the passivation layer 170 is used to insulate between the redistribution layers 160, and is also used to provide a process platform for the formation of the conductive bumps.
  • the passivation layer 170 can also play the roles of waterproof, anti-oxidation and anti-pollution.
  • the material of the passivation layer 170 is a photosensitive material.
  • the passivation layer 170 can be patterned by a photolithography process, which is beneficial to simplify the process steps and reduce the process cost.
  • the material of the passivation layer 170 may be photosensitive polyimide (PI), photosensitive benzocyclobutene (BCB) or photosensitive polybenzoxazole (PBO).
  • PI photosensitive polyimide
  • BCB photosensitive benzocyclobutene
  • PBO photosensitive polybenzoxazole
  • the passivation layer 170 covering the redistribution layer 160 is formed on the cover layer 150 by coating.
  • a photolithography process is used to pattern the passivation layer 170 to expose part of the redistribution layer 160 .
  • conductive bumps 180 are formed in the openings 175 (shown in FIG. 7 ), and the conductive bumps 180 and the redistribution layer 160 constitute lead terminals 190 .
  • the conductive bumps 180 are formed by a bumping process. By selecting the bump process, it is beneficial to reduce the thickness of the conductive bumps 180 , thereby reducing the thickness of the package structure.
  • the material of the conductive bumps 180 is copper.
  • the lead-out terminal may also be formed by a ball-mounting process.
  • the wafer-level packaging method further includes the formation of the cover layer and the exposure of the interconnection chip and the formation of the lead-out terminal. This includes: forming plugs embedded in the interconnect chips from the fourth surface of the interconnect chips, the plugs being connected to the interconnect lines.
  • 9 to 13 are schematic structural diagrams corresponding to each step in another embodiment of the wafer level packaging method of the present invention.
  • a carrier substrate 400 is provided; a plurality of mutually separated second chips 500 and a plurality of mutually separated interconnect chips 600 are arranged in positions corresponding to the first chips, and temporarily bonded to the carrier substrate 400 .
  • the carrier substrate 400 is used for supporting the second chip 500 and the interconnecting chip 600, so as to facilitate the subsequent bonding of the second chip 500 and the interconnecting chip 600 to the wafer in a wafer-level manner; and through temporary bonding Temporary bonding) to facilitate subsequent debonding.
  • the carrier substrate 400 is a carrier wafer.
  • the carrier substrate 400 may be a semiconductor substrate (eg, a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer, Organic plastic wafers, inorganic oxide wafers or ceramic material wafers.
  • the surface of the second chip 500 has the second interconnection electrode 510 .
  • the second interconnect electrode 510 is directed toward the carrier substrate 400 , and the second chip 500 is bonded to the carrier substrate 400 .
  • the interconnection chip 600 is formed with an interconnection structure 605, the interconnection chip 600 includes a third surface 600a and a fourth surface 600b opposite to each other, and the interconnection structure 605 includes interconnection lines 610 and Pads (not shown), and plugs 620 embedded in the interconnect chip 600 from the fourth surface 600b, the plugs 620 are connected to the interconnect lines 610.
  • the interconnect chip 600 is bonded to the carrier substrate 400 .
  • a plastic sealing layer 410 is formed on the carrier substrate 400 to at least fill the space between the second chip 500 and the interconnecting chip 600 , and the plastic sealing layer 410 embedded with the second chip 500 and the interconnecting chip 600 is used as the second chip. circle (not labeled).
  • the second chip 500 and the interconnecting chip 600 are bonded to the wafer in a wafer-level manner, and the wafer is used as the first wafer.
  • the second chip 500 and the interconnecting chip 600 are embedded in a plastic package.
  • a second wafer is formed in the layer 410, so that the second wafer can be bonded to the first wafer in a wafer-level bonding manner.
  • the plastic sealing layer 410 is formed through an injection molding process. By adopting the injection molding process, the subsequent removal of the plastic sealing layer 410 is facilitated. As an example, the plastic encapsulation layer 410 covers the second chip 500 and the interconnecting chip 600 .
  • a De-bonding process is performed to remove the carrier substrate 400 (as shown in FIG. 10 ).
  • the packaging method further includes: etching back a partial thickness of the plastic packaging layer 410 from the surface on which the second chip 500 and the interconnecting chip 600 are embedded. By etching back a part of the thickness of the plastic packaging layer 410, more surfaces of the second chip 500 and the interconnecting chip 600 are exposed, which is beneficial to improve the reliability of the subsequent bonding process.
  • a wafer 700 ie, a first wafer
  • a second wafer (not shown) is bonded to the wafer 700 using an adhesive layer 740 .
  • a plurality of first chips 710 are formed in the wafer 700 .
  • the first chips 710 include opposite first surfaces (not shown) and second surfaces (not shown), and the first surface has first interconnect electrodes 730 and external electrodes 720 .
  • the second wafer is bonded to the first surface.
  • the second interconnection electrodes 510 and the first interconnection electrodes 730 are made to face each other up and down to enclose the first cavity 40, and the interconnection structure 605 and the external electrodes 720 are placed up and down. On the contrary, the second cavity 50 is enclosed.
  • the method further includes: removing the plastic sealing layer 410 .
  • the plastic sealing layer 410 is removed by ashing, dry etching or wet etching.
  • the plastic encapsulation layer may not be formed.
  • the second interconnection electrode of the second chip faces away from the carrier substrate, the second chip is bonded to the carrier substrate, the fourth surface of the interconnection chip faces the carrier substrate, and the interconnection chip is bonded to the carrier substrate so that after bonding, the first cavity and the second cavity can be formed.
  • 14 to 16 are schematic structural diagrams corresponding to each step in another embodiment of the wafer level packaging method of the present invention.
  • the interconnect structure 820 includes interconnection lines 810 and pads 815 , which are exposed portions of a third surface (not labeled) of interconnect chip 800 .
  • the third surface exposes the part of the interconnection line 810 , and the part of the interconnection line 810 exposed by the third surface is used as the bonding pad 815 .
  • the packaging method further includes: forming a plug 830 embedded in the interconnect chip 800 from the fourth surface.
  • the interconnect chip 800 is etched from the fourth surface to form interconnect holes 805 exposing the interconnect lines 810 .
  • the interconnection holes 805 are used to provide spatial locations for subsequent formation of plugs.
  • plugs 830 are formed in interconnect holes 805 (shown in FIG. 15).
  • FIG. 8 is a schematic structural diagram of an embodiment of the packaging structure of the present invention.
  • the package structure includes: a base (not shown), a first chip 110 is formed in the base, and the first chip 110 includes an opposite first surface 110a (as shown in FIG. 1 ) and a second surface 110b (as shown in FIG. 1 ) ), the first surface 110a has the first interconnection electrode 130 and the external electrode 120; the second chip 200 is bonded to the first surface 110a of the first chip 110, and the surface of the second chip 200 has the second interconnection electrode 210
  • the interconnect chip 300 is bonded to the first surface 110a of the first chip 110, and the interconnect chip 300 includes an opposite third surface 300a (as shown in FIG. 2) and a fourth surface 300b (as shown in FIG.
  • an interconnection structure 305 is formed in the interconnection chip 300, and a part of the interconnection structure 305 is exposed on the third surface 300a of the interconnection chip 300; the first interconnection bump 31 electrically connects the first interconnection electrode 130 and the second interconnection The connecting electrode 210 ; the second interconnecting bump 32 is electrically connected to the external electrode 120 and the first connecting structure 305 .
  • the substrate is a wafer-level substrate, that is, the substrate is a wafer 100 , thereby realizing wafer-level packaging.
  • Wafer 100 includes opposing wafer front and wafer back surfaces, which refers to the bottom surface of the substrate in wafer 100 . Therefore, a plurality of first chips 110 are formed in the wafer 100 .
  • the first surface 110a of the first chip 110 has the first interconnection electrodes 130 and the external electrodes 120, and at the edge of the first surface 110a, the first interconnection electrodes 130 and the external electrodes 120 are exposed.
  • the first surface 110a and the front surface of the wafer are the same surface.
  • the first interconnection electrode 130 is used to achieve electrical connection with the second chip 200 .
  • the external electrodes 120 are used to electrically lead out the chip module formed by the first chip 110 and the second chip 200 .
  • the package structure is a structure obtained after dicing, and therefore, the substrate is a chip-level substrate, that is, the substrate includes a chip.
  • the exposed positions of the first interconnection electrode 130 and the external electrode 120 are protected by a dielectric layer (not shown) to prevent short circuits, and during the fabrication process of the wafer 100 , the dielectric layer is etched to expose the The first interconnection electrode 130 and the externally connected electrode 120, therefore, the surfaces of the first interconnected electrode 130 and the externally connected electrode 120 are lower than the first surface 110a.
  • this embodiment is described by taking as an example that three first chips 110 are formed in the wafer 100 . However, the number of the first chips 110 is not limited to three.
  • the second chip 200 may be one or more of active elements, passive elements, micro-electromechanical systems, optical elements, and the like. Specifically, the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip or a logic chip. In other embodiments, the second chip may also be other functional chips. A plurality of the second chips 200 are integrated in the wafer 100, and a packaging integration process is completed on the wafer 100 to realize wafer-level packaging, thereby greatly reducing the area of the packaging structure.
  • the number of the second chips 200 is the same as the number of the first chips 110 . In other embodiments, the numbers of the first chips and the second chips may also be different.
  • the second chip 200 includes a substrate.
  • the surface of the second chip 200 has the second interconnection electrodes 210 , and at the edge of the surface of the second chip 200 , the second interconnection electrodes 210 are exposed.
  • the second chip 200 includes a front side of the chip and a back side of the chip, and the second interconnect electrodes 210 are located on the front side of the chip, that is, the second interconnect electrodes 210 are exposed from the front side of the chip.
  • the backside of the chip refers to the bottom surface of the substrate in the second chip 200 .
  • the second chip 200 may have a surface structure similar to that of the first chip 110 , the exposed positions of the second interconnect electrodes 210 are protected by a dielectric layer (not shown) to prevent short circuits, and the surfaces of the second interconnect electrodes 210 lower than the surface of the second chip 200 . It should also be noted that the size of the second chip 200 is smaller than that of the first chip 110 , so as to reserve a space for the interconnecting chip 300 .
  • the second interconnection electrode 210 and the first interconnection electrode 130 face each other up and down, so as to realize the electrical connection between the second interconnection electrode 210 and the first interconnection electrode 130 .
  • the interconnection chip 300 is used to lead out the electrical properties of the external electrodes 120 .
  • the third surface 300 a of the interconnect chip 300 exposes a part of the interconnect structure 305 , so that the interconnect structure 305 can be electrically connected with the external electrodes 120 .
  • the leading end eg, the I/O end
  • the chip module formed by the first chip 110 and the second chip 200 can be led to the first interconnection electrode 130 and the external connection electrode 120 in the wafer 100 .
  • subsequent processing of the wafer 100 for example, backside thinning or through silicon vias
  • interconnection process thereby reducing damage to the wafer 100 and improving packaging reliability, and making the packaging method suitable for system integration of various wafers 100, thereby improving packaging compatibility.
  • interconnect chip 300 includes a semiconductor substrate in which interconnect structure 305 is located.
  • the semiconductor substrate may be a silicon substrate.
  • the interconnection structure 305 penetrates the interconnection chip 300, and both ends of the interconnection structure 305 are exposed, one end of which is electrically connected to the external electrode 120, and the other end is connected to other interconnection structures (eg, input-output interconnection) structure) to achieve electrical connection.
  • the interconnect structure 305 includes a plug 320 , an interconnect line 310 connected to the plug 320 , and a pad 315 , which is an exposed portion of the third surface 300 a of the interconnect chip 300 .
  • the interconnect structure 305 includes interconnect lines 310 and pads 315 located on the third surface 300a, and plugs 320 embedded in the interconnect chip 300 from the fourth surface 300b, the plugs 320 and the interconnect lines 310 connected.
  • the third surface 300a exposes a part of the interconnection line 310 , and the part of the interconnection line 310 exposed by the third surface 300a serves as the bonding pad 315 .
  • the bottom end of the plug 320 is in contact with the face of the interconnection line 310 facing the fourth surface 300b.
  • the interconnection line 310 can function as a redistribution layer.
  • the plurality of external electrodes 120 can be connected by interconnecting wires 310 , and the electrical properties of the plurality of external electrodes 120 can be drawn out through a plug 320 .
  • the plug 320 has a certain height, which is beneficial to reduce the difficulty of forming the lead-out end.
  • the third surface 300 a of the interconnect chip 300 is bonded to the first surface 110 a of the first chip 110 .
  • the material of the interconnection line 310 is aluminum. In other embodiments, the interconnect lines can also be other applicable conductive materials. In this embodiment, the material of the plug 320 is copper. In other embodiments, the plug may also be of other applicable conductive materials.
  • the interconnect structure may also only include plugs penetrating through the interconnect chip, the plugs being correspondingly exposed portions of the third surface of the interconnect chip.
  • the thickness of the interconnect chip 300 is greater than or equal to the thickness of the second chip 200 .
  • the thickness difference between the interconnecting chip 300 and the second chip 200 is 0 ⁇ m to 100 ⁇ m.
  • the interconnection structure 305 and the external electrode 120 face each other up and down, so as to realize the electrical connection between the interconnection structure 305 and the external electrode 120 .
  • the wafer level packaging structure further includes: an adhesive layer 140 located between the second chip 200 and the first chip 110 and between the interconnecting chip 300 and the first chip 110 .
  • the material of the adhesive layer 140 is For photosensitive materials. Using the adhesive layer 140, the adhesive bonding is realized, and the bonding temperature of the adhesive bonding is low, which is beneficial to reduce the influence on the performance of the chip. Moreover, the process of adhesive bonding is simple. Specifically, the adhesive layer 140 may be a dry film. In other embodiments, other types of adhesive layers, such as adhesive films, may also be employed.
  • the thickness of the adhesive layer 140 should not be too small or too large. If the thickness is too small, the adhesive force of the adhesive layer 140 may be insufficient, thereby reducing the bonding strength between the second chip 200 or the interconnecting chip 300 and the wafer 100 , and also increasing the first interconnect bumps 31 . and the difficulty of forming the second interconnection bump 32; if the thickness is too large, the thickness of the package structure will be too large, which is not conducive to the development of device miniaturization. Therefore, in this embodiment, the thickness of the adhesive layer 140 is 5 micrometers to 50 meters.
  • the bonding is realized by silicon oxide-silicon oxide fusion bonding.
  • the adhesive layer between the second chip and the first chip and between the interconnecting chip and the first chip may be a dielectric layer such as a silicon oxide layer.
  • the first interconnection bumps 31 are electrically connected to the first interconnection electrodes 130 and the second interconnection electrodes 210 , thereby realizing the interconnection package of the second chip 200 and the wafer 100 ;
  • the second interconnection bumps 32 are electrically connected to the external electrodes 120 and the interconnection structure 305 , so as to realize the interconnection packaging of the interconnected chip 300 and the wafer 100 , and lead out the electrical properties of the wafer 100 , thereby preparing for the subsequent packaging process.
  • the electrical connection of the first chip 110 to other substrates eg, circuit boards
  • the first interconnection bump 31 is located between the first interconnection electrode 130 and the second interconnection electrode 210
  • the second interconnection bump 32 is located between the external electrode 120 and the interconnection structure 305 .
  • the second interconnection bumps 32 are electrically connected to the external electrodes 120 and the interconnection lines 310 .
  • the first interconnect bump 31 and the second interconnect bump 32 are both plated interconnect structures. That is, the first interconnect bumps 31 and the second interconnect bumps 32 are formed by an electroplating process, and the first interconnect bumps 31 and the second interconnect bumps 32 formed by the electroplating process can be A good filling effect is achieved between the connecting electrode 130 and the second interconnecting electrode 210, and between the external electrode 120 and the first structure 305, thereby improving the electrical connection between the first interconnecting electrode 130 and the second interconnecting electrode 210. reliability, and reliability of the electrical connection between the external electrodes 120 and the interconnect structure 305 .
  • the material of the first interconnect bump 31 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten and magnesium
  • the material of the second interconnect bump 32 includes copper, One or more of nickel, zinc, tin, silver, gold, tungsten and magnesium.
  • the WLP structure further includes: a cover layer 150 located on the wafer 100 and covering the second chip 200 , the interconnect chip 300 , the first interconnect bump 31 and the second interconnect bump 32 , The top surface of the capping layer 150 exposes the surface of the interconnect chip 300 facing away from the substrate (ie, the fourth surface 300 b );
  • the capping layer 150 is used to insulate and protect the second chip 200 , the interconnect chip 300 , the first interconnect bump 31 and the second interconnect bump 32 . Therefore, the material of the cover layer 150 is an insulating material. In this embodiment, the material of the cover layer 150 includes one or both of a dielectric material and a molding material, wherein the dielectric material may be silicon oxide, silicon nitride or other dielectric materials.
  • the surface of the capping layer 150 is flush with the fourth surface 300 b of the interconnect chip 300 .
  • the cover layer 150 is a flat surface to facilitate the formation of the lead-out end 190 .
  • the surface of the cover layer may also be higher than the fourth surface of the interconnect chip, and the cover layer is formed with interconnect openings exposing the interconnect chip.
  • the second chip 200 and the corresponding first chip 110 constitute a chip module, and the lead terminal 190 is used as an input and output terminal of the chip module, and the chip module can be subsequently bonded to other substrates (circuit boards) through the lead terminal 190 .
  • the lead terminal 190 includes a conductive bump 180, and the conductive bump 180 is a solder bump, which is formed by a bump process.
  • the package structure described in the example can be obtained by a wafer level packaging method.
  • the lead terminal 190 includes: the redistribution layer 160 on the top surface of the capping layer 170 and connected to the top of the plug 320 ; the conductive bump 180 on the redistribution layer 160 and electrically connected to the redistribution layer 160 .
  • the redistribution layer 160 is used to redistribute the interconnect structure 305 .
  • the material of the redistribution layer 160 is aluminum. In other embodiments, the redistribution layer may also be other applicable conductive materials.
  • the material of the conductive bumps 180 is copper.
  • the WLP structure further includes: a passivation layer 170 covering a portion of the redistribution layer 160 , and the conductive bumps 180 are located in the passivation layer 170 .
  • the passivation layer 170 is used to insulate the redistribution layers 160, and is also used to provide a process platform for the formation of the conductive bumps 180.
  • the passivation layer 170 can also play the role of waterproof, anti-oxidation and anti-pollution. .
  • the material of the passivation layer 170 is a photosensitive material.
  • the material of the passivation layer 170 may be photosensitive polyimide, photosensitive benzocyclobutene or photosensitive polybenzoxazole.
  • the terminations may also include balls.
  • the package structure may be formed by the packaging method described in the foregoing embodiments, or may be formed by other packaging methods.
  • the packaging structure in this embodiment reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

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Abstract

一种晶圆级封装方法以及封装结构，方法包括：提供有多个第一芯片的晶圆，包括相对的第一表面和第二表面，第一表面有第一互连电极和外接电极；提供多个第二芯片和多个互连芯片，第二芯片表面有第二互连电极，互连芯片包括第三表面和第四表面，互连芯片中有互连结构，第三表面暴露部分互连结构；将第二芯片和互连芯片键合于第一表面上；形成第一互连凸块，用于实现第一互连电极和第二互连电极电连接，形成第二互连凸块，用于实现外接电极和互连结构电连接。本发明实现晶圆级封装，且通过互连芯片将第一芯片和第二芯片构成的芯片模块的引出端引至第一表面一侧，从而减小对晶圆的损伤，且适用于各种晶圆的系统集成，进而提高封装兼容性和可靠性。

Description

晶圆级封装方法以及封装结构 技术领域
本发明实施例涉及半导体封装技术领域，尤其涉及一种晶圆级封装方法以及封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装（ball grid array，BGA）、芯片尺寸封装（chip scale package，CSP）、晶圆级封装（wafer level package，WLP）、三维封装（3D）和系统封装（system in package，SiP）。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用三维立体堆叠模式的晶圆级系统封装（wafer level package system in package，WLPSIP），与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
在晶圆级系统封装工艺中，不仅需要将两片裸芯片键合在一起以实现物理连接，同时还需要连接其互连引线，从而实现电性连接。
 技术问题
本发明实施例解决的问题是提供一种晶圆级封装方法以及封装结构，在实现晶圆级封装的同时，提高封装兼容性和封装可靠性。
 技术解决方案
为解决上述问题，本发明实施例提供一种晶圆级封装方法，包括：提供形成有多个第一芯片的晶圆，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有第一互连电极和外接电极；提供多个第二芯片和多个互连芯片，所述第二芯片的表面具有第二互连电极，所述互连芯片包括相对的第三表面和第四表面，所述互连芯片中形成有互连结构，所述互连芯片的第三表面暴露部分所述互连结构；将所述第二芯片和所述互连芯片键合于所述第一芯片的第一表面上；形成第一互连凸块，用于实现所述第一互连电极和所述第二互连电极之间的电连接，形成第二互连凸块，用于实现所述外接电极和所述互连结构之间的电连接。
相应的，本发明实施例提供一种封装结构，包括：基底，所述基底中形成有第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有第一互连电极以及外接电极；第二芯片，键合于所述第一芯片的第一表面上，所述第二芯片的表面具有第二互连电极；互连芯片，键合于所述第一芯片的第一表面上，所述互连芯片包括相对的第三表面和第四表面，所述互连芯片中形成有互连结构，所述互连芯片的第三表面暴露部分所述互连结构；第一互连凸块，电连接所述第一互连电极和所述第二互连电极；第二互连凸块，电连接所述外接电极和所述第一互连结构。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例在第一芯片中具有第一互连电极和外接电极的面上键合互连芯片和第二芯片，互连芯片中形成有互连结构，互连芯片包括相对的第三表面和第四表面，第三表面暴露部分互连结构，并形成用于电连接第一互连电极和第二互连电极的第一互连凸块、以及用于电连接外接电极和外接互连结构的第二互连凸块，因此，本发明实施例所述封装方法能够实现晶圆级封装，而且，本发明实施例能够通过互连芯片，将第一芯片和第二芯片构成的芯片模块的引出端（例如，I/O端）引至晶圆中具有第一互连电极和外接电极的一侧，与将引出端引至晶圆中背向第一互连电极和外接电极的一侧的方案相比，本发明实施例后续能够不对晶圆进行处理（例如，进行背面减薄处理或者硅通孔互连工艺），从而减小对晶圆的损伤，有利于提高封装可靠性，而且，使所述封装方法适用于各种晶圆的系统集成，相应提高封装兼容性。
可选方案中，将所述第二芯片键合于所述第一芯片上后，所述第二互连电极和所述第一互连电极上下相对，围成第一空腔；利用电镀工艺在所述第一空腔中形成所述第一互连凸块，将所述互连芯片键合于所述第一芯片上后，所述互连结构和所述外接电极上下相对，围成第二空腔；利用电镀工艺在所述第二空腔中形成所述第二互连凸块，本发明实施例通过电镀工艺，可在第一空腔和第二空腔中实现良好的填充效果，从而提高电连接的可靠性，进而提高封装可靠性。
可选方案中，每个所述第二芯片以及每个所述互连芯片均以芯片级的方式单独键合于所述晶圆，以便于能够精准地将每个第二芯片或每个互连芯片键合至预设的位置处，从而提高封装可靠性。
 附图说明
图1至图8是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
图9至图13是本发明晶圆级封装方法另一实施例中各步骤对应的结构示意图。
图14至图16是本发明晶圆级封装方法又一实施例中各步骤对应的结构示意图。
 本发明的实施方式
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺。其中，最典型的封装方式可以是：1）通过固化胶将上下裸芯片立体堆叠至基板上，并采用引线互连（wire bond）工艺将两个裸芯片的引线焊盘引线至基板上；2）通过固化胶将上下裸芯片立体堆叠至基板上，并采用wire bond工艺将上裸芯片的引线焊盘引线至下裸芯片的引线焊盘上，再将下裸芯片的引线焊盘引线至基板上；3）通过预制于上裸芯片表面的凸点焊（bump）或预制于下裸芯片表面的凸点焊实现倒装焊接，并采用wire bond将下裸芯片的引线焊盘引线至基板上；4）通过预制于上裸芯片表面的凸点焊或预制于下裸芯片表面的凸点焊实现倒装焊接，并采用预制于下裸芯片内的硅通孔互连（TSV）结构将下裸芯片的引线焊盘连至下裸芯片的背面。
其中，凸点倒装焊接工艺得到越来越多的应用，尤其是基于硅通孔互连工艺以及微凸点倒装焊的高密度系统集成封装。然而，由于预制于下裸芯片内的TSV结构会将下裸芯片的引线焊盘连至下裸芯片的背面，需要进行光刻、深孔刻蚀等复杂工艺，容易对下裸芯片造成损伤，从而导致良率下降，而且，还会导致成本增加。此外，随着集成电路的发展趋势，集成电路设计的复杂度不断提高，金属互连结构的布局相应越来越复杂，从而导致TSV工艺的难度增大，甚至出现因下裸芯片中的功能结构（例如，金属互连结构）的阻挡作用，无法形成TSV结构的问题。
为了解决所述技术问题，本发明实施例提供一种晶圆级封装方法，包括：提供形成有多个第一芯片的晶圆，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有第一互连电极和外接电极；提供多个第二芯片和多个互连芯片，所述第二芯片的表面具有第二互连电极，所述互连芯片包括相对的第三表面和第四表面，所述互连芯片中形成有互连结构，所述互连芯片的第三表面暴露部分所述互连结构；将所述第二芯片和所述互连芯片键合于所述第一芯片的第一表面上；形成第一互连凸块，用于实现所述第一互连电极和所述第二互连电极之间的电连接，形成第二互连凸块，用于实现所述外接电极和所述互连结构之间的电连接。
本发明实施例所述封装方法能够实现晶圆级封装，而且，本发明实施例能够通过互连芯片，将第一芯片和第二芯片构成的芯片模块的引出端（例如，I/O端）引至晶圆中具有第一互连电极和外接电极的一侧，与将引出端引至晶圆中背向第一互连电极和外接电极的一侧的方案相比，本发明实施例后续能够不对晶圆进行处理（例如，进行背面减薄处理或者硅通孔互连工艺），从而减小对晶圆的损伤，有利于提高封装可靠性，而且，使所述封装方法适用于各种晶圆的系统集成，相应提高封装兼容性。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图8是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
参考图1，提供形成有多个第一芯片110的第一晶圆100，第一芯片110包括相对的第一表面110a和第二表面110b，第一表面110a具有第一互连电极130和外接电极120。
所述封装方法用于实现晶圆级系统封装，晶圆100用于在后续工艺中与待集成芯片进行键合。本实施例中，晶圆100为器件晶圆（CMOS Wafer），采用集成电路制作技术所制成。本实施例中，所述晶圆100包括衬底。作为一种示例，衬底为硅衬底。在其他实施例中，衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
本实施例中，晶圆100包括相对的晶圆正面和晶圆背面，晶圆背面指的是晶圆100中衬底的底部表面。晶圆100中形成有多个第一芯片110，第一芯片110的第一表面110a具有第一互连电极130和外接电极120，且在第一表面110a的边缘处，第一互连电极130和外接电极120被裸露。其中，第一表面110a与晶圆正面为同一表面，第一互连电极130和外接电极120均为第一芯片110的互连引线焊盘（Pad），用于实现第一芯片110与其他芯片的电连接。后续在第一芯片110上键合第二芯片，第一互连电极130用于实现与第二芯片的电连接。外接电极120用于将第一芯片110和第二芯片构成的芯片模块的电性引出。
需要说明的是，第一互连电极130和外接电极120露出的位置利用介质层（未标示）进行保护以防止短路，且在晶圆100的制作过程中，通过对介质层进行刻蚀以暴露第一互连电极130和外接电极120，因此，第一互连电极130和外接电极120的表面低于第一表面110a，即形成有凹槽。还需要说明的是，为了便于图示，本实施例以晶圆100中形成有三个第一芯片110为例进行说明。但第一芯片110的数量不仅限于三个。
参考图2，提供多个第二芯片200和多个互连芯片300，第二芯片200的表面具有第二互连电极210，互连芯片300包括相对的第三表面300a和第四表面300b，互连芯片300中形成有互连结构305，互连芯片300的第三表面300a暴露部分互连结构305。
第二芯片200作为晶圆级系统封装中的待集成芯片。第二芯片200可以为有源元件、无源元件、微机电系统、光学元件等元件中的一种或多种。具体地，第二芯片200可以为存储芯片、通讯芯片、处理芯片、闪存芯片或逻辑芯片等功能芯片。后续将多个第二芯片200集成于晶圆100上，并在晶圆100上完成封装集成制程，以实现晶圆级封装，从而大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显降低工作量与设备需求。
作为一种示例，第二芯片200的数量与第一芯片110的数量相同。在其他实施例中，第一芯片和第二芯片的数量也可以不同。本实施例中，第二芯片200采用集成电路制作技术所制成，第二芯片200包括衬底。对第二芯片200的衬底的描述，可结合参考前述对第一芯片110的相关描述，在此不再赘述。
第二芯片200的表面具有第二互连电极210，且在第二芯片200的表面边缘处，第二互连电极210被裸露，第二互连电极210为第二芯片200的互连引线焊盘。本实施例中，第二芯片200包括相对的芯片正面和芯片背面，第二互连电极210位于芯片正面，即芯片正面露出第二互连电极210。其中，芯片背面指的是第二芯片200中衬底的底部表面。
需要说明的是，第二芯片200可以具有第一芯片110类似的表面结构，第二互连电极210露出的位置利用介质层（未标示）进行保护以防止短路，且第二互连电极210的表面低于介质层的表面，即形成有凹槽。还需要说明的是，后续会在第一芯片110上键合互连芯片300，因此第二芯片200的尺寸小于第一芯片110的尺寸，从而为互连芯片300预留空间位置。
后续将互连芯片300键合于第一芯片100上，并与外接电极120实现电连接，从而将外接电极120的电性引出，因此，互连芯片300的至少一个面露出部分互连结构305，从而使互连结构305能够与外接电极120实现电连接。通过互连芯片300，能够将第一芯片110和第二芯片200构成的芯片模块的引出端（例如，I/O端）引至晶圆100中具有第一互连电极130和外接电极120的一侧，与将引出端引至晶圆中背向第一互连电极和外接电极的一侧的方案相比，本实施例后续能够不对晶圆100进行处理（例如，进行背面减薄处理或者硅通孔互连工艺），从而减小对晶圆100的损伤，有利于提高封装可靠性，而且，使所述封装方法适用于各种晶圆100的系统集成，相应提高封装兼容性。
本实施例中，采用半导体工艺制备互连芯片300，以提高互连芯片300制备工艺的工艺兼容性，且便于通过晶圆级的制备方法形成互连芯片300，提高制备效率。具体地，提供半导体衬底（未标示）；在半导体衬底中形成多个互连结构305；形成互连结构305后，对半导体衬底进行切割，获得多个分立的互连芯片300。其中，半导体衬底可以为硅衬底。
作为一种示例，互连结构305贯穿互连芯片300，互连结构305的两端均被暴露，其中一端用于与外接电极120实现电连接，另一端用于与其他互连结构（例如，引出端）实现电连接。具体地，互连芯片300包括相对的第三表面300a和第四表面300b，互连结构305包括插塞320、与插塞320连接的互连线310、以及焊垫315，焊垫315为互连芯片300的第三表面300a暴露的部分。也就是说，互连结构305包括位于第三表面300a的互连线310和焊垫315、以及从第四表面300b嵌于互连芯片300中的插塞320，插塞320与互连线310相连。其中，第三表面300a暴露部分的互连线310，且互连线310中被第三表面300a暴露的部分作为焊垫315。
互连线310能够起到再布线层（redistribution layer，RDL）的作用。例如，当第一芯片110具有多个外接电极120时，能够通过互连线310连接多个外接电极120，并通过一个插塞320将多个外接电极120的电性引出。插塞320用于与后续形成的引出端实现电连接。而且，插塞320具有一定的高度，从而有利于降低后续引出端的形成难度。
本实施例中，互连线310的材料为铝。铝工艺较为简单，且工艺成本较低，因此通过选用铝互连层，有利于降低封装工艺的工艺难度和工艺成本。在其他实施例中，互连线还可以为其他可适用的导电材料。
本实施例中，插塞320的材料为铜。铜的电阻率较低，通过选取铜材料，有利于提高插塞320的导电性能；而且，插塞320形成于互连孔中，铜的填充性较好，从而提高插塞320在互连孔内的形成质量。在其他实施例中，插塞还可以为其他可适用的导电材料。
在另一些实施例中，互连结构也可以仅包括贯穿互连芯片的插塞，插塞相应为互连芯片的第三表面暴露的部分。在其他实施例中，互连结构包括互连线和焊垫，焊垫为互连芯片的第三表面暴露的部分。
本实施例中，在形成互连线310之后，形成插塞320。具体地，形成位于第三表面300a的互连线310；以互连线310朝向第四表面300b的表面作为刻蚀停止位置，从第四表面300b刻蚀互连芯片300，形成互连孔（图未示）；填充互连孔，形成插塞320。通过先形成互连线310，在形成互连孔的过程中，易于控制刻蚀停止的位置。在其他实施例中，也可以在形成插塞之后，形成互连线。
本实施例中，互连芯片300的厚度大于或等于第二芯片200的厚度。后续将第二芯片200和互连芯片300均键合至第一芯片110的第一表面110a（如图1所示）上，且还会在晶圆100上形成覆盖第二芯片200和互连芯片300的覆盖层，覆盖层背向晶圆100的面露出互连芯片300的第四表面300b，因此，通过使互连芯片300的厚度大于或等于第二芯片200的厚度，便于覆盖层露出第四表面300b的同时，将第二芯片200掩埋在内。但是，如果互连芯片300和第二芯片200的厚度差值过大，相应会导致后续所形成封装结构的厚度过大，不利于器件小型化的发展。为此，本实施例中，互连芯片300和第二芯片200的厚度差值为0微米至100微米。
继续参考图2，将第二芯片200和互连芯片300键合于第一芯片110的第一表面110a上。
通过将第二芯片200和互连芯片300均键合于第一芯片110上，实现第二芯片200以及互连芯片300与第一晶圆100的系统集成。而且，第二芯片200和互连芯片300均键合于第一表面110a上，以便于实现第二芯片200与第一芯片110的电连接、以及互连芯片300与第一芯片110的电连接。具体地，将互连芯片300的第三表面300a键合于第一芯片110上，从而使第三表面300a暴露的互连结构305朝向外接电极120，以便于实现互连结构305和外接电极120的电连接。
本实施例中，在键合后，沿第一表面110a法线的方向，第二互连电极210和第一互连电极130上下相对，围成第一空腔10，第一互连电极130和第二互连电极210位于第一空腔10内。第一空腔10用于为后续形成电连接第一互连电极130和第二互连电极210的第一互连凸块提供空间位置。第一互连电极130所在的凹槽和第二互连电极所在的凹槽扣合形成第一空腔10，第一空腔10不密闭，以便于电镀体能够填充至第一空腔10中。
作为一种示例，每个第二芯片200以芯片级的方式单独键合于晶圆100上，第二芯片200与第一芯片110一一对应，以便于能够精准地将每个第二芯片200键合至预设的位置处。
本实施例中，利用光学对准工艺实现键合。在第二芯片200和晶圆100的制备过程中，第二芯片200和第一芯片110的表面有相对应的光学对准标记，因此，能够采用光学对准工艺实现键合，从而有利于提高键合精度。其中，光学对准工艺采用的光源包括红外光源或可见光源。作为一种示例，光学对准工艺采用红外光源，以进一步提高对准精度。在其他实施例中，根据实际情况，也可以采用机械对准的方式实现键合。例如，当芯片表面未形成有对准标记时。
同理，本实施例中，在键合后，互连结构305和外接电极120上下相对，围成第二空腔20，外接电极120和互连结构305位于第二空腔20内。第二空腔20用于为后续形成电连接外接电极120和互连结构305的第二互连凸块提供空间位置。第二空腔20不密闭，以便于电镀体能够填充至第二空腔20中。
作为一种示例，每个互连芯片300以芯片级的方式单独键合于晶圆100上，互连芯片300与第一芯片110一一对应，以便于能够精准地将每个互连芯片300键合至预设的位置处。具体地，利用光学对准工艺实现键合。在其他实施例中，当第一芯片具有多个外接电极时，可以将多个互连芯片键合至同一个第一芯片上，从而分别与对应的外接电极实现电连接。
本实施例中，利用粘接层140将第二芯片200和互连芯片300键合于第一表面110a上，粘接层140的材料为光敏材料。粘接层140具有一定厚度，从而能够形成不密闭的第一空腔10和不密闭的第二空腔20。而且粘接层140的材料为光敏材料，从而能够通过光刻工艺实现图形化，进而降低对电极或互连线的损伤，粘接层140具有粘性，能够实现黏着键合，黏着键合的键合温度低，有利于减小对芯片性能的影响。此外，黏着键合的工艺简单。具体地，粘接层140可以为干膜（Dry Film）。在其他实施例中，也可以采用其他类型的粘接层，例如，粘片膜（Die Attach Film，DAF）。
本实施例中，粘接层140形成于第一互连电极130和外接电极120露出的第一表面110a，从而能够在同一步骤中，在多个第一芯片110上形成粘接层140，进而提高封装效率。在其他实施例中，也可以分别在第二芯片和互连芯片上形成粘接层后，再分别将第二芯片和互连芯片键合至第一芯片上。而且，粘接层140露出第一互连电极130、外接电极120、第二互连电极210和互连结构305，从而形成不密闭的第一空腔10和不密闭的第二空腔20。
需要说明的是，粘接层140的厚度不宜过小，也不宜过大。如果厚度过小，容易导致粘接层140的粘接力不足，从而降低第二芯片200或互连芯片300与晶圆100的键合强度，而且，还容易导致第一空腔10或第二空腔20的高度过小，从而增加后续电镀体填充于第一空腔10或第二空腔20时的难度；如果厚度过大，则相应会导致后续所形成封装结构的厚度过大，不利于器件小型化的发展。为此，本实施例中，粘接层140的厚度是5微米至50微米。
需要说明的是，本实施例以黏着键合为例进行说明，在其他实施例中，还可以采用其他键合方式将第二芯片和互连芯片键合至晶圆上，例如，通过氧化硅-氧化硅熔融键合的方式实现键合，相应的，用于实现键合的介质层作为粘接层，介质层可以为氧化硅层。
参考图3，形成第一互连凸块31，用于实现第一互连电极130和第二互连电极210之间的电连接，形成第二互连凸块32，用于实现外接电极120和互连结构305之间的电连接。
通过第一互连凸块31电连接第一互连电极130和第二互连电极210，从而实现第二芯片200和晶圆100的互连封装，第二互连凸块32电连接外接电极120和互连结构305，从而实现互连芯片300和晶圆100的互连封装，并将第一芯片110的电性引出，进而为后续的封装制程做准备。例如，后续能够通过互连结构305，实现第一芯片110与其他基板（例如，电路板）的电连接。
本实施例中，进行电镀工艺，使电镀体从第二芯片200的边界填充至第一空腔10中，第一空腔10中的电镀体与第一互连电极130和第二互连电极210均相接触，从而形成电连接第一互连电极130和第二互连电极210的第一互连凸块31；同理，使电镀体从互连芯片300的边界填充至第二空腔20中，第二空腔20中的电镀体与外接电极120和外接互连结构305均相接触，从而形成电连接外接电极120和互连结构305的第二互连凸块32。
通过电镀工艺，可在第一空腔10和第二空腔20中实现良好的填充效果，从而提高电连接的可靠性，进而提高封装良率。而且，能够在同一工艺中形成第一互连凸块31和第二互连凸块32，从而提高封装效率。
本实施例中，电镀工艺为无极电镀（即化学镀）。具体地，键合后的第二芯片200、互连芯片300与晶圆100放置到含有金属离子的溶液（例如，化学镀银、镀镍、镀铜等溶液）中，不需要通电，根据氧化还原反应原理，利用强还原剂使金属离子还原成金属而沉积在第一互连电极130、第二互连电极210、外接电极120和互连结构305的表面，形成致密金属镀层，经过一段反应时间之后，金属镀层将第一空腔10和第二空腔20填满，从而分别形成第一互连凸块31和第二互连凸块32。
通过采用无极电镀，不需要通电，电镀体沉积在裸露的电极表面，从而减小对电极在芯片内部的互连方式的要求，工艺灵活性更高。
因此，第一互连凸块31的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种，第二互连凸块32的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。
需要说明的是，互连芯片300的第三表面300a键合于第一芯片110上，因此，第一互连凸块32用于实现外接电极120和互连线310之间的电连接。
还需要说明的是，在其他实施例中，也可以在将第二芯片键合于第一芯片上之前，利用凸块（bumping）工艺在第二互连电极或第一互连电极上形成第一互连凸块，利用压焊工艺将第二芯片焊接至第一芯片上，使第一互连电极和第二互连电极通过第一互连凸块电连接；其中，压焊工艺为该键合工艺，或者，在压焊工艺之后进行所述键合工艺。
同理，在其他实施例中，也可以在将互连芯片键合于第一芯片上之前，利用凸块工艺在互连结构或外接电极上形成第二互连凸块，利用压焊工艺将互连芯片焊接至第一芯片上，使互连结构和外接电极通过第二互连凸块电连接；其中，压焊工艺为该键合工艺，或者，在压焊工艺之后进行所述键合。
结合参考图4和图5，形成第一互连凸块31和第二互连凸块32后，还包括：在晶圆100上形成覆盖第二芯片200、互连芯片300、第一互连凸块31和第二互连凸块32的覆盖层150，覆盖层150露出互连芯片300的第四表面300b。
覆盖层150用于实现对第二芯片200、互连芯片300、第一互连凸块31和第二互连凸块32的绝缘和保护。因此，覆盖层150的材料为绝缘材料。本实施例中，覆盖层150的材料包括介电材料和塑封材料中的一种或两种，其中，介电材料可以为氧化硅、氮化硅或者其他介电材料。
本实施例中，如图4所示，形成覆盖层150后，覆盖层150覆盖第二芯片200和互连芯片300的第四表面300b。因此，如图5所示，封装方法还包括：对覆盖层150进行平坦化处理，直至露出互连芯片300。覆盖层150为平坦面，以便于后续引出端的形成。在其他实施例中，也可以在形成覆盖层后，刻蚀互连芯片上方的覆盖层，从而露出互连芯片。
结合参考图6至图8，在覆盖层150的顶面上形成与互连结构305电连接的引出端190。
第二芯片200和相对应的第一芯片110构成芯片模块，引出端190用于作为芯片模块的输入输出端，且后续能够通过引出端190将芯片模块键合至其他基板（例如电路板）上。
本实施例中，形成芯片模块190的工艺包括凸块工艺，与打线（wire bond）工艺相比，本实施例能够实现晶圆级封装。具体地，芯片模块190包括与互连结构305相连的再布线层160以及位于再布线层160上的导电凸块180。
具体地，形成输入输出互连结构190的步骤包括。
如图6所示，在覆盖层150的顶面上形成与互连结构305的顶端（即被第四表面300b露出的一端）相连的再布线层160。
再布线层160用于对互连结构305的顶端进行再分布。本实施例中，再布线层160的材料为铝。在其他实施例中，再布线层还可以为其他可适用的导电材料。作为一种示例，可以通过相应材料的沉积和刻蚀，形成再布线层160。其中，第二芯片200被覆盖层150所覆盖，从而实现再布线层160与第二芯片200的隔离，相应的，再布线层160可以延伸至第二芯片200上方的覆盖层150上，以便于根据实际封装需求，对互连结构305进行再分布。
如图7所示，形成覆盖再布线层160的钝化层170，钝化层170中形成有露出部分的再布线层160的开口175。
开口175用于为导电凸块的形成提供空间位置。钝化层170用于对再布线层160之间进行绝缘，且还用于为导电凸块的形成提供工艺平台，此外，钝化层170还能够起到防水、防氧化和防污染等作用。
本实施例中，钝化层170的材料为光敏材料。相应的，可以通过光刻工艺对钝化层170进行图形化，有利于简化工艺步骤、降低工艺成本。具体地，钝化层170的材料可以为光敏聚酰亚胺（polyimide，PI）、光敏苯并环丁烯（benzocyclobutene，BCB）或光敏聚苯并恶唑（polybenzoxazole，PBO）。本实施例中，通过涂布的方式，在覆盖层150上形成覆盖再布线层160的钝化层170。相应的，采用光刻工艺图形化钝化层170，露出部分的再布线层160。
如图8所示，在开口175（如图7所示）中形成导电凸块180，导电凸块180和再布线层160构成引出端190。
本实施例中，采用凸块（Bumping）工艺形成导电凸块180。通过选用凸块工艺，有利于降低导电凸块180的厚度，从而减小封装结构的厚度。本实施例中，导电凸块180的材料为铜。
需要说明的是，在其他实施例中，在形成覆盖层、并露出互连芯片后，也可以采用植球工艺形成引出端。
还需要说明的是，在其他实施例中，当互连结构仅包括互连线和焊垫时，形成覆盖层、并露出互连芯片后，形成引出端之前，所述晶圆级封装方法还包括：形成从互连芯片的第四表面嵌于互连芯片中的插塞，插塞与互连线相连。
图9至图13是本发明晶圆级封装方法另一实施例中各步骤对应的结构示意图。
本发明实施例与前述实施例的相同之处在此不再赘述，本发明实施例与前述实施例的不同之处在于：通过晶圆级键合的方式，将第二芯片500和互连芯片600键合至晶圆700上。
参考图9，提供承载基板400；将多个相互分离的第二芯片500以及多个相互分离的互连芯片600按照和第一芯片对应的位置排列，并临时键合至承载基板400上。
承载基板400用于对第二芯片500和互连芯片600起到支撑作用，从而便于后续将第二芯片500和互连芯片600以晶圆级的方式键合至晶圆上；而且通过临时键合（temporary bonding）的方式，便于后续进行解键合。
本实施例中，承载基板400为载体晶圆（carrier wafer）。具体地，承载基板400可以半导体衬底（例如硅衬底）、有机玻璃晶圆、无机玻璃晶圆、树脂晶圆、半导体材料晶圆、氧化物晶体晶圆、陶瓷晶圆、金属晶圆、有机塑料晶圆、无机氧化物晶圆或陶瓷材料晶圆。
第二芯片500的表面具有第二互连电极510。本实施例中，使第二互连电极510朝向承载基板400，将第二芯片500键合至承载基板400上。
本实施例中，互连芯片600中形成有互连结构605，互连芯片600包括相对的第三表面600a和第四表面600b，互连结构605包括位于第三表面600a的互连线610和焊垫（未标示）、以及从第四表面600b嵌于互连芯片600中的插塞620，插塞620与互连线610相连。具体地，使第三表面600a朝向承载基板400，将互连芯片600键合至承载基板400上。
参考图10，在承载基板400上形成塑封层410，至少填充满第二芯片500和互连芯片600之间的空间，嵌有第二芯片500和互连芯片600的塑封层410作为第二晶圆（未标示）。
后续将第二芯片500和互连芯片600以晶圆级的方式键合至晶圆上，以该晶圆作为第一晶圆，本实施例通过将第二芯片500和互连芯片600嵌入塑封层410中以形成第二晶圆，以便后续能够以晶圆级键合的方式将第二晶圆键合至第一晶圆上。
本实施例中，通过注塑工艺，形成塑封层410。通过采用注塑工艺，以便于后续去除塑封层410。作为一种示例，塑封层410覆盖第二芯片500和互连芯片600。
参考图11，形成塑封层410后，进行解键合（De-bonding）工艺，去除承载基板400（如图10所示）。
本实施例中，在解键合后，封装方法还包括：从嵌有第二芯片500和互连芯片600的面，回刻蚀部分厚度的塑封层410。通过回刻蚀部分厚度的塑封层410，以更多地暴露第二芯片500和互连芯片600的表面，有利于提高后续的键合工艺的可靠性。
参考图12，提供晶圆700（即第一晶圆），并利用粘接层740，将第二晶圆（未标示）键合至晶圆700上。
晶圆700中形成有多个第一芯片710，第一芯片710包括相对的第一表面（未标示）和第二表面（未标示），第一表面具有第一互连电极730和外接电极720。因此，将第二晶圆键合于第一表面上。
将第二晶圆键合至第一晶圆上后，使第二互连电极510和第一互连电极730上下相对，围成第一空腔40，使互连结构605和外接电极720上下相对，围成第二空腔50。
参考图13，将第二晶圆键合至晶圆700上后，还包括：去除塑封层410。
通过去除塑封层410，从而避免塑封层410对后续电镀工艺的影响，并暴露出第一空腔40和第二空腔50，便于电镀体能够进入第一空腔40和第二空腔50中。具体地，采用灰化、干法刻蚀或者湿法刻蚀，去除塑封层410。
需要说明的是，在其他实施例中，当第二芯片和互连芯片的厚度相等，或者相近时，也可以不形成塑封层。相应的，使第二芯片的第二互连电极背向承载基板，将第二芯片键合至承载基板上，使互连芯片的第四表面朝向承载基板，将互连芯片键合至承载基板上，从而在键合后，即可形成第一空腔和第二空腔。
后续制程与前述实施例相同，在此不再赘述。对本实施例所述封装方法的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
图14至图16是本发明晶圆级封装方法又一实施例中各步骤对应的结构示意图。
本发明实施例与前述实施例的相同之处在此不再赘述，本发明实施例与前述实施例的不同之处在于：如图14所示，提供互连芯片800的步骤中，互连结构820包括互连线810和焊垫815，焊垫815为互连芯片800的第三表面（未标示）暴露的部分。其中，第三表面暴露部分的互连线810，且互连线810中被第三表面暴露的部分作为焊垫815。
相应的，结合参考图15和图16，形成覆盖层820后，封装方法还包括：形成从第四表面嵌于互连芯片800中的插塞830。
具体地，如图15所示，从第四表面刻蚀互连芯片800，形成露出互连线810的互连孔805。互连孔805用于为后续形成插塞提供空间位置。
如图16所示，在互连孔805（如图15所示）中形成插塞830。
对插塞830的具体描述，可参考前述实施例中的相应描述，在此不再赘述。
后续制程与前述实施例相同，在此不再赘述。对本实施例所述封装方法的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
相应的，本发明还提供一种封装结构。图8是本发明封装结构一实施例的结构示意图。
所述封装结构包括：基底（未标示），基底中形成有第一芯片110，第一芯片110包括相对的第一表面110a（如图1所示）和第二表面110b（如图1所示），第一表面110a具有第一互连电极130和外接电极120；第二芯片200，键合于第一芯片110的第一表面110a上，第二芯片200的表面具有第二互连电极210；互连芯片300，键合于第一芯片110的第一表面110a上，互连芯片300包括相对的第三表面300a（如图2所示）和第四表面300b（如图2所示），互连芯片300中形成有互连结构305，互连芯片300的第三表面300a暴露出部分互连结构305；第一互连凸块31，电连接第一互连电极130和第二互连电极210；第二互连凸块32，电连接外接电极120和第一连结构305。
本实施例中，基底为晶圆级基底，即所述基底为晶圆100，从而实现晶圆级封装。晶圆100包括相对的晶圆正面和晶圆背面，晶圆背面指的是晶圆100中衬底的底部表面。因此，晶圆100中形成有多个第一芯片110。第一芯片110的第一表面110a具有第一互连电极130和外接电极120，且在第一表面110a的边缘处，第一互连电极130和外接电极120被裸露。其中，第一表面110a与晶圆正面为同一表面。第一互连电极130用于实现与第二芯片200的电连接。外接电极120用于将第一芯片110和第二芯片200构成的芯片模块的电性引出。
在其他实施例中，所述封装结构为切割后获得的结构，因此，基底为芯片级基底，即基底包括一个芯片。
需要说明的是，第一互连电极130和外接电极120露出的位置利用介质层（未标示）进行保护以防止短路，且在晶圆100的制作过程中，通过对介质层进行刻蚀以暴露第一互连电极130和外接电极120，因此，第一互连电极130和外接电极120的表面低于第一表面110a。还需要说明的是，为了便于图示，本实施例以晶圆100中形成有三个第一芯片110为例进行说明。但第一芯片110的数量不仅限于三个。
第二芯片200可以为有源元件、无源元件、微机电系统、光学元件等元件中的一种或多种。具体地，第二芯片200可以为存储芯片、通讯芯片、处理芯片、闪存芯片或逻辑芯片。在其他实施例中，第二芯片还可以是其他功能芯片。多个所述第二芯片200集成于晶圆100中，并在晶圆100上完成封装集成制程，以实现晶圆级封装，从而能够大幅减小封装结构的面积。
作为一种示例，第二芯片200的数量与第一芯片110的数量相同。在其他实施例中，第一芯片和第二芯片的数量也可以不同。本实施例中，第二芯片200包括衬底。对第二芯片200的衬底的描述，可结合参考前述对第一芯片110的相关描述，在此不再赘述。第二芯片200的表面具有第二互连电极210，且在第二芯片200的表面边缘处，第二互连电极210被裸露。本实施例中，第二芯片200包括相对的芯片正面和芯片背面，第二互连电极210位于芯片正面，即芯片正面露出第二互连电极210。其中，芯片背面指的是第二芯片200中衬底的底部表面。
需要说明的是，第二芯片200可以具有第一芯片110类似的表面结构，第二互连电极210露出的位置利用介质层（未标示）进行保护以防止短路，第二互连电极210的表面低于第二芯片200的表面。还需要说明的是，第二芯片200的尺寸小于第一芯片110的尺寸，从而为互连芯片300预留空间位置。
本实施例中，第二互连电极210和第一互连电极130上下相对，以便于实现第二互连电极210和第一互连电极130的电连接。
互连芯片300用于将外接电极120的电性引出。互连芯片300的第三表面300a暴露部分互连结构305，从而使互连结构305能够与外接电极120实现电连接。通过互连芯片300，能够将第一芯片110和第二芯片200构成的芯片模块的引出端（例如，I/O端）引至晶圆100中具有第一互连电极130和外接电极120的一侧，与将引出端引至晶圆中背向第一互连电极和外接电极的一侧的方案相比，后续能够不对晶圆100进行处理（例如，进行背面减薄处理或者硅通孔互连工艺），从而减小对晶圆100的损伤，有利于提高封装可靠性，而且，使封装方法适用于各种晶圆100的系统集成，进而提高封装兼容性。
本实施例中，采用半导体工艺制备互连芯片300，从而提高互连芯片300制备工艺的工艺兼容性，而且，便于通过晶圆级的制备方法形成互连芯片300，提高制备效率。因此，互连芯片300包括半导体衬底，互连结构305位于半导体衬底中。其中，半导体衬底可以为硅衬底。
作为一种示例，互连结构305贯穿互连芯片300，互连结构305的两端均被暴露，其中一端与外接电极120实现电连接，另一端与其他互连结构（例如，输入输出互连结构）实现电连接。具体地，互连结构305包括插塞320、与插塞320连接的互连线310、以及焊垫315，焊垫315为互连芯片300的第三表面300a暴露的部分。也就是说，互连结构305包括位于第三表面300a的互连线310和焊垫315、以及从第四表面300b嵌于互连芯片300中的插塞320，插塞320与互连线310相连。其中，第三表面300a暴露部分的互连线310，且互连线310中被第三表面300a暴露的部分作为焊垫315。具体地，插塞320的底端与互连线310朝向第四表面300b的面相接触。
互连线310能够起到再布线层的作用。例如，当第一芯片110具有多个外接电极120时，能够通过互连线310连接多个外接电极120，并通过一个插塞320将多个外接电极120的电性引出。而且，插塞320具有一定的高度，从而有利于降低引出端的形成难度。相应的，互连芯片300的第三表面300a键合于第一芯片110的第一表面110a上。
本实施例中，互连线310的材料为铝。在其他实施例中，互连线还可以为其他可适用的导电材料。本实施例中，插塞320的材料为铜。在其他实施例中，插塞还可以为其他可适用的导电材料。
在另一些实施例中，互连结构也可以仅包括贯穿互连芯片的插塞，插塞相应为互连芯片的第三表面暴露的部分。
本实施例中，互连芯片300的厚度大于或等于第二芯片200的厚度。通过使互连芯片300的厚度大于或等于第二芯片200的厚度，当封装结构还包括覆盖第二芯片200、互连芯片300、第一互连凸块31和第二互连凸块32的覆盖层时，便于覆盖层露出互连芯片300的第四表面300b的同时，将第二芯片200掩埋在内。但是，如果互连芯片300和第二芯片200的厚度差值过大，相应会导致封装结构的厚度过大，不利于器件小型化的发展。为此，本实施例中，互连芯片300和第二芯片200的厚度差值为0微米至100微米。
本实施例中，互连结构305和外接电极120上下相对，以便于实现互连结构305和外接电极120的电连接。
本实施例中，晶圆级封装结构还包括：粘接层140，位于第二芯片200和第一芯片110之间、以及互连芯片300和第一芯片110之间，粘接层140的材料为光敏材料。利用粘接层140，实现黏着键合，黏着键合的键合温度低，有利于减小对芯片性能的影响。而且，黏着键合的工艺简单。具体地，粘接层140可以为干膜。在其他实施例中，也可以采用其他类型的粘接层，例如，粘片膜。
需要说明的是，粘接层140的厚度不宜过小，也不宜过大。如果厚度过小，则容易导致粘接层140的粘接力不足，从而降低第二芯片200或互连芯片300与晶圆100的键合强度，而且，还容易增加第一互连凸块31和第二互连凸块32的形成难度；如果厚度过大，则相应会导致封装结构的厚度过大，不利于器件小型化的发展。为此，本实施例中，粘接层140的厚度是5微米至50米。
在其他实施例中，还可以采用其他键合方式，将第二芯片和互连芯片键合至第一晶圆上，例如，通过氧化硅-氧化硅熔融键合的方式实现键合，相应的，位于第二芯片和第一芯片之间、以及互连芯片和第一芯片之间的粘接层可以为氧化硅层等介质层。
第一互连凸块31电连接第一互连电极130和第二互连电极210，从而实现第二芯片200和晶圆100的互连封装；第二互连凸块32电连接外接电极120和互连结构305，从而实现互连芯片300和晶圆100的互连封装，并将晶圆100的电性引出，进而为后续的封装制程做准备。例如，能够通过互连结构305，实现第一芯片110与其他基板（例如，电路板）的电连接。
本实施例中，第一互连凸块31位于第一互连电极130和第二互连电极210之间，第二互连凸块32位于外接电极120和互连结构305之间。具体地，第二互连凸块32电连接外接电极120和互连线310。
本实施例中，第一互连凸块31和第二互连凸块32均为电镀互连结构。也就是说，第一互连凸块31和第二互连凸块32通过电镀工艺形成，通过电镀工艺形成的第一互连凸块31和第二互连凸块32，可在第一互连电极130和第二互连电极210之间、在外接电极120和第一结构305之间实现良好的填充效果，进而提高第一互连电极130和第二互连电极210之间电连接的可靠性、以及外接电极120和互连结构305之间电连接的可靠性。
本实施例中，第一互连凸块31的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种，第二互连凸块32的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。
本实施例中，晶圆级封装结构还包括：覆盖层150，位于晶圆100上且覆盖第二芯片200、互连芯片300、第一互连凸块31和第二互连凸块32，覆盖层150的顶面露出互连芯片300背向基底的面（即第四表面300b）；引出端190，位于覆盖层150的顶面上且电连接互连结构305。
覆盖层150用于实现对第二芯片200、互连芯片300、第一互连凸块31和第二互连凸块32的绝缘和保护。因此，覆盖层150的材料为绝缘材料。本实施例中，覆盖层150的材料包括介电材料和塑封材料中的一种或两种，其中，介电材料可以为氧化硅、氮化硅或者其他介电材料。
本实施例中，覆盖层150表面和互连芯片300的第四表面300b齐平。覆盖层150为平坦面，以便于引出端190的形成。在其他实施例中，覆盖层表面也可以高于互连芯片的第四表面，且覆盖层中形成有露出互连芯片的互连开口。
第二芯片200和相对应的第一芯片110构成芯片模块，引出端190用于作为芯片模块的输入输出端，且后续能够通过引出端190将芯片模块键合至其他基板（电路板）上。
本实施例中，引出端190包括导电凸块（bump）180，导电凸块180即为焊料凸点，采用凸块工艺形成，与通过打线（wire bond）工艺形成的引线相比，本实施例所述封装结构能够通过晶圆级封装方法获得。具体地，引出端190包括：再布线层160，位于覆盖层170的顶面上且与插塞320的顶端相连；导电凸块180，位于再布线层160上且电连接再布线层160。
再布线层160用于对互连结构305进行再分布。本实施例中，再布线层160的材料为铝。在其他实施例中，再布线层还可以为其他可适用的导电材料。
通过选用导电凸块180，有利于降低导电凸块180的厚度，从而减小封装结构的厚度。本实施例中，导电凸块180的材料为铜。
因此，晶圆级封装结构还包括：覆盖部分再布线层160的钝化层170，导电凸块180位于钝化层170中。钝化层170用于对再布线层160之间进行绝缘，且还用于为导电凸块180的形成提供工艺平台，此外，钝化层170还能够起到防水、防氧化和防污染等作用。
本实施例中，钝化层170的材料为光敏材料。具体地，钝化层170的材料可以为光敏聚酰亚胺、光敏苯并环丁烯或光敏聚苯并噁唑。
在其他实施例中，引出端也可以包括植球。
所述封装结构可以采用前述实施例所述的封装方法所形成，也可以采用其他封装方法所形成。对本实施例所述封装结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种晶圆级封装方法，其特征在于，包括：
    提供形成有多个第一芯片的晶圆，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有第一互连电极和外接电极；
    提供多个第二芯片和多个互连芯片，所述第二芯片的表面具有第二互连电极，所述互连芯片包括相对的第三表面和第四表面，所述互连芯片中形成有互连结构，所述互连芯片的第三表面暴露部分所述互连结构；
    将所述第二芯片和所述互连芯片键合于所述第一芯片的第一表面上；
    形成第一互连凸块，用于实现所述第一互连电极和所述第二互连电极之间的电连接，形成第二互连凸块，用于实现所述外接电极和所述互连结构之间的电连接。
  2. 如权利要求1所述的晶圆级封装方法，其特征在于，所述互连结构包括插塞，所述插塞为所述互连芯片的第三表面暴露的部分；
    或者，
    所述互连结构包括插塞、与所述插塞连接的互连线、以及焊垫，所述焊垫为所述互连芯片的第三表面暴露的部分。
  3. 如权利要求1所述的晶圆级封装方法，其特征在于，所述互连结构包括互连线和焊垫，所述焊垫为所述互连芯片的第三表面暴露的部分；
    形成所述第一互连凸块和第二互连凸块后，所述晶圆级封装方法还包括：形成从所述第四表面嵌于所述互连芯片中的插塞，所述插塞与所述互连线相连。
  4. 如权利要求1所述的晶圆级封装方法，其特征在于，提供多个互连芯片的步骤包括：提供半导体衬底；
    在所述半导体衬底中形成多个第一互连结构；
    形成所述第一互连结构后，对所述半导体衬底进行切割，获得多个分立的互连芯片。
  5. 如权利要求1所述的晶圆级封装方法，其特征在于，将所述第二芯片键合于所述第一芯片上后，所述第二互连电极和所述第一互连电极上下相对，围成第一空腔；利用电镀工艺在所述第一空腔中形成所述第一互连凸块；
    或者，
    将所述第二芯片键合于所述第一芯片上之前，在所述第二互连电极或所述第一互连电极上形成所述第一互连凸块，利用压焊工艺将所述第二芯片焊接至所述第一芯片上，使所述第一互连电极和所述第二互连电极通过所述第一互连凸块电连接；其中，所述压焊工艺为所述键合，或者，在所述压焊工艺之后进行所述键合。
  6. 如权利要求1所述的晶圆级封装方法，其特征在于，将所述互连芯片键合于所述第一芯片上后，所述互连结构和所述外接电极上下相对，围成第二空腔；利用电镀工艺在所述第二空腔中形成所述第二互连凸块；
    或者，
    将所述互连芯片键合于所述第一芯片上之前，在所述互连结构或所述外接电极上形成所述第二互连凸块，利用压焊工艺将所述互连芯片焊接至所述第一芯片上，使所述互连结构和所述外接电极通过所述第二互连凸块电连接；其中，所述压焊工艺为所述键合，或者，在所述压焊工艺之后进行所述键合。
  7. 如权利要求5或6所述的晶圆级封装方法，其特征在于，所述电镀工艺为无极电镀工艺。
  8. 如权利要求1所述的晶圆级封装方法，其特征在于，每个所述第二芯片以及每个所述互连芯片均以芯片级的方式单独键合于所述晶圆上；
    或者，
    在将所述第二芯片和所述互连芯片键合于所述晶圆之前，所述第二芯片和所述互连芯片临时键合于承载基板上；
    在将所述第二芯片和所述互连芯片键合于所述晶圆之后，去除所述承载基板。
  9. 如权利要求1所述的晶圆级封装方法，其特征在于，利用粘接层将所述第二芯片和所述互连芯片键合于所述第一芯片的第一表面上，所述粘接层的材料为光敏材料。
  10. 如权利要求1所述的晶圆级封装方法，其特征在于，所述互连芯片的厚度大于或等于所述第二芯片的厚度。
  11. 如权利要求1所述的晶圆级封装方法，其特征在于，所述晶圆级封装方法还包括：形成所述第一互连凸块和第二互连凸块后，在所述晶圆上形成覆盖所述第二芯片、互连芯片、第一互连凸块和第二互连凸块的覆盖层，所述覆盖层露出所述互连芯片的第四表面；
    在所述覆盖层的顶面上形成与所述互连结构电连接的引出端。
  12. 如权利要求11所述的晶圆级封装方法，其特征在于，利用凸块工艺或植球工艺，形成所述引出端。
  13. 一种封装结构，其特征在于，包括：
    基底，所述基底中形成有第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有第一互连电极以及外接电极；
    第二芯片，键合于所述第一芯片的第一表面上，所述第二芯片的表面具有第二互连电极；
    互连芯片，键合于所述第一芯片的第一表面上，所述互连芯片包括相对的第三表面和第四表面，所述互连芯片中形成有互连结构，所述互连芯片的第三表面暴露部分所述互连结构；
    第一互连凸块，电连接所述第一互连电极和所述第二互连电极；
    第二互连凸块，电连接所述外接电极和所述互连结构。
  14. 如权利要求13所述的封装结构，其特征在于，所述互连结构包括插塞，所述插塞为所述互连芯片的第三表面暴露的部分；
    或者；
    所述互连结构包括插塞、与所述插塞连接的互连线、以及焊垫，所述焊垫为所述互连芯片的第三表面暴露的部分。
  15. 如权利要求13所述的封装结构，其特征在于，所述第二互连电极和所述第一互连电极上下相对，所述第一互连结构和所述外接电极上下相对；
    所述第一互连凸块位于所述第一互连电极和所述第二互连电极之间，所述第二互连凸块位于所述外接电极和所述第一互连结构之间。
  16. 如权利要求13所述的封装结构，其特征在于，所述封装结构还包括：粘接层，位于所述第二芯片和所述第一芯片之间、以及所述互连芯片和所述第一芯片之间，所述粘接层的材料为光敏材料。
  17. 如权利要求13所述的封装结构，其特征在于，所述互连芯片的厚度大于或等于所述第二芯片的厚度。
  18. 如权利要求13所述的封装结构，其特征在于，所述封装结构还包括：覆盖层，位于所述基底上且覆盖所述第二芯片、互连芯片、第一互连凸块和第二互连凸块，所述覆盖层露出所述互连芯片背向所述基底的面；
    引出端，位于所述覆盖层的顶面上且电连接所述互连结构。
  19. 如权利要求18所述的封装结构，其特征在于，所述引出端包括焊料凸点或植球。
  20. 如权利要求13所述的封装结构，其特征在于，所述基底为晶圆级基底或芯片级基底。
PCT/CN2021/105827 2020-07-14 2021-07-12 晶圆级封装方法以及封装结构 WO2022012475A1 (zh)

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