TWI787917B - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

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TWI787917B
TWI787917B TW110127036A TW110127036A TWI787917B TW I787917 B TWI787917 B TW I787917B TW 110127036 A TW110127036 A TW 110127036A TW 110127036 A TW110127036 A TW 110127036A TW I787917 B TWI787917 B TW I787917B
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Taiwan
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die
layer
isolation
isolation layer
top surface
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TW110127036A
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TW202230541A (zh
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陳憲偉
陳明發
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台灣積體電路製造股份有限公司
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Abstract

提供封裝及其製作方法。所述封裝包括：第一晶粒，其中 所述第一晶粒包括自所述第一晶粒的第一表面朝向所述第一晶粒的第二表面的多個穿孔；第二晶粒，設置於第一晶粒下方，其中所述第一晶粒的所述第二表面接合至所述第二晶粒；隔離層，設置於所述第一晶粒中，其中所述多個穿孔延伸貫穿所述隔離層；包封體，在側向上圍繞所述第一晶粒，其中所述包封體在側向上與所述隔離層分離；緩衝層，設置於所述第一晶粒、所述隔離層及所述包封體上方；以及多個導電端子，設置於所述隔離層上方，其中所述多個導電端子電性連接至所述多個穿孔中的對應穿孔。

Description

半導體封裝及其製作方法
本揭露實施例是有關於封裝及其製作方法。
積體電路的封裝正變得日益複雜，越來越多的元件晶粒封裝在同一封裝中以達成更多的功能。舉例而言，已開發出積體晶片上系統(System on Integrate Chip，SoIC)以在同一封裝中包括多個元件晶粒，例如處理器及記憶體立方體。SoIC可包括使用不同技術形成的元件晶粒，並且具有接合至同一元件晶粒的不同功能，藉此形成系統。此可節省製造成本並最佳化元件效能。
依據本發明實施例提出一種封裝，包括：第一晶粒，其中所述第一晶粒包括自所述第一晶粒的第一表面朝向所述第一晶粒的第二表面延伸的多個穿孔；第二晶粒，設置於所述第一晶粒下方，其中所述第一晶粒的所述第二表面接合至所述第二晶粒；隔離層，設置於所述第一晶粒中，其中所述多個穿孔延伸貫穿所述隔離層；包封體，在側向上圍繞所述第一晶粒，其中所述包封體在側向 上與所述隔離層分離；緩衝層，設置於所述第一晶粒、所述隔離層及所述包封體上方；以及多個導電端子，設置於所述隔離層上方，其中所述多個導電端子電性連接至所述多個穿孔中的對應穿孔。
依據本發明實施例提出一種封裝，包括：第一晶粒，其中所述第一晶粒包括第一基底，所述第一晶粒更包括自所述第一基底的頂表面朝向所述第一晶粒的底表面延伸的第一穿孔及第二穿孔；隔離層，設置於所述第一基底的所述頂表面中的凹陷中，所述隔離層圍繞所述第一穿孔及所述第二穿孔，其中所述第一基底在俯視圖中圍繞所述隔離層；以及第一包封體，在側向上圍繞所述第一晶粒，其中所述第一基底夾置於所述隔離層與所述第一包封體之間。
依據本發明實施例提出一種製造封裝結構的方法，所述方法包括：將第一晶粒的第一表面接合至第二晶粒，其中所述第一晶粒包括第一穿孔；在所述第一晶粒的旁邊側向上形成包封體；在所述第一晶粒的第二表面中形成第一凹陷，所述第一凹陷在所述第一穿孔周圍延伸；以及在所述第一凹陷中形成隔離層，其中所述隔離層藉由所述第一晶粒與所述包封體分離。
100:晶圓
101、151:開口
102:載體基底
104、104’、204:晶粒
104a、105a’、204a:前表面
104b’、105b’:後表面
105、105’:基底
108、117、133、146、150、154、158、217:介電層
109’:基底穿孔(TSV)
109i’、209i:黏著劑層
109j’:襯墊
111:介電結構/介電層
113:金屬化結構
114、114’、214:內連線結構
115:接觸接墊
116:鈍化層
118:導電柱/穿孔/積體扇出型穿孔(TIV)
119、219:絕緣層/介電層
120、120’、220:接合結構
121:通孔/開口
123、123’、223、503、504:接合接墊
124:釋放層
125:虛設接墊/虛設接合接墊
125’、225:虛設接墊
127:包封體
127b:最頂部表面/頂表面
127S、130S:側壁
128:黏著劑
129:罩幕層
130’:隔離材料層
1301:氮化物層
1301’:氮化物材料層
1302:氧化物層
1302’:氧化物材料層
130A、130B、130C、130E、130F、130G、130H、130I:隔離層
130a、204b、209a、209b:頂表面
130D:隔離部/隔離層
130E1、130E2、130F1、130F2、130F3、130F4、130G1、130G2、130G3:隔離部
130P、130P1、130P2、130P21、130P22:虛設部分
131:重佈線結構
135、148、152、156:金屬化圖案
135M、148C、152C、156C:導線
135V、148V、152V、156V:導通孔
137:緩衝層
139:晶種層
141:導電材料
142:包封體
143:導電端子/晶粒連接件
143P:虛設端子
144:前側重佈線結構
145:導電帽
147:絕緣層
160:凸塊下金屬(UBM)
162、168:導電連接件
166:封裝
170:底部填料
204c:背側表面
205、502:基底
205a:前表面/頂表面
205b:頂表面
205-BS:底部
205c:表面
205M:部分
205R:凹陷
205S:台階
209:導通孔/穿孔(TV)/基底穿孔(TSV)
209j:襯墊/介電層
215:接觸接墊
221:通孔
301、302、303:放大圖
500:頂部封裝
506:穿孔
508:堆疊晶粒/堆疊記憶體晶粒
510:引線接合
512:模塑材料
1000:晶圓級晶粒結構
1002、1003、1004、10041、10042、10043、10044、1006、1007、1008、1009、1010、1011、1012:三維積體電路(3DIC)結構
A、B:區
C、C1、C2、C3、C4:中心線
d1、d1L、d1R、d2L、d2R、d3L、d3R、dpp:距離
I-I、II-II:線
R1:第一區
R2:第二區
S10、S12、S14、S16、S18、S20、S22、S24、S26:步驟
W、W1、W1’、W2、W2’、W3、W3’、W4、WDT:寬度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺 寸。
圖1A至圖1J是示出根據本揭露一些實施例的一種形成三維積體電路(three-dimensional integrated circuit，3DIC)結構的方法的示意性剖視圖。
圖2A至圖12是示出根據本揭露一些實施例的3DIC結構的各種示意圖。
圖13A至圖13E示出根據一些實施例形成封裝的剖視圖。
圖14示出根據一些實施例用於形成3DIC結構的製程流程。
以下揭露內容提供用於實施所提供標的物的不同特徵的許多不同的實施例或實例。以下闡述部件及排列的具體實例以簡化本揭露。當然，該些僅為實例而非旨在進行限制。舉例而言，在以下說明中，在第一特徵上方或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且亦可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複參考編號及/或字母。此種重複使用是為了簡明及清晰起見，且自身並不指示所討論的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「在...之下(beneath)」、「在...下方(below)」、「下部的(lower)」、「在...上(on)」、「在...上方(above)」、「上部的(upper)」等空間相對性用 語來闡述圖中所示一個組件或特徵與另一(其他)組件或特徵的關係。除了圖中所繪示的取向以外，所述空間相對性用語還旨在囊括元件在使用或操作中的不同取向。裝置可以其他方式取向(旋轉90度或處於其他取向)，且本文所用的空間相對性描述語可同樣相應地作出解釋。
根據各種實施例提供了封裝結構及其形成方法。在一些實施例中，封裝結構是積體晶片上系統(SoIC)封裝。根據一些實施例示出形成SoIC封裝的中間階段。在各種圖式及說明性實施例通篇中，相同的參考編號用於指示相同的組件。應理解，儘管使用SoIC封裝的形成作為實例來闡釋本揭露的實施例的概念，但本揭露的實施例可輕易應用於其中覆蓋圍繞頂部晶粒的包封體的表面以防止/減少包封體的蝕刻的其他封裝結構及封裝方法。因此，可保護包封體的頂表面不受凹坑缺陷的影響，並且可在露出頂部晶粒的基底穿孔(through substrate via，TSV)期間減少腔室污染。
圖1A至圖1J是示出根據本揭露一些實施例形成3DIC結構的方法的示意性剖視圖。圖2A是圖1G的俯視圖。圖2B是圖2A中一個區的放大圖。圖2C是圖2B的示意性剖視圖。圖1A至圖1J亦示意性地反映在圖14所示的製程流程中。
圖1A至圖1C示出接合至晶圓100並在側向上由包封體127包封的晶粒204。
參照圖1A，提供具有多個晶粒104的晶圓100。根據本揭露的一些實施例，晶粒104包括IC晶粒，且可為邏輯晶粒(例 如，中央處理單元、圖形處理單元、系統晶片、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(digital signal processing，DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end，AFE)晶粒)、類似物或其組合。此外，在一些實施例中，晶粒104可為不同的大小(例如，不同的高度及/或表面積)，並且在其他實施例中，晶粒104可為相同的大小(例如，相同的高度及/或表面積)。
晶圓100包括基底105及位於基底105上方的接合結構120。在一些實施例中，基底105可由矽形成，但其亦可由其他III族、IV族及/或V族元素或化合物(例如，矽、鍺、鎵、砷及其組合)形成。基底105亦可呈絕緣體上矽(silicon-on-insulator，SOI)的形式。SOI基底可包括形成於絕緣體層(例如，掩埋氧化物及/或類似物)上方的半導體材料(例如，矽、鍺及/或類似物)層，所述絕緣體層形成在半導體(例如，矽)基底上。此外，可使用的其他基底包括多層式基底、梯度基底、混合取向基底、其任意組合及/或類似物。
晶圓100可更包括一或多個積體電路元件、內連線結構 114、接觸接墊115、鈍化層116及位於基底105與接合結構120之間的介電層117。積體電路元件可包括主動及/或被動元件。一或多個主動及/或被動元件可形成在基底105上及/或基底105中。在一些實施例中，所述一或多個主動及/或被動元件可包括各種n型金屬氧化物半導體(NMOS)及/或p型金屬氧化物半導體(PMOS)元件，例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲及/或類似物。內連線結構114形成於基底105及所述一或多個主動及/或被動元件上方。內連線結構114可在基底105上形成的一或多個積體電路元件之間提供電性連接。內連線結構114可包括形成於介電結構111中的金屬化結構113。
介電結構111可包括多個介電層(例如，層間介電層(ILD)及金屬間介電層(IMD)。在一些實施例中，介電結構111包括一或多層無機及/或有機介電材料。舉例而言，介電層111的材料可包括一或多層氧化矽、氮化矽、氮氧化矽、碳化矽、低介電常數介電材料，例如未經摻雜的矽酸鹽玻璃(USG)、磷矽酸鹽玻璃(PSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、氟化二氧化矽玻璃(FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合或類似物。
金屬化結構113包括多個彼此內連並嵌入介電結構111中的導電特徵。導電特徵可包括多層導線、導通孔及導電接觸件。導電接觸件可形成於ILD中，以將導線電性連接至元件；導通孔可形成於IMD中，以電性連接不同層中的導線。金屬化結構113 的導電特徵可包含金屬、金屬合金或其組合。舉例而言，導電特徵可包含鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或其組合。在一些實施例中，金屬化結構113的最頂部導電特徵具有與介電結構111的頂表面實質上共面的頂表面，但本揭露並非僅限於此。
在一些實施例中，鈍化層116形成於內連線結構114上，以覆蓋介電結構111及金屬化結構113。鈍化層116可包含介電材料，例如氧化矽、氮化矽、氮氧化矽或其組合。在實施例中，鈍化層116的材料不同於介電結構111的下伏介電層。舉例而言，介電結構111的最頂部介電層包含氧化矽，而鈍化層116包含氮化矽。然而，本揭露並非僅限於此。
接觸接墊115形成於內連線結構114上方。接觸接墊115形成於鈍化層116上並穿透鈍化層116，以電性連接至內連線結構114的頂部導電特徵，並且可經由金屬化結構113電性耦合至一或多個主動及/或被動元件。在一些實施例中，接觸接墊115可包含導電材料，例如鋁、銅、鎢、銀、金、其組合或類似物。
介電層117形成於內連線結構114及接觸接墊115上方。在一些實施例中，介電層117可包含一或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、其組合或類似物。在其他實施例中，介電層可包含一或多層可光圖案化的絕緣材料，例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合或類似物。在一些實施例中，使用化學機械研磨(CMP)製 程、拋光製程、蝕刻製程、其組合或類似製程來平坦化介電層。
參照圖1A，於介電層117上形成接合結構120。接合結構120包括形成於介電層117上的絕緣層119及形成於絕緣層119中的接合接墊123。在一些實施例中，接合結構120更包括形成於絕緣層119中的虛設接墊125。在一些實施例中，接合接墊123與形成於介電層117且穿透鈍化層116的通孔121直接電性接觸，以電性連接至金屬化結構113的最頂部導電特徵。在替代實施例中，接合接墊123與著陸在接觸接墊115上的通孔(未示出)直接電性接觸。
在一些實施例中，絕緣層119包括一或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、其組合或類似物，並且可使用化學氣相沈積(CVD)、物理氣相沈積(PVD)、原子層沈積(ALD)、旋塗製程、其組合或類似技術形成。在一些實施例中，使用CMP製程、拋光製程、蝕刻製程、其組合或類似製程來平坦化絕緣層119。在一些實施例中，絕緣層119與下伏介電層可包含相同的材料。在其他實施例中，絕緣層119與下伏介電層可包含不同的材料。
在一些實施例中，接合接墊123、虛設接墊125及通孔121可包含例如鋁、銅、鎢、銀、金、其組合或類似物等導電材料。在一些實施例中，可使用例如PVD、ALD、電化學鍍覆、無電鍍覆、其組合或類似技術在內連線結構上方形成導電材料。隨後，使 用合適的微影及蝕刻方法圖案化導電材料以形成接觸接墊。接合接墊123、虛設接墊125及通孔121可使用例如鑲嵌製程、雙鑲嵌製程、其組合或類似製程形成於絕緣層119中。在一些實施例中，接合接墊123、虛設接墊125及絕緣層119被平坦化，使得接合接墊123最頂部表面及虛設接墊125的最頂部表面實質上與絕緣層119的最頂部表面齊平或共面。
參照圖1A，將晶粒204接合至晶圓100的第一側上的晶粒104，以開始形成晶圓級晶粒結構1000。相應的製程被示出為圖14所示製程流程中的步驟S10。晶粒204可為已自另一半導體晶圓單體化的晶粒。儘管圖中示出一個晶粒104及一個晶粒204，但晶粒104及204的數量在本揭露中不受限制。
晶粒204及晶粒104可為相同類型的晶粒或不同類型的晶粒，並且晶粒的類型在本揭露中不受限制。晶粒204可為邏輯晶粒(例如，中央處理單元、圖形處理單元、系統晶片、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(DSP)晶粒)、前端晶粒(例如，類比前端(AFE)晶粒)、類似物或其組合。此外，在其中多個晶粒204接合至晶圓100的一些實施例中，晶粒204可為不同的大小(例如，不同的高度及/或表面積)，而在其他實施例中，晶粒204可為相同的大小(例如，相 同的高度及/或表面積)。
晶粒204可包括基底205、一或多個主動及/或被動元件(未示出)、及內連線結構214、接觸接墊215、介電層217、通孔221及接合結構220。接合結構220包括接合接墊223、虛設接墊225及絕緣層219。在一些實施例中，晶粒204的基底205、內連線結構214、接觸接墊215、介電層217、通孔221以及接合結構220的材料及形成方法可類似於晶圓100的基底105、內連線結構114、接觸接墊115、介電層117、通孔121及接合結構120，且因此在此不再予以贅述。
在一些實施例中，晶粒204更包括形成於基底205中並電性連接至內連線結構214的導通孔209。在一些實施例中，導通孔209可排列成陣列、多個陣列、不規則排列或以其組合形式排列。導通孔209可延伸至內連線結構214中，以與內連線結構214的導電特徵物理及電性接觸。在一些實施例中，藉由在基底205中形成開口並用合適的導電材料填充所述開口來形成導通孔209。在一些實施例中，可使用合適的微影及蝕刻方法來形成開口。可使用物理氣相沈積(PVD)、原子層沈積(ALD)、電化學鍍覆、無電鍍覆或其組合、類似技術來用銅、銅合金、銀、金、鎢、鉭、鋁、鋁合金、其組合或類似物來填充開口。在一些實施例中，在用合適的導電材料填充開口之前，可在開口中形成襯墊209j及/或黏著劑層209i。襯墊209j可包含介電材料，例如氧化矽、氮化矽、氮氧化矽或類似物、或其組合。黏著劑層209i可包含Ta、TaN、Ti、TiN 或其組合。
可應用各種合適的接合技術將晶粒204接合至晶圓100。舉例而言，可藉由混合接合、熔融接合或類似接合、或其組合將晶粒204接合至晶圓100。舉例而言，晶粒204至晶圓100的接合可藉由混合接合來實現，所述混合接合涉及至少兩種類型的接合，包括例如金屬對金屬接合及非金屬對非金屬接合(例如，介電質對介電質接合)。在一些實施例中，接合接墊223接合至晶粒(或稱為底部晶粒)104的接合接墊123，並且虛設接墊225藉由金屬對金屬直接接合接合至晶粒104的虛設接墊125。根據本揭露的一些實施例，金屬對金屬直接接合是銅對銅直接接合。接合接墊223的大小可大於、等於或小於相應接合接墊123的大小。虛設接墊225的大小可大於、等於或小於相應虛設接合接墊125的大小。此外，可藉由介電質對介電質接合(其可為例如產生Si-O-Si接合的熔融接合)將絕緣層219接合至絕緣層119。
在一些實施例中，可如下所述執行接合製程。首先，為避免出現未接合區域(例如，介面氣泡)，將晶粒204及晶粒104的待接合表面處理得足夠乾淨及光滑。然後，將晶粒204拾取並放置在晶粒10上，將晶粒204及晶粒104對準並在室溫下以輕微的壓力放置成物理接觸，以啟動接合操作。此後，執行熱處理，例如高溫下的退火製程，以增強晶粒204及晶粒104的待接合表面之間的化學鍵，並將化學鍵轉化為共價鍵。在一些實施例中，在晶粒104的接合結構120與元件晶粒20的接合結構220之間形成接合 介面。在一些實施例中，接合介面是混合接合介面，包括接合接墊123與接合接墊223之間以及虛設接墊125與虛設接墊225之間的金屬對金屬接合介面以及介電層119與介電層219之間的介電質對介電質接合介面。
在一些實施例中，晶粒204以面對面的配置接合至晶粒104。亦即，晶粒204的前表面面向晶粒104的前表面104a。然而，本揭露並非僅限於此。在一些實施例中，晶粒204可以如圖12所示的面對背配置接合至晶粒104’。換言之，晶粒104’及晶粒204中的一者的前表面可面向晶粒104’及晶粒204中的另一者的後表面，或者晶粒204的後表面可面向晶粒104’的後表面。在說明書通篇中，晶粒的「前表面」是指靠近接觸接墊的表面，且亦可被稱為主動表面；晶粒的「後表面」是與前表面相對的表面，並且可為基底的表面，其亦可被稱為後方表面。
參照圖1A，在將晶粒204接合至晶粒104之後，可執行背側研磨製程以使晶粒204變薄，並且在背側研磨製程之後導通孔209可不露出。如圖1A所示，在一些實施例中，導通孔209可不自晶粒204的頂表面(例如，後表面)204b露出，當存在基底205的薄層覆蓋導通孔209時，停止背側研磨。然而，本揭露並非僅限於此。在一些其他實施例中，此時露出導通孔209，並且導通孔209的頂表面及襯墊209j的頂表面可實質上與基底205的頂表面(例如，後表面)共面。在一些實施例中，可跳過背側研磨製程。在一些實施例中，在執行平坦化製程以移除包封體127(如圖1B 所示)的位於晶粒204頂部上方的一部分之後，可露出導通孔209。
參照圖1B，於晶粒204上方並圍繞晶粒204形成包封體127。相應的製程被示出為圖14所示製程流程中的步驟S12。在一些實施例中，包封體127包含一或多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、其組合或類似物，並且可使用CVD、PVD、ALD、旋塗製程、其組合或類似技術形成。在其他一些實施例中，包封體127包含一或多層可光圖案化的絕緣材料，例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合或類似物，並且可使用旋塗製程或類似製程形成。此種可光圖案化的絕緣材料可使用與光阻材料類似的微影方法來圖案化。在一些實施例中，包封體127包含模塑化合物，例如環氧樹脂、樹脂、可模塑聚合物、其組合或類似物。模塑化合物可在實質上為液體的情況下施加，且然後可例如在環氧樹脂或樹脂中經由化學反應固化。在一些實施例中，模塑化合物是紫外線(UV)或熱固化聚合物，所述聚合物作為能夠設置在晶粒204周圍及之間的凝膠或延展性固體來施加。
參照圖1C，將包封體127及晶粒204平坦化，使得晶粒204的背側表面204c實質上與包封體127的最頂部表面127b齊平或共面。在一些實施例中，此時露出導通孔209，並且導通孔209的頂表面209b及襯墊209j的頂表面可實質上與基底205的頂表面(例如，後表面)205b共面。在此類實施例中，導通孔209亦 可被稱為穿孔(through via，TV)209或基底穿孔(through substrate via，TSV)209。在一些實施例中，平坦化製程可包括CMP製程、拋光製程、蝕刻製程、其組合或類似製程。為簡潔起見，在圖1D至圖1I中未示出基底105與絕緣層119之間以及基底205與絕緣層219之間的層、接觸接墊及組件。
圖1D至圖1E示出根據本揭露一些實施例在晶粒204中形成凹陷205R。在一些實施例中，使用罩幕層129藉由圖案化製程形成凹陷205R。相應的製程被示出為圖14所示製程流程中的步驟S14至步驟S18。
參照圖1D，於晶粒104上形成罩幕層129，以覆蓋包封體127的頂表面127b及晶粒204的頂表面204b的一些部分。在一些實施例中，罩幕層129包括光阻層，並且可藉由旋轉塗佈形成。然後藉由可接受的製程，例如藉由使用將光阻層暴露至光而將光阻層圖案化。圖案化形成開口101，開口101暴露出TSV 209的頂表面209b及基底205的頂表面205b在TSV 209周圍的中心部分。
參照圖1D及圖1E，在一些實施例中，使由開口101暴露出的基底205凹陷，使得遍歷基底205形成凹陷205R，並且TSV 209自基底205突出。舉例而言，基底205的在側向上位於TSV 209旁邊的一些部分可藉由例如濕式蝕刻製程、乾式蝕刻製程或其組合等蝕刻製程移除。蝕刻製程可利用基底205與其他相鄰材料(即，TSV 209及襯墊209j)之間的高蝕刻選擇率。在一些 實施例中，在蝕刻製程之後，襯墊209j可實質上保留，但本揭露並非僅限於此。在一些實施例中，襯墊209j的一些部分亦可藉由蝕刻製程被移除。
在執行凹陷製程之後，由罩幕層129覆蓋的剩餘基底205形成凹陷205R的側壁，並且由開口101暴露出的剩餘基底205的表面205c形成凹陷205R的底部205-BS。凹陷205R可具有例如1微米至3微米的深度。在一些實施例中，如圖1E所示，凹陷205R的側壁可為直的，並且垂直於基底205的前表面205a。在一些實施例中，如圖3所示，凹陷205R的側壁可為傾斜的，並且朝向基底205的前表面205a呈錐形。
凹陷205R的底部暴露出基底205的表面205c，並且基底205的表面205c低於基底205的頂表面205b，並且所述兩者之間具有台階205S。此外，基底205的表面205c低於TSV 209的頂表面209a，使得TSV 209具有自基底205的表面205c(例如，凹陷205R的底部205-BS)突出的一些部分。
包封體127的頂表面127b及基底205的部分205M的頂表面205b被罩幕層129覆蓋，以防止/減少包封體127的蝕刻，並且在蝕刻製程期間不被凹陷205R暴露出。因此，可保護包封體127的頂表面127b免受凹坑缺陷的影響，並且可在露出TSV 209期間減少腔室污染。
圖1F至圖1G示出根據本揭露一些實施例形成嵌入晶粒204的基底205中的隔離層130A。在一些實施例中，隔離層130A 被形成為塊狀層並與包封體127分離。相應的製程被示出為圖14所示製程流程中的步驟S18至步驟S24。
參照圖1F，藉由可接受的灰化或剝離製程例如使用氧電漿或類似物來移除罩幕層129。於晶粒204及包封體127上形成隔離材料層130’，以覆蓋基底205的頂表面205a、TSV 209的頂表面209a及包封體127的頂表面127b，並填充凹陷205R。在一些實施例中，隔離材料層130’被形成為具有至少等於凹陷205R的高度的厚度(例如，TSV 209的自基底205的表面205c突出的部分的厚度)。換言之，隔離材料層130’完全填充凹陷205R。在一些實施例中，隔離材料層130’為共形層，亦即，隔離材料層130’具有沿著上面形成有隔離材料層130’的區延伸的在製程變化範圍內實質上相等的厚度。
隔離材料層130’可包含例如氮化矽等介電材料，但亦可將例如以下其他介電材料用於隔離材料層130’：氧化矽、碳化矽、氮化矽、氮氧化矽、摻氧碳化矽、摻氮碳化矽、聚合物(其可為例如PBO、聚醯亞胺或BCB等感光性材料)、低介電常數介電材料(例如，PSG、BPSG、FSG、SiOxCy、SOG)、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合或類似物。隔離材料層130’可使用例如CVD、原子層沈積(ALD)或類似沈積等合適的沈積製程形成。在一些實施例中，隔離材料層130’可為如圖1F所示的單個層。在一些實施例中，隔離材料層130’可為如圖4C所示的多個層，這將在稍後進行詳細描述。
參照圖1F及圖1G，執行平坦化製程以移除隔離材料層130’的位於TSV 209的頂表面209a及基底205的頂表面205b上方的一部分，從而露出TSV 209，並且形成隔離層130A。平坦化製程可包括CMP製程。
圖2A示出圖1G的俯視圖。圖2B示出圖2A中區A的放大圖。圖2C示出圖2B中線I-I的剖視圖。
參照圖1G及圖2A至圖2C，隔離層130A嵌入基底205中並在側向上圍繞TSV 209。隔離層130A圍繞TSV 209的上側壁。隔離層130A的側壁及底部被基底205圍繞。基底205的部分205M被包封體127圍繞。換言之，隔離層130A藉由基底205的先前被罩幕層129覆蓋的部分205M在側向上與包封體127分離，並且隔離層130A的側壁130S及包封體127的側壁127S具有非零距離d1。在一些實施例中，隔離層130A的側壁130S可為直的，並且垂直於基底205的前表面205a，但本揭露並非僅限於此。
參照圖1G，在一些實施例中，隔離層130A的頂表面130a在製程變化範圍內可與TSV 209的頂表面209a、基底205的頂表面205b及包封體127的頂表面127b實質上共面。在一些實施例中，隔離層130A可進一步延伸以覆蓋包封體127的頂表面127b(未示出)。
參照圖1G、圖2A、圖2B及圖2C，隔離層130A是塊狀層(或被稱為整體層或連續層)。隔離層130A可具有各種形狀，例如正方形、矩形、圓形及橢圓形或其組合。TSV 209的上側壁被 隔離層130A圍繞，TSV 209的中間側壁被基底205圍繞，且TSV 209的下側壁被內連線結構214圍繞。此外，在一些實施例中，黏著劑層209i及襯墊209j可夾置於TSV 209與隔離層130A、TSV 209與基底205、以及TSV 209與內連線結構214之間。
圖1H至圖1J示出根據本揭露一些實施例在包封體127及晶粒204之上形成緩衝層137、導電端子143及絕緣層147。相應的製程被示出為圖14所示製程流程中的步驟S20。
參照圖1H，於包封體127及晶粒204之上形成緩衝層137。緩衝層137可包括單個層或多個層。緩衝層137可包含氧化矽、氮化矽、氮氧化矽、USG、TEOS、聚合物或其組合。所述聚合物包含感光性材料，例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合或類似物。緩衝層137的形成方法包括合適的製作技術，例如旋轉塗佈、化學氣相沈積(CVD)、電漿增強化學氣相沈積(PECVD)、層疊或類似技術。
此後，於緩衝層137中形成開口151。開口151的大小可大於、等於或小於TSV 209的大小。在一些實施例中，開口151是介層窗孔並穿透緩衝層137以暴露出對應的TSV 209。在一些實施例中，開口151是溝渠，並穿透緩衝層137以暴露出TSV 209。形成開口151以進一步暴露出TSV 209周圍的隔離層130A。開口151的形成方法可包括微影及蝕刻製程、雷射鑽孔製程或其組合。在一些實施例中，隔離層130A及緩衝層137具有不同的材料，因此隔離層130A可在用於形成開口151的蝕刻製程期間用作蝕刻 終止層。開口151的側壁可為直的或傾斜的。在一些實施例中，開口151的側壁是傾斜的，並且朝向基底205的前表面205a呈錐形，但本揭露並非僅限於此。
參照圖1I，於緩衝層137上及開口151中形成導電端子143，以電性耦合至TSV 209。導電端子143可被稱為晶粒連接件143。在一些實施例中，導電端子143是例如銅柱等金屬柱。導電端子143的材料可包含銅、鋁、無鉛合金(例如，金、錫、銀、鋁或銅合金)或鉛合金(例如，鉛錫合金)。舉例而言，導電端子143可由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金或類似物形成，並且可為無鉛的或含鉛的。
在其中導電端子143是金屬柱的一些實施例中，導電端子143可包括位於開口151中的晶種層139及位於晶種層139上的導電材料141。作為形成導電端子143的實例，晶種層139形成於開口151的表面及緩衝層137的頂表面的一部分上。在一些實施例中，晶種層139是金屬層，所述金屬層可為單個層或包括由不同材料形成的多個子層的複合層。晶種層139可包含銅、鈦、氮化鈦、鉭、氮化鉭或類似物，並且可藉由ALD、CVD、物理氣相沈積(PVD)或類似技術形成。舉例而言，晶種層139包括鈦層及位於所述鈦層之上的銅層。晶種層139可使用例如PVD或類似技術形成。於晶種層139上形成光阻並將其圖案化。光阻可藉由旋轉塗佈或類似技術形成，並且可被暴露於光以進行圖案化。圖案化形成貫穿光阻的開口，以暴露出晶種層139。導電材料141形成於 光阻的開口中及晶種層139的被暴露出的部分上。導電材料141可藉由例如電鍍覆或無電鍍覆或類似鍍覆等鍍覆形成。導電材料141可包含金屬，如銅、鈦、鎢、鋁或類似物。移除光阻及晶種層139的上面未形成導電材料141的一些部分。可例如使用氧電漿或類似物藉由可接受的灰化或剝離製程移除光阻。一旦光阻被移除，便例如藉由使用可接受的蝕刻製程，例如藉由濕式蝕刻或乾式蝕刻來移除晶種層139的被暴露出的部分。晶種層139的剩餘部分及導電材料141形成導電端子143。
在一些實施例中，如放大圖303所示，導電端子143的底部著陸在TSV 209上。在一些實施例中，如放大圖302所示，導電端子143的底部著陸在TSV 209及襯墊209j上。在一些實施例中，如放大圖301所示，導電端子143的底部著陸在TSV 209、襯墊209j及隔離層130A上，並且導電端子143藉由隔離層130A與基底205隔離。
在一些實施例中，金屬柱可為無焊料的，並且具有實質上垂直的側壁。在一些實施例中，於導電端子143的頂部上形成導電帽145。所述導電帽可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物或其組合，並且可藉由鍍覆製程形成。
參照圖1I及圖1J，對晶圓100執行晶片探測製程或其他合適的晶片測試製程，以辨識已知良好晶粒及不良晶粒。在晶片探測製程之後，移除導電帽145。此後，於導電端子143及緩衝層137上形成絕緣層147。在一些實施例中，絕緣層147可包含一或 多層不可光圖案化的絕緣材料，例如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、其組合或類似物，並且可使用CVD、PVD、ALD、旋塗製程、其組合或類似技術形成。在其他實施例中，絕緣層147可包含一或多層可光圖案化的絕緣材料，例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合或類似物，並且可使用旋塗製程或類似技術形成。此種可光圖案化的絕緣材料可使用與光阻材料類似的微影方法來圖案化。在一些實施例中，使用CMP製程、拋光製程、蝕刻製程、其組合或類似製程來平坦化絕緣層147。
在一些實施例中，此後，例如藉由鋸切、雷射燒蝕、蝕刻、其組合或類似技術將晶圓100單體化，以形成個別3DIC結構1002，並且3DIC結構1002中的一者在圖1J中示出。3DIC結構1002亦被稱為SoIC結構。相應的製程被示出為圖14所示製程流程中的步驟S26。
圖3至圖12是示意性剖視圖，其示出根據本揭露其他一些實施例的各種3DIC結構1003、1004、10041、10042、10043、10044、1006、1007、1008、1009、1010、1011及1012。
參照圖3，3DIC結構1003類似於3DIC結構1002，不同之處在於3DIC結構1003的隔離層130B的側壁130S是傾斜的，並且朝向基底205的前表面205a呈錐形，但本揭露並非僅限於此。隔離層130B的側壁130S的形狀可藉由調整用於在基底205中形成凹陷205R的蝕刻製程的蝕刻參數來形成。
參照圖4C，3DIC結構1004類似於3DIC結構1002，其中3DIC結構1004的隔離層130C包括多個層。所述多個層包含例如氮化矽等介電材料，但亦可使用例如以下其他介電材料：氧化矽、碳化矽、氮化矽、氮氧化矽、摻氧碳化矽、摻氮碳化矽、聚合物(其可為例如PBO、聚醯亞胺或BCB等感光性材料)、低介電常數介電材料(例如，PSG、BPSG、FSG、SiOxCy、SOG)、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合或類似物。在一些實施例中，3DIC結構1004的隔離層130C包括例如氮化矽層等氮化物層1301及例如氧化矽層等氧化物層1302。氮化物層1301形成於基底205上以提供良好的耐水性，而氧化物層1302形成於氮化物層1301上以釋放來自氮化物層1301的應力。
圖4A至圖4C是示出根據本揭露一些實施例形成3DIC結構1004的方法的示意性剖視圖。
參照圖4A至圖4C，可藉由各種方法形成氧化物層1302及氮化物層1301。在一些實施例中，共形地形成氮化物材料層1301’，並且所述氮化物材料層1301’具有沿著包封體127的頂表面127b、基底的頂表面205b、凹陷205R的側壁及底部、襯墊209j的側壁以及TSV 209的頂表面209a延伸的實質上相等的厚度。如圖4A所示，然後在氮化物層1301上形成氧化物材料層1302’。執行平坦化製程以移除氧化物材料層1302’及氮化物材料層1301’的一部分，從而露出TSV 209，並且如圖4B所示形成氧化物層1302及氮化物層1301。此後，如圖4C所示，在包封體127及晶粒204之上形 成緩衝層137、導電端子143及絕緣層147。
3DIC結構1004可為圖5A至圖5D所示的3DIC結構10041、10042、10043或10044。圖5A至圖5D示出根據各種實施例的圖4C中區B的放大圖。
參照圖5A至圖5D，氮化物層1301填充在凹陷205R的空間中，使得氮化物層1301的底表面與基底205接觸，並且氮化物層1301的側壁與襯墊209j接觸。氧化物層1302填充在自氮化物層1301保留的凹陷205R的空間中。
在一些實施例中，如圖5A所示，氮化物層1301的頂表面及氧化物層1302的頂表面與緩衝層137接觸，而不與導電端子143接觸。在一些實施例中，如圖5B所示，氮化物層1301的頂表面與導電端子143接觸，且氧化物層1302與緩衝層137接觸。在一些實施例中，如圖5C所示，氮化物層1301的頂表面與導電端子143接觸，且氧化物層1302與導電端子143及緩衝層137接觸。在一些實施例中，如圖5D所示，氮化物層1301的頂表面與導電端子143及緩衝層137接觸，且氧化物層1302與緩衝層137接觸。在一些實施例中，氧化物層1302的頂表面實質上與氮化物層1301的頂表面、基底205的頂表面205b、包封體127的頂表面207a、及襯墊209j的頂表面、黏著劑層209i的頂表面及TSV 209的頂表面共面。
圖6A至圖6G是示出根據本揭露一些實施例的3DIC結構1006的各種示意圖。圖6B至圖6D示出圖6A中線II-II的俯 視圖。圖6F及圖6G示出圖6E中線II-II的俯視圖。
參照圖6A至圖6G，3DIC結構1006類似於3DIC結構1002，其中利用了多個隔離部130D。所述多個隔離部130D中的每一者可具有例如以上參照130A、130B及/或130C論述的形式等形式。在一些實施例中，所述多個隔離部130D中的一者或每一者可為如圖6B及圖6F所示在TSV 209中的對應一或多者周圍的圓，如圖6D及圖6G所示在TSV 209中的對應一或多者周圍的條帶、或如圖6D及圖6H所示在TSV 209中的對應一或多者周圍的彎曲線。然而，本揭露的實施例並非僅限於該些實施例，所述多個隔離部130D可包括各種形狀，並且該些形狀可為規則的或不規則的。
所述多個隔離部130D中的每一者可圍繞相同數量的TSV 209。在一些實施例中，如圖6B及圖6F所示，所述多個隔離部130D中的每一者圍繞一個TSV 209。在一些實施例中，如圖6C及圖6G所示，所述多個隔離部130D中的每一者圍繞四個TSV 209。所述多個隔離部130D可具有近似相同的寬度W及相同的面積。所述多個隔離部130D的在對應的介電層209j的側壁與隔離部130D的最近邊緣之間的一部分的寬度w1或w2例如為約0.5微米至1.5微米。
在一些實施例中，如圖6A至圖6D所示，所述多個隔離部130D中的每一者被佈置成與對應的TSV 209的中心或中心線C對齊。在一些實施例中，如圖6E至圖6H所示，所述多個隔離 部130D中的每一者被佈置成偏離對應的TSV 209的中心或中心線C。所述多個隔離部130D中的相鄰隔離部之間的距離dpp可相同或不同。
圖7A及圖7B是示出根據本揭露一些實施例的3DIC結構1007的各種示意圖。圖7B示出圖7A中線II-II的俯視圖。
參照圖7A及圖7B，3DIC結構1007類似於3DIC結構1006，其中3DIC結構1006的隔離層130E包括彼此分離的隔離部130E1及130E2。所述多個隔離部130E1及130E2中的每一者可具有例如以上參照130A、130B及/或130C論述的結構等結構。隔離部130E1及130E2可圍繞不同數量的TSV 209。此外，隔離部130E1及130E2可具有便於佈局設計的不同的寬度W1及W2、不同的面積或不同的形狀。在一些實施例中，隔離部130E1圍繞一行TSV 209，且隔離部130E2圍繞兩行TSV 209，並且隔離部130E1的寬度W1小於隔離部130E2的寬度W2，但本揭露並非僅限於此。
如圖7A所示，3DIC結構1007更包括設置於導電端子143之間的虛設端子143P。虛設端子143P浮置設置於緩衝層137上，並且不穿入緩衝層137中。TSV 209不設置於虛設端子143P下方，並且隔離層130E不延伸至虛設端子143P下方。在一些實施例中，如圖7A及圖7B所示，隔離部P1與P2之間的距離dpp在一些實施例中大於虛設端子143P的寬度WDT。
圖8A至圖8C是示出根據本揭露一些實施例的3DIC結構1008的各種示意圖。圖8B及圖8C示出圖8A中線II-II的俯 視圖。
參照圖8A至圖8C，3DIC結構1008類似於3DIC結構1007，其中3DIC結構1009的隔離層130F包括彼此分離的隔離部130F1、130F2、130F3及130F4。所述多個隔離部130F1、130F2、130F3及130F4中的每一者可具有例如以上參照130A、130B及/或130C論述的結構等結構。
3DIC結構1008的晶粒205包括第一區R1及第二區R2。第一區R1中TSV 209的密度低於第二區R2中TSV 209的密度。在一些實施例中，如圖8B所示，為達成CMP均勻性，隔離部130F1、130F2、130F3及130F4中的每一者被形成為圍繞相同數量的TSV 209的條帶。在一些實施例中，如圖8C所示，為達成CMP均勻性，隔離部130F1及130F2中的每一者被形成為圍繞兩個TSV 209的矩形，並且隔離部130F3及130F4中的每一者被形成為圍繞四個TSV 209的條帶。隔離部130F1、130F2、130F3及130F4可分別形成為具有不同的寬度W1、W2、W3及W4以及不同的面積。在一些實施例中，寬度W1大於寬度W2，寬度W2大於W3，寬度W3大於W4，但本揭露並非僅限於此。此外，隔離部130F1及130F2可在虛設端子143P下方延伸，以進一步改善CMP均勻性。在一些實施例中，隔離部130F1、130F2及130F3被佈置成分別與對應的TSV 209的中心線C1、C3及C4對準。隔離部130F2被佈置成自對應的TSV 209的中心線C2偏離。
圖9A至圖9C是示出根據本揭露一些實施例的3DIC結 構1009的各種示意圖。圖9B及圖9C示出圖9A中線II-II的俯視圖。
參照圖9A至圖9C，3DIC結構1009類似於3DIC結構1006，不同之處在於3DIC結構1009的隔離層130G包括彼此分離的隔離部130G1、130G2及130G3以及虛設部分130P。隔離部130G1、130G2及130G3以及虛設部分130P中的每一者可具有例如以上參照130A、130B及/或130C論述的結構等結構。隔離部130G1、130G2及130G3圍繞相同數量的TSV 209。隔離部130G1、130G2及130G3具有近似相同的寬度W，但本揭露並非僅限於此。虛設部分130P包括虛設部分130P1及130P2。虛設部分130P1及130P2不圍繞任何TSV 209。
虛設部分130P1設置於虛設端子143P下方，並且在側向上與隔離部130G1、130G2及130G3分離。虛設部分130P2包括虛設部分130P21及虛設部分130P22。每一虛設部分130P21及130P22在側向上與隔離部130G1、130G2及130G3以及包封體127分離。虛設端子143P及導電端子143不設置於虛設部分130P21及130P22上，並且不將TSV 209設置為穿透虛設部分130P2。
虛設部分130P1、130P21及130P22可具有相同的形狀或不同的形狀。虛設部分130P1、130P21及130P22的形狀可與隔離部130G1、130G2及130G3的形狀相同或不同。在一些實施例中，虛設部分130P1、130P21及130P22以及隔離部P是如圖9B所示的條帶。在一些實施例中，虛設部分130P1、130P21及130P22以 及隔離部130G1、130G2及130G3是如圖9C所示的圓。然而，本揭露的實施例並非僅限於此，且虛設部分130P1、130P21及130P22以及隔離部130G1、130G2及130G3的形狀不受特別限制，並且可根據設計進行調節及改變。
虛設部分130P1、130P21及130P22具有寬度W1’、W2’及W3’，並且寬度W1’、W2’及W3’可相同或不同。此外，寬度W1’、W2’及W3’可與隔離部130G1、130G2及130G3的寬度W相同或不同。虛設部分130P1與隔離部130G1之間的距離d1L可與虛設部分130P1與隔離部P2之間的距離d1R相同或不同。虛設部分130P21與包封體127之間的距離d2L可與虛設部分130P21與隔離部130G1之間的距離d2R相同或不同。虛設部分130P22與隔離部130G3之間的距離d3L可與虛設部分130P22及包封體127之間的距離d3R相同或不同。
圖10至圖12是示出根據本揭露一些實施例的3DIC結構1010、1011及1012的示意性剖視圖。
參照圖10及圖11，3DIC結構1010及1011類似於3DIC結構1002，其中3DIC結構1010及1011各自更包括形成於晶粒204的背側表面204c之上的重佈線結構131，以電性連接晶粒204的TSV 209及/或電性連接至外部元件。出於說明目的，示出類似於以上論述的3DIC結構1002的3DIC結構，並且在一些實施例中，可使用例如以上論述的結構等其他3DIC結構。重佈線結構131可包括一或多個介電層133及位於所述一或多個介電層133 中的相應金屬化圖案135。金屬化圖案135有時被稱為重佈線走線(redistribution line，RDL)。介電層133可包含氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料(例如，PSG、BPSG、FSG、SiOxCy)、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合或類似物。介電層133可藉由例如旋轉、CVD、PECVD、HDP-CVD或類似方法等任何合適的方法沈積。如圖10所示，金屬化圖案135包括導線135M。在一些實施例中，如圖11所示，金屬化圖案135包括導線135M及導通孔135V。導通孔135V的側壁及導線135M的側壁可為直的或傾斜的。在一些實施例中，導通孔135V具有傾斜的側壁，並且朝向基底205呈錐形。
可例如藉由使用微影技術在介電層133上沈積及圖案化光阻材料以暴露出將成為金屬化圖案135的介電層133的一些部分而在介電層133中形成金屬化圖案135。可使用例如非等向性乾式蝕刻製程等蝕刻製程在介電層133中生成對應於介電層133的被暴露出的部分的凹陷及/或開口。凹陷及/或開口可襯有擴散阻擋層並填充以導電材料。擴散阻擋層可包括由ALD或類似技術沈積的一或多層TaN、Ta、TiN、Ti、CoW或類似物，且導電材料可包括由CVD、PVD或類似技術沈積的銅、鋁、鎢、銀及其組合或類似物。可例如藉由使用CMP來移除介電層上的任何過量的擴散阻擋層及/或導電材料。
3DIC結構1010的隔離層130G可類似於隔離層130A、130B或130C。3DIC結構1011的隔離層130H可類似於隔離層 130A、130B、130C、130D、130E或130F。
在一些實施例中，至少一個積體被動元件(Integrated Passive Device，IPD)(未示出)亦可設置於重佈線結構131上。IPD可使用例如薄膜及微影處理等標準晶圓製作技術製作而成，並且可藉由例如倒裝晶片接合或引線接合等而安裝於重佈線結構131上。
參照圖12，3DIC結構1012類似於3DIC結構1002、1003、1004、1006、1007、1008、1009、1010或1011，並且3DIC結構1012的隔離層130I可類似於隔離層130A、130B、130C、130D、130E或130F。如圖12所示，晶粒204以面向背的配置接合至晶粒104’。亦即，晶粒204的前表面204a面向晶粒104’的後表面104b’。晶粒104’類似於晶粒104，其中晶粒104’更包括位於基底105’中的TSV 109’及位於基底105的後表面105b’上的接合結構120’。TSV 109’與TSV 209類似。在一些實施例中，TSV 109’穿透基底105’並連接至形成於基底105’的前表面105a’上的內連線結構114’。在一些實施例中，襯墊109j’及/或黏著劑層109i’可在形成TSV 109’之前形成，使得TSV 109’可與基底105’分離。
接合結構120’形成於基底105’的後表面105b’上，並與晶粒204的接合結構220接合。接合結構120’類似於接合結構120。在一些實施例中，接合結構120’可包括接合接墊123’及虛設接墊125’。接合接墊123’及虛設接墊125’可將晶粒204的接合接墊223及虛設接墊225作為3DIC結構1002連接至晶粒104’的內連線結 構114’。如圖12所示，接合結構120’的接合接墊123’經由TSV 109’連接至內連線結構114’。
圖13A至圖13E示出根據一些實施例形成封裝的剖視圖。
參照圖13A，提供載體基底102，並且在載體基底102上形成釋放層124。載體基底102可為玻璃載體基底、陶瓷載體基底或類似物。載體基底102可為晶圓，使得可同時在載體基底102上形成多個封裝。釋放層124可由聚合物系材料形成，其可與載體基底102一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層124是在被加熱時失去其黏著性質的環氧樹脂系熱釋放材料，例如光-熱轉換(LTHC)釋放塗層。在一些實施例中，釋放層124可為紫外線(UV)膠，其在暴露於UV光時失去其黏著性質。釋放層124可作為液體分配並固化，可為層疊在載體基底102上的層疊膜，或者可為類似物。釋放層124的頂表面可為齊平的，並且可具有高的平面度。
在釋放層124上形成介電層108。在一些實施例中，介電層108由例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)或類似物等聚合物形成。在其他實施例中，介電層108由以下形成：氮化物，例如氮化矽；氧化物，例如氧化矽；磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)或類似物；或類似物。可藉由例如旋轉塗佈、化學氣相沈積(CVD)、層疊、類似技術或其組合等任何可接受的沈積製程來形成介電層108。
參照圖13A，於釋放層124上形成導電柱118。作為形成導電柱118的實例，在釋放層124上方形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或包括由不同材料形成的多個子層的複合層。舉例而言，晶種層包括鈦層及位於所述鈦層上方的銅層。晶種層可使用例如PVD或類似技術形成。在晶種層上形成光阻並將光阻圖案化。光阻可藉由旋轉塗佈或類似技術形成，並且可被暴露至光以進行圖案化。圖案化形成穿過光阻的開口，以暴露出晶種層。導電材料形成於光阻的開口中及晶種層的被暴露出的部分上。導電材料可藉由例如電鍍或無電鍍覆等鍍覆或類似技術形成。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似物。移除光阻以及晶種層的上面未形成導電材料的部分。可例如使用氧電漿或類似物藉由可接受的灰化或剝除製程來移除光阻。一旦光阻被移除，便例如使用可接受的蝕刻製程(例如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的被暴露出的部分。晶種層的剩餘部分及導電材料形成導電柱118。
參照圖13B，藉由黏著劑128將3DIC結構1002黏著至介電層108。示出3DIC結構1002用於例示目的，且在一些實施例中，可使用以上論述的其他3DIC結構。黏著劑128位於3DIC結構1002的背側表面上，並將3DIC結構1002黏著至釋放層124。黏著劑128可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(DAF)或類似物。
參照圖13C，在各種部件上形成包封體142。在形成之後， 包封體142在側向上包封導電柱118及3DIC結構1002。在一些實施例中，包封體142包含模塑化合物、模塑底部填料、例如環氧樹脂等樹脂、其組合或類似物。在一些其他實施例中，包封體142包含感光性材料，例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合或類似物，所述材料可易於藉由曝光及顯影製程或雷射鑽孔製程被圖案化。在替代實施例中，包封體142包含氮化物(例如，氮化矽)、氧化物(例如，氧化矽)、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、其組合或類似物。
在一些實施例中，包封體142包含複合材料，所述複合材料包括基材(例如，聚合物)以及位於基材中的多種填充劑。填充劑可為單一元素、化合物(例如，氮化物、氧化物)或其組合。舉例而言，填充劑可包括氧化矽、氧化鋁、氮化硼、鋁氧化物、二氧化矽或類似物。填充劑的剖面形狀可為圓形、橢圓形或任何其他形狀。在一些實施例中，填充劑是球形顆粒或類似物。填充劑的剖面形狀可為圓形、橢圓形或任何其他形狀。在一些實施例中，填充劑包括固體填充劑，但本揭露並非僅限於此。在一些實施例中，一小部分填充劑可為中空填充劑。
包封體142可藉由壓縮模塑、轉移模塑(transfer molding)、旋轉塗佈、層疊、沈積或類似製程來施加，並且可形成於載體基底102上方，使得導電柱118及/或3DIC結構1002被掩埋或覆蓋。然後將包封體142固化。導電柱118穿透包封體142，並且導電柱 118有時被稱為穿孔118或積體扇出型穿孔(through integrated fan-out via，TIV)118。
參照圖13C，然後對包封體142執行平坦化製程，以移除包封體142的一部分，使得穿孔118的頂表面及導電端子(晶粒連接件)143的頂表面被暴露出。在其中穿孔118的頂表面與3DIC結構1002的前側表面不共面的一些實施例中，穿孔118的一些部分或/及介電材料140的一些部分亦可藉由平坦化製程被移除。在一些實施例中，穿孔118的頂表面、導電端子143的頂表面、絕緣層147的頂表面及包封體142的頂表面在平坦化製程之後實質上共面。平坦化製程可為例如化學機械研磨(CMP)、拋光製程或類似製程。在一些實施例中，舉例而言，若穿孔118及導電端子143已被暴露出，則可省略平坦化。
參照圖13D，在穿孔118、包封體142及3DIC結構1002的前側表面上方形成前側重佈線結構144。前側重佈線結構144包括：介電層146、150、154及158；金屬化圖案148、152及156；以及凸塊下金屬(UBM)160。金屬化圖案148、152及156亦可被稱為導電重佈線層或重佈線走線。前側重佈線結構144被示出作為實例。可在前側重佈線結構144中形成更多或更少的介電層及金屬化圖案。若將形成更少的介電層及金屬化圖案，則可省略以下論述的步驟及製程。若將形成更多的介電層及金屬化圖案，則可重複以下論述的步驟及製程。
作為形成前側重佈線結構144的實例，在包封體142、穿 孔118及導電端子143上沈積介電層146。在一些實施例中，介電層146由感光性材料(例如，PBO、聚醯亞胺、BCB或類似物)形成，所述材料可使用微影罩幕來圖案化。介電層146可藉由旋轉塗佈、層疊、CVD、類似技術或其組合來形成。然後，將介電層146圖案化。圖案化形成暴露出穿孔118及導電端子143的一些部分的開口。圖案化可藉由可接受的製程進行，例如當介電層146是感光性材料時藉由將介電層146暴露於光，或者藉由使用例如非等向性蝕刻進行蝕刻。若介電層146是感光性材料，則介電層146可在曝光後顯影。
然後形成金屬化圖案148。金屬化圖案148包括位於介電層146的頂表面上並沿所述頂表面延伸的導線148L。金屬化圖案148更包括延伸貫穿介電層146以物理及電性連接至穿孔118及3DIC結構1002的導通孔148V。導通孔148V的側壁及導線148C的側壁可為直的或傾斜的。在一些實施例中，導通孔148V具有傾斜的側壁，並且朝向3DIC結構1002呈錐形。為形成金屬化圖案148，在介電層146上方及延伸貫穿介電層146的開口中形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層上方的銅層。晶種層可使用例如PVD或類似技術形成。然後在晶種層上形成光阻並將光阻圖案化。光阻可藉由旋轉塗佈或類似技術形成，並且可被暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案148。圖案化形成貫穿光阻 的開口，以暴露出晶種層。然後在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。導電材料可藉由例如電鍍覆或無電鍍覆等鍍覆或類似技術形成。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似物。導電材料與晶種層的下伏部分的組合形成金屬化圖案148。移除光阻以及晶種層的上面未形成導電材料的部分。可例如使用氧電漿或類似物藉由可接受的灰化或剝除製程來移除光阻。一旦光阻被移除，便例如使用可接受的蝕刻製程(例如，藉由濕式蝕刻或乾式蝕刻)移除晶種層的被暴露出的部分。
交替形成介電層150、154、158及金屬化圖案152、156。介電層150、154及158可以類似於介電層146的方式形成，並且可由與介電層146相同的材料形成。金屬化圖案152及156可包括位於下伏介電層上的導線152C及156C及分別延伸貫穿下伏介電層的導通孔152V及156V。金屬化圖案152及156可以類似於金屬化圖案148的方式形成，並且可由與金屬化圖案148相同的材料形成。UBM 160視情況形成於介電層158上並延伸貫穿介電層158。UBM 160可以類似於金屬化圖案148的方式形成，並且可由與金屬化圖案148相同的材料形成。
參照圖13D，在UBM 160上形成導電連接件162。導電連接件162可為球柵陣列(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(ENEPIG)形成的凸塊或類似物。導電連接件162包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD或類 似技術形成的金屬柱(例如，銅柱)。金屬柱可為無焊料的，並且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物或其組合，並且可藉由鍍覆製程形成。在另一實施例中，導電連接件162可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合。在一些實施例中，導電連接件162藉由首先由例如蒸鍍、電鍍、印刷、焊料轉移、植球或類似方法等此類常用方法形成焊料層來形成。一旦已在結構上形成了焊料層，便可執行回焊製程，以將材料成形為期望的凸塊形狀。
參照圖13D及圖13E，執行載體基底剝離以自介電層108分離(或「剝離」)載體基底102，以形成封裝166。根據一些實施例，剝離包括將例如雷射光或UV光等光投射至釋放層124上，使得釋放層124在光的熱量下分解，並且載體基底102可被移除。然後，將封裝166翻轉並放置在膠帶(未示出)上。
參照圖13E，可將頂部封裝500接合至封裝166。頂部封裝500包括基底502及耦合至基底502的一或多個堆疊晶粒(或晶粒)508。基底502可由例如矽、鍺、金剛石或類似物等半導體材料製成。在一些實施例中，亦可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化鎵砷、磷化鎵銦、其組合或類似物。另外，基底502可為SOI基底。一般而言，SOI基底包括半導體材料(例如，外延矽、鍺、矽鍺、SOI、絕緣 體上矽鍺(silicon germanium on insulator，SGOI)或其組合)層。在一些實施例中，基底502基於絕緣芯，例如玻璃纖維增強樹脂芯。芯材的一個實例是玻璃纖維樹脂，例如FR4。可用於芯材的其他材料包括雙馬來醯亞胺-三嗪(bismaleimide-triazine，BT)樹脂，或作為另一選擇，包括其他印刷電路板(printed circuit board，PCB)材料或膜。可將例如味之素構成膜(Ajinomoto build-up film，ABF)等構成膜或其他層疊體用於基底502。
基底502可包括主動及被動元件(未示出)。如此項技術中具有通常知識者將認識到，可使用例如電晶體、電容器、電阻器、其組合及類似物等各種各樣的元件來產生頂部封裝500的設計的結構及功能要求。可使用任何合適的方法來形成元件。
基底502亦可包括金屬化層(未示出)及穿孔506。金屬化層可形成於主動及被動元件上方，並且被設計成連接各種元件以形成功能電路系統。金屬化層可由交替的介電質(例如，低介電常數介電材料)層及導電材料(例如，銅)層(其中通孔內連各導電材料層)形成，並且可藉由任何合適的製程(例如，沈積、鑲嵌、雙鑲嵌或類似技術)形成。在一些實施例中，基底502實質上不具有主動元件及被動元件。
基底502可在基底502的第一側上具有接合接墊503以耦合至堆疊晶粒508，並且在基底502的第二側上具有接合接墊504以耦合至導電連接件168，其中基底502的第二側與第一側相對。在一些實施例中，藉由在基底502的第一側及第二側上的介 電層(未示出)中形成凹陷(未示出)來形成接合接墊503及504。可形成凹陷以允許接合接墊503及504嵌入介電層中。在其他實施例中，由於接合接墊503及504可形成於介電層上，因此省略了凹陷。在一些實施例中，接合接墊503及504包括由銅、鈦、鎳、金、鈀、類似物或其組合製成的薄晶種層(未示出)。接合接墊503及504的導電材料可沈積於薄晶種層上方。所述導電材料可藉由電化學鍍覆製程、無電鍍覆製程、CVD、ALD、PVD、類似技術或其組合來形成。在實施例中，接合接墊503及504的導電材料是銅、鎢、鋁、銀、金、類似物或其組合。在一些實施例中，接合接墊503及504是使用與較早接合UBM 160描述的相同或相似製程形成的UBM。
在所示實施例中，藉由引線接合510將堆疊晶粒508耦合至基底502，但亦可使用其他連接，例如導電凸塊。在一些實施例中，堆疊晶粒508是堆疊記憶體晶粒。舉例而言，堆疊記憶體晶粒508可包括低功率(low-power，LP)雙倍資料速率(double data rate，DDR)記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。
在一些實施例中，可由模塑材料512包封堆疊晶粒508及引線接合510。模塑材料512可例如使用壓縮模塑而被模塑在堆疊晶粒508及引線接合510上。在一些實施例中，模塑材料512是模塑化合物、聚合物、環氧樹脂、氧化矽填充劑材料、類似物或其組合。可執行固化步驟以固化模塑材料512，其中固化可為熱固化、 UV固化、類似固化或其組合。
在一些實施例中，將堆疊晶粒508及引線接合510埋置於模塑材料512中，並且在固化模塑材料512之後，執行平坦化步驟(例如，研磨)以移除模塑材料512的多餘部分，並且為頂部封裝500提供實質上平面的表面。
在形成頂部封裝500之後，藉由導電連接件168及接合接墊504將頂部封裝500接合至InFO封裝166。在一些實施例中，堆疊記憶體晶粒508可經由引線接合510、接合接墊503及504、穿孔506、導電連接件168及穿孔118耦合至3DIC結構1002。
導電連接件168可類似於上述導電連接件162，並且在此不再予以贅述，但導電連接件168與162不必相同。在一些實施例中，在接合導電連接件168之前，用例如免清洗助焊劑(non-clean flux)等助焊劑(未示出)對導電連接件168進行塗佈。可將導電連接件168浸入助焊劑中，或者可將助焊劑噴射至導電連接件168上。
在一些實施例中，導電連接件168在被回焊之前可在其上形成有環氧樹脂助焊劑(未示出)，其中在將頂部封裝500貼合至封裝166之後，環氧樹脂助焊劑的至少一些環氧樹脂部分存留。此存留的環氧樹脂部分可充當底部填料，以減少應力並保護由回焊導電連接件168產生的接頭。在一些實施例中，可在頂部封裝500與封裝166之間且圍繞導電連接件168形成底部填料170。底部填料170可在貼合頂部封裝500之後藉由毛細流動製程 (capillary flow process)形成，或者可在貼合頂部封裝500之前藉由合適的沈積方法形成。
頂部封裝500與封裝166之間的接合可為焊料接合或直接金屬對金屬(例如，銅對銅或錫對錫)接合。在實施例中，藉由回焊製程將頂部封裝500接合至封裝166。在此回焊製程期間，導電連接件168與接合接墊504及穿孔118接觸，以將頂部封裝500物理及電性耦合至封裝166。
基於以上論述，可見本揭露提供了各種優點。然而，應理解，在本文中未必論述所有優點，並且其他實施例可提供不同的優點，並且並非所有的實施例皆需要特定的優點。在一些實施例中，包封體的頂表面及基底的部分的頂表面被罩幕層覆蓋以防止/減少對包封體的蝕刻，並且在蝕刻製程中不藉由凹陷被暴露出。因此，可保護包封體的頂表面不受凹坑缺陷的影響，並且可在露出TSV期間減少腔室污染。
以上論述了各種實施例。亦可包括其他特徵及製程。舉例而言，可包括測試結構以幫助對3D封裝或3DIC元件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊(test pad)，以便允許對3D封裝或3DIC進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所揭露的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法接合使用，以提高良率並降低成本。
在實施例中，一種封裝包括：第一晶粒，其中所述第一晶粒包括自所述第一晶粒的第一表面朝向所述第一晶粒的第二表面延伸的多個穿孔；第二晶粒，設置於所述第一晶粒下方，其中所述第一晶粒的所述第二表面接合至所述第二晶粒；隔離層，設置於所述第一晶粒中，其中所述多個穿孔延伸貫穿所述隔離層；包封體，在側向上圍繞所述第一晶粒，其中所述包封體在側向上與所述隔離層分離；緩衝層，設置於所述第一晶粒、所述隔離層及所述包封體上方；以及多個導電端子，設置於所述隔離層上方，其中所述多個導電端子電性連接至所述多個穿孔中的對應穿孔。在實施例中，所述隔離層包括圍繞所述第一晶粒中的所述多個穿孔的塊狀層。在實施例中，所述隔離層包括多個隔離部，其中所述多個隔離部中的每一隔離部圍繞所述多個穿孔中的至少一個穿孔。在實施例中，所述多個隔離部中的每一隔離部圍繞相同數量的所述多個穿孔。在實施例中，所述多個隔離部包括第一隔離部及第二隔離部，其中所述第一隔離部圍繞所述多個穿孔中的第一數量的穿孔，其中所述第二隔離部圍繞所述多個穿孔中的第二數量的穿孔，其中所述第一數量不同於所述第二數量。在實施例中，所述多個隔離部中的每一隔離部具有相同的寬度。在實施例中，所述多個隔離部包括第一隔離部及第二隔離部，其中所述第一隔離部具有第一寬度，其中所述第二隔離部具有第二寬度，其中所述第一寬度不同於所述第二寬度。在實施例中，所述隔離層包括與所述多個隔離部分離的虛設隔離部，所述虛設隔離部設置於所述多個隔離部中的相 鄰隔離部之間，並且其中所述多個穿孔中無穿孔貫穿所述虛設隔離部。在實施例中，所述隔離層包括與所述多個隔離部分離的虛設隔離部，所述虛設隔離部設置於所述多個隔離部中的第一隔離部與所述包封體之間，其中所述第一隔離部是最靠近所述第一晶粒的邊緣的隔離部，並且其中所述多個穿孔中無穿孔貫穿所述虛設隔離部。
在實施例中，一種封裝包括：第一晶粒，其中所述第一晶粒包括第一基底，所述第一晶粒更包括自所述第一基底的頂表面朝向所述第一晶粒的底表面延伸的第一穿孔及第二穿孔；隔離層，設置於所述第一基底的所述頂表面中的凹陷中，所述隔離層圍繞所述第一穿孔及所述第二穿孔，其中所述第一基底在俯視圖中圍繞所述隔離層；以及第一包封體，在側向上圍繞所述第一晶粒，其中所述第一基底夾置於所述隔離層與所述第一包封體之間。在實施例中，所述第一基底的所述頂表面與所述第一包封體的頂表面及所述隔離層的頂表面齊平。在實施例中，所述封裝更包括設置於所述第一包封體、所述第一晶粒及所述隔離層上方的緩衝層，其中所述緩衝層的底表面與所述第一包封體的所述頂表面、所述第一晶粒的頂表面及所述隔離層的所述頂表面接觸。在實施例中，所述封裝更包括位於所述緩衝層上方的虛設端子，其中所述隔離層在所述虛設端子下方延伸。在實施例中，所述封裝更包括位於所述緩衝層上方的虛設端子，其中所述隔離層不在所述虛設端子下方延伸。在實施例中，所述隔離層包括多個層。
在實施例中，一種製造封裝結構的方法包括：將第一晶粒的第一表面接合至第二晶粒，其中所述第一晶粒包括第一穿孔；在所述第一晶粒的旁邊在側向上形成包封體；在所述第一晶粒的第二表面中形成第一凹陷，所述第一凹陷在所述第一穿孔周圍延伸；以及在所述第一凹陷中形成隔離層，其中所述隔離層藉由所述第一晶粒與所述包封體分離。在實施例中，所述第一晶粒包括第二穿孔，其中所述第一凹陷在所述第一穿孔及所述第二穿孔周圍連續延伸。在實施例中，所述第一晶粒包括第二穿孔，所述方法更包括形成圍繞所述第二穿孔的第二凹陷，其中形成所述隔離層包括在所述第一凹陷中形成第一隔離部，並在所述第二凹陷中形成第二隔離部，其中所述第一隔離部與所述第二隔離部分離。在實施例中，所述方法更包括：形成第二凹陷，其中所述第二凹陷不暴露出導電特徵；以及在所述第二凹陷中形成所述隔離層。在實施例中，所述方法更包括：在所述包封體、所述隔離層、所述多個穿孔及所述第一晶粒上形成緩衝層；以及在所述緩衝層上形成導電端子，其中所述導電端子電性連接至所述第一穿孔。
151:開口
104、204:晶粒
104a:前表面
105:基底
114、214:內連線結構
120、220:接合結構
123、223:接合接墊
125:虛設接墊/虛設接合接墊
225:虛設接墊
127:包封體
130a:頂表面
137:緩衝層
205:基底
205S:台階
209:導通孔/穿孔(TV)/基底穿孔(TSV)
1000:晶圓級晶粒結構

Claims (10)

  1. 一種半導體封裝，包括：第一晶粒，其中所述第一晶粒包括自所述第一晶粒的第一表面朝向所述第一晶粒的第二表面延伸的多個穿孔；第二晶粒，設置於所述第一晶粒下方，其中所述第一晶粒的所述第二表面接合至所述第二晶粒；隔離層，設置於所述第一晶粒的半導體基底中，其中所述多個穿孔延伸貫穿所述隔離層；包封體，在側向上圍繞所述第一晶粒，其中所述包封體在側向上與所述隔離層分離；緩衝層，設置於所述第一晶粒、所述隔離層及所述包封體上方；以及多個導電端子，設置於所述隔離層上方，其中所述多個導電端子電性連接至所述多個穿孔中的對應穿孔。
  2. 如請求項1所述的半導體封裝，其中所述隔離層包括圍繞所述第一晶粒中的所述多個穿孔的塊狀層。
  3. 如請求項1所述的半導體封裝，其中所述隔離層包括多個隔離部，其中所述多個隔離部中的每一隔離部圍繞所述多個穿孔中的至少一個穿孔。
  4. 如請求項3所述的半導體封裝，其中所述多個隔離部中的每一隔離部圍繞相同數量的所述多個穿孔。
  5. 如請求項3所述的半導體封裝，其中所述多個隔離部包括第一隔離部及第二隔離部，其中所述第一隔離部圍繞所述多個穿孔中的第一數量的穿孔，其中所述第二隔離部圍繞所述多個穿孔中的第二數量的穿孔，其中所述第一數量不同於所述第二數量。
  6. 一種半導體封裝，包括：第一晶粒，其中所述第一晶粒包括半導體基底，所述第一晶粒更包括自所述半導體基底的頂表面朝向所述第一晶粒的底表面延伸的第一穿孔及第二穿孔；隔離層，設置於所述半導體基底的所述頂表面中的凹陷中，所述隔離層圍繞所述第一穿孔及所述第二穿孔，其中所述半導體基底在俯視圖中圍繞所述隔離層；以及第一包封體，在側向上圍繞所述第一晶粒，其中所述半導體基底夾置於所述隔離層與所述第一包封體之間。
  7. 如請求項6所述的半導體封裝，其中所述半導體基底的所述頂表面與所述第一包封體的頂表面及所述隔離層的頂表面齊平。
  8. 如請求項7所述的半導體封裝，更包括設置於所述第一包封體、所述第一晶粒及所述隔離層上方的緩衝層，其中所述緩衝層的底表面與所述第一包封體的所述頂表面、所述第一晶粒的頂表面及所述隔離層的所述頂表面接觸。
  9. 一種製造半導體封裝結構的方法，所述方法包括： 將第一晶粒的第一表面接合至第二晶粒，其中所述第一晶粒包括第一穿孔；在所述第一晶粒的旁邊側向上形成包封體；在所述第一晶粒的第二表面的半導體基底中形成第一凹陷，所述第一凹陷在所述第一穿孔周圍延伸；以及在所述第一凹陷中形成隔離層，其中所述隔離層藉由所述第一晶粒與所述包封體分離。
  10. 如請求項9所述的製造半導體封裝結構的方法，其中所述第一晶粒包括第二穿孔，其中所述第一凹陷在所述第一穿孔及所述第二穿孔周圍連續延伸。
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