TW201919193A - 晶粒堆疊結構及其製作方法 - Google Patents

晶粒堆疊結構及其製作方法 Download PDF

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Publication number
TW201919193A
TW201919193A TW107109003A TW107109003A TW201919193A TW 201919193 A TW201919193 A TW 201919193A TW 107109003 A TW107109003 A TW 107109003A TW 107109003 A TW107109003 A TW 107109003A TW 201919193 A TW201919193 A TW 201919193A
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Taiwan
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bonding
layer
die
substrate
dielectric layer
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TW107109003A
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English (en)
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陳怡秀
邱文智
陳勇龍
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台灣積體電路製造股份有限公司
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Publication of TW201919193A publication Critical patent/TW201919193A/zh

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Abstract

一種晶粒堆疊結構，包括第一晶粒、第二晶粒、第一接合結構以及第二接合結構。所述第一接合結構設置在所述第一晶粒的背面上。所述第二接合結構設置在所述第二晶粒的正面上。所述第一晶粒及所述第二晶粒通過所述第一接合結構及所述第二接合結構接合在一起，且與所述第二接合結構進行接合的所述第一接合結構的表面的可接合拓撲變化小於1 mm/1 mm範圍。還提供一種製作晶粒堆疊結構的方法。

Description

晶粒堆疊結構及其製作方法
本發明實施例提供一種晶粒堆疊結構及其製作方法。
近年來，由於各種電子元件（即，電晶體、二極體、電阻器、電容器等）的積體密度的持續改進，半導體行業已經歷了快速成長。積集密度的此種改進來自於最小特徵尺寸（minimum feature size）的一再減小，以允許更多的較小的元件能夠整合在一定的面積中。
與先前的封裝體相比，這些較小的電子元件也需要利用較小面積的較小的封裝體。半導體封裝體的示例性類型包括四面扁平封裝（quad flat package，QFP）、針格陣列（pin grid array，PGA）、球格陣列（ball grid array，BGA）、覆晶技術（flip chip，FC）、三維積體電路（three dimensional integrated circuit，3DIC）、晶圓級封裝體（wafer level package，WLP）及疊層封裝體（package on package，PoP）裝置。一些三維積體電路是通過將晶片（chip）放置在半導體晶圓級上的晶片上方製備而成。由於堆疊晶片之間的內連線的長度減小，因此三維積體電路提供更高的積體密度及其他優點，例如更快的速度及更高的頻寬。然而，對於三維積體電路技術來說仍存在很多待處理的挑戰。
本發明實施例提供一種晶粒堆疊結構，所述晶粒堆疊結構包括第一晶粒、第二晶粒、第一接合結構以及第二接合結構。所述第一接合結構設置在所述第一晶粒的背面上。所述第二接合結構設置在所述第二晶粒的正面上。所述第一晶粒及所述第二晶粒通過所述第一接合結構及所述第二接合結構接合在一起，且與所述第二接合結構進行接合的所述第一接合結構的表面的可接合拓撲變化小於1 mm/1 mm範圍。
以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，且也可包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件符號及/或字母。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
此外，為易於說明，本文中可能使用例如「在...下方（beneath）」、「在...下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對術語來闡述圖中所示的一個元件或特徵與另一（些）元件或特徵的關係。所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明進行三維（3D）封裝體或三維積體電路裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊，所述測試墊使得能夠測試3D封裝體或3DIC、使用探針（probe）及/或探針卡（probe card）等。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可接合包括對已知良好晶粒（known good dies）的中間驗證的測試方法一起使用，以提高良率（yield）及降低成本。
圖1A到圖1G是根據第一實施例的一種形成晶粒堆疊結構的方法的剖視圖。
參照圖1A，提供上面形成有剝離層（de-bonding layer）DB及介電層DI的載體C，其中剝離層DB形成於載體C與介電層DI之間。在一些實施例中，載體C是玻璃基底、矽基底或用於封裝體的製造製程的任意適當的載體，剝離層DB是形成在玻璃基底上的光-熱轉換（light-to-heat conversion，LTHC）離形層，且介電層DI是形成在剝離層DB上的光敏聚苯噁唑（polybenzoxazole，PBO）層。在一些替代實施例中，剝離層DB可以是黏性通過光固化製程而減小的可光固化釋放膜，或黏性通過熱固化製程而減小的可熱固化釋放膜，且介電層DI可由其他光敏或非光敏介電材料所製成。在一些實施例中，介電層DI可以是聚苯噁唑（PBO）層、聚醯亞胺（PI）層或其他適當的介電層。在一些替代實施例中，剝離層DB可以是不同於介電層DI的介電層。
參照圖1A，在介電層DI中形成多個對準標記AM，且介電層DI暴露出所述多個對準標記AM。在一些實施例中，對準標記AM可用於在微影製程期間使載體C與待形成的隔離結構118（如圖1B所示）對準，以將晶片10安裝在載體C之上。在一些實施例中，對準標記AM可包括金屬，例如銅、銅合金、鋁、鋁合金或其組合。對準標記AM可通過電化學鍍覆製程、物理氣相沉積（PVD）等形成。
參照圖1A，將晶片10安裝在載體C之上。在一些實施例中，晶片10包括彼此相對的正面S1及背面S2。晶片10的正面S1面朝載體C，而晶片10的背面S2面朝上。在一些實施例中，晶片10的正面S1是主動表面。詳細來說，晶片10包括第一基底102、第一裝置層103、第一內連線結構104、第一鈍化層110、第一接墊112及至少一個第一基底穿孔（through-substrate via，TSV）115。
在一些實施例中，第一基底102可包括矽或其他半導體材料。另外或作為另一選擇，第一基底102可包括其他元素半導體材料，例如鍺。在一些實施例中，第一基底102是由化合物半導體（例如，碳化矽、砷化鎵、砷化銦或磷化銦）所製成。在一些實施例中，第一基底102是由合金半導體（例如，矽鍺、矽鍺碳化物、砷化鎵磷化物或鍺銦磷化物）所製成。在一些實施例中，第一基底102包括磊晶層。舉例來說，第一基底102具有上覆在塊狀半導體（bulk semiconductor）上的磊晶層。
參照圖1A，在第一基底102之上形成第一裝置層103。第一裝置層103包括形成在第一基底102之上的各種積體電路裝置（圖中未示出）。在一些實施例中，積體電路裝置可包括主動裝置（例如，二極體、電晶體、光電裝置等）、被動裝置（例如，電阻器、電容器、電感器等）。在第一裝置層103之上形成第一內連線結構104。詳細來說，第一內連線結構104包括第一絕緣材料106及多個第一金屬特徵108。第一金屬特徵108形成在第一絕緣材料106中並彼此電性連接。第一金屬特徵108的一部分（例如，頂部金屬特徵）外露於第一絕緣材料106。在一些實施例中，第一絕緣材料106包括氧化矽、氮氧化矽、氮化矽、低介電常數（low-k）材料或其組合。在一些替代實施例中，第一絕緣材料106可以是單層或多層。在一些實施例中，第一金屬特徵108包括插塞（plug）及金屬線。第一金屬特徵108可由鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金或其組合所製成。
參照圖1A，第一基底穿孔115穿透第一基底102以電性連接到第一內連線結構104。在一些實施例中，第一基底穿孔115包括導電通孔及環繞所述導電通孔的擴散阻擋層（圖中未示出）。導電通孔可包括銅、銅合金、鋁、鋁合金或其組合。擴散阻擋層可包括Ta、TaN、Ti、TiN、CoW或其組合。
參照圖1A，在第一內連線結構104之上形成第一鈍化層110。第一鈍化層110覆蓋第一絕緣材料106及頂部金屬特徵108b的一部分。此外，頂部金屬特徵108b的所述部分被第一鈍化層110所覆蓋，而頂部金屬特徵108a的另一部分被第一鈍化層110所暴露出，使得頂部金屬特徵108a的所述另一部分可與第一接墊112電性連接。在一些實施例中，第一鈍化層110包括氧化矽、氮化矽、本並環丁烯（BCB）聚合物、聚醯亞胺（PI）、聚苯噁唑（PBO）或其組合，且是通過例如旋轉塗布、化學氣相沉積（CVD）等適當的製程形成。
參照圖1A，在頂部金屬特徵108b之上形成第一接墊112，且第一接墊112延伸以覆蓋第一鈍化層110的一部分。舉例來說，第一測試墊112的材料不同於第一金屬特徵108的材料。在一些實施例中，第一測試墊112的材料軟於第一金屬特徵108的材料。在一些實施例中，第一接墊112包括金屬材料，例如鋁、銅、鎳、金、銀、鎢或其組合。第一接墊112可通過以下方式形成：通過例如電化學鍍覆製程、CVD、原子層沉積（atomic layer deposition，ALD）、PVD等適當的製程來沉積金屬材料層，然後對所述金屬材料層進行圖案化。
參照圖1A，在晶片10的正面S1之上形成介電層114。也就是說，介電層114覆蓋第一接墊112及第一鈍化層110。在一些實施例中，介電層114包括氧化矽、氮化矽、聚合物或其組合。介電層114是通過以下方式形成：通過例如旋轉塗布、CVD等適當的製程沉積介電材料，然後對所述介電材料執行平坦化製程。在形成介電層114之後，在介電層114之上形成介電層116。在一些實施例中，介電層116包括氧化矽、氮化矽、聚合物或其組合，且是通過例如旋轉塗布、CVD等適當的製程形成。
參照圖1A，通過介電層DI及介電層116將晶片10與載體C接合在一起。也就是說，介電層DI及介電層116是通過介電質對介電質接合（dielectric-to-dielectric bonding）或熔融接合（fusion bonding）來進行接合。
參照圖1B，在晶片10中形成多個隔離結構118，以將晶片10劃分成多個第一晶粒100。也就是說，隔離結構118分別設置在多個第一晶粒100之間，以使得第一晶粒100彼此分隔開。第一晶粒100可具有相同的功能或不同的功能。在一些實施例中，第一晶粒100包括特殊應用積體電路（application-specific integrated circuit，ASIC）晶片、類比晶片、感測器晶片、無線（例如，藍牙及射頻）晶片、電壓調節器晶片或記憶體晶片（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶片或靜態隨機存取記憶體（static random access memory，SRAM）晶片）。舉例來說，隔離結構118通過如下所述的步驟來形成。形成多個開口（圖中未示出）以穿透第一基底102、第一裝置層103、第一內連線結構104、第一鈍化層110、以及介電層114及116，使得對準標記AM的表面被所述開口暴露出。將隔離材料填充在所述開口中，以形成隔離結構118。在一些實施例中，隔離結構118中的一者與對準標記AM中的一者對準。在一些實施例中，隔離材料包括氧化矽、氮化矽、氮氧化矽或其組合，且是通過CVD形成。在一些替代實施例中，隔離結構118中的一者包括間隙填充介電柱以及包封所述間隙填充介電柱的襯墊層（圖中未示出）。在本公開內容中不對第一晶粒100及隔離結構118的數目進行限制。
參照圖1B，在形成隔離結構118之後，對晶片10的背面S2執行薄化製程以暴露出第一基底穿孔115。在一些實施例中，所述薄化製程包括化學機械研磨（chemical mechanical polishing，CMP）製程、回蝕刻製程或其組合。在所述情形中，在薄化製程之後，晶片10的背面S2、隔離結構118的頂表面118S以及第一基底穿孔115的頂表面115S共面。在本文中，由於晶片10被劃分成多個第一晶粒100，因此晶片10的正面S1及背面S2可被稱為第一晶粒100的正面S1及背面S2或第一基底102的正面S1及背面S2。
參照圖1C，在執行薄化製程之後，在第一晶粒100的背面S2之上形成第一接合介電層120。第一接合介電層120覆蓋第一晶粒100的背面S2、第一基底穿孔115以及隔離結構118。在一些實施例中，第一接合介電層120包括依序堆疊的接合介電材料120a、120b、120c以及120d。在一些實施例中，接合介電材料120a、120b、120c以及120d可包括氧化矽、氮化矽、聚合物或其組合，且是通過以下方式形成：通過例如旋轉塗布、CVD等適當的製程來沉積介電材料，然後對所述介電材料執行平坦化製程。在一些實施例中，接合介電材料120a、120b、120c以及120d的功能及材料可彼此相同或不同。舉例來說，介電材料120a及120c可以是氮化矽且用於蝕刻停止層，而介電材料120b及120d可以是氧化矽並用於接合。
參照圖1C及圖1D，在第一接合介電層120中形成多個開口122及124。在一些實施例中，開口122對應於第一基底穿孔115且暴露出第一基底穿孔115的頂表面115S。開口122可以是但不限於雙鑲嵌開口。也就是說，開口122包括較窄的通孔122a以及位於較窄的通孔122a之上的較寬的溝渠122b。在一些實施例中，通孔122a通過如下所述的步驟（稱為溝渠優先製程（trench first process））來形成。通過微影及蝕刻製程圖案化介電材料120d，以在其中形成溝渠122b。溝渠122b對應於第一基底穿孔115。在蝕刻製程期間，介電材料120c充當蝕刻停止層，且因此介電材料120c外露於溝渠122b。在一些替代實施例中，可對介電材料120c進行蝕刻，以暴露出介電材料120b（如圖1D所示）。接下來，通過微影及蝕刻製程圖案化介電材料120b，以在其中形成通孔122a。在蝕刻製程期間，介電材料120a充當蝕刻停止層。隨後，通過蝕刻製程移除被通孔122a所暴露的介電材料120a，使得通孔122a暴露出第一基底穿孔115的頂表面115S。
在一些實施例中，較窄的通孔122a的底部寬度（或面積）小於第一基底穿孔115的頂表面115S的寬度（或面積）。在一些替代實施例中，較窄的通孔122a的底部寬度（或面積）等於第一基底穿孔115的頂表面115S的寬度（或面積）。另一方面，開口124可以是但不限於單鑲嵌開口。在一些實施例中，開口124可被稱為溝渠124，其通過圖案化介電材料120d所形成，其仲介電材料120c當作蝕刻停止層。在一些實施例中，開口124可在介電材料120c處終止並暴露出介電材料120c。在一些其他實施例中，開口124暴露出介電材料120b的頂表面。
參照圖1E，在第一接合介電層120之上形成金屬材料126並將金屬材料126填充在開口122及124中。在一些實施例中，金屬材料126可以是鋁、銅、鎳、金、銀、鎢或其組合，且是通過電化學鍍覆製程、CVD、PVD等形成。
參照圖1E及圖1F，執行平坦化製程以移除金屬材料126的一部分，使得第一接合介電層120的頂表面120S被暴露出。在一些實施例中，所述平坦化製程包括CMP製程、回蝕刻製程或其組合。在所述情形中，如圖1F所示，在所述平坦化製程之後，第一接合結構130形成在第一晶粒100或第一基底102的背面S2之上。詳細來說，第一接合結構130可包括第一接合介電層120及形成或嵌入在第一接合介電層120中的第一接合金屬層128。第一接合金屬層128可包括：第一接合金屬材料128a以及第一接合金屬材料128b。第一接合金屬材料128a是由填充在開口122中的金屬材料126所形成的；第一接合金屬材料128b是由填充在開口124中的金屬材料126所形成的。在一些實施例中，第一接合金屬材料128a可以是雙鑲嵌結構並與第一基底穿孔115連接。在一些實施例中，如圖1F所示，第一接合金屬材料128a的底面積小於與第一接合金屬材料128a連接的第一基底穿孔115的頂面積。第一接合金屬材料128b可以是單鑲嵌結構並形成在接合介電材料120b之上。換句話說，第一接合金屬材料128a可包括凸塊通孔及位於所述凸塊通孔之上的凸塊金屬線，且所述第一接合金屬材料128b可包括凸塊金屬線。
應注意，在平坦化製程之後，第一接合介電層120的頂表面120S與第一接合金屬層128的頂表面128S共面。在一些實施例中，第一接合結構130的頂表面130S的可接合拓撲變化（bondable topography variation，BTV）可小於1 mm/1 mm範圍，以易於直接接合到其他晶粒或晶片。此處，可接合拓撲變化（BTV）被稱為第一接合結構130的頂表面130S的最高點與最低點之間的高度差。在一些替代實施例中，第一接合結構130的頂表面130S的可接合拓撲斜率（bondable topography slope，BTS）可小於0.001。此處，可接合拓撲斜率（BTS）被稱為第一接合結構130的頂表面130S的最高點與最低點之間的垂直變化對水準變化的比率。
參照圖1F及圖1G，提供具有彼此相對的正面200a及背面200b的第二晶粒200。在一些實施例中，第二晶粒200包括第二基底202、第二裝置層203、第二內連線結構204（其包括第二絕緣材料206及多個第二金屬特徵208）、第二鈍化層210、第二接墊212以及至少一個第二基底穿孔（TSV）215。第二晶粒200的配置、材料及形成方法類似于第一晶粒100的配置、材料及形成方法。因此，於此便不再贅述。在一些實施例中，第二晶粒200與第一晶粒100可具有相同的功能或不同的功能。在一些實施例中，第二晶粒200包括特殊應用積體電路（ASIC）晶片、類比（analog）晶片、感測器晶片、無線（例如，藍牙及射頻）晶片、電壓調節器（voltage regulator）晶片或記憶體晶片（例如，動態隨機存取記憶體（DRAM）晶片或靜態隨機存取記憶體（SRAM）晶片）。
參照圖1G，在第二晶粒200的正面200a之上形成第二接合結構230。在一些實施例中，第二接合結構230具有第二接合介電層220及形成或嵌入在第二接合介電層220中的第二接合金屬層228。第二接合金屬層228通過形成在第二鈍化層210之上的介電層214中的凸塊通孔225以與第二內連線結構204電性連接。將第二晶粒200翻轉，使得第二晶粒200的正面200a面朝第一晶粒100的背面S2。第一晶粒100與第二晶粒200通過第一接合結構130及第二接合結構230接合在一起。也就是說，第一接合結構130與第二接合結構230通過混合接合而接合在一起，以形成混合接合結構30。通過施加壓力及熱量而將第一接合結構130與第二接合結構230混合接合在一起。
應注意，混合接合涉及至少兩種類型的接合，包括金屬對金屬接合以及非金屬對非金屬接合，例如介電質對介電質接合或熔融接合。如圖1G所示，混合接合結構30包括通過金屬對金屬接合而進行接合的第一接合金屬層128及第二接合金屬層228、以及通過非金屬到非金屬接合而進行接合的第一接合介電層120及第二接合介電層220。
如圖1G所示，在將第一晶粒100與第二晶粒200接合在一起之後完成製作晶粒堆疊結構1。在一些實施例中，與傳統晶圓上晶片（chip-on-wafer，CoW）結構相比，一些實施例的晶粒堆疊結構1的第一接合結構130的頂表面130S的可接合拓撲變化更小。因此，晶粒堆疊結構1能夠在晶片10之上堆疊更多晶粒或晶片，以增加晶粒堆疊結構1的使用面積。
圖2A到圖2I是根據第二實施例的一種形成晶粒堆疊結構的方法的剖視圖。
參照圖2A，圖2A所示的結構類似於圖1B所示的結構。以上論述了圖2A所示的元件的材料及形成方法。因此，於此便不再贅述。
參照圖2B，在執行薄化製程之後，移除第一基底102的一部分或凹陷第一基底102的所述部分，以在第一基底穿孔115旁邊形成凹槽132。凹槽132是通過以下方式形成：在第一基底102的背面S2之上沉積罩幕圖案（圖中未示出）以暴露出第一基底102的待形成凹槽132的表面、然後對第一基底102的背面S2執行蝕刻製程。在一些實施例中，凹槽132環繞第一基底穿孔115並暴露出第一基底穿孔115的上側壁115U。在一些實施例中，凹槽132的深度D1可為500 Å到1000 Å，且凹槽132的寬度W1可為0.8 μm到100 μm。在一些替代實施例中，凹槽132可為環繞第一基底穿孔115的上部部分的環形開口。
參照圖2C，在第一基底102的背面S2之上以毯覆方式形成隔離材料134。隔離材料134填充在凹槽132中並延伸以覆蓋第一基底102的背面S2、第一基底穿孔115以及隔離結構118。在一些實施例中，隔離材料134包括介電材料，例如氧化矽、氮化矽、氮氧化矽或其組合，且是通過例如CVD、ALD等適當的製程而形成。在一些實施例中，隔離材料134的厚度大於4000 Å。
參照圖2C及圖2D，對隔離材料134執行平坦化製程，以暴露出第一基底102的背面S2，以形成環繞第一基底穿孔115的上部部分的隔離結構134a。在一些實施例中，環繞第一基底穿孔115的上部部分的隔離結構134a能夠避免第一基底穿孔115或待形成第一接合金屬層128（如圖2H所示）的金屬（例如，Cu）擴散到第一基底102中。換句話說，第一基底穿孔115或待形成第一接合金屬層128與第一基底102通過環繞第一基底穿孔115的上部部分的隔離結構134a而彼此電性隔離。因此，能夠預防漏電流問題。在一些實施例中，在平坦化製程之後，第一基底102的背面S2、隔離結構118的頂表面118S以及第一基底穿孔115的頂表面115S共面。在一些實施例中，平坦化製程包括化學機械研磨（CMP）製程、回蝕刻製程或其組合。
參照圖2E到圖2H，在第一基底102的背面S2、隔離結構134a以及第一基底穿孔115之上形成第一接合結構130。第一接合結構130的形成方法類似於圖1C到圖1F所示的形成方法。以上論述了上述元件的材料及形成方法。因此，於此便不再贅述。
應注意，在一些實施例中，環繞第一基底穿孔115的上部部分的隔離結構134a可避免第一基底穿孔115的金屬（例如，Cu）擴散到第一基底102中，且可增大形成開口122（圖2F所示）的製程裕度（process window）。也就是說，即使開口122未對準，第一基底102的一部分仍不會受損或被移除，使得漏電流相應地減小。換句話說，隔離材料134a能夠減小或避免第一接合金屬材料128a與第一基底102直接接觸的可能性。
參照圖2I，提供在其正面200a之上形成有第二接合結構230的第二晶粒200。第二晶粒200的形成方法類似於圖1G所示的形成方法。以上論述了上述元件的材料及形成方法。因此，於此便不再贅述。在一些實施例中，將第二晶粒200翻轉，使得第二晶粒200的正面200a面朝第一晶粒100的背面S2。第一晶粒100與第二晶粒200通過第一接合結構130及第二接合結構230接合在一起。如圖1G所示，在將第一晶粒100與第二晶粒200接合在一起之後，便完成製作具有隔離結構134a環繞第一基底穿孔115的上部部分的晶粒堆疊結構2。
圖3A到圖3H是根據第三實施例的一種形成晶粒堆疊結構的方法的剖視圖。
參照圖3A，圖3A所示的結構類似於圖1B所示的結構。以上論述了圖3A所示的元件的材料及形成方法。因此，於此便不再贅述。
參照圖3B，在執行薄化製程之後，在第一基底102的背面S2之上以毯覆方式形成蝕刻停止層136。蝕刻停止層136覆蓋第一基底102的背面S2、第一基底穿孔115以及隔離結構118。在一些實施例中，蝕刻停止層136包括介電材料，例如氧化矽、氮化矽、氮氧化矽或其組合，且是通過例如CVD、ALD等適當的製程而形成。在一些實施例中，蝕刻停止層136的厚度是500 Å到4000 Å。
參照圖3B及圖3C，在形成蝕刻停止層136之後，執行圖案化製程以移除蝕刻停止層136的一部分。隨後，移除第一基底102的一部分或凹陷第一基底102的所述部分，以在第一基底穿孔115旁邊形成凹槽332。凹槽332是通過利用蝕刻停止層136a作為蝕刻罩幕對第一基底102的背面S2執行蝕刻製程而形成。在一些實施例中，凹槽332環繞第一基底穿孔115並暴露出第一基底穿孔115的上側壁115U’。在一些實施例中，凹槽332的深度D2可大於4000 Å，且凹槽332的寬度W2可為0.8 μm到100 μm。在一些替代實施例中，凹槽332可為環繞第一基底穿孔115的上部部分的環形開口。
參照圖3D，在第一基底102的背面S2之上以毯覆方式形成隔離材料334。隔離材料334填充在凹槽332中並延伸以覆蓋第一基底102的背面S2、第一基底穿孔115以及隔離結構118。在一些實施例中，隔離材料334包括介電材料，例如氧化矽、氮化矽、氮氧化矽或其組合，且是通過例如CVD、ALD等適當的製程而形成。在一些實施例中，隔離材料334的厚度大於400 nm。
在一些實施例中，凹槽332的深度D2深於凹槽132的深度D1（圖2B所示），因此隔離材料334的頂表面不平整。也就是說，隔離材料334可包括對應於第一基底穿孔115的不平整的結構335。不平整的結構335可包括凹陷部分335a、隆起部分335b以及平坦部分335c。詳細來說，凹陷部分335a對應於凹槽332，隆起部分335b對應於第一基底穿孔115，而平坦部分335c對應於蝕刻停止層136a。隆起部分335b位於凹陷部分335a中。在一些實施例中，隆起部分335b可為但不限於山丘狀輪廓。凹陷部分335a可以是但不限於環繞隆起部分335b的環形結構。詳細來說，如圖3D所示，隆起部分335b的頂表面可為中間高於周邊的弧形外形。平坦部分335c環繞隆起部分335b。在一些實施例中，凹陷部分335a的頂表面低於隆起部分335b的頂表面以及平坦部分335c的頂表面。隆起部分335b的頂表面可等於或低於平坦部分335c的頂表面。
參照圖3D，然後在隔離材料334之上形成第一接合介電層320。第一接合介電層320的材料不同於隔離材料334的材料。在一些實施例中，第一接合介電層320可包括氧化矽、氮化矽、聚合物或其組合，且是通過例如旋轉塗布、CVD等適當的製程而形成。在一些實施例中，第一接合介電層320共形地覆蓋隔離材料334，因此第一接合介電層320的頂表面也不平整。在一些實施例中，如圖3D所示，第一接合介電層320的頂表面的不平整度小於隔離材料334的頂表面的不平整度。
參照圖3D及圖3E，執行圖案化製程，以在第一接合介電層320a及隔離結構334a中形成至少一個開口322。開口322暴露出第一基底穿孔115的頂表面115S。在一些實施例中，開口322的底部寬度（或面積）Wb大於第一基底穿孔115的頂表面115S的寬度（或面積）。由於第一基底穿孔115的上部部分被隔離結構334a環繞，因此即使開口322大於頂表面115S或未對準，第一基底102的一部分仍不會受損或被移除，使得漏電流相應地減小。換句話說，開口322的底部寬度（或面積）Wb小於第一基底穿孔115及位於第一基底穿孔115旁邊的隔離結構334a的總寬度Ws。在一些實施例中，如圖3E所示，開口322不切斷隔離結構334a，因此隔離結構334a不僅設置在開口322中，而且從第一基底穿孔115的上側壁115U’延伸到位於蝕刻停止層136a與第一接合介電層320a之間的空間中。換句話說，隔離結構334a是從第一基底穿孔115的上側壁115U’延伸到位於蝕刻停止層136a與第一接合介電層320a之間的空間中的連續結構。
參照圖3F及圖3G，在第一接合介電層320a之上形成金屬材料326並將金屬材料326填充在開口322中。在一些實施例中，金屬材料326可為鋁、銅、鎳、金、銀、鎢或其組合，且是通過電化學鍍覆製程、CVD、PVD等形成。隨後，執行平坦化製程（例如，CMP製程）以移除金屬材料326的一部分，使得第一接合介電層320a的頂表面320S被暴露出。在所述情形中，如圖3G所示，第一接合金屬層328形成在第一接合介電層320a及隔離結構334a中，且與第一基底穿孔115電性連接。在一些實施例中，在開口322中形成的第一接合金屬層328可為但不限於具有均勻寬度或面積的圓柱或柱子。
參照圖3H，提供在其正面200a之上形成有第二接合結構230的第二晶粒200。第二晶粒200的形成方法類似於圖1G所示的形成方法。以上論述了上述元件的材料及形成方法。因此，於此便不再贅述。在一些實施例中，將第二晶粒200翻轉，使得第二晶粒200的正面200a面朝第一晶粒100的背面S2。第一晶粒100與第二晶粒200通過混合接合而被接合在一起以形成混合接合結構30a。混合接合結構30a可包括第一接合結構330及第二接合結構230。如圖3H所示，在將第一晶粒100與第二晶粒200接合在一起之後，便完成製作隔離結構334a環繞第一基底穿孔115的上部部分且延伸到位於蝕刻停止層136a與第一接合介電層320a之間的空間的晶粒堆疊結構3。
圖4A到圖4I是根據第四實施例，一種形成晶粒堆疊結構的方法的剖視圖。
參照圖4A，圖4A所示的結構類似於圖1B所示的結構。以上論述了圖4A所示的元件的材料及形成方法。因此，於此便不再贅述。
參照圖4B，在執行薄化製程之後，通過回蝕刻製程全面性地移除第一基底102的一部分或全面性地凹陷第一基底102的所述部分，使得第一基底102的背面S2與第一基底穿孔115的頂表面115S之間存在高度差H。也就是說，在執行回蝕刻製程之後，第一基底穿孔115的上部部分及隔離結構118的上部部分被暴露出。在一些實施例中，第一基底102的背面S2與第一基底穿孔115的頂表面115S之間的高度差H是0.4 μm到2 μm。
參照圖4C及圖4D，在第一基底102的背面S2之上形成第一接合介電層420。在一些實施例中，如圖4C所示，第一接合介電層420共形地覆蓋第一基底穿孔115的上部部分以及隔離結構118的上部部分。詳細來說，由於第一基底102的背面S2與第一基底穿孔115的頂表面115S具有高度差H，因此共形地形成於其上的第一接合介電層420具有凹凸表面。也就是說，第一接合介電層420可包括不平整的結構421。不平整的結構421可包括凸出部分421a、隆起部分421b以及平坦部分421c。凸出部分421a對應於隔離結構118，隆起部分421b對應於第一基底穿孔115，且平坦部分421c對應於第一基底102的背面S2。在一些實施例中，第一基底穿孔115的寬度W3是0.8 μm到12 μm，且隔離結構118的寬度W4是30 μm到1000 μm。寬度W4對寬度W3的比率（W4/W3）可為2.5到1250。也就是說，凸出部分421a的體積大於隆起部分421b的體積。換句話說，隔離結構118之上的第一接合介電層420的體積大於第一基底穿孔115之上的第一接合介電層420的體積。在一些實施例中，第一接合介電層420可包括氧化矽、氮化矽、聚合物或其組合，且是通過例如旋轉塗布、CVD等適當的製程形成。此後，通過例如旋轉塗布等適當的製程在第一接合介電層420之上形成光阻層422。
參照圖4D及圖4E，對光阻層422及第一接合介電層420執行圖案化製程，以在隔離結構118之上形成開口424。在一些實施例中，如圖4E所示，隔離結構118之上的光阻層422及第一接合介電層420被移除以形成開口424。隔離結構118的頂表面118S被開口424暴露出。詳細來說，平行於隔離結構118的頂表面118S（或第一基底穿孔115的頂表面115S）的平面之上的第一接合介電層420的體積減小，使得後續平坦化製程（例如，CMP製程）的性能提高。換句話說，第一接合介電層420的位於隔離結構118的頂表面118S之上的體積佔據第一接合介電層420的總體積的約20%到40%。開口424有利於大幅減少位於隔離結構118的頂表面118S之上的第一接合介電層420的體積，以提高後續平坦化製程（例如，CMP製程）的性能。
參照圖4E及圖4G，移除光阻層422a以暴露出第一接合介電層420a。此後，如圖4G所示，對第一接合介電層420a執行平坦化製程（例如，CMP製程），以形成環繞第一基底穿孔115的上部部分以及隔離結構118的上部部分的第一接合介電層420b。換句話說，隔離結構118的頂表面118S以及第一基底穿孔115的頂表面115S被第一接合介電層420b暴露出。
返回參照圖4G，在執行平坦化製程之後，第一接合介電層420b的頂表面420S的可接合拓撲變化（BTV）減小，且小於在不執行上述圖案化製程以移除隔離結構118的頂表面118S之上的第一接合介電層420的情況下的第一接合介電層的頂表面的BTV。在一些實施例中，在執行平坦化製程之後，第一接合介電層420b的頂表面420S、隔離結構118的頂表面118S以及第一基底穿孔115的頂表面115S共面。
返回參照圖4G及圖4H，在第一接合介電層420b之上形成另一第一接合介電層420c。在一些實施例中，第一接合介電層420c的材料相同于第一接合介電層420b的材料。在一些其他實施例中，第一接合介電層420c的材料不同于第一接合介電層420b的材料。通過微影及蝕刻製程將第一接合介電層420c圖案化，以在其中形成開口。在一些實施例中，第一接合介電層420b的材料不同于第一接合介電層420c的材料，在蝕刻製程期間，第一接合介電層420b充當蝕刻停止層，且因此當微影製程未對準時，第一接合介電層420b外露於所述開口。然後在第一接合介電層420c中的所述開口中形成第一接合金屬層428，以電性連接到第一基底穿孔115。在一些實施例中，第一接合介電層420b、420c以及第一接合金屬層428被稱為第一接合結構430。
參照圖4H及圖4I，提供在其正面200a之上形成有第二接合結構230的第二晶粒200。第一晶粒100與第二晶粒200通過混合接合而被接合在一起，以形成混合接合結構30b。混合接合結構30b可包括第一接合結構430及第二接合結構230。詳細來說，第二接合金屬層228與第一接合金屬層428是通過金屬對金屬接合進行接合，而第二接合介電層220與第一接合介電層420c是通過非金屬對非金屬接合進行接合。在一些實施例中，如圖4I所示，在將第一晶粒100與第二晶粒200接合在一起之後便完成製作具有第一接合介電層420b環繞第一基底穿孔115的上部部分的晶粒堆疊結構4。
圖5是根據第五實施例的晶粒堆疊結構的剖視圖。
參照圖4G及圖5，在一些實施例中，在平坦化製程之後，第一接合介電層420b的頂表面420S、隔離結構118的頂表面118S以及第一基底穿孔115的頂表面115S共面，且第一接合介電層420b的頂表面420S的BTV可小於1 mm/1 mm範圍，以易於直接接合到其他晶粒或晶片。
舉例來說，如圖5所示，提供在其正面200a之上形成有第二接合結構230的第二晶粒200。第一晶粒100與第二晶粒200通過混合接合而被接合在一起，以形成混合接合結構30c。混合接合結構30c可包括第一接合結構530（包括第一接合介電層420b以及被第一接合介電層420b環繞的第一基底穿孔115的上部部分）及第二接合結構230。詳細來說，第二接合金屬層228與第一基底穿孔115是通過金屬對金屬接合進行接合，而第二接合介電層220與第一接合介電層420b是通過非金屬對非金屬接合進行接合。在一些實施例中，如圖5所示，在將第一晶粒100與第二晶粒200接合在一起之後便完成製作具有第一接合介電層420b環繞第一基底穿孔115的上部部分的晶粒堆疊結構5。
參照圖7，晶粒堆疊結構7的配置、材料及形成方法類似于晶粒堆疊結構1的配、材料及形成方法。因此，於此便不再贅述。所述兩者之間的差異在於：晶粒堆疊結構7包括多於兩個晶粒，其以背對面（back-to-face）的方式接合在一起。詳細來說，晶粒堆疊結構7包括被隔離結構118分隔開的第一晶粒100中的一者與被隔離結構218分隔開的第二晶粒200中的一者。第一晶粒100中的一者與第二晶粒200中的一者通過混合接合結構30被接合在一起。此後，在第二晶粒200的背面200b之上形成接合結構630。接合結構630可包括接合介電層620及形成在接合介電層620中的接合金屬層628。接合金屬層628與第二基底穿孔215電性連接。類似地，第二晶粒20可通過接合結構630與另一晶粒接合。如圖7所示，通過接合結構730將最頂部的晶粒（圖中未示出）與另一載體C’接合在一起。
圖6是根據一個實施例的封裝體的剖視圖。
參照圖6，提供包括晶粒堆疊結構6、絕緣包封體22以及重佈線層結構23的封裝體P1。詳細來說，通過黏著層21將具有彼此相對的第一表面6a及第二表面6b的晶粒堆疊結構6安裝在介電層11之上。晶粒堆疊結構6的第一表面6a朝上，且晶粒堆疊結構6的第二表面6b朝向介電層11。在一些實施例中，晶粒堆疊結構6可以是晶粒堆疊結構1、2、3、4及5中的一者，其包括第一晶粒100與第二晶粒200以背對面方式接合在一起。也就是說，第二晶粒200的正面（例如，主動表面）面朝第一晶粒100的背面。第一晶粒100及第二晶粒200可具有相同的功能或不同的功能。在一些實施例中，第一晶粒100或第二晶粒200的數目不受本公開內容的限制。換句話說，多個晶粒或晶片可以背對面的方式接合在一起以形成晶粒堆疊結構。舉例來說，如圖7所示，在晶粒堆疊結構7中的多於兩個晶粒以背對面的方式接合在一起。在一些替代實施例中，晶粒堆疊結構6的數目不受本公開內容的限制。舉例來說，在絕緣包封體22中平行排列有多個晶粒堆疊結構（圖中未示出）。
參照圖6，晶粒堆疊結構6進一步包括多個連接件18以及鈍化層19。連接件18形成在未被鈍化層150覆蓋的接合墊140b1之上，並電性連接到所述接合墊140b1。連接件18包括焊料凸塊、金凸塊、銅凸塊、銅杆、銅柱等。鈍化層19形成在鈍化層150之上並位於連接件18旁邊，以覆蓋連接件18的側壁。以晶粒堆疊結構7為例，如圖7所示，晶粒堆疊結構7上下倒置，使得第一晶粒100的正面S1面朝上。在一些實施例中，介電層DI可與剝離層DB剝離，使得介電層DI與剝離層DB及載體C分離或脫層。在一些實施例中，剝離層DB（例如，LTHC離形層）可照射紫外光，使得介電層DI與載體C剝離。在一些替代實施例中，介電層DI可與第一晶粒100分離，以暴露出介電層116。此後，如圖6所示，可通過圖案化製程及沉積製程，以在第一接墊112（例如，接合墊140b1）之上形成連接件（例如，連接件18，例如微凸塊（μ-bump））。
參照圖6，在晶粒堆疊結構6旁邊形成絕緣包封體22，以包封晶粒堆疊結構6。多個導電柱14形成在絕緣包封體22中且環繞晶粒堆疊結構6。重佈線層（redistribution layer，RDL）結構23形成在晶粒堆疊結構6及導電柱14之上，並電性連接到晶粒堆疊結構6及導電柱14。在一些實施例中，重佈線層結構23包括交替堆疊的多個聚合物層PM1、PM2、PM3及PM4以及多個重佈線層RDL1、RDL2、RDL3及RDL4。聚合物層或重佈線層的數目不受本公開內容的限制。
換句話說，重佈線層RDL1穿透聚合物層PM1並電性連接到晶粒堆疊結構6的連接件18及導電柱14。重佈線層RDL2穿透聚合物層PM2並電性連接到重佈線層RDL1。重佈線層RDL3穿透聚合物層PM3並電性連接到重佈線層RDL2。重佈線層RDL4穿透聚合物層PM4並電性連接到重佈線層RDL3。在一些實施例中，聚合物層PM1、PM2、PM3及PM4中的每一者包括光敏材料，例如聚苯噁唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）或其組合等。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4中的每一者包括導電材料。導電材料包括金屬，例如銅、鎳、鈦或其組合等，且是通過電鍍製程而形成。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包括晶種層（圖中未示出）及形成於其上的金屬層（圖中未示出）。晶種層可為金屬晶種層，例如銅晶種層。在一些實施例中，晶種層包括：第一金屬層（例如鈦層）以及位於第一金屬層之上的第二金屬層（例如銅層）。金屬層可為銅或其他適當的金屬。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包括彼此連接的多個通孔及多個跡線（trace）。所述通孔連接重佈線層RDL1、RDL2、RDL3及RDL4，且所述跡線分別位於聚合物層PM1、PM2、PM3及PM4上且分別在聚合物層PM1、PM2、PM3及PM4的頂表面上延伸。
在一些實施例中，最頂部的重佈線層RDL4包括RDL4a及RDL4b。重佈線層RDL4a也被稱為用於植球的球下金屬（under-ball metallurgy，UBM）層。重佈線層RDL4b可為用於連接到在隨後的製程中形成的積體被動裝置（integrated passive device，IPD）26的微凸塊。
隨後，多個連接件24形成在重佈線層結構23的重佈線層RDL4a之上並電性連接到重佈線層RDL4a。在一些實施例中，連接件24是由具有低電阻率的導電材料（例如，Sn、Pb、Ag、Cu、Ni、Bi或其合金）所製成，且是通過蒸鍍、鍍覆、球滴（ball drop）或絲網印刷等適當的製程而形成。積體被動裝置26形成在重佈線層結構23的重佈線層RDL4b之上並通過焊料凸塊28電性連接到重佈線層RDL4b。積體被動裝置26可為電容器、電阻器、電感器等或其組合。積體被動裝置26的數目並不限於圖6中所示者，而是可根據產品的設計進行調整。底部填充層27形成在積體被動裝置26與聚合物層PM4之間，並環繞且覆蓋被暴露出的RDL4b、焊料凸塊28及積體被動裝置26的底表面。
如圖6所示，然而圖案化介電層11，使得導電柱14的下表面被介電層11暴露出。在導電柱14的下表面之上分別形成導電端子40之後便完成了製作具有雙側端子的積體扇出型封裝體P1。然後提供另一封裝體P2。在一些實施例中，封裝體P2是例如記憶體裝置。封裝體P2堆疊在積體扇出型封裝體P1之上並通過導電端子40電性連接到積體扇出型封裝體P1，以製成疊層封裝體（POP）結構。
根據一些實施例，一種晶粒堆疊結構包括第一晶粒、第二晶粒、第一接合結構以及第二接合結構。所述第一接合結構設置在所述第一晶粒的背面上。所述第二接合結構設置在所述第二晶粒的正面上。所述第一晶粒及所述第二晶粒通過所述第一接合結構及所述第二接合結構接合在一起，且與所述第二接合結構進行接合的所述第一接合結構的表面的可接合拓撲變化小於1 mm/1 mm範圍。
在一些實施例中，所述第一晶粒包括：第一基底、第一內連線以及至少一個第一基底穿孔。第一內連線設置在所述第一基底的正面之上。至少一個第一基底穿孔穿透所述第一基底，以電性連接到所述第一內連線及所述第一接合結構。
在一些實施例中，所述第一接合結構包括第一接合介電層與第一接合金屬層。第一接合介電層設置在所述第一基底穿孔之上及所述第一基底的背面之上。第一接合金屬層設置在所述第一接合介電層中，以與所述第一基底穿孔及所述第二接合結構電性連接。
在一些實施例中，所述第一接合金屬層包括單鑲嵌結構、雙鑲嵌結構或其組合。
在一些實施例中，所述單鑲嵌結構包括凸塊金屬線，且所述雙鑲嵌結構包括凸塊通孔及位於所述凸塊通孔之上的另一凸塊金屬線。
在一些實施例中，所述第一接合金屬層是雙鑲嵌結構，所述第一接合金屬層的底面積小於所述第一基底穿孔的頂面積。
在一些實施例中，所述晶粒堆疊結構更包括隔離結構，所述隔離結構環繞所述第一基底穿孔的上部部分，以電性隔離所述第一接合金屬層與所述第一基底。
在一些實施例中，所述隔離結構從所述第一基底穿孔的上側壁延伸到所述第一基底與所述第一接合介電層之間的空間。
在一些實施例中，所述第一接合結構包括第一接合介電層。所述第一接合介電層設置在所述第一基底的背面之上且環繞所述第一基底穿孔的上部部分，使得所述第一基底穿孔的頂表面外露於所述第一接合介電層。
在一些實施例中，所述第一接合結構更包括第二接合介電層與第一接合金屬層。第二接合介電層設置在所述第一接合介電層之上。第一接合金屬層，設置在所述第二接合介電層中，以與所述第一基底穿孔及所述第二接合結構電性連接。
根據一些實施例，一種製作晶粒堆疊結構的方法包括：提供第一晶粒，在所述第一晶粒中具有至少一個第一基底穿孔（TSV）；對所述第一晶粒的背面執行薄化製程，以暴露出所述第一基底穿孔；在所述薄化製程之後，在所述第一晶粒的所述背面之上直接形成第一接合結構；在第二晶粒的正面之上形成第二接合結構；以及通過所述第一接合結構及所述第二接合結構將所述第一晶粒與所述第二晶粒接合在一起。
在一些實施例中，所述第一晶粒包括第一基底、第一內連線以及第一基底穿孔。第一內連線設置在所述第一基底的正面之上。第一基底穿孔穿透所述第一基底，以與所述第一內連線及所述第一接合結構電性連接。
在一些實施例中，所述形成所述第一接合結構包括：在所述第一基底穿孔之上及所述第一基底的背面之上形成第一接合介電層；以及通過鑲嵌法在所述第一接合介電層中形成第一接合金屬層，以與所述第一基底穿孔及所述第二接合結構電性連接。
在一些實施例中，與所述第二接合結構進行接合的所述第一接合結構的表面的可接合拓撲變化小於1 mm/1 mm範圍。
根據一些實施例，一種製作晶粒堆疊結構的方法包括：提供第一晶粒，所述第一晶粒具有第一基底、設置在所述第一基底的正面之上的第一內連線及位於所述第一基底中的至少一個第一基底穿孔（TSV）；凹陷所述第一基底的背面，以在所述第一基底穿孔旁邊形成凹槽，其中所述凹槽環繞所述第一基底穿孔且暴露出所述第一基底穿孔的上側壁；在所述凹槽中形成隔離結構；在所述隔離結構之上形成第一接合介電層；在所述第一接合介電層中形成第一接合金屬層，以在所述第一基底的所述背面之上形成第一接合結構；在第二晶粒的正面之上形成第二接合結構；以及通過所述第一接合結構及所述第二接合結構將所述第一晶粒與所述第二晶粒接合在一起。
在一些實施例中，在所述凹槽中形成所述隔離結構的方法包括：在所述隔離材料之上形成所述第一接合介電層；圖案化所述第一接合介電層及所述隔離材料，以在所述第一接合介電層及所述隔離材料中形成至少一個開口，其中所述開口暴露出所述第一基底穿孔的頂表面；以及在所述開口中形成所述第一接合金屬層。
在一些實施例中，所述凹陷所述第一基底的所述背面包括：全面性地移除所述第一基底的所述背面，使得在所述第一基底的所述背面與所述第一基底穿孔的頂表面之間存在高度差。
在一些實施例中，所述在所述凹槽中形成所述隔離結構包括：在全面性地移除所述第一基底的所述背面之後，在所述第一基底的所述背面之上共形地形成第二接合介電層；移除所述第二接合介電層的一部分；以及平坦化所述第二接合介電層的另一部分，以暴露出所述第一基底穿孔的所述頂表面。
在一些實施例中，所述隔離結構是所述第二接合介電層且包括氧化矽、氮化矽、聚合物或其組合。
在一些實施例中，與所述第二接合結構進行接合的所述第一接合結構的表面的可接合拓撲變化小於1 mm/1 mm範圍。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
1、2、3、4、5、6、7‧‧‧晶粒堆疊結構
6a‧‧‧第一表面
6b‧‧‧第二表面
10‧‧‧晶片
11‧‧‧介電層
14‧‧‧導電柱
18‧‧‧連接件
19‧‧‧鈍化層
21‧‧‧黏著層
22‧‧‧絕緣包封體
23‧‧‧重佈線層結構
24‧‧‧連接件
26‧‧‧積體被動裝置
27‧‧‧底部填充層
28‧‧‧焊料凸塊
30、30a、30b、30c‧‧‧混合接合結構
40‧‧‧導電端子
100‧‧‧第一晶粒
102‧‧‧第一基底
103‧‧‧第一裝置層
104‧‧‧第一內連線結構
106‧‧‧第一絕緣材料
108‧‧‧第一金屬特徵
108a、108b‧‧‧頂部金屬特徵
110‧‧‧第一鈍化層
112‧‧‧第一接墊
114‧‧‧介電層
115‧‧‧第一基底穿孔
115S‧‧‧頂表面
115U、115U’‧‧‧上側壁
116‧‧‧介電層
118‧‧‧隔離結構
118S‧‧‧頂表面
120‧‧‧第一接合介電層
120a、120b、120c、120d‧‧‧接合介電材料
120S‧‧‧頂表面
122‧‧‧開口
122a‧‧‧通孔
122b‧‧‧溝渠
124‧‧‧開口
126‧‧‧金屬材料
128‧‧‧第一接合金屬層
128a、128b‧‧‧第一接合金屬材料
128S‧‧‧頂表面
130‧‧‧第一接合結構
130S‧‧‧頂表面
132‧‧‧凹槽
134‧‧‧隔離材料
134a‧‧‧隔離結構
136、136a‧‧‧蝕刻停止層
140b1‧‧‧接合墊
150‧‧‧鈍化層
200‧‧‧第二晶粒
200a‧‧‧正面
200b‧‧‧背面
202‧‧‧第二基底
203‧‧‧第二裝置層
204‧‧‧第二內連線結構
206‧‧‧第二絕緣材料
208‧‧‧第二金屬特徵
210‧‧‧第二鈍化層
212‧‧‧第二接墊
214‧‧‧介電層
215‧‧‧第二基底穿孔
218‧‧‧隔離結構
220‧‧‧第二接合介電層
225‧‧‧凸塊通孔
228‧‧‧第二接合金屬層
230‧‧‧第二接合結構
320‧‧‧第一接合介電層
320a‧‧‧第一接合介電層
320S‧‧‧頂表面
322‧‧‧開口
326‧‧‧金屬材料
328‧‧‧第一接合金屬層
330‧‧‧第一接合結構
332‧‧‧凹槽
334‧‧‧隔離材料
334a‧‧‧隔離結構
335‧‧‧不平整的結構
335a‧‧‧凹陷部分
335b‧‧‧隆起部分
335c‧‧‧平坦部分
420、420a、420b、420c‧‧‧第一接合介電層
420S‧‧‧頂表面
421‧‧‧不平整的結構
421a‧‧‧凸出部分
421b‧‧‧隆起部分
421c‧‧‧平坦部分
422、422a‧‧‧光阻層
424‧‧‧開口
428‧‧‧第一接合金屬層
430‧‧‧第一接合結構
530‧‧‧第一接合結構
620‧‧‧接合介電層
628‧‧‧接合金屬層
630‧‧‧接合結構
730‧‧‧接合結構
AM‧‧‧對準標記
C、C’‧‧‧載體
D1、D2‧‧‧深度
DB‧‧‧剝離層
DI‧‧‧介電層
H‧‧‧高度差
P1、P2‧‧‧封裝體
PM1、PM2、PM3、PM4‧‧‧聚合物層
RDL1、RDL2、RDL3、RDL4、RDL4a、RDL4b‧‧‧重佈線層
S1‧‧‧正面
S2‧‧‧背面
W1、W2、W3、W4‧‧‧寬度
Wb‧‧‧底部寬度
Ws‧‧‧總寬度
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A到圖1G是根據第一實施例的一種形成晶粒堆疊結構的方法的剖視圖。 圖2A到圖2I是根據第二實施例的一種形成晶粒堆疊結構的方法的剖視圖。 圖3A到圖3H是根據第三實施例的一種形成晶粒堆疊結構的方法的剖視圖。 圖4A到圖4I是根據第四實施例的一種形成晶粒堆疊結構的方法的剖視圖。 圖5是根據第五實施例的晶粒堆疊結構的剖視圖。 圖6是根據一個實施例的封裝體的剖視圖。 圖7是根據第六實施例的晶粒堆疊結構的剖視圖。

Claims (1)

  1. 一種晶粒堆疊結構，包括： 第一晶粒及第二晶粒，通過第一接合結構及第二接合結構接合在一起，其中 所述第一接合結構設置在所述第一晶粒的背面上， 所述第二接合結構設置在所述第二晶粒的正面上，且 與所述第二接合結構進行接合的所述第一接合結構的表面的可接合拓撲變化小於1 mm/1 mm範圍。
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