TWI760561B - 三維積體電路結構及其製造方法 - Google Patents

三維積體電路結構及其製造方法 Download PDF

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TWI760561B
TWI760561B TW107132252A TW107132252A TWI760561B TW I760561 B TWI760561 B TW I760561B TW 107132252 A TW107132252 A TW 107132252A TW 107132252 A TW107132252 A TW 107132252A TW I760561 B TWI760561 B TW I760561B
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die
layer
circuit structure
bonding
top surface
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TW107132252A
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TW202002188A (zh
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陳憲偉
楊慶榮
陳明發
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台灣積體電路製造股份有限公司
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Abstract

一種三維積體電路結構，包括晶粒堆疊結構、金屬電路 結構及保護結構。晶粒堆疊結構包括面對面接合在一起的第一晶粒與第二晶粒。金屬電路結構設置在第二晶粒的後側之上。保護結構設置在第二晶粒的後側內且分隔第二晶粒的多個基底穿孔中的一者與金屬電路結構。

Description

三維積體電路結構及其製造方法
本發明實施例是有關於一種三維積體電路結構及其製造方法。
近年來，由於各種電子元件(即，電晶體、二極體、電阻器、電容器等)的積體密度的持續改進，半導體行業已經歷了快速成長。積集密度的此種改進來自於最小特徵尺寸(minimum feature size)的一再減小，以允許更多的較小的元件能夠整合在一定的面積中。
與先前的封裝體相比，這些較小的電子元件也需要利用較小面積的較小的封裝體。半導體封裝體的示例性類型包括四面扁平封裝(quad flat package，QFP)、針格陣列(pin grid array，PGA)、球格陣列(ball grid array，BGA)、覆晶技術(flip chip，FC)、三維積體電路(three dimensional integrated circuit，3DIC)、晶圓級封裝體(wafer level package，WLP)及疊層封裝體(package on package，PoP)裝置。一些三維積體電路是通過將晶片(chip)放置在半導體晶圓級上的晶片上方製備而成。由於堆疊晶片之間的內連線的長度減小，因此三維積體電路提供更高的積體密度及其他優點，例如更快的速度及更高的頻寬。然而，對於三維積體電路技術來說仍存在很多待處理的挑戰。
本發明實施例提供一種三維積體電路結構，包括晶粒堆疊結構、金屬電路結構及保護結構。晶粒堆疊結構包括面對面接合在一起的第一晶粒與第二晶粒。金屬電路結構設置在第二晶粒的後側之上。保護結構設置在第二晶粒的後側內且分隔第二晶粒的多個基底穿孔中的一者與金屬電路結構。
1、2、3、4:三維積體電路結構
10:晶粒堆疊結構
11、226、402:介電層
14:導電柱
15:界面
18:連接件
19、410、406:鈍化層
21:黏合劑層
22:絕緣包封體
23:重佈線層結構
24:連接件
26:整合被動元件
27:底部填充膠層
28:焊料凸塊
30:導電端子
100:第一晶粒
100a:前側
100b:後側
102:第一半導體基底
103:第一元件層
104:第一內連結構
106:第一絕緣材料
108:第一金屬特徵
108a、108b:頂部金屬特徵
110:第一鈍化層
114:第一接合結構
116:第一接合介電層
118、120:第一接合金屬層
118a、120a、218a:通孔插塞
118b、120b、218b、404:金屬特徵
200、201a、201a:第二晶粒
200a:第二晶粒的前側
200b:第二晶粒的後側
202:第二半導體基底
202b:後表面
203:第二元件層
204:第二內連結構
205、205a、205b:基底穿孔
205s、205s’、222t、226t、300t、310t:頂表面
208:第二金屬特徵
210:第二鈍化層
214:第二接合結構
216:第二接合介電層
218:第二接合金屬層
220、224、304:氮化物層
222:氧化物層
250:混合接合結構
300、301、302、303:保護結構
305:共形層
306:填充層
307:罩幕圖案
308:開口
310:介電層穿孔
400:金屬電路結構
408:接合墊
D1:方向
P1:整合扇出型封裝體
P2:封裝體
PM1、PM2、PM3、PM4:聚合物層
R1、R2:凹槽
RDL1、RDL2、RDL3、RDL4、RDL4a、RDL4b:重佈線層
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A到圖1E是根據第一實施例的形成三維積體電路(3DIC)結構的方法的剖視圖。
圖2是根據第二實施例的三維積體電路結構的剖視圖。
圖3是根據第三實施例的三維積體電路結構的剖視圖。
圖4是根據一些實施例的封裝體的剖視圖。
以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，且也可包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件符號及/或字母。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
此外，為易於說明，本文中可能使用例如「在...下方(beneath)」、「在...下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對術語來闡述圖中所示的一個元件或特徵與另一(些)元件或特徵的關係。所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向)，而本文所用的空間相對術語相應地作出解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明進行三維(3D)封裝體或三維積體電路裝置的驗證測試。 測試結構可包括例如形成於重佈線層中或基底上的測試墊，所述測試墊使得能夠測試3D封裝體或3DIC、使用探針(probe)及/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可接合包括對已知良好晶粒(known good dies)的中間驗證的測試方法一起使用，以提高良率(yield)及降低成本。
圖1A到圖1E是根據第一實施例的形成三維積體電路結構的方法的剖視圖。
參照圖1A，形成晶粒堆疊結構10。具體來說，晶粒堆疊結構10包括第一晶粒100、第二晶粒200及混合接合結構250。第一晶粒100與第二晶粒200藉由混合接合結構250混合接合在一起。晶粒堆疊結構10根據例如以下步驟形成。
如圖1A所示，提供包括第一半導體基底102、第一元件層103、第一內連結構104及第一鈍化層110的第一晶粒100。
在一些實施例中，半導體基底102可包括矽或其他半導體材料。另外或額外的，第一半導體基底102可包括其他元素半導體材料，例如鍺。在一些實施例中，第一半導體基底102是由例如碳化矽、砷化鎵、砷化銦及磷化銦等化合物半導體製成。在一些實施例中，第一半導體基底102是由例如矽鍺、碳化矽鍺、磷化鎵砷或磷化鎵銦等合金半導體製成。在一些實施例中，第一半導體基底102包括外延層。舉例來說，第一半導體基底102具有上覆在塊狀半導體上的外延層。
在一些實施例中，第一元件層103是在前段(front-end-of-line，FEOL)製程中形成在第一半導體基底102之上。第一元件層103包括各種各樣的元件。在一些實施例中，所述元件包括主動元件、被動元件或它們的組合。在一些實施例中，所述元件可包括積體電路元件。所述元件是例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲元件或其他類似元件。在一些實施例中，第一元件層103包括閘極結構、源極區及汲極區、以及隔離結構，例如淺溝渠隔離(shallow trench isolation，STI)結構(圖中未示出)。在第一元件層103中，可形成且內連各種N型金屬氧化物半導體(NMOS)和/或P型金屬氧化物半導體(PMOS)元件(例如電晶體或記憶體等)來進行一個或多個功能。也可在第一半導體基底102之上形成其他元件，例如電容器、電阻器、二極體、光電二極體、熔絲等。所述元件的功能可包括記憶體、處理器、感測器、放大器、功率分配、輸入/輸出電路等。
參照圖1A，第一內連結構104形成在第一元件層103之上。詳細來說，第一內連結構104包括第一絕緣材料106及多個第一金屬特徵108。第一金屬特徵108形成在第一絕緣材料106中且電連接到第一元件層103。第一金屬特徵108的一部分(例如頂部金屬特徵108a及108b)外露於第一絕緣材料106。在一些實施例中，第一絕緣材料106包括位於第一元件層103上的層間介電(inner-layer dielectric，ILD)層以及位於層間介電層之上的至少一個金屬間介電(inter-metal dielectric，IMD)層。在一些實施 例中，第一絕緣材料106包括氧化矽、氮氧化矽、氮化矽、低介電常數(低k)材料或它們的組合。在一些替代實施例中，第一絕緣材料106可以是單層或多層。在一些實施例中，第一金屬特徵108包括插塞及金屬線。所述插塞可包括形成在層間介電層中的接觸窗(contacts)以及形成在金屬間介電層中的通孔(vias)。所述接觸窗形成在第一元件層103與底部金屬線之間且與第一元件層103及底部金屬線連接。所述通孔形成在兩條金屬線之間且與所述兩條金屬線連接。第一金屬特徵108可由鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或它們的組合製成。在一些替代實施例中，可在第一金屬特徵108與第一絕緣材料106之間形成障壁層(圖中未示出)，以防止第一金屬特徵108的材料遷移或擴散到第一元件層103。障壁層的材料包括例如鉭、氮化鉭、鈦、氮化鈦、鈷-鎢(CoW)或它們的組合。
參照圖1A，第一鈍化層110形成在第一內連結構104之上。第一鈍化層110覆蓋第一絕緣材料106和頂部金屬特徵108a及108b的一些部分。在一些實施例中，第一鈍化層110包括氧化矽、氮化矽、苯並環丁烯(benzocyclobutene，BCB)聚合物、聚醯亞胺(polyimide，PI)、聚苯並惡唑(polybenzoxazole，PBO)或它們的組合，且藉由例如旋塗、化學氣相沉積等合適的製程形成。將第一鈍化層110形成在第一內連結構104之上之後，第一晶粒100便已完成。如圖1A所示，第一晶粒100具有彼此相對的前側100a與後側100b。本文中，第一晶粒100的前側100a面朝 上，而第一晶粒100的後側100b面朝下。在一些實施例中，第一晶粒100的前側100a被稱為主動表面。
參照圖1A，在第一晶粒100的前側100a之上形成第一接合結構114。詳細來說，第一接合結構114包括第一接合介電層116和多個第一接合金屬層118及120。在一些實施例中，第一接合金屬層118及120形成在第一接合介電層116中。第一接合金屬層118包括通孔插塞118a及設置在通孔插塞118a之上的金屬特徵118b，而第一接合金屬層120包括通孔插塞120a及設置在通孔插塞120a之上的金屬特徵120b。如圖1A所示，通孔插塞118a貫穿第一鈍化層110且與第一金屬特徵108a連接，而通孔插塞120a貫穿第一鈍化層110且與第一金屬特徵108b連接。
在一些實施例中，第一接合金屬層118及120可包括銅、銅合金、鎳、鋁、鎢、它們的組合。在一些實施例中，第一接合金屬層118及120可使用相同的材料且同時形成。在一些其他實施例中，第一接合金屬層118及120可使用不同的材料且依次形成。第一接合金屬層118及120可藉由下述方式形成：在第一接合介電層116中的溝渠及通孔開口(圖中未示出)中沉積導電材料，然後藉由平坦化製程(例如化學機械拋光製程)移除第一接合介電層116的頂表面之上的導電材料。在平坦化製程之後，第一接合介電層116的頂表面與第一接合金屬層118及120的頂表面實質上共面。
參照圖1A，第二晶粒200與第二晶粒100類似。即，第 二晶粒200包括第二半導體基底202、第二元件層203、第二內連結構204、第二絕緣材料206及第二鈍化層210。第二晶粒200的配置、材料及形成方法與第一晶粒100的配置、材料及形成方法類似。因此，這裡省略其細節。在一些實施例中，第二晶粒200的尺寸小於第一晶粒的100的尺寸。本文中，用語「尺寸(size)」是指長度、寬度或面積。舉例來說，如圖1A所示，第二晶粒200的長度小於第一晶粒100的長度。
在一些實施例中，第一晶粒100及第二晶粒200中的一者可以是例如特殊應用積體電路(application-specific integrated circuit，ASIC)晶片、類比晶片、感測器晶片、無線及射頻晶片、調壓器晶片或記憶體晶片。在一些替代實施例中，第一晶粒100及第二晶粒200可包括相同的功能或不同的功能。圖1A所示的晶粒堆疊結構10是晶圓上晶片(chip-on-wafer，CoW)結構。舉例來說，第二晶粒200可以是晶粒(die)，第一晶粒100可以是晶圓(wafer)，且晶粒200設置在晶圓100之上。然而，本發明的實施例並不僅限於此。在其他實施例中，晶粒堆疊結構10包括晶片上晶片結構(chip-on-chip structure)、晶粒上晶粒結構(die-on-die structure)或它們的組合。
參照圖1A，在第二晶粒200的前側200a之上形成第二接合結構214。詳細來說，第二接合結構214包括第二接合介電層216及第二接合金屬層218。在一些實施例中，第二接合金屬層218形成在第二接合介電層216中。第二接合金屬層218包括通孔插 塞218a及金屬特徵218b。如圖1A所示，通孔插塞218a貫穿第二鈍化層210且與第二內連結構204的第二金屬特徵208連接。金屬特徵218b藉由通孔插塞218a電連接到第二金屬特徵208。
在一些實施例中，第二接合金屬層218可包括銅、銅合金、鎳、鋁、鎢、它們的組合。第二接合金屬層218可藉由下述方式形成：在第二接合介電層216中的溝渠及通孔開口(圖中未示出)中沉積導電材料，然後藉由平坦化製程(例如化學機械拋光製程)移除第二接合介電層216的頂表面之上的導電材料。在平坦化製程之後，第二接合介電層216的頂表面與第二接合金屬層218的頂表面實質上共面。
參照圖1A，將第二晶粒200進一步上下顛倒且安裝到第一晶粒100上。詳細來說，第一晶粒100與第二晶粒200藉由第一接合結構114及第二接合結構214面對面(face-to-face)接合在一起。在一些實施例中，在將第二晶粒200接合到第一晶粒100之前，將第一接合結構114與第二接合結構214對齊，以使第二接合金屬層218可接合到第一接合金屬層118，且第一接合介電層116可接合到第二接合介電層216。在一些實施例中，第一接合結構114與第二接合結構214的對齊可藉由使用光學感測方法來實現。在實現對齊之後，第一接合結構114與第二接合結構214藉由混合接合法(hybrid bonding)接合在一起，以形成混合接合結構250。
第一接合結構114與第二接合結構214藉由施加壓力及 熱而混合接合在一起。應注意，混合接合法有關於至少兩種類型的接合法，包括金屬對金屬接合法及非金屬對非金屬接合法(例如介電質對介電質接合法或熔融接合法)。如圖1A所示，混合接合結構250包括藉由金屬對金屬接合法接合在一起的第一接合金屬層118與第二接合金屬層218以及藉由非金屬對非金屬接合法接合在一起的第一接合介電層116與第二接合介電層216。然而，本發明的實施例並不僅限於此。在其他實施例中，第一接合結構114與第二接合結構214可藉由其他接合法(例如熔融接合法(fusion bonding))接合在一起。
另外，如圖1A所示，第二晶粒200還包括多個基底穿孔(through-substrate vias，TSV)205。在一些實施例中，基底穿孔205形成在第二半導體基底202中以電連接到第二內連結構204。在一些實施例中，基底穿孔205中的一者包括導電通孔及環繞導電通孔的側壁及底表面的襯層(圖中未示出)。導電通孔可包括銅、銅合金、鋁、鋁合金、Ta、TaN、Ti、TiN、CoW或它們的組合。襯層可包括介電材料，例如氧化矽。在一些實施例中，基底穿孔205在開始時不會穿透過第二半導體基底202，且基底穿孔205的底表面仍然被第二半導體基底202覆蓋。在後續的製程中，對第二半導體基底202的後表面202b進行薄化製程，以暴露出基底穿孔205的頂表面205s，且基底穿孔205可連接到其他元件。在一些實施例中，薄化製程可包括研磨製程或化學機械拋光(CMP)製程。
在進行薄化製程之後，第二半導體基底202的後表面202b低於基底穿孔205的頂表面205s，以確保基底穿孔205能夠連接到待形成的金屬電路結構400(如圖1E所示)。在暴露出基底穿孔205的頂表面205s之後，在第二晶粒200之上形成氮化物層220(例如，氮化矽層)。氮化物層220共形地覆蓋被第二半導體基底202暴露出的基底穿孔205的表面、第二半導體基底202的後表面202b、第二晶粒200的側壁及未接合到第二接合結構214的第一接合結構114的頂表面。氧化物層222(例如，氧化矽層)共形地形成在氮化物層220之上。氮化物層224(例如，氮化矽層)共形地形成在氧化物層222之上。介電層226(例如，間隙填充介電層(gap-fill dielectric layer))形成在第一晶粒100之上且包封第二晶粒200。即，介電層226覆蓋第二晶粒200的側壁及第二半導體基底202的底表面202a。在一些實施例中，介電層226可包括氧化物(例如氧化矽)、氮化物(例如氮化矽)、氮氧化物(例如氮氧化矽)、模塑化合物、模塑底部填充膠(molding underfill)、樹脂(例如環氧樹脂)、它們的組合等。
然後進行平坦化製程(或稱為第一平坦化製程)。在一些實施例中，平坦化製程是化學機械拋光製程。在進行平坦製程之後，移除過量的介電層226、過量的氮化物層224、過量的氧化物層222及過量的氮化物層220，以暴露出基底穿孔205的頂表面205s及剩餘氧化物層222的頂表面222t，如圖1A所示。剩餘氧化物層222在側向上包封基底穿孔205的一部分。剩餘介電層226 則在側向上包封第二晶粒200，以分隔第二晶粒200與接合在第一晶粒100之上的另一晶粒(圖中未示出)。在進行平坦化製程之後，完成晶粒堆疊結構10。在這種情況下，剩餘氧化物層222的頂表面222t可稱為第二晶粒200的後側200b。在進行平坦化製程之後，第二晶粒200的後側200b、基底穿孔205的頂表面205s及剩餘介電層226的頂表面226t處於實質上相同的水平高度。本文中，當元件被闡述為「處於實質上相同的水平高度(at substantially the same level)」時，這些元件是在相同的層中形成實質上相同的高度，或者嵌置在相同的層中的相同的位置。在一些實施例中，處於實質上相同的水平高度的元件是使用相同的製程步驟且由相同的材料形成。在一些實施例中，處於實質上相同的水平高度的元件的頂部實質上共面。舉例來說，如圖1A所示，第二晶粒200的後側200b、基底穿孔205的頂表面205s以及剩餘介電層226的頂表面226t實質上共面。
應注意，在進行平坦化製程(或稱為第一平坦化製程)或薄化製程之後，在第二晶粒200的後側200b中形成凹槽R1。凹槽R1可以是各種缺陷，例如裂縫(cracks)、尖銳形態(sharp morphology)、隆起(bulge)等。形成凹槽R1是因為一些不期望的顆粒可能會落在待研磨表面上，然後進行平坦化製程或薄化製程會損壞第二晶粒200的後側200b。如圖1A所示，凹槽R1沿著從第二晶粒200的後側200b朝混合接合結構250的方向D1延伸。凹槽R1使第二晶粒200的基底穿孔205b凹陷，以使得基底穿孔 205b的頂表面205s’低於基底穿孔205a的頂表面205s。另外，基底穿孔205b的頂表面205s’具有不平坦表面或尖銳形態。相比之下，沒有受到缺陷的損壞的基底穿孔205a的頂表面205s具有光滑的表面或平整的表面。
參照圖1B，在進行平坦化製程之後，在晶粒堆疊結構10之上形成共形層305。共形層305共形地覆蓋第二晶粒200的後側200b、基底穿孔205的頂表面205s及剩餘介電層226的頂表面226t。另外，共形層305也共形地且完全地覆蓋凹槽R1的表面(或基底穿孔205b的頂表面205s’)，以防止在後續的圖案化期間出現電漿體蝕刻電弧放電(plasma etching arcing)。在一些實施例中，當檢測到凹槽R1時，可形成共形層305來覆蓋凹槽R1的表面。在一些替代實施例中，當凹槽R1太輕微而不能被檢測到時，仍可形成共形層305來覆蓋凹槽R1的表面。共形層305藉由例如原子層沉積(atomic layer deposition，ALD)製程形成。在一些實施例中，共形層305可包括氧化矽、氮化矽、氮氧化矽或它們的組合。在替代實施例中，共形層305可以是單層結構、雙層結構或多層結構。在其他實施例中，共形層305的厚度為500Å到3500Å。在本文中，所謂共形層可視為具有均勻厚度的層，且所述層具有小於50Å(舉例來說，30Å~50Å)的厚度差。
另外，在一些實施例中，在形成共形層305之前，在第二晶粒200上形成氮化物層304(例如，氮化矽層)。在一些實施例中，氮化物層304藉由合適的沉積製程(例如化學氣相沉積製 程或原子層沉積製程)形成，且氮化物層304的厚度為300Å到1000Å。在替代實施例中，共形層305的厚度大於氮化物層304的厚度。在其他實施例中，氮化物層304與共形層305包括相同的材料或不同的材料。
參照圖1C，進行化學氣相沉積製程以在共形層305之上形成填充層306。在一些實施例中，填充層306可包括氧化矽、氮化矽、氮氧化矽、或它們的組合。在其他實施例中，填充層306的厚度為5KÅ到30KÅ。由於共形層305具有比填充層306更好的階梯覆蓋性(step coverage)，因此共形層305能夠完全覆蓋具有尖銳形態的凹槽R1的表面。在一些實施例中，共形層305與填充層306具有相同的材料或不同的材料。在一些替代實施例中，填充層306的厚度大於或等於共形層305的厚度。然而，本發明的實施例並不僅限於此。
在形成填充層306之後，在填充層306之上形成罩幕圖案307。在一些實施例中，罩幕圖案307包括光阻且藉由合適的製程(例如旋塗及微影製程)形成。在形成罩幕圖案307之後，藉由使用罩幕圖案307作為蝕刻罩幕來進行蝕刻製程，以移除填充層306、共形層305、氮化物層304、介電層226、氮化物層224、氧化物層222及氮化物層220的一些部分，從而形成開口308。如圖1C所示，開口308暴露出第一接合金屬層120。在形成開口308之後，移除罩幕圖案307。
參照圖1C及圖1D，形成導電材料(圖中未示出)以填 充在開口308中，並使所述導電材料延伸以覆蓋填充層306。進行平坦化製程(或稱為第二平坦化製程)，以移除導電材料、填充層306、共形層305及氮化物層304的一些部分並暴露出基底穿孔205的頂表面205s。在進行平坦化製程之後，介電層穿孔(through dielectric via，TDV)310形成在介電層226中，且保護結構300形成在第二晶粒200的後側200b中，如圖1D所示。介電層穿孔310形成在介電層226中，以電連接到第一接合金屬層120及待形成的金屬電路結構400(如圖1E所示)。
參照圖1D，在一些實施例中，保護結構300包括填充在凹槽R1中的氮化物層304、共形層305及填充層306。共形層305形成在氮化物層304與填充層306之間。圖1D所示的保護結構300是三層結構，然而，本發明的實施例並不僅限於此。在其他實施例中，保護結構300可包括單層結構、雙層結構或多層(即，多於三層)結構。舉例來說，保護結構300可由僅共形層305製成，或僅氮化物層304與共形層305製成，或僅共形層305與填充層306製成。在進行平坦化製程之後，保護結構300的頂表面300t、第二晶粒200的後側200b、基底穿孔205的頂表面205s、介電層226的頂表面226t與介電層穿孔310的頂表面310t實質上共面。儘管圖1D中僅示出一個介電層穿孔310，但可形成多於一個介電層穿孔310。
參照圖1E，以後段(back-end-of-line，BEOL)製程在第二晶粒200的後側200b之上形成金屬電路結構400。在形成金屬 電路結構400之後，三維積體電路結構1便已形成。詳細來說，在第二晶粒200的後側200b及介電層226的頂表面226t之上形成介電層402。藉由圖案化製程及合適的沉積製程(例如鍍覆製程)在介電層402中形成金屬特徵404。金屬特徵404電連接到未被保護結構300覆蓋的介電層穿孔310及基底穿孔205a。在一些實施例中，介電層402包括氧化矽、氮氧化矽、氮化矽、低介電常數(低k)材料或它們的組合。在一些替代實施例中，介電層402可以是單層或多層。在一些實施例中，金屬特徵404包括插塞及金屬線。插塞形成在兩條金屬線之間且與所述兩條金屬線連接。金屬特徵404可由鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或它們的組合製成。
在形成金屬特徵404之後，形成鈍化層406以覆蓋介電層402並暴露出金屬特徵404的一部分。在一些實施例中，鈍化層406包括氧化矽、氮化矽、苯並環丁烯(BCB)聚合物、聚醯亞胺(PI)、聚苯並惡唑(PBO)或它們的組合且藉由合適的製程(例如旋塗、化學氣相沉積等)形成。在鈍化層406之上形成接合墊408，且接合墊408延伸以覆蓋金屬特徵404。接合墊408的材料不同於第一金屬特徵404的材料。在一些實施例中，接合墊408的材料比第一金屬特徵404的材料軟。在一些實施例中，接合墊408包括金屬材料，例如鋁、銅、鎳、金、銀、鎢或它們的組合。接合墊408可藉由下述方式形成：藉由合適的製程(例如電化學鍍覆製程、化學氣相沉積、原子層沉積(ALD)、物理氣相沉 積等)來沉積金屬材料層，然後圖案化金屬材料層。
應注意，填充在凹槽R1中的保護結構300設置在第二晶粒200的基底穿孔205b與金屬電路結構400的金屬特徵404之間，以分隔或電隔離第二晶粒200的基底穿孔205b與金屬電路結構400的金屬特徵404。如圖1E所示，保護結構300完全覆蓋第二晶粒200的基底穿孔205b，因此，在金屬電路結構400的圖案化製程期間，具有尖銳形態的基底穿孔205b不會引起電漿體蝕刻電弧放電。也就是說，三維積體電路結構1的可靠性及良率相應地得到改善。另一方面，儘管基底穿孔205b與金屬電路結構400電隔離，但位於基底穿孔205b下方的第二元件層203的訊號還是能夠藉由其他基底穿孔(例如，基底穿孔205a)傳送到金屬電路結構400。儘管圖1E中僅示出兩個基底穿孔205a及205b，但可形成多於兩個基底穿孔205a及205b。也就是說，多於一個保護結構300完全覆蓋多於一個基底穿孔205b。
圖2是根據第二實施例的三維積體電路結構的剖視圖。
參照圖2，第二實施例的三維積體電路結構2與圖1E所示第一實施例的三維積體電路結構1類似。它們之間的不同之處在於，三維積體電路結構2的保護結構300的數目是多個。保護結構300包括保護結構301及302。如圖2所示，保護結構301及302形成在第二半導體基底202之上且都沿著從第二晶粒200的後側200b朝混合接合結構250的方向D1延伸。保護結構301覆蓋第二晶粒200的基底穿孔205b，而保護結構302不覆蓋第二 晶粒200的任何基底穿孔205(包括基底穿孔205a及205b)。具體來說，藉由平坦化製程或薄化製程得到的凹槽R2可形成在沒有形成任何基底穿孔205的區域中。共形層305沉積在凹槽R1及R2二者中以同時形成保護結構301及302。儘管圖1E僅示出兩個保護結構301及302，但可形成多於兩個保護結構301及302。
圖3是根據第三實施例的三維積體電路結構的剖視圖。
參照圖3，第三實施例的三維積體電路結構3與圖1E所示第一實施例的三維積體電路結構1類似。它們之間的不同之處在於，三維積體電路結構3包括從第二晶粒200的後側200b延伸到混合接合結構250中的保護結構303。在進行平坦化製程或薄化製程之後，形成凹槽R3。凹槽R3是深的且具有尖銳形態，因此共形層305能夠完全覆蓋凹槽R3及凹槽R1的不平坦及尖銳的表面以防止在金屬電路結構400的圖案化製程期間出現電漿體蝕刻電弧放電。在一些實施例中，保護結構303從第二晶粒200的後側200b延伸到位於第一晶粒100的第一接合結構114與第二晶粒200的第二接合結構214之間的界面15。
圖4是根據一些實施例的封裝體的剖視圖。
參照圖4，三維積體電路結構4藉由黏合劑層21安裝在介電層11之上。在一些實施例中，三維積體電路結構4可以是上述三維積體電路結構1、2及3中的一者。三維積體電路結構4包括在第一晶粒100之上平行地排列的多個第二晶粒201a及201b。第二晶粒201a及201b與第一晶粒100面對面接合在一起。第二 晶粒201a及201b的數目在本公開中不受限制。
在本實施例中，三維積體電路結構4還包括多個連接件18及鈍化層19。連接件18形成在未被鈍化層410覆蓋的接合墊408之上且電連接到未被鈍化層410覆蓋的接合墊408。出於清楚的目的，圖4中未示出接合墊408下方的其他元件，例如圖1E所示的介電層402及金屬特徵404。連接件18包括焊料凸塊、金凸塊、銅凸塊、銅柱、銅支柱等。鈍化層19形成在鈍化層410之上及連接件18旁，以覆蓋連接件18的側壁。
參照圖4，在三維積體電路結構4旁形成絕緣包封體22，以包封三維積體電路結構4。在絕緣包封體22中形成多個導電柱14，且所述多個導電柱14環繞三維積體電路結構4。在三維積體電路結構4及導電柱14之上形成重佈線層(redistribution layer，RDL)結構23，且所述重佈線層結構23電連接到三維積體電路結構4及導電柱14。在一些實施例中，重佈線層結構23包括交替堆疊的多個聚合物層PM1、PM2、PM3及PM4和多個重佈線層RDL1、RDL2、RDL3及RDL4。聚合物層或重佈線層的數目不受本公開的限制。
換句話說，重佈線層RDL1貫穿聚合物層PM1且電連接到三維積體電路結構4的連接件18及導電柱14。重佈線層RDL2貫穿聚合物層PM2且電連接到重佈線層RDL1。重佈線層RDL3貫穿聚合物層PM3且電連接到重佈線層RDL2。重佈線層RDL4貫穿聚合物層PM4且電連接到重佈線層RDL3。在一些實施例中， 聚合物層PM1、PM2、PM3及PM4中的每一者包括感光性材料，例如聚苯並惡唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(PCB)、它們的組合等。在一些實施例中，重佈線層RLD1、RDL2、RDL3及RDL4中的每一者包括導電材料。導電材料包括金屬(例如銅、鎳、鈦、它們的組合等)，且藉由電鍍製程形成。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包括晶種層(圖中未示出)及形成在晶種層上的金屬層(圖中未示出)。晶種層可以是金屬晶種層，例如銅晶種層。在一些實施例中，晶種層包括第一金屬層(例如鈦層)及位於第一金屬層之上的第二金屬層(例如銅層)。金屬層可以是銅或其他合適的金屬。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包括彼此連接的多個通孔及多條跡線。通孔連接跡線，且跡線分別位於聚合物層PM1、PM2、PM3及PM4上，且分別在聚合物層PM1、PM2、PM3及PM4的頂表面上延伸。
在一些實施例中，最頂部的重佈線層RDL4包括RDL4a及RDL4b。重佈線層RDL4a也被稱為用於球安裝的球下金屬(under-ball metallurgy，UBM)層。重佈線層RDL4b可以是用於連接到在後續製程中形成的整合被動元件(integrated passive device，IPD)26的微凸塊。
然後，在重佈線層結構23的重佈線層RDL4a之上形成多個連接件24，且所述多個連接件24電連接到重佈線層結構23的重佈線層RDL4a。在一些實施例中，連接件24由具有低電阻率 的導電材料(例如Sn、Pb、Ag、Cu、Ni、Bi或它們的合金)製成，且藉由合適的製程(例如蒸鍍、鍍覆、球滴或絲網印刷)形成。整合被動元件26形成在重佈線層結構23的重佈線層RDL4b之上且藉由焊料凸塊28電連接到重佈線層結構23的重佈線層RDL4b。整合被動元件26可以是電容器、電阻器、電感器等、或它們的組合。整合被動元件26的數目並不僅限於圖4所示的數目，而是可根據產品的設計進行調整。底部填充膠層27形成在整合被動元件26與聚合物層PM4之間，且環繞並覆蓋暴露出的RDL4b、焊料凸塊28及整合被動元件26的底表面。
如圖4所示，然後將介電層11圖案化，使得導電柱14的底表面被介電層11暴露出。在導電端子30分別形成在導電柱14的底表面之上之後，具有雙側端子的整合扇出型封裝體P1便已完成。然後提供另一封裝體P2。在一些實施例中，封裝體P2是例如記憶體元件。封裝體P2堆疊在整合扇出型封裝體P1之上且藉由導電端子30電連接到整合扇出型封裝體P1，從而製成疊層封裝體(PoP)結構。
根據一些實施例，一種三維積體電路(3DIC)結構包括晶粒堆疊結構、金屬電路結構及第一保護結構。所述第一晶粒具有前側及後側，且第二晶粒具有前側及後側。所述第一晶粒的所述前側接合到所述第二晶粒的所述前側。所述第二晶粒包括多個基底穿孔(TSV)。所述金屬電路結構設置在所述第二晶粒的所述後側之上。所述保護結構設置在所述第二晶粒的所述後側內且分 隔所述多個基底穿孔中的一者與所述金屬電路結構。
在一些實施例中，所述第一保護結構的頂表面與所述第二晶粒的所述後側實質上共面。
在一些實施例中，所述第一保護結構包括共形層或複合結構，所述複合結構包括共形層及設置在所述共形層之上的填充層。
在一些實施例中，所述共形層及所述填充層是由不同的材料形成。
在一些實施例中，所述晶粒堆疊結構還包括設置在所述第一晶粒與所述第二晶粒之間的混合接合結構。
在一些實施例中，所述三維積體電路結構還包括設置在所述第二晶粒的所述後側內的第二保護結構，其中所述第一保護結構直接接觸所述多個基底穿孔中的一者，而所述第二保護結構與所述多個基底穿孔間隔開。
在一些實施例中，所述第一保護結構從所述第二晶粒的所述後側延伸到所述混合接合結構內。
在一些實施例中，所述多個基底穿孔中的另一者電連接到所述金屬電路結構，且所述第二晶粒的所述多個基底穿孔中的所述一者的頂表面低於所述第二晶粒的所述多個基底穿孔中的所述另一者的頂表面。
在一些實施例中，所述三維積體電路結構還包括：介電層以及介電層穿孔(TDV)。介電層在側向上包封所述第二晶粒。 介電層穿孔設置在所述介電層中且電連接到所述第一晶粒及所述金屬電路結構。
在一些實施例中，所述介電層的頂表面、所述介電層穿孔的頂表面、所述第一保護結構的所述頂表面及所述第二晶粒的所述後側實質上共面。
在一些實施例中，所述晶粒堆疊結構包括晶圓上晶片(CoW)結構、晶片上晶片結構、晶粒上晶粒結構或它們的組合。
根據一些實施例，一種製造三維積體電路結構的方法包括以下步驟。形成包括面對面接合在一起的第一晶粒與第二晶粒的晶粒堆疊結構。進行第一平坦化製程以在所述第二晶粒的後側暴露出所述第二晶粒的多個基底穿孔(TSV)。所述第二晶粒具有延伸到所述第二晶粒的所述多個基底穿孔中的一者中的凹槽。以共形層的方式將保護結構填入所述第一凹槽中。在所述第二晶粒的所述後側之上形成金屬電路結構，以藉由所述多個基底穿孔中的另一者電連接到所述晶粒堆疊結構。
在一些實施例中，所述將所述保護結構填入所述第一凹槽中包括：進行原子層沉積(ALD)製程以在所述第二晶粒的所述後側上形成所述共形層，其中所述共形層完全覆蓋所述第一凹槽的表面；進行化學氣相沉積(CVD)製程以在所述共形層之上形成填充層；以及進行第二平坦化製程，以暴露出所述第二晶粒的所述多個基底穿孔中的所述另一者。
在一些實施例中，所述形成所述晶粒堆疊結構包括：提 供所述第一晶粒及所述第二晶粒；以及在所述第一晶粒與所述第二晶粒之間形成混合接合結構，以接合所述第一晶粒與所述第二晶粒。
在一些實施例中，在進行所述第一平坦化製程之後所述第二晶粒的所述後側包括第二凹槽，所述第一凹槽及所述第二凹槽沿著從所述第二晶粒的所述後側朝所述混合接合結構的方向延伸，且所述第二凹槽與所述第二晶粒的所述多個基底穿孔間隔開。
在一些實施例中，在進行所述第一平坦化製程後，所述第一凹槽從所述第二晶粒的所述後側延伸到所述混合接合結構中。
在一些實施例中，在進行所述第一平坦化製程後，所述第二晶粒的所述多個基底穿孔中的所述一者的頂表面低於所述第二晶粒的所述多個基底穿孔中的所述另一者的頂表面。
在一些實施例中，在進行所述第二平坦化製程後，所述保護結構的頂表面與所述第二晶粒的所述後側實質上共面。
根據一些實施例，一種封裝體包括三維積體電路結構、絕緣包封體、重佈線層(RDL)結構及多個連接件。所述三維積體電路結構包括晶粒堆疊結構、金屬電路結構及位於所述晶粒堆疊結構與所述金屬電路結構之間的保護結構。所述金屬電路結構藉由所述晶粒堆疊結構的多個基底穿孔(TSV)中的一者電連接到所述晶粒堆疊結構。所述保護結構分隔及電隔離所述晶粒堆疊結構的基底穿孔中的另一者與所述金屬電路結構。所述絕緣包封體 在側向上包封所述三維積體電路結構。所述重佈線層結構設置在所述三維積體電路結構及所述絕緣包封體之上。所述多個連接件設置在所述三維積體電路結構之上且藉由所述重佈線層結構電連接到所述三維積體電路結構。
在一些實施例中，所述晶粒堆疊結構包括第一晶粒及在所述第一晶粒之上平行地排列的多個第二晶粒。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
1:三維積體電路結構
10:晶粒堆疊結構
100:第一晶粒
114:第一接合結構
200:第二晶粒
200b:第二晶粒的後側
205、205a、205b:基底穿孔
214:第二接合結構
226、402:介電層
226t:頂表面
250:混合接合結構
300:保護結構
310:介電層穿孔
400:金屬電路結構
404:金屬特徵
406:鈍化層
408:接合墊
R1:凹槽

Claims (10)

  1. 一種三維積體電路結構，包括：晶粒堆疊結構，包括第一晶粒及第二晶粒，所述第一晶粒具有前側及後側，所述第二晶粒具有前側及後側，所述第一晶粒的所述前側接合到所述第二晶粒的所述前側，所述第二晶粒包括多個基底穿孔；金屬電路結構，設置在所述第二晶粒的所述後側之上；以及第一保護結構，設置在所述第二晶粒的所述後側內且分隔所述第二晶粒的所述多個基底穿孔中的一者與所述金屬電路結構。
  2. 如請求項1所述的三維積體電路結構，其中所述第一保護結構的頂表面與所述第二晶粒的所述後側實質上共面。
  3. 一種製造三維積體電路結構的方法，包括：形成晶粒堆疊結構，所述晶粒堆疊結構包括面對面接合在一起的第一晶粒與第二晶粒；進行第一平坦化製程，以在所述第二晶粒的後側暴露出所述第二晶粒的多個基底穿孔(TSV)，其中所述第二晶粒的所述後側具有第一凹槽，所述第一凹槽延伸到所述第二晶粒的所述多個基底穿孔中的一者中；以共形層的方式將保護結構填入所述第一凹槽中；以及在所述第二晶粒的所述後側之上形成金屬電路結構，以藉由所述多個基底穿孔中的另一者電連接到所述晶粒堆疊結構，其中所述保護結構電隔離所述第二晶粒的所述多個基底穿孔中的所述 一者與所述金屬電路結構。
  4. 一種封裝體，包括：三維積體電路結構，包括晶粒堆疊結構、金屬電路結構及位於所述晶粒堆疊結構與所述金屬電路結構之間的保護結構，其中所述金屬電路結構藉由所述晶粒堆疊結構的多個基底穿孔(TSV)中的一者電連接到所述晶粒堆疊結構，且所述保護結構分隔及電隔離所述晶粒堆疊結構的所述多個基底穿孔中的另一者與所述金屬電路結構；絕緣包封體，在側向上包封所述三維積體電路結構；重佈線層(RDL)結構，設置在所述三維積體電路結構及所述絕緣包封體之上；以及多個連接件，設置在所述三維積體電路結構之上且藉由所述重佈線層結構電連接到所述三維積體電路結構。
  5. 一種三維積體電路結構，包括：晶粒堆疊結構，包括接合在一起的第一晶粒及第二晶粒，所述第二晶粒包括多個基底穿孔；金屬電路結構，設置在所述第二晶粒的後側之上；以及第一保護結構，夾置在所述金屬電路結構的底表面與所述第二晶粒的所述多個基底穿孔中的一者的頂表面之間且接觸所述金屬電路結構的所述底表面與所述第二晶粒的所述多個基底穿孔中的所述一者的所述頂表面，其中所述第一保護結構內埋在所述第二晶粒的所述後側內，且分隔及電隔離所述第二晶粒的所述多個 基底穿孔中的所述一者與所述金屬電路結構。
  6. 一種製造三維積體電路結構的方法，包括：形成晶粒堆疊結構，所述晶粒堆疊結構包括面對面接合在一起的第一晶粒與第二晶粒；進行第一平坦化製程，以在所述第二晶粒的後側暴露出所述第二晶粒的多個基底穿孔，其中所述第二晶粒的所述後側具有第一凹槽，所述第一凹槽延伸到所述第二晶粒的所述多個基底穿孔中的一者中；將保護結構填入所述第一凹槽中；以及進行第二平坦化製程，以暴露出所述第二晶粒的所述多個基底穿孔中的另一者並在所述第一凹槽中形成保護結構，其中所述保護結構的頂表面與所述多個基底穿孔中的所述另一者的頂表面實質上共面。
  7. 一種三維積體電路結構，包括：晶粒堆疊結構，包括接合在一起的第一晶粒及第二晶粒，所述第二晶粒具有多個基底穿孔；金屬電路結構，設置在所述第二晶粒的頂表面之上；以及電隔離結構，內埋在第二晶粒的所述頂表面內，且電隔離所述第二晶粒的所述多個基底穿孔中的一者與所述金屬電路結構。
  8. 一種半導體封裝結構，包括：第一晶粒，具有第一接合結構於其上；第二晶粒，具有第二接合結構於其上，其中所述第二晶粒接 合至所述第一晶粒，以使所述第一接合結構的第一接合介電層接觸所述第二接合結構的第二接合介電層；金屬電路結構，設置在所述第二晶粒的頂表面之上；以及第一保護結構，內埋在所述第二晶粒的所述頂表面內，且夾置在所述金屬電路結構與所述第二晶粒之間。
  9. 一種製造半導體封裝結構的方法，包括：在第一晶粒上形成第一接合結構；在第二晶粒上形成第二接合結構；藉由將所述第一接合結構的第一接合介電層接觸所述第二接合結構的第二接合介電層的方式將所述第二晶粒接合在所述第一晶粒上；對所述第二晶粒的頂表面進行第一平坦化製程，以在所述第二晶粒的所述頂表面內形成第一凹槽；在所述第一凹槽中形成第一保護結構；以及在所述第二晶粒的所述頂表面與第一保護結構之上形成金屬電路結構，其中所述第一保護結構夾置在所述金屬電路結構與所述第二晶粒之間。
  10. 一種封裝體，包括：第一晶片；第二晶片，具有包括多個基底穿孔且接合在所述第一晶片上；間隙填充介电层，配置在所述第一晶片上且在側向上包封所述第二晶片； 金屬電路結構，設置在所述第二晶片的頂表面之上；以及電隔離結構，內埋在第二晶片的所述頂表面內，且電隔離所述第二晶片的所述多個基底穿孔中的一者與所述金屬電路結構。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11355404B2 (en) * 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11239225B2 (en) * 2019-07-17 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structures and methods of manufacturing the same
US11264343B2 (en) * 2019-08-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for semiconductor device and method of forming same
US12112981B2 (en) * 2020-04-27 2024-10-08 United Microelectronics Corp. Semiconductor device and method for fabricating semiconductor device
US11715755B2 (en) 2020-06-15 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for forming integrated high density MIM capacitor
US11658158B2 (en) 2020-09-03 2023-05-23 Taiwan Semiconductor Manufacturing Company Ltd. Die to die interface circuit
US11817392B2 (en) * 2020-09-28 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
US11862609B2 (en) * 2021-03-18 2024-01-02 Taiwan Semiconductor Manufacturing Company Limited Semiconductor die including fuse structure and methods for forming the same
US11676943B2 (en) * 2021-04-23 2023-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US20220352046A1 (en) * 2021-04-28 2022-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same
KR20230006731A (ko) * 2021-07-02 2023-01-11 삼성전자주식회사 반도체 패키지
CN117673003A (zh) * 2022-08-24 2024-03-08 达尔科技股份有限公司 电子组件封装件及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016010841A1 (en) * 2014-07-14 2016-01-21 Qualcomm Incorporated Air gap between tungsten metal lines for interconnects with reduced rc delay
TW201633366A (zh) * 2014-09-26 2016-09-16 高通公司 用於三維積體電路整合之晶圓轉移之微機電系統接合釋放結構及方法
TW201733068A (zh) * 2015-11-30 2017-09-16 台灣積體電路製造股份有限公司 三層式基板上覆晶圓上覆晶片結構
US20170358562A1 (en) * 2016-05-18 2017-12-14 Globalfoundries Inc. INTEGRATED DISPLAY SYSTEM WITH MULTI-COLOR LIGHT EMITTING DIODES (LEDs)
US20180033773A1 (en) * 2016-07-29 2018-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4248928B2 (ja) * 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
US6940181B2 (en) * 2003-10-21 2005-09-06 Micron Technology, Inc. Thinned, strengthened semiconductor substrates and packages including same
US8049310B2 (en) * 2008-04-01 2011-11-01 Qimonda Ag Semiconductor device with an interconnect element and method for manufacture
US8368228B2 (en) * 2009-10-19 2013-02-05 Jeng-Jye Shau Area efficient through-hole connections
US8232137B2 (en) * 2009-12-10 2012-07-31 Intersil Americas Inc. Heat conduction for chip stacks and 3-D circuits
US20110198609A1 (en) * 2010-02-12 2011-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Light-Emitting Devices with Through-Substrate Via Connections
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
KR101096042B1 (ko) * 2010-03-18 2011-12-19 주식회사 하이닉스반도체 반도체 패키지 및 그 제조방법
KR101677507B1 (ko) * 2010-09-07 2016-11-21 삼성전자주식회사 반도체 장치의 제조 방법
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9059097B2 (en) * 2012-08-09 2015-06-16 International Business Machines Corporation Inhibiting propagation of imperfections in semiconductor devices
KR101972969B1 (ko) * 2012-08-20 2019-04-29 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
WO2014181766A1 (ja) * 2013-05-07 2014-11-13 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及び半導体装置の製造方法
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9653341B2 (en) * 2014-03-05 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9252080B1 (en) * 2014-10-15 2016-02-02 Globalfoundries Inc. Dielectric cover for a through silicon via
US9869713B2 (en) * 2015-03-05 2018-01-16 Qualcomm Incorporated Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
KR20170011366A (ko) * 2015-07-22 2017-02-02 삼성전자주식회사 반도체 칩 및 이를 가지는 반도체 패키지
US9786839B2 (en) * 2015-07-23 2017-10-10 Globalfoundries Singapore Pte. Ltd. 3D MRAM with through silicon vias or through silicon trenches magnetic shielding
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9773737B2 (en) * 2015-11-23 2017-09-26 International Business Machines Corporation Advanced metallization for damage repair
CN107305861B (zh) * 2016-04-25 2019-09-03 晟碟信息科技（上海）有限公司 半导体装置及其制造方法
CA3063346A1 (en) * 2016-05-13 2017-11-16 MSI Coatings Inc. System and method for using a voc free low radiant flux led uv curable composition

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016010841A1 (en) * 2014-07-14 2016-01-21 Qualcomm Incorporated Air gap between tungsten metal lines for interconnects with reduced rc delay
TW201633366A (zh) * 2014-09-26 2016-09-16 高通公司 用於三維積體電路整合之晶圓轉移之微機電系統接合釋放結構及方法
TW201733068A (zh) * 2015-11-30 2017-09-16 台灣積體電路製造股份有限公司 三層式基板上覆晶圓上覆晶片結構
US20170358562A1 (en) * 2016-05-18 2017-12-14 Globalfoundries Inc. INTEGRATED DISPLAY SYSTEM WITH MULTI-COLOR LIGHT EMITTING DIODES (LEDs)
US20180033773A1 (en) * 2016-07-29 2018-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same

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US10867968B2 (en) 2020-12-15
US11532598B2 (en) 2022-12-20
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US20210074681A1 (en) 2021-03-11
US20200098731A1 (en) 2020-03-26

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