TW202238911A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW202238911A TW202238911A TW111103461A TW111103461A TW202238911A TW 202238911 A TW202238911 A TW 202238911A TW 111103461 A TW111103461 A TW 111103461A TW 111103461 A TW111103461 A TW 111103461A TW 202238911 A TW202238911 A TW 202238911A
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- connection
- stack
- stacked
- plane
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims description 35
- 239000002245 particle Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 74
- 230000008569 process Effects 0.000 description 26
- 239000010949 copper Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 18
- 239000000463 material Substances 0.000 description 16
- 238000007789 sealing Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- KAESVJOAVNADME-UHFFFAOYSA-N Pyrrole Chemical compound C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- -1 resin and filler Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/091—Disposition
- H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/09181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/091—Disposition
- H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/09183—On contiguous sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3018—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/30181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Combinations Of Printed Boards (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
一種半導體封裝包括第一連接晶粒和第一晶粒堆疊,第一連接晶粒包括半導體基板和互連結構,第一晶粒堆疊設置於第一連接晶粒上且包括多個堆疊式晶粒,各個堆疊式晶粒包括半導體基板和包括第一連接接線的互連結構,第一連接接線電性連接至第一連接晶粒的互連結構。形成於第一連接晶粒之平面與各個堆疊式晶粒之平面之間的角度範圍為約45°至約90°。
Description
無
歸因於例如電晶體、二極體、電阻器、電容器等各種電子元件之整合密度持續改進,半導體行業連續發展。通常而言,整合密度的改進來自最小特徵尺寸的連續減小,最小特徵尺寸的連續減小允許更多元件整合至給定區域中。
除了較小的電子元件外,對元件之封裝的改進試圖提供相較於先前封裝佔據較小面積的較小封裝。用於半導體之封裝類型的示例包括方型扁平封裝(quad flat pack,QFP)、插針網格陣列(pin grid array,PGA)、球形網格陣列(ball grid array,BGA)、倒裝晶片(flip chip,FC)、三維積體電路(three-dimensional integrated circuit,3DIC)、晶圓層級封裝(wafer level package,WLP)、層疊封裝(package on package,PoP)、晶片上系統(System on Chip,SoC)或積體電路上系統(System on Integrated Circuit,SoIC)裝置。藉由將晶片置放於半導體晶圓層級上的晶片上方來製備這些三維裝置中的一些裝置(例如,3DIC、SoC、SoIC)。這些三維裝置因為減少堆疊式晶片之間的互連長度而提供改良之整合密度和其他優勢,諸如更快速度和較高帶寬。然而,依然存在與三維裝置相關的許多挑戰。
無
為了實現提及主題的不同特徵,以下公開內容提供了許多不同的實施例或示例。以下描述組件、配置等的具體示例以簡化本公開。當然,這些僅僅是示例,而不是限制性的。例如,在以下的描述中,在第二特徵之上或上方形成第一特徵可以包括第一特徵和第二特徵以直接接觸形成的實施例,並且還可以包括在第一特徵和第二特徵之間形成附加特徵,使得第一特徵和第二特徵可以不直接接觸的實施例。另外,本公開可以在各種示例中重複參考數字和/或字母。此重複是為了簡單和清楚的目的,並且本身並不表示所討論的多種實施例和/或配置之間的關係。
此外,本文可以使用空間相對術語,諸如「在…下面」、「在…下方」、「下部」、「在…上面」、「上部」等,以便於描述一個元件或特徵與如圖所示的另一個元件或特徵的關係。除了圖中所示的取向之外,空間相對術語旨在包括使用或操作中的裝置的不同取向。裝置可以以其他方式定向(旋轉90度或在其他方向上),並且同樣可以相應地解釋在此使用的空間相對描述符號。除非以其他方式明確陳述,否則具有相同參考數字的每一部件假定為具有相同材料組成且具有在同一厚度範圍內的厚度。
習知半導體封裝可包括設置於第二晶粒上的晶粒堆疊。具體而言,晶粒堆疊可包括第一晶粒,其中第一晶粒在平行於第二晶粒之平面的平面中對準且在垂直方向上彼此堆疊。第一晶粒可包括矽穿孔(through-silicon via,TSV)結構以將第一晶粒電性連接至彼此。然而,在此組態中,非相鄰的第一晶粒不可直接電性連接。因此,可能隨著晶粒堆疊中之晶粒的數目增大而顯著增大晶粒至晶粒之電阻。
本公開是針對包括設置於第二晶粒上的晶粒堆疊的半導體封裝。具體而言,晶粒堆疊可包括垂直對準且水平堆疊的多個晶粒,晶粒可經由第二晶粒直接電性連接。因此,晶粒堆疊實施例的晶粒至晶粒電阻可顯著減小。
第1圖為根據本公開之多種實施例的晶粒100之垂直橫截面圖。參照第1圖,晶粒100可為例如特殊應用積體電路(application-specific integrated circuit,ASIC)晶片、類比晶片、感測器晶片、無線射頻晶片、電壓調節器晶片或記憶體晶片。在一些實施例中,晶粒100可為主動式元件或被動式元件。在一些實施例中,晶粒100包括平坦半導體基板102、介電結構104、嵌入於介電結構104內的互連結構110、密封環130和矽穿孔結構162。
在一些實施例中,半導體基板102可包括諸如矽或鍺之元素半導體,及/或諸如矽鍺、碳化矽、砷化鎵、砷化銦、氮化鎵或磷化銦的化合物半導體。在一些實施例中,半導體基板102可為絕緣體上半導體(semiconductor-on-insulator,SOI)基板。在多種實施例中,半導體基板102可採用平面基板、具有多個鰭片之基板、奈米導線或對於本領域技術人員已知之其他形式。取決於設計要求,半導體基板102可為P型基板或N型基板,且其中可具有摻雜區。摻雜區可配置成用於N型裝置或P型裝置。
在一些實施例中,半導體基板102包括界定至少一個主動區域的隔離結構,且裝置層可設置於主動區域上或主動區域中。裝置層可包括多種裝置。在一些實施例中,裝置可包括主動式元件、被動式元件或其組合。在一些實施例中,裝置可包括積體電路裝置。裝置可為例如電晶體、電容器、電阻器、二極體、光電二極體、熔斷裝置或其他類似裝置。在一些實施例中,裝置層包括閘極結構、源極/汲極區、間隔物和類似者。
介電結構104可設置於半導體基板102的前側上。在一些實施例中,介電結構104可包括氧化矽、氮氧化矽、氮化矽、低介電常數(low-k)材料或其組合。其他適合的介電材料可在本公開之預期範疇內。介電結構104可為單一層或多層介電結構。舉例而言,如第1圖中所繪示,介電結構104可包括多個介電層,其中介電結構104可包括基板氧化物層104A、層間介電質(inter-layer dielectric,ILD)層104B至層間介電質層104F以及鈍化層104G。然而,雖然第1圖繪示七個介電層,但本公開之多種實施例並未限於任何特定層數。可使用更多或更少介電層。
介電結構104可由任何合適沉積製程所形成。本文中,「合適沉積製程」可包括化學氣相沉積(chemical vapor deposition,CVD)製程、物理氣相沉積(physical vapor deposition,PVD)製程、原子層沉積(atomic layer deposition,ALD)製程、高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)製程、金屬有機物化學氣相沉積(metalorganic CVD,MOCVD)製程、電漿增強化學氣相沉積(plasma enhanced CVD,PECVD)製程、濺鍍製程、雷射剝蝕或類似者。
互連結構110可形成於介電結構104中。互連結構110可包括設置於介電結構104中的金屬特徵112。金屬特徵112可為任何多個金屬接線以及電性連接相鄰層間介電質層104B至層間介電質層104F的金屬接線的通孔結構。金屬特徵112可包括第一連接接線112A,第一連接接線112A可用於晶粒至晶粒連接電路中,如下文詳細地論述。金屬特徵112可視需要包括第二連接接線112B,第二連接接線112B可用於晶粒至晶粒連接電路中,如下文亦論述。
互連結構110可電性連接至設置於半導體基板102上的基板電極108,使得互連結構110可電性連接形成於半導體基板102上的半導體裝置。在一些實施例中,基板電極108可包括形成於半導體基板102之裝置層中的電晶體之金屬閘極。
互連結構110可由任何合適導電材料所形成,諸如銅(Cu)、銅合金、鋁(Al)、鋁合金、銀(Ag)、其組合或類似者。舉例而言,互連結構110可以較佳地包括銅,其中銅的原子百分比大於80%,諸如大於90%及/或大於95%,儘管可使用較大或較小百分比的銅。其他合適導電材料在本公開之預期範疇內。
在一些實施例中,阻障層(圖中未示出)可設置於金屬特徵112和介電結構104的介電層之間,以防止金屬特徵112的材料遷移至半導體基板102中。舉例而言,阻障層可包括Ta、TaN、Ti、TiN、CoW或其組合。其他合適阻障層材料可在本公開之預期範疇內。
密封環130可延伸圍繞晶粒100之周邊。換言之,密封環130可設置相鄰於晶粒100的側表面。舉例而言,密封環130可設置於介電結構104中,且可側向包圍互連結構110。密封環130可用於在裝置製程(諸如電漿蝕刻及/或沉積製程)期間保護互連結構110不受污染物擴散及/或物理損害影響。
密封環130可以包括銅,其中銅的原子百分比大於80%,諸如大於90%及/或大於95%,儘管可使用較大或較小百分比。用作密封環130的其他合適材料在本公開之預期範疇內。密封環130可包括連接至彼此的導電接線和通孔結構,且可與互連結構110之金屬特徵112同時形成。密封環130可與金屬特徵112電性隔離。密封環130可由與金屬特徵112相同或不同的材料所形成。
在一些實施例中,金屬特徵112及/或密封環130可由雙鑲嵌(dual-damascene)製程或由多個單鑲嵌製程形成。單鑲嵌製程通常在每個鑲嵌階段形成單一特徵且用銅填充單一特徵。雙鑲嵌製程通常一次形成兩個特徵且由銅填充兩個特徵,例如可使用雙鑲嵌製程的單次銅沉積來填充溝槽和重疊穿孔。在替代性實施例中,金屬特徵112及/或密封環130可由電鍍製程形成。
舉例而言,鑲嵌製程可包括圖案化介電結構104以形成開口,諸如溝槽及/或穿孔(例如,通孔)。可執行沉積製程以在開口中沉積導電金屬(例如,銅)。可接著執行諸如化學機械平坦化(chemical-mechanical planarization,CMP)的平坦化製程以移除沉積於介電結構104之頂部上的過量(例如,過載(overburden))銅。
具體而言,可針對層間介電質層104B至層間介電質層104F中的每一者執行圖案化、金屬沉積和平坦化製程,以便形成互連結構110及/或密封環130。舉例而言,層間介電質層104B可經沉積並圖案化以形成開口。可接著執行沉積製程以填充層間介電質層104B中的開口。可接著執行平坦化製程以移除過載銅,且在層間介電質層104B中形成金屬特徵112。這些製程步驟可經重複以形成層間介電質層104C至層間介電質層104F和對應的金屬特徵112,從而完成互連結構110及/或密封環130。
前側接合層50A可設置於介電結構104上方。前側接合層50A可由諸如環氧樹脂的介電接合層形成。前側接合襯墊52A可形成於前側接合層50A中。背側接合層50B可形成於半導體基板102的背側上。然而,在一些實施例中,依據堆疊內晶粒100的所欲位置,可省略背側接合層50B。背側接合襯墊52B可形成於背側接合層50B中。
前側接合層50A和背側接合層50B可藉由任何合適沉積方法來沉積接合材料所形成。合適接合材料可包括如上文所述之氧化矽或結合聚合物或類似者,諸如環氧樹脂、聚醯亞胺(polyimide,PI)、苯并環丁烯(benzocyclobutene,BCB)和聚苯并噁唑(polybenzoxazole,PBO)。其他合適接合材料可在本公開之預期範疇內。前側接合襯墊52A和背側接合襯墊52B可以是由與金屬特徵112相同之材料所形成的導電特徵。舉例而言,前側接合襯墊52A和背側接合襯墊52B可包括鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金、其組合或類似者。
介電封裝(dielectric encapsulation,DE)層40可形成於晶粒100的側表面上。介電封裝層40可由介電材料所形成,諸如氧化矽、氮化矽、包括樹脂和填充劑的封膠(molding)化合物或類似者。介電封裝層40可由任何合適沉積製程所形成,諸如旋塗、層壓、沉積或類似者。
矽穿孔結構162可設置於形成在半導體基板102中的溝槽中。矽穿孔結構162可電性連接至互連結構110和背側接合襯墊52B。矽穿孔結構162可由合適導電材料來形成,諸如銅(Cu)、銅合金、鋁(Al)、鋁合金、銀(Ag)、鎢(W)、其組合或類似者。舉例而言,矽穿孔結構162可以較佳地包括銅,其中銅的原子百分比大於80%,諸如大於90%及/或大於95%,儘管可使用較大或較小百分比的銅。用於矽穿孔結構162中的其他合適導電材料在本公開之預期範疇內。
在一些實施例中,阻障層可設置於矽穿孔結構162與半導體基板102和介電結構104之間。舉例而言,阻障層可包括Ta、TaN、Ti、TiN、CoW或其組合。其他合適阻障層材料可在本公開之預期範疇內。
第2A圖為根據本公開之多種實施例的半導體封裝10之簡化俯視圖。第2B圖為第2A圖之半導體封裝10之第一側的簡化視圖,且第2C圖為第2A圖之半導體封裝10之第二側的簡化視圖。
參照第1圖、第2A圖、第2B圖和第2C圖,半導體封裝10可包括第一晶粒堆疊20A、第二晶粒堆疊20B、第一連接晶粒200和介電封裝(dielectric encapsulation,DE)層40。然而,本公開不限於任何特定數目的晶粒堆疊。舉例而言,在一些實施例中,半導體封裝10可包括一個晶粒堆疊或者兩個以上晶粒堆疊。
如下文詳細地論述,第一連接晶粒200可包括平面半導體基板202和可以電性連接至第一晶粒堆疊20A的第一連接晶粒互連結構210。第一連接晶粒互連結構210亦可電性連接至第二晶粒堆疊20B。本文中,晶粒之「平面」可代指由晶粒之平面半導體基板所界定的平面。換言之,晶粒基板的平面界定晶粒的平面。因此,第一連接晶粒200的平面(亦即,半導體基板202的平面)可在第一水平方向H1和垂直於第一水平方向H1之第二水平方向H2上延伸。
第一晶粒堆疊20A和第二晶粒堆疊20B可各自包括多個堆疊式晶粒100,其中堆疊式晶粒100可堆疊並接合在一起。堆疊式晶粒100和第一連接晶粒200可獨立地選自特殊應用積體電路(application-specific integrated circuit,ASIC)晶片、類比晶片、感測器晶片、無線射頻晶片、電壓調節器晶片、記憶體晶片或類似者。在一些實施例中,堆疊式晶粒100可為靜態隨機存取記憶體(static random access memory,SRAM)晶片,且第一連接晶粒200可為SOC被動式裝置。
雖然第一晶粒堆疊20A和第二晶粒堆疊20B繪示為包括四個堆疊式晶粒100,但本公開不限於此。舉例而言,第一晶粒堆疊20A及/或第二晶粒堆疊20B可包括四個至二十個或者二十個以上的堆疊式晶粒100,諸如四個至十五個堆疊式晶粒100,或四個至十個堆疊式晶粒100。
可對準第一晶粒堆疊20A和第二晶粒堆疊20B,使得堆疊式晶粒100的堆疊方向垂直於第一水平方向H1和第二水平方向H2。換言之,各個第一晶粒堆疊20A和第二晶粒堆疊20B中的堆疊式晶粒100之平面可在垂直方向V上延伸,垂直方向V垂直於第一水平方向H1和第二水平方向H2。換言之,各個第一晶粒堆疊20A和第二晶粒堆疊20B中的堆疊式晶粒100之平面可垂直於第一連接晶粒200的平面。因此,形成於每一堆疊式晶粒100之平面與第一連接晶粒200之間的角度可為約90°。然而,在一些其他實施例中,形成於每一堆疊式晶粒100之平面與第一連接晶粒200之平面之間的角度範圍可為90°至45°。
如下文詳細地論述,第一連接晶粒200上的堆疊式晶粒100的定向允許堆疊式晶粒100經由連接電路直接電性連接至第一連接晶粒200,這些連接電路通過堆疊式晶粒100之側壁且通過第一連接晶粒200。具體而言,半導體封裝10可包括堆疊內連接電路114和堆疊間連接電路116,堆疊內連接電路114直接電性連接第一晶粒堆疊20A或第二晶粒堆疊20B之堆疊式晶粒100,堆疊間連接電路116直接電性連接第一晶粒堆疊20A之堆疊式晶粒100與第二晶粒堆疊20B的堆疊式晶粒100。
第3圖為繪示根據本公開之多種實施例形成半導體封裝之方法的步驟流程圖。第4A圖至第4G圖為繪示隨著第3圖之方法的步驟執行的中間結構橫截面圖。
參照第3圖和第4A圖,在步驟702中,第一晶粒堆疊20A可形成於第一載體60上。第一晶粒堆疊20A可包括多個堆疊式晶粒100,諸如堆疊式晶粒100A至堆疊式晶粒100D。例如,堆疊式晶粒100A至堆疊式晶粒100D可獨立地選自特殊應用積體電路(application-specific integrated circuit,ASIC)晶片、類比晶片、感測器晶片、無線射頻晶片、電壓調節器晶片、記憶體晶片或類似者。第4A圖繪示具有至少四個堆疊式晶粒100A至堆疊式晶粒100D的第一晶粒堆疊20A,但諸如第一晶粒堆疊20A之晶粒堆疊可包括更多或更少晶粒。
堆疊式晶粒100A至堆疊式晶粒100D可類似於第1圖之晶粒100。舉例而言,堆疊式晶粒100A至堆疊式晶粒100D可各自包括半導體基板102、介電結構104、包括第一連接接線112A的互連結構110、密封環130、前側接合層50A、背側接合層50B、前側接合襯墊52A和背側接合襯墊52B。在一些實施例中,堆疊式晶粒100B至堆疊式晶粒100D可包括矽穿孔結構162。最下方的堆疊式晶粒100A可省略矽穿孔結構162。此外,一些堆疊式晶粒可能不需要前側接合襯墊52A或背側接合襯墊52B。舉例而言,堆疊式晶粒100A不包括背側接合襯墊52B。
堆疊式晶粒100A至堆疊式晶粒100D可堆疊於第一載體60上且彼此接合,以形成第一晶粒堆疊20A。具體而言,可對準堆疊式晶粒100A至堆疊式晶粒100D,使得堆疊式晶粒100A至堆疊式晶粒100D的第一連接接線112A相鄰於第一晶粒堆疊20A之第一側S1(或第一表面)設置。
可使用混合式熔融接合(hybrid fusion bonding)製程接合堆疊式晶粒100A至堆疊式晶粒100D。具體而言,可使用介電質至介電質接合製程或聚合物至聚合物接合製程接合相鄰的堆疊式晶粒100A至堆疊式晶粒100D的前側接合層50A和背側接合層50B,且可使用金屬至金屬接合製程來接合相鄰的堆疊式晶粒100A至堆疊式晶粒100D的前側接合襯墊52A和背側接合襯墊52B。最下方的堆疊式晶粒100A可由堆疊式晶粒100A之背側接合層50B接合至第一載體60。
舉例而言,第一載體60可為矽晶圓、藍寶石晶圓或任何其他合適載體,諸如玻璃或塑膠載體。保護層54可沉積於最上方的堆疊式晶粒100D上。保護層54可包括介電材料,諸如氧化矽、氮化矽、氮氧化矽或類似者。
步驟702可包括在第一載體60上形成額外晶粒堆疊。舉例而言,第一晶粒堆疊20A和第二晶粒堆疊20B(參見第4B圖)在同一製造製程期間可各自形成於第一載體60上。因此,第一晶粒堆疊20A和第二晶粒堆疊20B可具有類似元件。在其他實施例中,相較於第一晶粒堆疊20A,第二晶粒堆疊20B可形成於不同載體上,且可具有不同元件或不同元件組態。
雖然第一晶粒堆疊20A和第二晶粒堆疊20B在各種圖中繪示為包括四個堆疊式晶粒(例如,堆疊式晶粒100A至堆疊式晶粒100D),但本公開不限於在晶粒堆疊中包括任何特定數目的堆疊式晶粒100。舉例而言,第一晶粒堆疊20A及/或第二晶粒堆疊20B可包括四個以上堆疊式晶粒,諸如至少5個、至少10個、至少15個或至少20個堆疊式晶粒。晶粒堆疊中可包括更少或更多晶粒。
參照第3圖和第4B圖,在步驟704中,第一晶粒堆疊20A和第二晶粒堆疊20B可自第一載體60移除、旋轉90°,且由載體接合層66接合至第二載體64。具體而言,與第一晶粒堆疊20A和第二晶粒堆疊20B之第一側S1(或第一表面)相對的第一晶粒堆疊20A和第二晶粒堆疊20B的第二側S2(或第二表面)可接合至第二載體64,使得第一側S1(或第一表面)暴露於第二載體64上方。在一些實施例中,載體接合層66可為垂直熔融凸塊或類似者。
參照第3圖和第4C圖,在步驟706中,介電填充層56可沉積於第一晶粒堆疊20A和第二晶粒堆疊20B周圍以及兩者之間。可使用任何合適沉積方法來沉積介電填充層56,且介電填充層56可包括任何合適介電材料,諸如氧化矽、氮化矽或類似者。其他合適介電材料在本公開之預期範疇內。
參照第3圖和第4D圖,在步驟708中,可對第一晶粒堆疊20A之第一側S1、第二晶粒堆疊20B的第一側S1和介電填充層56執行諸如化學機械平坦化(chemical mechanical planarization,CMP)之平坦化製程。具體而言,第一晶粒堆疊20A和第二晶粒堆疊20B可經拋光以移除介電封裝層40和密封環130的多個部分,使得第一連接接線112A可暴露於第一晶粒堆疊20A和第二晶粒堆疊20B的第一側S1上。
參照第3圖和第4E圖,在步驟710中,連接接合層70和連接接合襯墊72可形成於第一晶粒堆疊20A和第二晶粒堆疊20B之第一側S1上以及介電填充層56上。連接接合層70可包括沉積於晶粒100之前側和背側上的接合材料。合適接合材料可包括氧化矽或結合聚合物,諸如環氧樹脂、聚醯亞胺(polyimide,PI)、苯并環丁烯(benzocyclobutene,BCB)和聚苯并噁唑(polybenzoxazole,PBO)。其他合適接合材料可在本公開之預期範疇內。連接接合襯墊72可以是由與第一連接接線112A相同之材料所形成的導電特徵。舉例而言,連接接合襯墊72可包括鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金、其組合或類似者。用於連接接合襯墊72的其他合適材料在本公開之預期範疇內。
可使用混合式接合製程來形成連接接合層70和連接接合襯墊72。因此,連接接合襯墊72可熔融至第一連接接線112A,且連接接合層70可接合至介電填充層56以及其下方的第一晶粒堆疊20A和第二晶粒堆疊20B的介電層。
參照第3圖和第4F圖,在步驟712中,可使用任何合適接合製程(諸如混合式接合製程)來將第一連接晶粒200接合至連接接合層70和連接接合襯墊72。第一連接晶粒200可類似於第1圖之晶粒100。舉例而言,第一連接晶粒200可包括半導體基板202、介電結構204、互連結構210、密封環230和矽穿孔結構262。在一些實施例中,第一連接晶粒200可為被動式元件(例如,半導體基板202可不包括裝置層)。
互連結構210可由導電金屬接線和通孔結構所形成,如上文關於互連結構110所述。互連結構210可配置成經由堆疊內連接電路114直接電性連接第一晶粒堆疊20A的非相鄰堆疊式晶粒100A至堆疊式晶粒100D至彼此,且直接電性連接第二晶粒堆疊20B之相鄰及/或非相鄰堆疊式晶粒100A至堆疊式晶粒100D至彼此。在一些實施例中,互連結構210可用以經由堆疊間連接電路116將第一晶粒堆疊20A之一或多個堆疊式晶粒100A至堆疊式晶粒100D直接電性連接至第二晶粒堆疊20B的一或多個堆疊式晶粒100A至堆疊式晶粒100D。本文中,第一晶粒堆疊20A之堆疊式晶粒100A至堆疊式晶粒100D可被稱作「第一堆疊式晶粒」,且第二晶粒堆疊20B之堆疊式晶粒100A至堆疊式晶粒100D可被稱作「第二堆疊式晶粒」。
參照第3圖和第4G圖,在步驟714中,可薄化第一連接晶粒200之半導體基板202以暴露形成於其中的矽穿孔結構262。介電層84和電性接觸件86(諸如焊料凸塊)可形成於半導體基板202的背側上。電性接觸件86可電性連接至經暴露的矽穿孔結構262。可移除第二載體64,且第一晶粒堆疊20A、第二晶粒堆疊20B和第一連接晶粒200可經反轉以形成半導體封裝10,如第4G圖中所繪示。
第5圖為根據本公開之多種實施例的半導體封裝12之橫截面圖。半導體封裝12可為繪示於第4G圖中之半導體封裝10的修改版本。因此,類似參考數字代表類似元件,且僅詳細描述彼此之間的差異。
參照第5圖,半導體封裝12可包括第一晶粒堆疊22A、第二晶粒堆疊22B和第一連接晶粒200。相對於半導體封裝10,半導體封裝12亦可包括第二連接晶粒300,其中第一連接晶粒200和第二連接晶粒300設置於第一晶粒堆疊22A和第二晶粒堆疊22B的相對側上。
第一晶粒堆疊22A和第二晶粒堆疊22B可各自包括堆疊式晶粒101A至堆疊式晶粒101D。堆疊式晶粒101A至堆疊式晶粒101D可類似於第1圖之晶粒100。舉例而言,堆疊式晶粒101A至堆疊式晶粒101D可各自包括半導體基板102、介電結構104,以及包括第一連接接線112A和第二連接接線112B的互連結構110(參照第1圖)。第一連接接線112A和第二連接接線112B可設置於第一晶粒堆疊22A之相對側和第二晶粒堆疊22B的相對側上。
第一連接晶粒200可類似於半導體封裝10之第一連接晶粒200。舉例而言,第一連接晶粒200可包括半導體基板202、介電結構204、互連結構210、密封環230和矽穿孔結構262。
第二連接晶粒300可類似於第一連接晶粒200。舉例而言,第二連接晶粒300可包括半導體基板302、介電結構304、互連結構310和密封環330。在一些實施例中,第二連接晶粒300可為被動式元件。
互連結構210可電性連接至第一連接接線112A,且互連結構310可電性連接至第二連接接線112B。第一連接晶粒200和第二連接晶粒300可配置成經由堆疊內連接電路114將相同晶粒堆疊(第一晶粒堆疊22A或第二晶粒堆疊22B)之非相鄰堆疊式晶粒101A至堆疊式晶粒101D直接電性連接至彼此,或經由堆疊間連接電路116直接連接不同晶粒堆疊(第一晶粒堆疊22A和第二晶粒堆疊22B)的堆疊式晶粒101A至堆疊式晶粒101D。具體而言,互連結構210和第一連接接線112A可形成晶粒連接電路,且互連結構310和第二連接接線112B可形成晶粒連接電路。
第6圖為根據本公開之多種實施例的半導體封裝14之橫截面視圖。半導體封裝14可包括元件類似於半導體封裝10的元件。因此,類似參考數字代表類似元件,且僅詳細描述彼此之間的差異。
參照第6圖,半導體封裝14可包括設置於第一連接晶粒200上的第一晶粒堆疊20A和第二晶粒堆疊24。第一晶粒堆疊20A和第一連接晶粒200可類似於半導體封裝10的第一晶粒堆疊20A和第一連接晶粒200。具體而言,第一晶粒堆疊20A可包括堆疊式晶粒100A至堆疊式晶粒100D,堆疊式晶粒100A至堆疊式晶粒100D由第一連接接線112A電性連接至第一連接晶粒200。
第二晶粒堆疊24可包括類似於第1圖之晶粒100的堆疊式晶粒103A至堆疊式晶粒103D,但堆疊式晶粒103A至堆疊式晶粒103D並不包括連接接線(例如,第一連接接線112A和第二連接接線112B)。堆疊式晶粒103A至堆疊式晶粒103D可由矽穿孔結構162電性連接至彼此,且可電性連接至第一連接晶粒200。第二晶粒堆疊24可定向於第一連接晶粒200上,使得堆疊式晶粒103A至堆疊式晶粒103D的平面可平行於第一連接晶粒200的平面。因此,堆疊式晶粒103A至堆疊式晶粒103D的平面可垂直於堆疊式晶粒100A至堆疊式晶粒100D的平面。
本公開之多種實施例提供半導體封裝10,半導體封裝10包括設置於至少一個第一連接晶粒200上的第一晶粒堆疊20A、第二晶粒堆疊20B。第一晶粒堆疊20A、第二晶粒堆疊20B包括堆疊式晶粒100A至堆疊式晶粒100D,其中堆疊式晶粒100A至堆疊式晶粒100D的平面和第一連接晶粒200的平面以一角度對準,此角度範圍為約45°至約90。第一連接晶粒200可使堆疊式晶粒100A至堆疊式晶粒100D直接電性連接至彼此,從而減小電路電阻。因此,可增加堆疊式晶粒100A至堆疊式晶粒100D的數目,而不會因為使用矽穿孔結構162間接連接堆疊式晶粒而遭受增大的電路電阻。
多種實施例提供一種半導體封裝10,半導體封裝10可包括第一連接晶粒200和第一晶粒堆疊20A,第一連接晶粒200包括第一半導體基板202和互連結構210,第一晶粒堆疊20A設置於第一連接晶粒200上且包括堆疊式晶粒100,各個堆疊式晶粒100包括半導體基板102和可包括第一連接接線112A的互連結構110,第一連接接線112A電性連接至第一連接晶粒200的互連結構210,其中形成於第一連接晶粒200的平面與各個堆疊晶粒100的平面之間的角度範圍為約45°至約90°。
在一個實施例中,第一連接晶粒200的互連結構210可將堆疊式晶粒100A至堆疊式晶粒100D中之至少兩者的第一連接接線112A直接電性連接至彼此。在一個實施例中,每一堆疊式晶粒100A至堆疊式晶粒100D的半導體基板102各自界定每一堆疊式晶粒100A至堆疊式晶粒100D的平面;第一連接晶粒200的半導體基板202界定第一連接晶粒200的平面;以及堆疊式晶粒100A至堆疊式晶粒100D的平面可垂直於第一連接晶粒200的平面。在一個實施例中,堆疊式晶粒100A至堆疊式晶粒100D可包括記憶體晶片;以及第一連接晶粒200可為被動式元件。在一個實施例中,第一晶粒堆疊20A可包括至少四個堆疊式晶粒100。在一個實施例中,第一晶粒堆疊20A可包括第一側S1和相對的第二側S2,第一側S1可接合至第一連接晶粒200;以及第一連接接線112A可暴露在第一晶粒堆疊20A的第一側S1上。在一個實施例中,半導體封裝10亦可包括接合至第一晶粒堆疊20A的第二側S2的第二連接晶粒300,第二連接晶粒300可包括半導體基板302和互連結構310,其中堆疊式晶粒100A至堆疊式晶粒100D的互連結構110各自包括第二連接接線112B,第二連接接線112B可暴露於第一晶粒堆疊20A的第二側S2上且可電性連接至第二連接晶粒300的互連結構310。在一個實施例中,半導體封裝10亦可包括第二晶粒堆疊20B,第二晶粒堆疊20B設置於第一連接晶粒200上且可包括堆疊式晶粒100A至堆疊式晶粒100D,各個堆疊式晶粒100A至堆疊式晶粒100D可包括半導體基板102和可包括第一連接接線112A的互連結構110,第一連接接線112A可電性連接至第一連接晶粒200的互連結構210。在一個實施例中,第二晶粒堆疊20B的每一堆疊式晶粒100A至堆疊式晶粒100D的平面可平行於第一連接晶粒200的平面。在一個實施例中,第二晶粒堆疊20B的每一堆疊式晶粒100A至堆疊式晶粒100D的平面可垂直於第一連接晶粒200的平面。
多種實施例提供一種半導體封裝10,半導體封裝10可包括第一連接晶粒200,第一連接晶粒200可包括半導體基板202和互連結構210。半導體封裝10可包括第一晶粒堆疊20A,第一晶粒堆疊20A設置於第一連接晶粒200上且可包括第一堆疊式晶粒100,各個第一堆疊式晶粒100可包括半導體基板102和可包括第一連接接線112A的互連結構110,第一連接接線112A電性連接至第一連接晶粒200的互連結構210。半導體封裝10可包括第二晶粒堆疊20B,第二晶粒堆疊20B設置於第一連接晶粒200上且可包括第二堆疊式晶粒100,各個第二堆疊式晶粒可包括半導體基板102和可包括第一連接接線112A的互連結構110,第一連接接線112A電性連接至第一連接晶粒200的互連結構210,其中第一連接晶粒200的平面垂直於各個第一堆疊式晶粒100的平面。
在一個實施例中,每一第一堆疊式晶粒100A至堆疊式晶粒100D的半導體基板102界定每一第一堆疊式晶粒100A至堆疊式晶粒100D的平面;以及第一連接晶粒200的半導體基板202界定第一連接晶粒200的平面。在一個實施例中,每一第二晶粒堆疊20B的平面可平行於第一連接晶粒200的平面。在一個實施例中,每一第二晶粒堆疊20B的平面可垂直於第一連接晶粒200的平面。在一個實施例中,第一連接晶粒200的互連結構210直接電性連接第一晶粒堆疊20A中之至少兩者的第一連接接線112A;以及第一連接晶粒200的互連結構210直接電性連接第二晶粒堆疊20B中之至少兩者的第一連接接線112A。在一個實施例中,第一晶粒堆疊20A和第二晶粒堆疊20B可包括記憶體晶片;以及第一連接晶粒200可為被動式元件。在一個實施例中,第一晶粒堆疊20A可包括可接合至第一連接晶粒200的第一側S1和相對的第二側S2;第一晶粒堆疊20A的第一連接接線112A可暴露在第一晶粒堆疊20A的第一側S1上;第二晶粒堆疊20B可包括可接合至第一連接晶粒200的第一側S1和相對的第二側S2;以及第二晶粒堆疊20B的第一連接接線112A可暴露在第二晶粒堆疊20B的第一側S1上。在一個實施例中,半導體封裝10可進一步包括接合至第一晶粒堆疊20A的第二側S2和第二晶粒堆疊20B的第二側S2的第二連接晶粒300,第二連接晶粒300可包括半導體基板302和互連結構310,其中第一晶粒堆疊20A的互連結構110各自可包括第二連接接線112B,第二連接接線112B可暴露於第一晶粒堆疊20A的第二側S2上且可電性連接至第二連接晶粒300的互連結構310,以及其中第二晶粒堆疊20B的互連結構110各自可包括第二連接接線112B,第二連接接線112B可暴露於第二晶粒堆疊20B的第二側S2上且可電性連接至第二連接晶粒300的互連結構310。
多種實施例進一步提供一種形成半導體封裝10的方法,方法可包括以下步驟。接合多個堆疊式晶粒100以形成第一晶粒堆疊20A,各個堆疊式晶粒100可包括半導體基板102和可包括第一連接接線112A的互連結構110。平坦化第一晶粒堆疊20A的第一側S1以暴露第一連接接線112A。將第一晶粒堆疊20A的第一側S1接合至第一連接晶粒200,第一連接晶粒200可包括半導體基板202和互連結構210,使得第一連接接線112A電性連接至第一連接晶粒200的互連結構210,其中形成於第一連接晶粒200的平面與每一堆疊式晶粒100的平面之間的角度範圍為約45°至約90°。
前面概述一些實施例的特徵,使得本領域技術人員可更好地理解本公開的觀點。本領域技術人員應該理解,他們可以容易地使用本公開作為設計或修改其他製程和結構的基礎,以實現相同的目的和/或實現與本文介紹之實施例相同的優點。本領域技術人員還應該理解,這樣的等同構造不脫離本公開的精神和範圍,並且在不脫離本公開的精神和範圍的情況下,可以進行各種改變、替換和變更。
10:半導體封裝
12:半導體封裝
14:半導體封裝
20A:第一晶粒堆疊
20B:第二晶粒堆疊
22A:第一晶粒堆疊
22B:第二晶粒堆疊
24:第二晶粒堆疊
40:介電封裝層
50A:前側接合層
50B:背側接合層
52A:前側接合襯墊
52B:背側接合襯墊
54:保護層
56:介電填充層
60:第一載體
64:第二載體
66:載體接合層
70:連接接合層
72:連接接合襯墊
84:介電層
86:電性接觸件
100:晶粒
100A,100B,100C,100D:堆疊式晶粒
101A,101B,101C,101D:堆疊式晶粒
102:半導體基板
103A,103B,103C,103D:堆疊式晶粒
104:介電結構
104A:基板氧化物層
104B,104C,104D,104E,104F:層間介電質層
104G:鈍化層
108:基板電極
110:互連結構
112:金屬特徵
112A:第一連接接線
112B:第二連接接線
114:堆疊內連接電路
116:堆疊間連接電路
130:密封環
162:矽穿孔結構
200:第一連接晶粒
202:半導體基板
204:介電結構
210:互連結構
230:密封環
262:矽穿孔結構
300:第二連接晶粒
302:半導體基板
304:介電結構
310:互連結構
330:密封環
702:步驟
704:步驟
706:步驟
708:步驟
710:步驟
712:步驟
714:步驟
H1:第一水平方向
H2:第二水平方向
S1:第一側
S2:第二側
V:垂直方向
當結合附圖閱讀時,從以下詳細描述中可以最好地理解本公開的各方面。應注意,根據工業中的標準方法,各種特徵未按比例繪製。實際上,為了清楚地討論,可任意增加或減少各種特徵的尺寸。
第1圖為根據本公開之多種實施例的半導體晶粒100之橫截面圖。
第2A圖為根據本公開之多種實施例的半導體封裝10之簡化俯視圖。
第2B圖為第2A圖之半導體封裝10之第一側的簡化視圖。
第2C圖為第2A圖之半導體封裝10之第二側的簡化視圖。
第3圖為根據本公開之多種實施例的形成半導體封裝之方法的步驟流程圖。
第4A圖至第4G圖為繪示第3圖之方法步驟的垂直橫截面圖。
第5圖為根據本公開之多種實施例的半導體封裝之橫截面圖。
第6圖為根據本公開之多種實施例的半導體封裝之橫截面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記)
無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記)
無
10:半導體封裝
20A:第一晶粒堆疊
20B:第二晶粒堆疊
56:介電填充層
84:介電層
86:電性接觸件
200:第一連接晶粒
202:平面半導體基板
262:矽穿孔結構
Claims (20)
- 一種半導體封裝,包括: 一第一連接晶粒,包括一半導體基板和一互連結構;及 一第一晶粒堆疊,設置於該第一連接晶粒上且包括多個堆疊式晶粒,各該堆疊式晶粒包括一半導體基板和包括一第一連接接線的一互連結構,該第一連接接線電性連接至該第一連接晶粒的該互連結構, 其中形成於該第一連接晶粒的一平面與各該堆疊式晶粒的一平面之間的一角度範圍為約45°至約90°。
- 如請求項1所述之半導體封裝,其中該第一連接晶粒的該互連結構將該些堆疊式晶粒中之至少兩者的該些第一連接接線直接電性連接至彼此。
- 如請求項1所述之半導體封裝,其中: 各該堆疊式晶粒的該半導體基板各自界定各該堆疊式晶粒的該平面; 該第一連接晶粒的該半導體基板界定該第一連接晶粒的該平面;及 該些堆疊式晶粒的該些平面垂直於該第一連接晶粒的該平面。
- 如請求項1所述之半導體封裝,其中: 該些堆疊式晶粒包括記憶體晶片;及 該第一連接晶粒為一被動式元件。
- 如請求項1所述之半導體封裝,其中該第一晶粒堆疊包括至少四個該些堆疊式晶粒。
- 如請求項1所述之半導體封裝,其中: 該第一晶粒堆疊包括接合至該第一連接晶粒的一第一側和相對的一第二側;及 該些第一連接接線暴露在該第一晶粒堆疊的該第一側上。
- 如請求項6所述之半導體封裝,進一步包括一第二連接晶粒,該第二連接晶粒接合至該第一晶粒堆疊的該第二側,該第二連接晶粒包括一半導體基板和一互連結構, 其中該些堆疊式晶粒的該些互連結構各自包括一第二連接接線,該第二連接接線暴露於該第一晶粒堆疊的該第二側上且電性連接至該第二連接晶粒的該互連結構。
- 如請求項1所述之半導體封裝,進一步包括一第二晶粒堆疊,該第二晶粒堆疊設置於該第一連接晶粒上且包括多個堆疊式晶粒,該第二晶粒堆疊的各該堆疊式晶粒包括一半導體基板和包括一第一連接接線的一互連結構,該第一連接接線電性連接至該第一連接晶粒的該互連結構。
- 如請求項8所述之半導體封裝,其中該第二晶粒堆疊的各該堆疊式晶粒的一平面平行於該第一連接晶粒的該平面。
- 如請求項8所述之半導體封裝,其中該第二晶粒堆疊的各該堆疊式晶粒的一平面垂直於該第一連接晶粒的該平面。
- 一種半導體封裝,包括: 一第一連接晶粒,包括一半導體基板和一互連結構; 一第一晶粒堆疊,設置於該第一連接晶粒上且包括多個第一堆疊式晶粒,各該第一堆疊式晶粒包括一半導體基板和包括一第一連接接線的一互連結構,該第一連接接線電性連接至該第一連接晶粒的該互連結構;及 一第二晶粒堆疊,設置於該第一連接晶粒上且包括多個第二堆疊式晶粒,各該第二堆疊式晶粒包括一半導體基板和包括一第一連接接線的一互連結構,該第一連接接線電性連接至該第一連接晶粒的該互連結構, 其中該第一連接晶粒的一平面垂直於各該第一堆疊式晶粒的一平面。
- 如請求項11所述之半導體封裝,其中: 各該第一堆疊式晶粒的該半導體基板界定各該第一堆疊式晶粒的該平面;及 該第一連接晶粒的該半導體基板界定該第一連接晶粒的該平面。
- 如請求項11所述之半導體封裝,其中各該第二堆疊式晶粒的一平面平行於該第一連接晶粒的該平面。
- 如請求項11所述之半導體封裝,其中各該第二堆疊式晶粒的一平面垂直於該第一連接晶粒的該平面。
- 如請求項11所述之半導體封裝,其中: 該第一連接晶粒的該互連結構直接電性連接該些第一堆疊式晶粒中之至少兩者的該些第一連接接線;及 該第一連接晶粒的該互連結構直接電性連接該些第二堆疊式晶粒中之至少兩者的該些第一連接接線。
- 如請求項11所述之半導體封裝,其中: 該些第一堆疊式晶粒和該些第二堆疊式晶粒包括記憶體晶片;及 該第一連接晶粒為一被動式元件。
- 如請求項11所述之半導體封裝,其中: 該第一晶粒堆疊包括接合至該第一連接晶粒的一第一側和相對的一第二側; 該些第一堆疊式晶粒的該些第一連接接線暴露在該第一晶粒堆疊的該第一側上; 該第二晶粒堆疊包括接合至該第一連接晶粒的一第一側和相對的一第二側;及 該些第二堆疊式晶粒的該些第一連接接線暴露在該第二晶粒堆疊的該第一側上。
- 如請求項17所述之半導體封裝,進一步包括一第二連接晶粒,該第二連接晶粒接合至該第一晶粒堆疊的該第二側和該第二晶粒堆疊的該第二側,該第二連接晶粒包括一半導體基板和一互連結構, 其中該些第一堆疊式晶粒的該些互連結構各自包括一第二連接接線,該第二連接接線暴露於該第一晶粒堆疊的該第二側上且電性連接至該第二連接晶粒的該互連結構,及 其中該些第二堆疊式晶粒的該些互連結構各自包括一第二連接接線,該第二連接接線暴露於該第二晶粒堆疊的該第二側上且電性連接至該第二連接晶粒的該互連結構。
- 一種形成一半導體封裝的方法,包括: 接合多個堆疊式晶粒以形成一第一晶粒堆疊,各該堆疊式晶粒包括一半導體基板和包括一第一連接接線的一互連結構; 平坦化該第一晶粒堆疊的一第一側以暴露該些第一連接接線;及 將該第一晶粒堆疊的該第一側接合至包括一半導體基板和一互連結構的一第一連接晶粒,使得該些第一連接接線電性連接至該第一連接晶粒的該互連結構, 其中形成於該第一連接晶粒的一平面與各該堆疊式晶粒的一平面之間的一角度範圍為約45°至約90°。
- 如請求項19所述之方法,其中: 該些堆疊式晶粒各自包括包圍該互連結構的一密封環;及 平坦化該第一晶粒堆疊包括移除各該密封環的一部分以暴露該些第一連接接線。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163166371P | 2021-03-26 | 2021-03-26 | |
US63/166,371 | 2021-03-26 | ||
US17/476,703 US12009349B2 (en) | 2021-03-26 | 2021-09-16 | Vertical semiconductor package including horizontally stacked dies and methods of forming the same |
US17/476,703 | 2021-09-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202238911A true TW202238911A (zh) | 2022-10-01 |
Family
ID=82424105
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111103461A TW202238911A (zh) | 2021-03-26 | 2022-01-26 | 半導體封裝 |
Country Status (3)
Country | Link |
---|---|
US (2) | US12009349B2 (zh) |
CN (1) | CN114783957A (zh) |
TW (1) | TW202238911A (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11862609B2 (en) * | 2021-03-18 | 2024-01-02 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor die including fuse structure and methods for forming the same |
US11855130B2 (en) * | 2021-08-26 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company Limited | Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same |
US11728288B2 (en) * | 2021-08-27 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor die including guard ring structure and three-dimensional device structure including the same |
US20240203851A1 (en) * | 2022-12-14 | 2024-06-20 | Western Digital Technologies, Inc. | Semiconductor Device Package with Coupled Substrates |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8290319B2 (en) * | 2010-08-25 | 2012-10-16 | Oracle America, Inc. | Optical communication in a ramp-stack chip package |
KR102108325B1 (ko) * | 2013-10-14 | 2020-05-08 | 삼성전자주식회사 | 반도체 패키지 |
US11373977B1 (en) * | 2020-09-15 | 2022-06-28 | Rockwell Collins, Inc. | System-in-package (SiP) with vertically oriented dielets |
-
2021
- 2021-09-16 US US17/476,703 patent/US12009349B2/en active Active
-
2022
- 2022-01-26 TW TW111103461A patent/TW202238911A/zh unknown
- 2022-01-30 CN CN202210114011.7A patent/CN114783957A/zh active Pending
-
2023
- 2023-08-03 US US18/230,147 patent/US20230387089A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US12009349B2 (en) | 2024-06-11 |
CN114783957A (zh) | 2022-07-22 |
US20220310570A1 (en) | 2022-09-29 |
US20230387089A1 (en) | 2023-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10461069B2 (en) | Hybrid bonding with through substrate via (TSV) | |
US11532598B2 (en) | Package structure with protective structure and method of fabricating the same | |
US12009349B2 (en) | Vertical semiconductor package including horizontally stacked dies and methods of forming the same | |
US11908838B2 (en) | Three-dimensional device structure including embedded integrated passive device and methods of making the same | |
TWI826910B (zh) | 包括封裝密封環的半導體封裝及其形成方法 | |
US20230386972A1 (en) | Semiconductor die including through substrate via barrier structure and methods for forming the same | |
US11728301B2 (en) | Semiconductor package including test pad and bonding pad structure for die connection and methods for forming the same | |
US11855130B2 (en) | Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same | |
US11862609B2 (en) | Semiconductor die including fuse structure and methods for forming the same | |
TW202322324A (zh) | 晶片堆疊 | |
US20230060265A1 (en) | Three-dimensional integrated circuit | |
TW202238869A (zh) | 半導體封裝 | |
US20230067714A1 (en) | Three-dimensional device structure including seal ring connection circuit | |
TW202240823A (zh) | 半導體裝置 |