TW202333249A - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TW202333249A TW202333249A TW111146600A TW111146600A TW202333249A TW 202333249 A TW202333249 A TW 202333249A TW 111146600 A TW111146600 A TW 111146600A TW 111146600 A TW111146600 A TW 111146600A TW 202333249 A TW202333249 A TW 202333249A
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Abstract
本發明實施例為一種半導體裝置的形成方法,包括在第一基底上形成第一內連線結構,在第一內連線結構上形成重佈通孔,重佈通孔電耦合到第一內連線結構的金屬化圖案中的至少一個,在重佈通孔上形成重佈墊,重佈墊電耦合到重佈通孔,在重佈墊上形成第一介電層,在第一介電層上形成第二介電層。該方法還包括圖案化第一和第二介電層,在重佈墊上方和第一介電層中形成接合通孔,接合通孔電耦合到重佈墊,接合通孔與重佈通孔重疊,以及在接合通孔上方和第二介電層中形成第一接合墊。第一接合墊電耦合到接合通孔。
Description
由於各種電子元件(例如電晶體、二極管、電阻器、電容器等)的集成密度不斷提高,半導體行業經歷了快速增長。在大多數情況下,集成密度的提高是由於最小特徵尺寸的迭代減小,這允許將更多組件集成到給定區域中。隨著對縮小電子裝置的需求不斷增長,出現了對更小、更具創造性的半導體晶粒封裝技術的需求。這種封裝系統的一個例子是封裝疊層(PoP)技術。在PoP裝置中,頂部半導體封裝堆疊在底部半導體封裝的頂部,以提供高水平的集成度和組件密度。PoP技術通常能夠在印刷電路板(PCB)上生產具有增強功能和小尺寸的半導體裝置。
下方公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。為簡化本公開,下文闡述裝置及佈置的具體實例。當然,這些僅為實例而非旨在進行限制。例如,下方說明中將第二特徵形成在第一特徵“上”或第一特徵“上”可包括其中第二特徵與第一特徵被形成為直接接觸的實施例,且也可包括其中第二特徵與第一特徵之間可形成有附加特徵、進而使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。此外,本公開可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡明及清晰的目的,且自身並不表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可使用例如“在……之下(beneath)”、“在……下方(below)”、“下部的(lower)”、“在……上方(above)”、“上部的(upper)”及類似用語等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除圖中所繪示的取向以外,所述空間相對性用語還旨在囊括裝置在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或處於其他取向),且本文所使用的空間相對性描述語可同樣相應地加以解釋。
本文討論的實施例可以在特定上下文中討論,即可以集成到裝置(例如,晶片或晶粒)或封裝(例如,晶圓上晶片(CoW)封裝結構或晶圓上的重佈結構-晶圓(矽)封裝結構)。重佈結構包括一個重佈通孔,其具有水平或平坦的上表面和一個上覆墊,以允許相鄰重佈通孔和上覆墊之間的較小間距和最小距離。在一些實施例中,使用例如單鑲嵌製程與上覆墊分開形成重佈通孔。在一些實施例中,重佈通孔是在與上覆墊相同的製程中形成的,例如,使用雙鑲嵌製程隨後進行平坦化製程以平整或平坦化上覆墊的上表面。在一些結構中,重佈通孔不具有迫使上覆接合通孔和接合墊與重佈通孔偏移的平坦表面。通過使重佈通孔的頂面和/或上覆墊的頂面為平坦或水平表面,上覆於墊的接合通孔和接合墊可以形成在重佈通孔正上方,並且可以使最小間距減少至少35%。
此外,本公開的教示適用於任何重佈結構,其中重佈通孔和/或墊的平坦頂面可以減小重佈結構的最小間距。其他實施例考慮了其他應用,例如本領域普通技術人員在閱讀本公開後將容易明白的不同封裝類型或不同配置。應當注意,本文討論的實施例不一定說明結構中可能存在的每個組件或特徵。例如,當對其中一個組件的討論就可能足以傳達實施例時,可以從圖中省略多個組件。此外,本文討論的方法實施例可以被討論為以特定順序執行;然而,可以以任何邏輯順序執行其他方法實施例。
圖1至圖26示出了根據一些實施例的封裝形成中的中間階段的剖面圖。
圖1圖示了根據一些實施例的積體電路晶粒20的剖面圖。積體電路晶粒20將在後續加工中進行封裝,以形成積體電路封裝。積體電路晶粒20可以是邏輯晶粒(例如,中央處理單元(CPU)、圖形處理單元(GPU)、晶片上系統(SoC)、應用處理器(AP)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、電源管理晶粒(例如,電源管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器裸片、微機電系統(MEMS)裸片、訊號處理裸片(例如,數位訊號處理(DSP)裸片)、前端裸片(例如,模擬前端(AFE)裸片)等或它們的組合。
積體電路晶粒20可以形成在晶圓中,該晶圓可以包括不同的裝置區域,這些區域在隨後的步驟中被單體化以形成多個積體電路晶粒。可以根據適用的製造製程處理積體電路晶粒20以形成積體電路。例如,積體電路晶粒20包括基底22,例如摻雜或未摻雜的矽或絕緣體上半導體(SOI)基底的主動層。基底22可以包括其他半導體材料,例如鍺;一種化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或其組合。也可以使用其他基底,例如多層或梯度基底。基底22具有主動表面(例如,圖1中朝上的表面,有時稱為正面),和非主動表面(例如,圖1中朝下的表面,有時稱為背面)。
裝置(未示出)可以形成在基底22的前表面。裝置可以是主動裝置(例如電晶體、二極管等)、電容器、電阻器等或它們的組合。層間介電質(ILD)(未單獨顯示)位於基底22的前表面上方。ILD圍繞並可能覆蓋裝置。ILD可以包括由諸如磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)、未摻雜矽酸鹽玻璃(USG)等材料形成的一個或多個介電層。
導電插塞(未單獨示出)延伸穿過ILD以電耦合和物理耦合裝置。例如,當裝置是電晶體時,導電插塞可以耦合電晶體的閘極和源極/汲極區。導電插塞可由鎢、鈷、鎳、銅、銀、金、鋁等或它們的組合形成。內連線結構24在ILD和導電插塞上方。內連線結構24將裝置內連以形成積體電路。例如,可以通過ILD上的介電層中的金屬化圖案來形成內連線結構24。金屬化圖案包括形成在一個或多個低k介電層中的金屬線和通孔。內連線結構24的金屬化圖案通過導電插塞電耦合到裝置。金屬化圖案可以使用任何合適的製程形成,例如單鑲嵌製程、雙鑲嵌製程、電鍍製程以及它們的組合等。
形成內連線結構24後,如圖2所示,在內連線結構23上形成罩幕30並圖案化。在一些實施例中,罩幕30是光阻並且可以通過旋塗等形成並且可以暴露於光以進行圖案化。光阻的圖案對應於隨後形成的基底穿孔(TSV)44的上部(參見例如圖6)。圖案化形成至少一個穿過罩幕30的開口以暴露內連線結構24。在一些實施例中,在形成罩幕30之前,在內連線結構24的頂面上沉積例如化學機械拋光(CMP)終止層等終止層(未示出)。通過阻擋隨後的CMP製程和/或通過為隨後的CMP製程提供可偵測的終止點,CMP終止層可用於來防止隨後的CMP製程去除過多的材料。在一些實施例中,CMP終止層可以包括一層或多層介電材料。合適的介電材料可以包括氧化物(例如氧化矽、氧化鋁等)、氮化物(例如SiN等)、氮氧化物(例如SiON等)、碳氧化物(例如SiOC等)、碳氮化物(例如SiCN等)、碳化物(例如SiC等)以及它們的組合等,並且可以使用旋塗、化學氣相沉積(CVD)、電漿形成-增強型CVD(PECVD)、原子層沉積(ALD)等或它們的組合。
在圖3中,剩餘的罩幕30在蝕刻過程中用作罩幕,以去除內連線結構24的介電層和基底22的經暴露下面部分。可以使用單次蝕刻製程來蝕刻內連線結構24和基底22中的開口34,或者可以使用第一蝕刻製程來蝕刻內連線結構24並且可以使用第二蝕刻製程來蝕刻基底22。在一些實施例中,開口34通過電漿乾式蝕刻製程或例如深RIE(DRIE)製程等反應離子蝕刻(RIE)製程形成。在一些實施例中,DRIE製程包括蝕刻週期和鈍化週期,其中蝕刻週期使用例如SF
6,鈍化週期使用例如C
4F
8。使用具有鈍化週期和蝕刻週期的DRIE製程能夠實現高度各向異性的蝕刻製程。在一些實施例中,蝕刻製程可以是任何可接受的蝕刻製程,例如通過濕式或乾式蝕刻。
如圖4所示,在形成開口34之後,去除罩幕30。可以通過可接受的灰化或剝離製程去除罩幕30,例如使用氧電漿等。
此外,在圖4中,襯層38共形沉積在內連線結構24上以及開口34的底面和側壁上。在一些實施例中,襯層38包括一層或多層介電材料並且可以用於將隨後形成的穿孔與基底22物理隔離和電隔離。合適的介電材料可包括氧化物(例如氧化矽、氧化鋁等)、氮化物(例如SiN等)、氧氮化物(例如SiON等)以及它們的組合等。可以使用CVD、PECVD、ALD等或它們的組合來形成襯層38。
在隨後的步驟中,如圖4所示,在襯層38上形成晶種層40。在一些實施例中,晶種層40是金屬層,其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層40包括鈦層和鈦層上方的銅層。可以使用例如物理氣相沉積(PVD)等來形成晶種層。在一些實施例中,可以在形成晶種層40之前在襯層38上形成阻障層(未示出)。阻障層可以包括Ti、TiN等或它們的組合。
在圖5中,在晶種層40上形成導電材料42,以填充開口34。導電材料42可以通過電鍍形成,例如電鍍,包括電化學電鍍、化學鍍等。導電材料可以包括金屬,例如銅、鈦、鎢、鋁等。
在形成導電材料42之後,然後執行退火製程。可以執行退火製程以防止TSV44的導電材料的後續擠壓(subsequent extrusion),有時也稱為TSV抽出(TSV pumping)。TSV抽出是由導電材料42和基底22之間的熱膨脹係數(CTE)不匹配引起的,並且可能損壞TSV上的結構(例如,金屬化圖案)。
在退火製程之後,執行平坦化製程以去除在開口34之外的導電材料42、晶種層40和襯層38在開口34的部分,以形成如圖6所示的TSV44。在平坦化製程之後,TSV44的頂面和內連線結構24的最頂部介電層在製程變化內是共面的。平坦化製程可以是例如化學機械拋光(CMP)、研磨製程等。TSV44的上部(形成在內連線結構24中)具有比TSV44的下部(形成在基底22中)更大的寬度。
參考圖7,在圖6的結構上形成一個內連線結構50。內連線結構50包括介電層52、金屬化圖案和通孔54以及頂部金屬56。可以形成比圖14所示更多或更少的介電層、金屬化圖案和通孔。內連線結構50通過形成在介電層52中的金屬化圖案和通孔而連接到內連線結構24和TSV44。金屬化圖案和通孔可以採用與內連線結構24類似的製程和材料形成,在此不再贅述。在一些實施例中,存在多於一層的頂部金屬56,例如兩個頂部金屬層。
在一些實施例中,介電層52是與內連線結構24的介電層相同的材料,例如低k介電質。在其他實施例中,介電層52由含矽氧化物(其可以包括或不包括氧)形成。例如,介電層52可以包括諸如氧化矽的氧化物、諸如氮化矽的氮化物等。
金屬化圖案和通孔54和頂部金屬56可以使用任何合適的製程形成,例如單鑲嵌製程、雙鑲嵌製程、電鍍製程以及它們的組合等。通過鑲嵌製程形成金屬化圖案和通孔54和頂部金屬56的示例包括蝕刻介電層52以形成開口,將導電阻障層沉積到開口中,電鍍例如銅或銅合金等金屬材料,以及執行平坦化以去除金屬材料的多餘部分。在其他實施例中,介電層52、金屬化圖案和通孔54以及頂部金屬56的形成可以包括形成介電層52、圖案化介電層52以形成開口、形成金屬晶種層(未示出)、形成圖案化鍍層罩幕(例如光阻)以覆蓋金屬晶種層的某些部分且同時使其他部分暴露,電鍍金屬化圖案和通孔54和頂部金屬56,去除電鍍層罩幕,以及蝕刻金屬晶種層的非期望部分。金屬化圖案和通孔54和頂部金屬56可以由鎢、鈷、鎳、銅、銀、金、鋁等或它們的組合製成。在一些實施例中,頂部金屬56比金屬化圖案和通孔54厚,例如比金屬化圖案和通孔54厚三倍、厚五倍或任何合適的厚度比。
圖7進一步說明了介電層52上的鈍化層58和鈍化層58中的重佈通孔60的形成。在一些實施例中,鈍化層58由與介電層52相同的材料形成。在一些實施例中,鈍化層58可以是聚合物,例如聚苯並噁唑(PBO)、聚酰亞胺、苯並環丁烯(BCB)等;氮化物,例如氮化矽等;氧化物,例如氧化矽、磷矽玻璃(PSG)、硼矽玻璃(BSG)、摻硼磷矽玻璃(BPSG)等;類似;或其組合。鈍化層58可以例如通過旋塗、層壓、化學氣相沉積(CVD)等形成。鈍化層58可以具有在製程變化範圍內實質上水平的上表面。
重佈通孔60可以使用任何合適的製程形成,例如單鑲嵌製程、雙鑲嵌製程、電鍍製程以及它們的組合等。重佈通孔60可以由與金屬化圖案和通孔54類似的材料和製程形成,在此不再贅述。通過使重佈通孔的頂面和/或上覆墊的頂面為平坦或水平表面,上覆於墊的接合通孔和接合墊可以形成在重佈通孔正上方,並且可以使最小間距減少至少35%。
圖8說明了在重佈通孔60和鈍化層58上形成重佈墊層62。因為重佈通孔60的頂面和鈍化層58是平的且彼此共面,所以重佈墊層62的頂面是平的或者水平的。正如前面和下面所討論的,這些平坦的頂面允許最小間距的縮小。重佈墊層62與重佈通孔60物理接觸。在一些實施例中,通過電鍍製程形成重佈墊層62。在一個實施例中,形成晶種層(未示出)並將金屬材料鍍在晶種層上。晶種層可以使用例如PVD等形成。電鍍製程可以是電鍍,包括電化學電鍍、化學鍍等。重佈墊層62可以採用與重佈通孔60類似的材料和製程,在此不再贅述。在一些實施例中,重佈通孔60和重佈墊層62由相同的材料形成,並且在其他實施例中,它們由不同的材料形成。
在圖9中,在重佈墊層62上形成光阻64並圖案化光阻64。光阻64可以通過旋塗等形成並且可以曝光以進行圖案化。光阻的圖案對應於重佈墊62’(見圖10)。
圖10說明了重佈墊層62的圖案化,使用經圖案化的光阻64作為罩幕以形成重佈墊62’。可以例如通過使用可接受的蝕刻製程(例如通過濕式和/或乾式蝕刻),以去除重佈墊層62的經暴露部分。晶種層和導電材料的其餘部分形成重佈墊62’。在圖案化之後,重佈墊62’的側壁可以垂直於鈍化層58的頂面。在一些實施例中,重佈墊62’的側壁可能不完全垂直於鈍化層58的頂面並且可能是傾斜的或成對角的。如圖10所示,重佈墊62’在接近鈍化層58的表面處可能比它們在遠離鈍化層58的表面處更寬。在一些實施例中,重佈墊62’在底表面處(即,接近鈍化層58的頂面)具有寬度W1。在一些實施例中,寬度W1小至1.8μm。在一些實施例中,寬度W1在從1.8μm到3.6μm的範圍內。
圖11說明了光阻64的去除以及在鈍化層58和重佈墊62’上形成介電層。可以通過可接受的灰化或剝離製程去除光阻64,例如使用氧電漿等。
此外,在圖11中,在鈍化層58和重佈墊62’上方形成介電層70、72和74。儘管圖11示出了三個介電層70、72和74,但是可以形成多於或少於三個介電層。介電層70提供平面頂面以在其上形成介電層72和74,並且介電層70可以被視為平坦化介電層70。介電層72可以在隨後形成接合墊和接合通孔期間提供蝕刻停止功能並且可以被視為蝕刻終止層。介電層74可以提供介電接合功能並且可以被視為接合介電層。
在一些實施例中,介電層70、72和74由含矽氧化物形成。例如,介電層52可以包括諸如氧化矽的氧化物、諸如氮化矽的氮化物、諸如氧氮化矽的氧氮化物等或它們的組合。
圖12到14說明了在介電層70、72和74中形成接合墊通孔92和接合墊94。可以使用任何合適的製程來形成接合墊通孔92和接合墊94,例如單鑲嵌製程、雙鑲嵌製程以及它們的組合等。圖12到14說明了雙鑲嵌製程。
在圖12中,在介電層74上形成光阻76並圖案化光阻76。光阻76可以通過旋塗等形成並且可以曝光以進行圖案化。光阻的圖案對應於接合墊94的開口78(參見圖14)。此外,在圖12中,使用經圖案化的光阻76作為罩幕並且使圖案化製程停在介電層72上,以圖案化介電層74,而形成開口78。例如通過使用可接受的蝕刻製程(例如通過濕式和/或乾式蝕刻)可以去除介電層74的經暴露部分。開口78具有寬度W2。在一些實施例中,寬度W2小至1.4μm。在一些實施例中,寬度W2在從1.4μm到2.5μm的範圍內。
圖13說明了光阻76的去除、光阻80的形成和圖案化以及介電層72和70的圖案化。光阻76可以通過可接受的灰化或剝離製程去除,例如使用氧電漿等。此外,在圖13中,在圖案化的介電層74上形成光阻80和圖案化光阻80。可以通過旋塗等形成光阻80並且可以曝光以進行光阻80的圖案化。光阻的圖案對應於接合墊通孔92的開口82(參見圖14)。此外,在圖13中,使用圖案化的光阻80作為罩幕,以圖案化介電層72和70,而形成開口82,其中圖案化製程暴露部分重佈墊62’。例如通過使用可接受的蝕刻製程(例如通過濕式和/或乾式蝕刻),可以去除介電層72和70的經暴露部分。開口82具有寬度W3。在一些實施例中,寬度W3小至0.6μm。在一些實施例中,寬度W3在從0.6μm到1.8μm的範圍內。
圖14說明了光阻80的去除以及在開口78和82中形成阻障層91、接合墊通孔92和接合墊94。在形成接合墊通孔92和接合墊94之前,可以在開口中形成阻障層91。在一些實施例中,阻障層91可包括Ti、TiN等或其組合。接合墊通孔92和接合墊94可以採用與金屬化圖案和通孔54、重佈通孔60和/或重佈墊62’類似的製程和材料形成,在此不再贅述。例如,接合墊94可以由銅形成或包括銅。相鄰的接合墊94之間具有間距P1。在一些實施例中,間距P1小至3.0μm。在一些實施例中,間距P1在從3.0μm到5.4μm的範圍內。根據在重佈通孔正上方(例如重疊)形成的結合通孔和接合墊的實施例,相鄰的重佈線和結合結構可以具有減少至少35%的最小間距。
接合墊94的頂面與最上面的介電層74的頂面共面。通過化學機械拋光(CMP)製程或機械研磨製程實現平坦化。
如圖15所示,在後續的單體化製程之前,通過對基底22進行減薄來對積體電路晶粒20進行減薄。可以通過諸如機械研磨製程或CMP製程的平坦化製程來執行減薄。減薄製程暴露了TSV44和襯層38。在減薄之後,通孔44提供從基底22的背面到基底22的正面的電連接(例如,內連線結構24和50以及接合墊94)。
圖16顯示了封裝結構100。封裝結構100包括類似於積體電路晶粒20的基底22的基底102以及包括接合墊106的內連線結構104。內連線結構104和接合墊106可以分別與上述的內連線結構24和50和接合墊94類似,在此不再贅述。
在圖17中,積體電路晶粒20連接到封裝結構100。積體電路晶粒20與封裝結構100的接合可以通過混合接合來實現,其中形成金屬對金屬的直接接合(在接合墊94和106之間)和介電質對介電質的接合(例如表面之間的Si-O-Si接合)積體電路晶粒20和封裝結構100中的介電層)。此外,可以有單個或多個積體電路晶粒20接合到同一封裝結構100的晶粒20。接合到相同封裝結構100的多個晶粒20可以彼此相同或不同,以形成同質或異質結構。
晶粒20被設置為面朝下,使得晶粒20的正面面向封裝結構100並且晶粒20的背面背向封裝結構100。晶粒20以介面108接合到封裝結構100。如圖16所示,混合接合製程通過熔合將封裝結構100的內連線結構104的最頂部介電層直接接合到介面108處的晶粒20的最頂部介電層90。在一個實施例中,內連線結構104的最頂部介電層和晶粒20的最頂部介電層90之間的結合可以是氧化物-氧化物結合。混合接合製程進一步通過直接金屬對金屬接合將晶粒20的接合墊94與介面108處的封裝結構100的接合墊106直接接合。因此,晶粒20和封裝結構100之間的電連接可以通過接合墊94到接合墊106的物理連接來提供。
作為示例,混合接合製程首先將晶粒20與封裝結構100對齊,例如,通過將接合墊94與接合墊106對齊。當晶粒20和封裝結構100對齊時,接合墊94可以與對應的接合墊106重疊。接下來,混合接合包括預接合步驟,在該步驟中,晶粒20與封裝結構100接觸。混合接合製程接著進行退火,例如在大約150°C和大約400°C之間的溫度下持續大約0.5小時和大約3小時之間的持續時間,以使接合墊94和接合墊106中的銅彼此相互擴散,因此形成直接的金屬對金屬接合。
接下來,如圖18所示,執行間隙填充製程,以將積體電路晶粒20包封在包封體110中。形成包封體110之後,包封體110包封了積體電路晶粒20。包封體110可以包括氧化物。或者,包封體110可以是模塑料、模塑底部填充物、樹脂、環氧樹脂等。可以通過壓縮成型、轉移成型等來施加包封體110,並且可以以液體或半液體形式施加包封體110,然後隨後固化包封體110。在沉積包封體110之後,執行平坦化製程以使積體電路晶粒20的背面與包封體110的頂面齊平並暴露TSV44。在平坦化製程之後,TSV44、基底22和包封體110的表面在製程變化內實質上共面。平坦化製程可以是例如CMP、研磨製程等。在一些實施例中,例如,TSV44已經暴露,則可以省略平坦化。
在圖19中,重佈結構112沉積在包封體110、TSV44和積體電路晶粒20上。重佈結構112可以包括重佈線(RDL),例如金屬跡線(或金屬線)以及位於金屬跡線下方並連接到金屬跡線的通孔。重佈結構112的重佈線物理連接和電連接到晶粒20的TSV44。
根據本公開的一些實施例,RDL通過電鍍製程形成,其中每個RDL包括晶種層(未示出)和晶種層上方的電鍍金屬材料。晶種層可以使用例如PVD等形成。然後在晶種層上形成光阻並圖案化光阻。光阻可以通過旋塗等形成並且可以曝光以進行圖案化。光阻的圖案對應於RDL。圖案化通過光阻形成暴露晶種層的開口。在光阻的開口中和晶種層的經暴露部分上形成導電材料。導電材料可以通過電鍍形成,例如電鍍或化學鍍等。晶種層和電鍍金屬材料可以由相同材料或不同材料形成。導電材料可以是金屬,例如銅、鈦、鎢、鋁等。然後,去除光阻和其上未形成有導電材料的晶種層部分。可以通過可接受的灰化或剝離製程去除光阻,例如使用氧電漿等。一旦光阻被去除,可以例如通過使用可接受的蝕刻製程(例如通過濕式和/或乾式蝕刻)去除晶種層的經暴露部分。晶種層和導電材料的其餘部分形成RDL。
可以在金屬跡線的每一層上形成介電質或鈍化層。在一些實施例中,介電質或鈍化層由聚合物形成,該聚合物可以是可以使用微影罩幕圖案化的諸如PBO、聚酰亞胺、BCB等的感光材料。在其他實施例中,介電質或鈍化層由氮化矽等氮化物、氧化矽、PSG、BSG、BPSG等氧化物或相似者形成。介電質或鈍化層可以通過旋塗、層壓、CVD等或其組合形成。
可以通過圖案化製程在頂部介電質或鈍化層中形成開口,以暴露部分或全部重佈結構112的頂部金屬層。圖案化製程可以是可接受的製程,例如當介電層是光敏材料時,通過將介電層或鈍化層暴露於光,或通過使用例如各向異性蝕刻進行蝕刻。
如圖20所示,凸塊114是通過重佈結構112中的介電層中的開口與重佈結構112中的金屬化圖案接觸而形成的。凸塊114可以是金屬柱、可控塌陷晶片連接(C4)凸塊、微型凸塊、化學鎳鈀金技術(ENEPIG)形成的凸塊、球格陣列(BGA)凸塊等。在一個實施例中,凸塊114是C4凸塊。凸塊114可以通過濺射、印刷、電鍍、化學鍍、CVD等形成。凸塊114可以是無焊料的並且具有實質上垂直的側壁。在一些實施例中,金屬頂蓋層(未示出)形成在凸塊114的頂部。金屬頂蓋層可以包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或它們的組合,並且可以通過電鍍製程形成。
再者,如圖20所示,導電連接件116是形成在凸塊114上。導電連接件116可由諸如焊料、銅、鋁、金、鎳、銀、鈀、錫等或它們的組合的導電材料形成。在一些實施例中,通過諸如蒸鍍、電鍍、印刷、焊料轉移、球放置等方法初始形成一層焊料來形成導電連接件116。一旦在結構上形成了焊料層,就可以進行回流以將導電連接件116成形為所需的凸塊形狀。
圖20中描繪的實施例是以面對面配置接合的晶圓上晶片結構。或者,積體電路晶粒20和封裝結構100可以以面對面的方式黏合,如圖21所示。例如,在圖21中,晶粒20的背面(例如,TSV44和基底22的暴露端)接合到封裝結構100的表面。本實施例與前述實施例類似的細節在此不再贅述。
圖22圖示了根據一些實施例的晶圓上晶圓結構的剖面圖。該實施例類似於圖1至圖19所示的實施例,除了該實施例是晶圓上晶圓結構而不是晶圓上晶片結構之外。本實施例與前述實施例類似的細節在此不再贅述。
在圖22中,該結構是以面對面配置接合的晶圓對晶圓結構,其中上部結構是包含晶粒20的晶圓。包含晶粒20的晶圓的形成與上述的晶粒20類似,在此不再贅述。在本實施例中,不再需要先前實施例中的對晶粒20進行單體化和形成包封體110的步驟,並且這些步驟可以從本實施例中省略。在本實施例中,包含晶粒20的晶圓與封裝結構100均為晶圓且尺寸相同。
在其他實施例中,包含晶粒20的晶圓可以以面對面配置結合到封裝結構100。例如,包含晶粒20的晶圓的背面(例如,TSV44和基底22的暴露端)可以接合到封裝結構100的表面。
圖23、圖24A、圖24B、圖25和圖26示出了根據各種實施例的重佈線和接合墊結構的剖面圖和平面圖。在圖23中,顯示了沒有鈍化層和介電層的相鄰重佈線和接合墊結構的詳細視圖。圖23包括頂部金屬56、重佈通孔60、重佈墊62’、接合墊通孔92和接合墊94。重佈通孔60具有寬度W4。在一些實施例中,寬度W4小至0.7μm。在一些實施例中,寬度W4在從0.7μm到2.7μm的範圍內。
相鄰的重佈線和接合結構的最小間距為距離D1。在一些實施例中,距離D1小至1.2μm。在一些實施例中,距離D1在從1.2μm到1.8μm的範圍內。重佈墊62’和覆蓋接合墊通孔92的側壁偏移一段距離D2。在一些實施例中,距離D2小至0.1μm。在一些實施例中,距離D2在從0.1μm到0.7μm的範圍內。重佈通孔60和覆蓋重佈墊62’的側壁偏移一段距離D3。在一些實施例中,距離D3小至0.1μm。在一些實施例中,距離D3在從0.1μm到0.5μm的範圍內。
圖24A和圖24B示出了與圖23類似的剖面圖,並且在此不再重複描述。在圖24A中,接合墊通孔92和接合墊94與重佈通孔60部分重疊,而不是如圖23所示的接合墊通孔92和接合墊94中的每一個都與重佈通孔60完全重疊。在圖24B中,重佈墊、接合墊通孔92和接合墊94與重佈通孔60部分重疊,而不是如圖23所示的接合墊通孔92和接合墊94中的每一個都與重佈通孔60完全重疊。
圖25示出了與圖23相似的剖面圖並且在此不再重複描述。在圖25中,重佈墊62’是通過鑲嵌製程形成的。圖26顯示了重佈通孔60、重佈墊62’、接合墊通孔92和接合墊94的平面圖。如圖所示,在一些實施例中,接合墊通孔92和接合墊94與重佈通孔60和重佈墊62’完全重疊。
圖27至圖32示出了根據一些實施例的形成積體電路晶粒20的中間階段的剖面圖。該實施例類似於圖1至圖26中的實施例。在本實施例中,重佈墊和重佈通孔由同一製程同時形成,並包括平坦化步驟。本實施例與前述實施例類似的細節在此不再贅述。
圖27處於與圖7類似的過程中間階段,此處不再重複描述。圖27和圖7的區別在於重佈通孔尚未形成在開口130中。
在圖28中,在鈍化層58上方、開口130中以及開口130中頂部金屬56的經暴露部分上形成重佈墊層132。重佈墊層132具有頂面132A。在一些實施例中,重佈墊層132通過共形製程形成,因此頂面132A與底表面一致。在一些實施例中,重佈墊層132的頂面132A不是平坦的並且可能在開口130上具有凹陷或低點。重佈墊層132的材料和形成製程與上述的重佈墊層62類似,在此不再贅述。
在圖29中,在重佈墊層132上形成光阻134並圖案化光阻134。此外,在圖29中,經圖案化的光阻134用作罩幕以圖案化重佈墊層132以形成重佈墊136。這些步驟與上述圖9和圖10所示的步驟類似,在此不再贅述。
如圖30所示,重佈墊136的頂面136A不是平坦的,可能在開口130上方具有凹陷或低點。在圖31中,對重佈墊136的頂面136A進行平坦化處理,為重佈墊136提供平坦的頂面136A。平坦化製程例如可以是化學機械拋光(CMP)、研磨製程等,並且可以減小重佈墊136的厚度。通過使重佈墊的頂面136A為平坦表面或水平表面,上覆於墊的通孔和接合墊可以形成在重佈通孔正上方,並且可以使最小間距減少至少35%。
圖32圖示了對圖31的結構的後續處理,該處理類似於上面在圖11至圖14中描述和圖示的處理,這裡不再重複描述。圖32中的結構可以經歷後續處理並包括在封裝結構中,如上文在圖17至圖22中描述和圖示的,並且在此不再重複描述。
圖33至圖38示出了根據一些實施例的形成積體電路晶粒20的中間階段的剖面圖。該實施例類似於圖1至圖26中的實施例。在本實施例中,重佈墊和重佈通孔是通過相同的製程同時形成的。此外,在該實施例中,重佈墊和重佈通孔是通過雙鑲嵌製程形成的。本實施例與前述實施例類似的細節在此不再贅述。
圖33處於與圖7類似的過程中間階段,此處不再重複描述。圖33和圖7的區別在於重佈通孔尚未形成在開口130中。
在圖34中,在鈍化層58上方、開口130中以及開口130中的頂部金屬56的經暴露部分上形成晶種層140。晶種層140的材料和形成製程與上述的晶種層40類似,在此不再贅述。
在圖35中,在晶種層140上形成光阻142並圖案化光阻142。這些步驟與上述說明的步驟類似,在此不再贅述。
在圖36中,導電材料144形成在位於光阻142的開口中的經暴露晶種層140上。導電材料144的材料和形成製程與上述的導電材料42類似,在此不再贅述。
在圖37中,移除光阻142和晶種層140的下面部分,以形成重佈墊146。光阻142可以通過可接受的灰化或剝離製程去除,例如使用氧電漿等。晶種層140的部分可以通過可接受的蝕刻製程去除。通過使重佈墊146中的頂面具有平坦表面或水平表面,上覆於墊的通孔和接合墊可以形成在重佈通孔正上方,並且可以使最小間距減少至少35%。
圖38示出了對圖37結構的後續處理,該處理類似於上面在圖11至圖14中描述和示出的處理,這裡不再重複描述。圖38中的結構可以經歷後續處理並包括在封裝結構中,如上文在圖17至圖22中描述和圖示的,並且在此不再重複描述。
也可以包括其他特徵和過程。例如,可以包括測試結構以幫助對3D封裝或3DIC裝置進行驗證測試。測試結構可包括例如形成在重佈線層中或基底上的測試墊,其允許使用探針和/或探針卡等測試3D封裝或3DIC。驗證測試可以在中間結構以及最終結構上執行。此外,本文公開的結構和方法可以與合併已知良好晶粒的中間驗證的測試方法結合使用,以提高產量並降低成本。
實施例可以實現優點。本文討論的實施例可以在特定上下文中討論,即可以集成到裝置(例如,晶片或晶粒)或封裝(例如,晶圓上晶片(CoW)封裝結構或晶圓上的重佈結構-晶圓(矽)封裝結構)。重佈結構包括一個重佈通孔,其具有水平或平坦的上表面和上覆墊,以允許相鄰重佈通孔和上覆墊之間的較小間距和最小距離。在一些實施例中,使用例如單鑲嵌製程與上覆墊分開形成重佈通孔。在一些實施例中,重佈通孔與上覆墊是在相同的製程中形成的,例如使用雙鑲嵌製程,隨後進行平坦化製程以使上覆墊的上表面變平或變平坦。通過使重佈通孔的頂面和/或上覆墊的頂面為平坦表面或水平表面,上覆於墊的接合通孔和接合墊可以直接形成在重佈通孔上方,並且可以使最小間距減少至少35%。
實施例包括一種方法,該方法包括在第一基底上形成第一內連線結構,所述第一內連線結構包括介電層以及位於所述介電層中的金屬化圖案。該方法還包括在所述第一內連線結構上形成重佈通孔,所述重佈通孔電耦合到所述第一內連線結構的所述金屬化圖案中的至少一個。該方法還包括在所述重佈通孔上形成重佈墊,所述重佈墊電耦合到所述重佈通孔。該方法還包括在所述重佈墊上形成第一介電層。該方法還包括在所述第一介電層上形成第二介電層。該方法還包括圖案化所述第一介電層和所述第二介電層。該方法還包括在所述重佈墊上且在所述第一介電層中形成接合通孔,所述接合通孔電耦合到所述重佈墊且所述接合通孔與所述重佈通孔重疊。該方法還包括在所述接合通孔上且在所述第二介電層中形成第一接合墊,所述第一接合墊電耦合到所述接合通孔。
實施例可以包括以下特徵中的一個或多個。所述重佈通孔和所述重佈墊各自在鑲嵌製程中形成。所述重佈通孔和所述重佈墊由單次沉積製程形成。所述重佈墊的整個頂面上是平坦的。在所述重佈通孔上形成所述重佈墊進一步包括沉積導電材料;以及對所述導電材料的頂面進行平坦化製程以形成具有平坦頂面的所述重佈墊。所述重佈墊具有與所述重佈通孔不同的材料成分。所述第一接合墊與所述重佈通孔重疊。該方法還包括圖案化所述第一內連線結構以形成暴露所述第一基底的一部分的第一開口,在所述第一開口中沉積襯層,用導電材料填充所述第一開口,以及減薄所述第一基底以暴露所述第一開口中的所述導電材料的一部分,所述導電材料延伸通過所述第一內連線結構和所述第一基底,以形成基底穿孔。該方法還包括混合接合所述第二介電層和所述第一接合墊到封裝結構的第三介電層和第二接合墊,所述封裝結構包括第二基底和在所述第二基底上的第二內連線結構,所述第三介電層和所述第二接合墊是所述第二內連線結構的一部分。該方法還包括在將所述第二介電層和所述第一接合墊混合接合到所述封裝結構的所述第三介電層和所述第二接合墊之後,在所述第一基底上形成第一重佈結構,所述第一重佈結構包括第四介電層和位於所述第四介電層中的第一金屬化圖案,所述第一重佈結構的所述第一金屬化圖案電耦合到所述基底穿孔,以及在所述第一重佈結構上形成一組第一導電凸塊,所述第一導電凸塊電耦合到所述第一重佈結構。該方法還包括在形成所述第一重佈結構之前,以包封體包封所述第一基底、所述第一內連線結構、所述第一介電層和所述第二介電層,其中所述第一重佈結構形成在所述包封體上。
實施例包括一種方法,該方法包括在第一基底上形成第一介電層,其中所述第一介電層中具有第一金屬化圖案。該方法還包括在位於所述第一介電層上的第二介電層中形成第一通孔,所述第一通孔電耦合到所述第一金屬化圖案。該方法還包括在所述第一通孔和所述第二介電層上形成導電墊,所述導電墊電耦合到所述第一通孔。該方法還包括在位於所述導電墊和所述第二介電層上的第三介電層中形成接合通孔,所述接合通孔電耦合到所述導電墊,所述接合通孔與所述第一通孔重疊。該方法還包括在位於所述接合通孔和所述第三介電層上的第四介電層中形成第一接合墊,所述第一接合墊電耦合到所述接合通孔,所述第一接合墊與所述第一通孔重疊。
實施例可以包括以下特徵中的一個或多個。該方法還包括進行鑲嵌製程以在所述第二介電層中形成所述第一通孔,在所述第一通孔和所述第二介電層上沉積第一導電材料,在所述第一導電材料上形成罩幕,以及使用所述罩幕圖案化所述第一導電材料,以在所述第一通孔上形成所述導電墊。所述第一通孔和所述導電墊通過單次沉積製程形成。在所述單次沉積製程之後,對所述導電墊進行平坦化製程,以形成具有平坦頂面的所述導電墊,其中在所述平坦化製程之前,所述導電墊具有非平坦的頂面。該方法進一步包括在所述第一介電層上形成第一圖案化罩幕,使用所述第一圖案化罩幕作為罩幕進行蝕刻製程,所述蝕刻製程形成穿過所述第一介電層和部分地穿過所述第一基底的第一開口,在所述第一開口中形成襯層,用導電材料填充所述第一開口,並且減薄所述第一基底以暴露所述第一開口中的所述導電材料的一部分,所述導電材料延伸穿過所述第一介電層和所述第一基底,以形成基底穿孔。該方法還包括將所述第四介電層和所述第一接合墊混合接合到封裝結構的第五介電層和第二接合墊,所述封裝結構包括第二基底。
實施例包括在第一基底上包括第一內連線結構,在第一基底上,所述第一內連線結構包括介電層和位於所述介電層中的金屬化圖案。該結構還包括基底穿孔,延伸穿過所述第一內連線結構和所述第一基底。該結構還包括重佈通孔,在所述第一內連線結構上,所述重佈通孔電耦合到所述第一內連線結構的所述金屬化圖案中的至少一個。該結構還包括重佈墊,在所述重佈通孔上,所述重佈墊與所述重佈通孔電耦合。該結構還包括接合通孔,在所述重佈墊上,所述接合通孔電耦合到所述重佈墊,所述接合通孔與所述重佈通孔重疊。該結構還包括第一接合墊,在所述接合通孔上,所述第一接合墊電耦合到所述接合通孔,所述第一接合墊與所述重佈通孔重疊。
實施例可以包括以下特徵中的一個或多個。所述重佈墊的整個頂面是平坦的。所述重佈通孔和所述重佈墊是連續導電結構。
前文概述若干實施例的特徵,以使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解,其可容易地使用本揭露作為設計或修改用於執行本文中所引入的實施例的相同目的及/或實現相同優勢的其他製程及結構的基礎。所屬領域中具有通常知識者亦應認識到,此類等效構造不脫離本揭露的精神及範疇,且所屬領域中具有通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
20:晶粒
22,102:基底
23,24,50,104:內連線結構
30:罩幕
34,78,82,130:開口
38:襯層
40,140:晶種層
42,144:導電材料
44:基底穿孔
52,70,72,74:介電層
54:金屬化圖案和通孔
56:頂部金屬
58:鈍化層
60:重佈通孔
62,132:重佈墊層
62’:重佈墊
64,76,80,134,142:光阻
91:阻障層
92:接合墊通孔
94,106:接合墊
100:封裝結構
108:介面
110:包封體
112:重佈結構
114:凸塊
116:導電連接件
132A,136A:頂面
136,146:重佈墊
D1,D2,D3:距離
P1:間距
W1,W2,W3,W4:寬度
在結合隨附圖式閱讀下方詳細描述時會最佳地理解本揭露的態樣。應注意,根據業界中的標準慣例,各種特徵未按比例繪製。實際上,可出於論述清楚起見而任意增大或減小各種特徵的尺寸。
圖1至20示出了根據一個實施例的封裝形成的中間階段的剖面圖。
圖21示出了根據一個實施例的封裝形成的中間階段的剖面圖。
圖22示出了根據一個實施例的封裝形成的中間階段的剖面圖。
圖23、圖24A、圖24B、圖25和圖26示出了根據實施例的重佈結構的剖面圖和平面圖。
圖27至圖32示出了根據一個實施例的封裝形成中的中間階段的剖面圖。
圖33至圖38示出了根據一個實施例的封裝形成的中間階段的剖面圖。
56:頂部金屬
60:重佈通孔
62’:重佈墊
92:接合墊通孔
94:接合墊
D1,D2,D3:距離
P1:間距
W1,W2,W3,W4:寬度
Claims (20)
- 一種半導體裝置的形成方法,包括: 在第一基底上形成第一內連線結構,所述第一內連線結構包括介電層以及位於所述介電層中的金屬化圖案; 在所述第一內連線結構上形成重佈通孔,所述重佈通孔電耦合到所述第一內連線結構的所述金屬化圖案中的至少一個; 在所述重佈通孔上形成重佈墊,所述重佈墊電耦合到所述重佈通孔; 在所述重佈墊上形成第一介電層; 在所述第一介電層上形成第二介電層; 圖案化所述第一介電層和所述第二介電層; 在所述重佈墊上且在所述第一介電層中形成接合通孔,所述接合通孔電耦合到所述重佈墊且所述接合通孔與所述重佈通孔重疊;以及 在所述接合通孔上且在所述第二介電層中形成第一接合墊,所述第一接合墊電耦合到所述接合通孔。
- 如請求項1所述的方法,其中所述重佈通孔和所述重佈墊各自在鑲嵌製程中形成。
- 如請求項1所述的方法,其中所述重佈通孔和所述重佈墊由單次沉積製程形成。
- 如請求項1所述的方法,其中所述重佈墊的整個頂面上是平坦的。
- 如請求項1所述的方法,其中在所述重佈通孔上形成所述重佈墊進一步包括: 沉積導電材料;以及 對所述導電材料的頂面進行平坦化製程以形成具有平坦頂面的所述重佈墊。
- 如請求項1所述的方法,其中所述重佈墊具有與所述重佈通孔不同的材料成分。
- 如請求項1所述的方法,其中所述第一接合墊與所述重佈通孔重疊。
- 如請求項1所述的方法,進一步包括: 圖案化所述第一內連線結構以形成暴露所述第一基底的一部分的第一開口; 在所述第一開口中沉積襯層; 用導電材料填充所述第一開口;以及 減薄所述第一基底以暴露所述第一開口中的所述導電材料的一部分,所述導電材料延伸通過所述第一內連線結構和所述第一基底,以形成基底穿孔。
- 如請求項8所述的方法,進一步包括: 混合接合所述第二介電層和所述第一接合墊到封裝結構的第三介電層和第二接合墊,所述封裝結構包括第二基底和在所述第二基底上的第二內連線結構,所述第三介電層和所述第二接合墊是所述第二內連線結構的一部分。
- 如請求項9所述的方法,進一步包括: 在將所述第二介電層和所述第一接合墊混合接合到所述封裝結構的所述第三介電層和所述第二接合墊之後,在所述第一基底上形成第一重佈結構,所述第一重佈結構包括第四介電層和位於所述第四介電層中的第一金屬化圖案,所述第一重佈結構的所述第一金屬化圖案電耦合到所述基底穿孔;以及 在所述第一重佈結構上形成一組第一導電凸塊,所述第一導電凸塊電耦合到所述第一重佈結構。
- 如請求項10所述的方法,進一步包括: 在形成所述第一重佈結構之前,以包封體包封所述第一基底、所述第一內連線結構、所述第一介電層和所述第二介電層,其中所述第一重佈結構形成在所述包封體上。
- 一種半導體裝置的形成方法,包括: 在第一基底上形成第一介電層,其中所述第一介電層中具有第一金屬化圖案; 在位於所述第一介電層上的第二介電層中形成第一通孔,所述第一通孔電耦合到所述第一金屬化圖案; 在所述第一通孔和所述第二介電層上形成導電墊,所述導電墊電耦合到所述第一通孔; 在位於所述導電墊和所述第二介電層上的第三介電層中形成接合通孔,所述接合通孔電耦合到所述導電墊,所述接合通孔與所述第一通孔重疊;以及 在位於所述接合通孔和所述第三介電層上的第四介電層中形成第一接合墊,所述第一接合墊電耦合到所述接合通孔,所述第一接合墊與所述第一通孔重疊。
- 如請求項12所述的方法,進一步包括: 進行鑲嵌製程以在所述第二介電層中形成所述第一通孔; 在所述第一通孔和所述第二介電層上沉積第一導電材料; 在所述第一導電材料上形成罩幕;以及 使用所述罩幕圖案化所述第一導電材料,以在所述第一通孔上形成所述導電墊。
- 如請求項12所述的方法,其中所述第一通孔和所述導電墊通過單次沉積製程形成。
- 如請求項14所述的方法,進一步包括: 在所述單次沉積製程之後,對所述導電墊進行平坦化製程,以形成具有平坦頂面的所述導電墊,其中在所述平坦化製程之前,所述導電墊具有非平坦的頂面。
- 如請求項12所述的方法,進一步包括: 在所述第一介電層上形成第一圖案化罩幕; 使用所述第一圖案化罩幕作為罩幕進行蝕刻製程,所述蝕刻製程形成穿過所述第一介電層和部分地穿過所述第一基底的第一開口; 在所述第一開口中形成襯層; 用導電材料填充所述第一開口;以及 減薄所述第一基底以暴露所述第一開口中的所述導電材料的一部分,所述導電材料延伸穿過所述第一介電層和所述第一基底,以形成基底穿孔。
- 如請求項12所述的方法,進一步包括: 將所述第四介電層和所述第一接合墊混合接合到封裝結構的第五介電層和第二接合墊,所述封裝結構包括第二基底。
- 一種半導體裝置,包括: 第一內連線結構,在第一基底上,所述第一內連線結構包括介電層和位於所述介電層中的金屬化圖案; 基底穿孔,延伸穿過所述第一內連線結構和所述第一基底; 重佈通孔,在所述第一內連線結構上,所述重佈通孔電耦合到所述第一內連線結構的所述金屬化圖案中的至少一個; 重佈墊,在所述重佈通孔上,所述重佈墊與所述重佈通孔電耦合; 接合通孔,在所述重佈墊上,所述接合通孔電耦合到所述重佈墊,所述接合通孔與所述重佈通孔重疊;以及 第一接合墊,在所述接合通孔上,所述第一接合墊電耦合到所述接合通孔,所述第一接合墊與所述重佈通孔重疊。
- 如請求項18所述的半導體裝置,其中所述重佈墊的整個頂面是平坦的。
- 如請求項18所述的半導體裝置,其中所述重佈通孔和所述重佈墊是連續導電結構。
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