TW202137345A - 具有小晶片中介物的晶圓上晶片結構 - Google Patents

具有小晶片中介物的晶圓上晶片結構 Download PDF

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TW202137345A
TW202137345A TW109135503A TW109135503A TW202137345A TW 202137345 A TW202137345 A TW 202137345A TW 109135503 A TW109135503 A TW 109135503A TW 109135503 A TW109135503 A TW 109135503A TW 202137345 A TW202137345 A TW 202137345A
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die
intermediary
forming
semiconductor structure
molding material
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TW109135503A
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TWI756864B (zh
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陳偉銘
丁國強
侯上勇
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台灣積體電路製造股份有限公司
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Priority claimed from US16/919,298 external-priority patent/US11380611B2/en
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Abstract

本發明提供一種形成半導體結構的方法，方法包含：將第一晶粒及第二晶粒分別接合至第一中介物的第一側及第二中介物的第一側，其中第一中介物與第二中介物橫向相鄰；用第一模製材料包封第一中介物及第二中介物；在與第一中介物的第一側相對的第一中介物的第二側中形成第一凹部；在與第二中介物的第一側相對的第二中介物的第二側中形成第二凹部；以及用第一介電材料填充第一凹部及第二凹部。

Description

具有小晶片中介物的晶圓上晶片結構
半導體工業已歸因於各種電子組件（例如電晶體、二極體、電阻器、電容器等）的整合密度的持續改進而經歷了快速增長。對於大多數情況，整合密度的此改進來自於最小特徵尺寸的反覆減小，此將允許更多組件整合至給定區域中。
隨著對縮小的電子元件的需求的增長，已出現對半導體晶粒的更小且更具創造性的封裝技術的需要。此類封裝系統的實例為層疊式封裝（Package-on-Package；PoP）技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部，以提供高水準的整合密度及組件密度。另一實例為基底上晶圓上晶片（Chip-On-Wafer-On-Substrate；CoWoS）結構。在一些實施例中，為形成CoWoS結構，將多個半導體晶片附接至晶圓，並且接著執行切割製程以將晶圓分成多個中介物，其中中介物中的每一者具有附接至其的一或多個半導體晶片。附接有半導體晶片的中介物被稱作晶圓上晶片（Chip-On-Wafer；CoW）結構。CoW結構隨後附接至基底（例如，印刷電路板）以形成CoWoS結構。此等及其他進階封裝技術使得能夠生產具有增強功能性及較小覆蓋面積的半導體元件。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例是為了簡化本揭露。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或第二特徵上形成第一特徵可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含在第一特徵與第二特徵之間可形成額外特徵以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。貫穿本描述，除非另外規定，否則不同圖式中的相同附圖標號指代藉由相同或類似方法使用相同或類似材料形成的相同或類似組件。
另外，為易於描述，本文中可使用諸如「在……之下（beneath）」、「在……下方（below）」、「下部（lower）」、「在……上方（above）」、「上部（upper）」以及類似者的空間相對術語來描述如圖式中所示出的一個部件或特徵與另一（些）部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地作出解釋。
在一些實施例中，藉由形成複合中介物且將多個晶粒附接至複合中介物來形成晶圓上晶片（CoW）結構。複合中介物包括嵌入於第一模製材料中的第一中介物及第二中介物。第一重佈線結構可視情況形成於第一模製材料上方及第一中介物以及第二中介物上方。在多個晶粒附接至複合中介物之後，第二模製材料圍繞多個晶粒形成。接著，第一中介物及第二中介物中的每一者自遠離晶粒的一側經薄化。在薄化製程之後，凹部形成於第一中介物及第二中介物中的每一者的遠離晶粒的一側中，其中凹部暴露相應中介物（第一中介物或第二中介物）中的穿孔的端部部分。接著，介電材料（例如，聚合物材料）形成於凹部中。隨後，介電層形成於介電材料上方，且外部連接件形成於介電層上方且電耦接至第一中介物及第二中介物的穿孔。
圖1至圖9示出在實施例中的在各個製造階段的晶圓上晶片（CoW）結構100的橫截面圖。參看圖1，兩個中介物110例如藉由黏著劑層151附接至載體150。載體150可由合適的材料（諸如矽、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、膠帶或用於結構支撐的其他合適的材料）製成。在一些實施例中，黏著劑層151沈積於載體150上方或疊層於載體150上方。黏著劑層151可為感光性的且可在後續載體剝離製程中藉由例如在載體150上照射紫外線（ultra-violet；UV）光而容易地與載體150分離。舉例而言，黏著劑層151可為光熱轉換（light-to-heat-conversion；LTHC）塗層。
中介物110中的每一者包含：基底101、基底101中的穿孔103（亦稱作通孔、基底穿孔（through-substrate via；TSV）或導電柱）、基底101的第一表面101A上方的重佈線結構107以及位於重佈線結構107上方且電耦接至重佈線結構107的導電墊109。圖1亦示出形成於基底101（例如，接近第一表面101A）中的電組件105。
基底101可為例如經摻雜或未經摻雜的矽基底或絕緣層上矽（silicon-on-insulator；SOI）基底的主動層。然而，替代地，基底101可為玻璃基底、陶瓷基底、聚合物基底或可提供合適的保護及/或內連功能性的任何其他基底。在所示出實施例中，基底101為矽基底（例如，塊狀矽基底）。
在一些實施例中，基底101包含電組件105，諸如電阻器、電容器、訊號分佈電路系統、經設計成實現特定功能（例如，訊號處理功能或邏輯功能）的電路系統、此等電組件之組合，或類似物。此等電組件可為主動的、被動的，或其組合。在其他實施例中，基底101在其中不含主動電組件及被動電組件兩者。所有此類組合全部意欲包含於本揭露的範疇內。在所示出實施例中，電組件105（諸如深溝渠電容器（deep trench capacitor；DTC））形成於基底101中。可形成多個DTC，且所述多個DTC並聯連接以提供較大電容且顯著地增加電容密度，從而允許建構諸如較高品質的電力輸送網路（power delivery network；PDN）的各種元件。
穿孔103自基底101的第一表面101A朝向基底101的第二表面101B延伸，但不會到達所述第二表面101B。在後續基底薄化製程中，基底101自第二表面101B經薄化，以使得穿孔103暴露於第二表面101B處（例如，延伸穿過基底101）。穿孔103可由合適的導電材料（諸如銅、鎢、鋁、合金、其組合以及類似物）形成。障壁層104（在圖1中未繪示但在圖9中示出）可形成於穿孔103與基底101之間。障壁層104可包括合適的導電材料，諸如氮化鈦，但替代地，亦可利用其他材料，諸如氮化鉭、鈦或類似物。在一些實施例中，障壁層104由介電材料（諸如SiO2 或SiN）形成。作為實例，穿孔103的寬度（例如，直徑）在約2微米與約50微米之間。
仍參看圖1，重佈線結構107形成於中介物110中的每一者上方。重佈線結構107包括導電特徵，諸如形成於一或多個介電層中的導電線及通孔的一或多個層。為簡單起見，重佈線結構107的導電特徵及介電層並未在圖1中單獨地示出。在一些實施例中，重佈線結構107在穿孔103、電組件105以及導電墊109之間提供電連接。
在一些實施例中，重佈線結構107的一或多個介電層由聚合物（諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似物）形成。在其他實施例中，介電層由以下各物形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽玻璃（borosilicate glass；BSG）或摻硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）；或類似物。一或多個介電層可藉由任何可接受的沈積製程（諸如旋轉塗佈、化學氣相沈積（chemical vapor deposition；CVD）、層壓、類似製程，或其組合）來形成。
在一些實施例中，重佈線結構107的導電特徵包括由合適的導電材料（諸如銅、鈦、鎢、鋁或類似物）形成的導電線及/或導通孔。可藉由例如以下步驟來形成導電特徵：在介電層中形成開口以暴露下伏導電特徵；在介電層上方且在開口中形成晶種層；在晶種層上方形成具有所設計圖案的經圖案化光阻；在所設計圖案中及晶種層上方鍍覆（例如，電鍍或無電式鍍覆）導電材料；以及移除其上未形成導電材料的光阻及晶種層的部分。用於形成重佈線結構107的導電特徵的其他方法是可能的，且意欲完全包含於本揭露的範疇內。
導電墊109形成於重佈線結構107的導電特徵上方且電耦接至所述導電特徵。導電墊109可屬於任何合適的類型，諸如微凸塊、銅柱、銅層、鎳層、無鉛（lead free；LF）層、化學鍍鎳鈀浸金（electroless nickel electroless palladium immersion gold；ENEPIG）層、Cu/LF層、Sn/Ag層、Sn/Pb、此等導電墊的組合，或類似物。
在圖1的實例中，重佈線結構107經形成為具有與基底101相同的寬度W1，以使得重佈線結構107的側壁與基底101的相應側壁對準。在一些實施例中，寬度W1在約1毫米與約52毫米之間。儘管圖1示出用於形成CoW結構100的兩個中介物110，但如所屬領域的技術人員將容易瞭解，其他數目的中介物110亦可用於形成CoW結構100。
接著，在圖2中，模製材料108圍繞中介物110形成於載體150上方，且重佈線結構112形成於模製材料108及中介物110上方。導電連接件114形成於重佈線結構112上方。
作為實例，模製材料108可包括環氧樹脂、有機聚合物、添加有或不添加二氧化矽類填充劑或玻璃填充劑之聚合物，或其他材料。在一些實施例中，模製材料108包括在塗覆時為凝膠型液體的液態模製化合物（liquid molding compound；LMC）。模製材料108在塗覆時亦可包括液態或固態。替代地，模製材料108可包括其他絕緣及/或包封材料。在一些實施例中，使用晶圓級模製製程來塗覆模製材料108。可使用例如壓縮模製、轉移模製、經模製底填充（molded underfill；MUF）或其他方法來模製模製材料108。
接著，在一些實施例中，使用固化製程來固化模製材料108。固化製程可包括：使用退火製程或其他加熱製程在預定時間段內將模製材料108加熱至預定溫度。固化製程亦可包括紫外（UV）光曝光製程、紅外（infrared；IR）能量曝光製程、其組合，或其與加熱製程的組合。替代地，可使用其他方法來固化模製材料108。在一些實施例中，不包含固化製程。
在形成模製材料108之後，可執行平坦化製程（諸如化學及機械平坦化（chemical and mechanical planarization；CMP））以移除模製材料108的多餘部分，使得模製材料108及導電墊109具有共面的上部表面。如圖2中所示出，模製材料108包圍且實體地接觸中介物110的側壁。
接著，重佈線結構112形成於模製材料108的上部表面上方且電耦接至導電墊109。重佈線結構112包含形成於一或多個介電層113中的導電特徵111（例如，導電線及/或通孔）的一或多個層。重佈線結構112的材料及形成方法可與重佈線結構107的材料及形成方法相同或類似，因此不重複細節。在圖2的實例中，重佈線結構112形成為與模製材料108相連（例如，與模製材料108具有相同寬度），使得重佈線結構112的側壁與模製材料108的相應側壁對準。圖2中的重佈線結構112自左側上的中介物110連續地延伸至右側上的中介物110。
接著，導電連接件114形成於重佈線結構112上方且電耦接至重佈線結構112的導電特徵111。導電連接件114可屬於任何合適的類型，諸如微凸塊、銅柱、銅層、鎳層、無鉛（LF）層、化學鍍鎳鈀浸金（ENEPIG）層、Cu/LF層、Sn/Ag層、Sn/Pb、此等導電連接件的組合，或類似物。焊料區115可形成於導電連接件114上方，如圖2中所示出。
在圖2的實例中，中介物110、模製材料108、重佈線結構112以及導電連接件114形成在CoW結構100中用作中介物的複合中介物160。由於多個中介物110用於形成複合中介物160，因此中介物110中的每一者亦可稱作小晶片中介物。
接著，在圖3中，半導體晶粒121（亦稱作晶粒或積體電路（integrated circuit；IC）晶粒）例如經由回焊製程附接至導電連接件114，使得晶粒121的晶粒連接件117接合至導電連接件114中的相應導電連接件。在一些實施例中，晶粒121可屬於不同類型。舉例而言，晶粒121中的一者可為邏輯晶粒，而另一晶粒121可為記憶體晶粒。在一些實施例中，所有晶粒121皆屬於相同類型。在圖3的實例中，晶粒121中的一者（例如，位於中部的晶粒121A）與左側上的中介物110交疊且與右側上的中介物110交疊。換言之，晶粒121A的第一部分安置於左側上的中介物110的橫向範圍內，且晶粒121A的第二部分安置於右側上的中介物110的橫向範圍內。
晶粒121中的每一者包含基底、形成於基底中/上的電組件（例如，電晶體、電阻器、電容器、二極體或類似物）以及基底上方的內連線結構，所述內連線結構連接電組件以形成晶粒121的功能電路。晶粒121亦包含將電連接提供至晶粒121的電路的晶粒連接件117。
晶粒121的基底可為經摻雜或未經摻雜的半導體基底或絕緣層上矽（SOI）基底的主動層。一般而言，SOI基底包括半導體材料（諸如矽、鍺、矽鍺、SOI、絕緣層上矽鍺（silicon germanium on insulator；SGOI），或其組合）層。可使用的其他基底包含多層基底、梯度基底或混合定向基底。
晶粒121的電組件包括多種主動元件（例如，電晶體）及被動元件（例如，電容器、電阻器、電感器）以及類似物。可在晶粒121的基底內或基底上使用任何合適的方法來形成晶粒121的電組件。晶粒121的內連線結構包括形成於一或多個介電層中的一或多個金屬化層（例如，銅層），且所述內連線結構用於連接各種電組件以形成功能電路系統。在實施例中，內連線結構由介電材料及導電材料（例如，銅）的交替層形成且可經由任何合適的製程（諸如沈積、金屬鑲嵌、雙金屬鑲嵌等）來形成。
一或多個鈍化層可形成於晶粒121的內連線結構上方，以便為晶粒121的下伏結構提供一定程度的保護。鈍化層可由一或多種合適的介電材料製成，所述介電材料諸如氧化矽、氮化矽、低k介電質（諸如摻碳的氧化物）、極低k介電質（諸如多孔摻碳的二氧化矽）、此等介電材料的組合，或類似物。鈍化層可經由諸如化學氣相沈積（CVD）的製程來形成，但亦可利用任何合適的製程。
導電墊可形成於鈍化層上方且可延伸穿過待與晶粒121的內連線結構電接觸的鈍化層。導電墊可包括鋁，但替代地，可使用其他材料，諸如銅。
晶粒121的晶粒連接件117形成於導電墊上以提供用於電連接至晶粒121的電路的導電區。晶粒連接件117可為銅柱、接觸凸塊（諸如微凸塊）或類似物，且可包括諸如銅、錫、銀或其他合適的材料的材料。
接著，在圖4中，底填充材料119形成於晶粒121與複合中介物160的重佈線結構112之間且形成於相鄰晶粒121之間。在形成底填充材料119之後，模製材料118圍繞晶粒121形成於重佈線結構112上方。
底填充材料119可包括液態環氧樹脂(liquid epoxy)，所述液態環氧樹脂例如使用分配針(dispensing needle)或其他合適的分配工具經分配於晶粒121與重佈線結構112之間的間隙中，且隨後經固化以便硬化。如圖4中所示出，底填充材料119填充晶粒121與重佈線結構112之間的間隙。在一些實施例中，晶粒121附接至重佈線結構112以使得相鄰晶粒121之間的間隙小於約10微米（例如，≤10微米），從而使得經分配的底填充材料119能夠經由毛細力填充晶粒121的側壁之間的間隙。在其他實施例中，省略了底填充材料119。
接著，模製材料118形成於複合中介物160上方且圍繞晶粒121形成。模製材料118的材料及形成方法可與模製材料108的材料及形成方法相同或類似，因此不重複細節。在一些實施例中，未形成底填充材料119，且經模製底填充（MUF）材料用作模製材料118，所述MUF材料填充晶粒121與複合中介物160之間的間隙，並且填充相鄰晶粒121之間的間隙。
接著，在圖5中，翻轉圖4的結構，且晶粒121例如經由黏著劑層152附接至載體153。載體153及黏著劑層152可分別與載體150及黏著劑層151相同或類似，因此不重複細節。接著，在載體剝離製程中移除載體150。載體剝離製程可使用任何合適的製程（諸如蝕刻、研磨以及機械剝落）來移除載體150。在一些實施例中，藉由在載體150的表面上方照射雷射或UV光來剝離載體150。雷射或UV光破壞連結至載體150的黏著劑層151的化學接合，且隨後可容易地使載體150分離。可藉由載體剝離製程來移除黏著劑層151。在一些實施例中，執行額外的清潔製程以移除黏著劑層151。
在載體剝離製程之後，執行薄化製程以減小基底101的厚度及模製材料108的厚度。薄化製程可為任何合適的製程，諸如CMP製程。自藉由移除載體150而暴露的基底101的第二表面101B來執行薄化製程。薄化製程繼續進行，直至暴露穿孔103為止。因此，在薄化製程之後，穿孔103、基底101以及模製材料108在圖5中具有共面的上部表面。應注意，歸因於薄化製程，圖5中的基底101的第一表面101A與第二表面101B之間的距離（例如，基底101的厚度）小於圖1中的距離。
接著，在圖6中，經圖案化罩幕層125（諸如光阻層）形成於圖5的結構上方。經圖案化罩幕層125經形成為覆蓋（例如，完全覆蓋）圖6中的模製材料108的上部表面。另外，經圖案化罩幕層125亦覆蓋直接下伏於經圖案化罩幕層125的基底101的部分（例如，實體地接觸模製材料108的部分）。換言之，除覆蓋模製材料108的上部表面外，經圖案化罩幕層125亦與基底101的部分交疊。在一些實施例中，在經圖案化罩幕層125（其與基底101交疊）的側壁125C與基底（其接觸模製材料108）的最近側壁101S之間所量測的距離W2在約0毫米與約10毫米之間（例如，0毫米＜W2＜10毫米）。
接著，藉由經圖案化罩幕層125的開口暴露的基底101的部分（例如，上部層）經移除以在基底101的第二表面101B處形成凹部124。可執行蝕刻製程（諸如，非等向性蝕刻製程）以形成凹部124。蝕刻製程可使用對基底101的材料具有選擇性的（例如，對基底101的材料具有較高蝕刻速率的）蝕刻劑，以使得在不實質上腐蝕穿孔103及障壁層104的情況下蝕刻基底101（參見圖9）。在完成蝕刻製程之後，藉由凹部124暴露穿孔103的端部部分。換言之，穿孔103的端部部分延伸至凹部124中。在一些實施例中，在基底101的第二表面101B與凹部124的底部之間的沿著圖6的豎直方向量測的凹部124中的每一者的深度D在約0微米與約10微米之間（例如，0微米＜D＜10微米）。
接著，在圖7中，材料123（例如，介電材料）形成於凹部124中，且經圖案化罩幕層125經移除。在實例實施例中，材料123為聚合物材料（諸如聚醯亞胺）且藉由合適的形成方法（諸如，旋轉塗佈）來形成。除聚合物材料外，亦可使用任何合適的形成方法（諸如化學氣相沈積（CVD）、物理氣相沈積（physical vapor deposition；PVD）、原子層沈積（atomic layer deposition；ALD）或類似形成方法）來使用其他合適的介電材料（諸如SiN或SiO2 ）形成材料123。材料123可過量填充凹部124且可形成於模製材料108上方，且因此可執行平坦化製程（諸如CMP）以移除材料123的多餘部分，從而使得材料123、基底101、穿孔103以及模製材料108在圖7中具有共面的上部表面。作為實例，材料123在平坦化製程之後的厚度T1可在0微米與約5微米之間（例如，0微米＜T1＜5微米）。如圖7中所示出，材料123嵌入於基底101（例如，矽基底）中且具有比基底101的寬度W1更小的寬度W3（沿著水平方向量測的）。在所示出實施例中，材料123覆蓋（例如，包圍）穿孔103的端部部分的側壁。在一些實施例中，藉由使用相對廉價的形成方法（例如，旋轉塗佈）形成材料123，避開了用以圍繞穿孔103形成SiN層的後續隔離沈積製程（諸如具有高水準真空的CVD製程），藉此避免了較高成本的高真空CVD製程。
接著，在圖8中，重佈線結構126形成於材料123、基底101以及模製材料108上方，且其後，聚合物層128形成於重佈線結構126上方。外部連接件127形成於聚合物層128上方且電耦接至穿孔103。
在一些實施例中，重佈線結構126包括一或多個介電層及使用與重佈線結構112相同或類似的形成方法形成於一或多個介電層中的導電特徵（例如，導電線、通孔）。為簡單起見，在理解了重佈線結構126可具有形成於一或多個介電層中的導電特徵的一或多個層的情況下，圖8及後續圖式可將重佈線結構126繪示為單一層。在一些實施例中，省略了重佈線結構126，且聚合物層128直接形成於材料123上（例如，接觸材料123）。在一些實施例中，聚合物層128由與材料123相同的聚合物材料（諸如聚醯亞胺）形成，但聚合物層128亦可由與材料123不同的聚合物材料形成。聚合物層128可充當CoW結構100的鈍化層。作為實例，聚合物層128的厚度大於0微米且小於約20微米。
接著，外部連接件127形成於聚合物層128上方。在所示出實施例中，外部連接件127延伸穿過聚合物層128且電耦接至穿孔103。外部連接件127可為例如微凸塊、銅柱、銅層、鎳層、無鉛（LF）層、化學鍍鎳鈀浸金（ENEPIG）層、Cu/LF層、Sn/Ag層、Sn/Pb、此等外部連接件的組合，或類似物。作為實例，外部連接件127的寬度（例如，直徑）可在約20微米與約300微米之間。焊料區129可形成於外部連接件127上方，如圖8中所示出。
接著，在圖9中，例如藉由載體剝離製程來移除載體153及黏著劑層152，且形成晶圓上晶片（CoW）結構100。儘管未示出，但如所屬領域的技術人員將容易瞭解，可執行切割製程以將CoW結構100與在製造製程期間與CoW結構100同時形成的其他CoW結構分開。CoW結構100的外部連接件127隨後可接合至基底（印刷電路板（printed circuit board；PCB））以形成基底上晶圓上晶片（CoWoS）結構。
圖10示出在另一實施例中的CoW結構100A的橫截面圖。CoW結構100A與圖9的CoW結構100類似，但利用重佈線結構132替換圖9中的聚合物層128及重佈線結構126（若形成）。在一些實施例中，CoW結構100A藉由遵循圖1至圖9中的相同或類似的處理步驟來形成，但在圖8的處理步驟中，形成重佈線結構132（其包含導電特徵131及一或多個介電層133），代替聚合物層128及重佈線結構126。
圖11示出在另一實施例中的CoW結構100B的橫截面圖。CoW結構100B與圖9的CoW結構100類似，但CoW結構100B不具有形成於複合中介物160中的重佈線結構112。在一些實施例中，CoW結構100B藉由遵循圖1至圖9中的相同或類似的處理步驟來形成，但在圖2的處理步驟中，省略了重佈線結構112，且導電連接件114直接形成於相應的下伏導電墊109上。接著，針對CoW結構100B，在與圖3的處理類似的處理中，晶粒121的晶粒連接件117接合至導電連接件114。
圖12示出在又一實施例中的CoW結構100C的橫截面圖。CoW結構100C與圖10的CoW結構100A類似，但晶粒121的數目可較少，且CoW結構100C的模製材料118具有比CoW結構100A的模製材料118的寬度更小的寬度。舉例而言，在CoW結構100、CoW結構100A以及CoW結構100B中，模製材料118及模製材料108具有相同寬度，使得模製材料118的側壁與模製材料108的相應側壁對準。在CoW結構100C中，模製材料118的左側壁與模製材料108的左側壁對準，而模製材料118的右側壁並未與模製材料108的右側壁對準（例如，橫向地間隔開）。CoW結構100C中的模製材料118的形狀可藉由例如執行蝕刻製程來形成，以移除模製材料118的部分（例如，圖12中的右側上的部分）。作為另一實例，模製材料118可使用合適的形成方法（例如，注射模製製程）形成，以直接具有圖12中所示出的形狀。CoW結構100C可適用於光學連接應用，其中藉由模製材料118來暴露形成於基底101中的光波導(optical waveguide)。
實施例可實現優點。舉例而言，藉由在中介物110的基底101形成電組件105，中介物110可經設計成包含用於實現不同功能而非僅伺服於電佈線（例如在中介物中僅具有通孔及導電線）的功能的各種功能電路。隨著CoW結構的整合密度增加，可增大中介物的大小以容納附接至中介物的晶粒的數目。然而，對於中介物的平坦度，較大中介物可能需要較高標準（因此需要較高成本），以便避免與中介物的非平坦度相關的問題，諸如與冷接縫（cold joint）及應力相關的結構損壞。本揭露允許使用多個較小的小晶片(chiplet)中介物110容易地形成較大複合中介物160，因此避免了與維持較大中介物的平坦度相關聯的成本。另外，藉由形成電組件105（諸如中介物110中的DTC）且經由例如重佈線結構112電耦接所有中介物110中的DTC，可極大地增加形成於複合中介物160中的DTC的數目。作為另一實例，形成材料123消除對執行高真空CVD製程的需要，藉此降低了製造成本。
圖13至圖17示出在又一實施例中的在各個製造階段的CoW結構100D的橫截面圖。CoW結構100D與CoW結構100類似，但可利用不同的處理步驟形成。
參看圖13，半導體晶粒121例如經由黏著劑層152附接至載體153。接著，模製材料118圍繞半導體晶粒121形成於載體153上方。可執行平坦化製程（諸如CMP）以獲得半導體晶粒的晶粒連接件117與模製材料118之間的共面的上部表面。
接著，在圖14中，多個中介物110附接至晶粒121。在所示出實施例中，中介物110的導電墊109經由焊料區115接合至晶粒121的晶粒連接件117。中介物110中的每一者具有形成於其基底101中的穿孔103。在圖14中，穿孔103確實延伸穿過基底101。在後續基底薄化製程中，薄化基底101使得穿孔103延伸穿過基底101。
接著，在圖15中，模製材料108形成於模製材料118上方且圍繞中介物110形成。在圖15中，執行薄化製程（諸如研磨製程）以薄化基底101，使得穿孔103暴露於基底101的上部表面處。作為薄化製程的結果，在基底101與模製材料108之間獲得共面的上部表面。圖15進一步示出模製穿孔106，所述模製穿孔106可藉由（例如，使用雷射鑽孔製程或微影及蝕刻技術）在模製材料108中形成開口以暴露對應晶粒連接件117且使用可接受的形成方法（諸如鍍覆）用導電材料（例如，銅）填充開口來形成。圖13至圖15繪示利用兩個單獨的處理步驟形成的模製材料（例如，模製材料118及模製材料108）作為非限制性實例，用以圍繞晶粒121及圍繞中介物110形成模製材料的其他方式亦是可能的且意欲完全包含於本揭露的範疇內。在一些實施例中，在晶粒121附接至載體153之後，中介物110在形成模製材料（例如，模製材料118）之前附接至晶粒121。隨後，在附接中介物110之後，執行單一模製製程以形成包圍晶粒121及中介物110的模製材料。
接著，在圖16中，材料123圍繞（例如，接觸）穿孔103的側壁形成於基底101中。在一些實施例中，可執行圖6至圖7中示出的處理以形成材料123。在形成之後，材料123、穿孔103、基底101以及模製材料108具有共面的上部表面。
接著，在圖17中，視情況選用的重佈線結構126形成於模製材料108上方。接著，聚合物層128形成於模製材料108上方及重佈線結構126上方（若形成）。形成延伸穿過聚合物層128且電耦接至穿孔103的外部連接件127。焊料區129可形成於外部連接件127的頂部上。
圖18示出在一些實施例中的形成半導體元件的方法1000的流程圖。應理解，圖18中所繪示的實施例方法僅為許多可能的實施例方法的實例。所屬技術領域中具有通常知識者將認識到許多變化、替代物以及修改。舉例而言，可添加、移除、替換、重新配置以及重複如圖18中所示出的各種處理區塊。
參看圖18，在區塊1010處，將第一晶粒及第二晶粒分別接合至第一中介物的第一側及第二中介物的第一側，其中第一中介物與第二中介物橫向相鄰。在區塊1020處，用第一模製材料包封第一中介物及第二中介物。在區塊1030處，第一凹部形成於與第一中介物的第一側相對的第一中介物的第二側中。在區塊1040處，第二凹部形成於與第二中介物的第一側相對的第二中介物的第二側中。在區塊1050處，用第一介電材料填充第一凹部及第二凹部。
根據實施例，一種形成半導體結構的方法包含：將第一晶粒及第二晶粒分別接合至第一中介物的第一側及第二中介物的第一側，其中第一中介物與第二中介物橫向相鄰；用第一模製材料包封第一中介物及第二中介物；在與第一中介物的第一側相對的第一中介物的第二側中形成第一凹部；在與第二中介物的第一側相對的第二中介物的第二側中形成第二凹部；以及用第一介電材料填充第一凹部及第二凹部。在實施例中，方法更包含：在接合第一晶粒及第二晶粒之前，將第一中介物及第二中介物附接至載體。在實施例中，方法更包含：在接合第一晶粒及第二晶粒之後，用第二模製材料包封第一晶粒及第二晶粒。在實施例中，方法更包含：用底填充材料填充第一晶粒與第二晶粒之間的間隙。在實施例中，方法更包含：在接合第一晶粒及第二晶粒之前，將第一晶粒及第二晶粒附接至載體。在實施例中，第一模製材料進一步包封第一晶粒及第二晶粒。在實施例中，方法更包含：用第二模製材料包封第一晶粒及第二晶粒。在實施例中，方法更包含：在第一模製材料中形成穿孔。在實施例中，第一介電材料為聚合物。在實施例中，方法更包含：在第一介電材料上形成導電連接件，其中導電連接件電耦接至第一中介物中的第一導電柱。
根據實施例，一種形成半導體結構的方法包含：將第一晶粒及第二晶粒分別附接至第一中介物及第二中介物，其中在附接之後，第一晶粒與第二晶粒橫向相鄰，且第一中介物與第二中介物橫向相鄰；用第一模製材料包圍第一中介物及第二中介物；在第一中介物的遠離第一晶粒的第一表面中形成第一凹部；在第二中介物的遠離第二晶粒的第一表面中形成第二凹部；以及用聚合物層填充第一凹部及第二凹部。在實施例中，聚合物層的遠離第一晶粒的表面與第一中介物的第一表面及第二中介物的第一表面齊平。在實施例中，其中形成第一凹部包括：在第一中介物的第一表面上形成經圖案化罩幕層，其中經圖案化罩幕層覆蓋第一模製材料；覆蓋接觸第一模製材料的第一中介物的第一部分並且暴露第一中介物的第二部分；以及執行非等向性蝕刻製程以移除第一中介物的第二部分的外部層。在實施例中，第一凹部的寬度形成為小於第一中介物的寬度，使得第一凹部的側壁與接觸第一模製材料的第一中介物的相應側壁間隔開。在實施例中，第一中介物包括第一基底及第一基底中的第一基底穿孔（TSV），其中在形成第一凹部之後，第一TSV延伸至第一凹部中。
根據實施例，一種半導體結構包含：多個中介物，彼此橫向相鄰且具有基底穿孔（TSV）；第一模製材料，圍繞多個中介物；至少一個晶粒，接合且電連接至多個中介物中的至少一者；以及介電層，位於背對至少一個晶粒的多個中介物的背側中。在實施例中，半導體結構更包含：第二模製材料，圍繞至少一個晶粒；及底填充材料，位於多個中介物與至少一個晶粒之間。在實施例中，第一模製材料包圍至少一個晶粒。在實施例中，半導體結構更包含第一模製材料中的穿孔，其中穿孔電連接至至少一個晶粒。在實施例中，介電層為聚合物層，其中半導體結構更包括介電層上的外部連接件。
前文概述若干實施例的特徵，以使得所屬技術領域中具有通常知識者可更佳地理解本揭露的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實施本文中所引入的實施例的相同目的及/或實現相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬技術領域中具有通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100,100A,100B,100C,100D:CoW結構 101:基底 101A:第一表面 101B:第二表面 101S:最近側壁 103:穿孔 104:障壁層 105:電組件 106:模製穿孔 107,112,126,132:重佈線結構 108,118:模製材料 109:導電墊 110:中介物 111,131:導電特徵 113,133:介電層 114:導電連接件 115,129:焊料區 117:晶粒連接件 119:底填充材料 121,121A:晶粒 123:材料 124:凹部 125:經圖案化罩幕層 125C:側壁 127:外部連接件 128:聚合物層 150,153:載體 151,152:黏著劑層 160:複合中介物 1000:方法 1010,1020,1030,1040,1050:區塊 D:深度 T1:厚度 W1,W3:寬度 W2:距離
當結合隨附圖式閱讀以下詳細描述時會最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清晰起見而任意地增大或減小各種特徵的尺寸。 圖1至圖9示出在實施例中的在各個製造階段的晶圓上晶片（CoW）結構的橫截面圖。 圖10示出在另一實施例中的CoW結構的橫截面圖。 圖11示出在另一實施例中的CoW結構的橫截面圖。 圖12示出在另一實施例中的CoW結構的橫截面圖。 圖13至圖17示出在又一實施例中的在各個製造階段的CoW結構的橫截面圖。 圖18示出在一些實施例中的形成半導體結構的方法的流程圖。
1000:方法
1010,1020,1030,1040,1050:區塊

Claims (20)

  1. 一種形成半導體結構的方法，所述方法包括： 將第一晶粒及第二晶粒分別接合至第一中介物的第一側及第二中介物的第一側，其中所述第一中介物與所述第二中介物橫向相鄰； 用第一模製材料包封所述第一中介物及所述第二中介物； 在與所述第一中介物的所述第一側相對的所述第一中介物的第二側中形成第一凹部； 在與所述第二中介物的所述第一側相對的所述第二中介物的第二側中形成第二凹部；以及 用第一介電材料填充所述第一凹部及所述第二凹部。
  2. 如請求項1之形成半導體結構的方法，更包括：在接合所述第一晶粒及所述第二晶粒之前，將所述第一中介物及所述第二中介物附接至載體。
  3. 如請求項2之形成半導體結構的方法，更包括：在接合所述第一晶粒及所述第二晶粒之後，用第二模製材料包封所述第一晶粒及所述第二晶粒。
  4. 如請求項3之形成半導體結構的方法，更包括：用底填充材料填充所述第一晶粒與所述第二晶粒之間的間隙。
  5. 如請求項1之形成半導體結構的方法，更包括：在接合所述第一晶粒及所述第二晶粒之前，將所述第一晶粒及所述第二晶粒附接至載體。
  6. 如請求項5之形成半導體結構的方法，其中所述第一模製材料進一步包封所述第一晶粒及所述第二晶粒。
  7. 如請求項5之形成半導體結構的方法，更包括：用第二模製材料包封所述第一晶粒及所述第二晶粒。
  8. 如請求項5之形成半導體結構的方法，更包括：在所述第一模製材料中形成穿孔。
  9. 如請求項1之形成半導體結構的方法，其中所述第一介電材料為聚合物。
  10. 如請求項9之形成半導體結構的方法，其中所述方法更包括：在所述第一介電材料上形成導電連接件，其中所述導電連接件電耦接至所述第一中介物中的第一導電柱。
  11. 一種形成半導體結構的方法，所述方法包括： 將第一晶粒及第二晶粒分別附接至第一中介物及第二中介物，其中在所述附接之後，所述第一晶粒與所述第二晶粒橫向相鄰，且所述第一中介物與所述第二中介物橫向相鄰； 用第一模製材料包圍所述第一中介物及所述第二中介物； 在所述第一中介物的遠離所述第一晶粒的第一表面中形成第一凹部； 在所述第二中介物的遠離所述第二晶粒的第一表面中形成第二凹部；以及 用聚合物層填充所述第一凹部及所述第二凹部。
  12. 如請求項11之形成半導體結構的方法，其中所述聚合物層的遠離所述第一晶粒的表面與所述第一中介物的所述第一表面及所述第二中介物的所述第一表面齊平。
  13. 如請求項11之形成半導體結構的方法，其中形成所述第一凹部包括： 在所述第一中介物的所述第一表面上形成經圖案化罩幕層，其中所述經圖案化罩幕層覆蓋所述第一模製材料，覆蓋接觸所述第一模製材料的所述第一中介物的第一部分並且暴露所述第一中介物的第二部分；以及 執行非等向性蝕刻製程以移除所述第一中介物的所述第二部分的外部層。
  14. 如請求項13之形成半導體結構的方法，其中所述第一凹部的寬度形成為小於所述第一中介物的寬度，使得所述第一凹部的側壁與接觸所述第一模製材料的所述第一中介物的相應側壁間隔開。
  15. 如請求項11之形成半導體結構的方法，其中所述第一中介物包括第一基底及所述第一基底中的第一基底穿孔（TSV），其中在形成所述第一凹部之後，所述第一TSV延伸至所述第一凹部中。
  16. 一種半導體結構，包括： 多個中介物，彼此橫向相鄰且具有基底穿孔（TSV）； 第一模製材料，圍繞所述多個中介物； 至少一個晶粒，接合且電連接至所述多個中介物中的至少一者；以及 介電層，位於背對所述至少一個晶粒的所述多個中介物的背側中。
  17. 如請求項16之半導體結構，更包括： 第二模製材料，圍繞所述至少一個晶粒；以及 底填充材料，位於所述多個中介物與所述至少一個晶粒之間。
  18. 如請求項16之半導體結構，其中所述第一模製材料包圍所述至少一個晶粒。
  19. 如請求項16之半導體結構，更包括所述第一模製材料中的穿孔，其中所述穿孔電連接至所述至少一個晶粒。
  20. 如請求項16之半導體結構，其中所述介電層為聚合物層，其中所述半導體結構更包括所述介電層上的外部連接件。
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US8237278B2 (en) 2009-11-16 2012-08-07 International Business Machines Corporation Configurable interposer
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