TW202105666A - 晶片結構 - Google Patents
晶片結構 Download PDFInfo
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- TW202105666A TW202105666A TW108137977A TW108137977A TW202105666A TW 202105666 A TW202105666 A TW 202105666A TW 108137977 A TW108137977 A TW 108137977A TW 108137977 A TW108137977 A TW 108137977A TW 202105666 A TW202105666 A TW 202105666A
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Abstract
一種晶片結構包括第一半導體晶片及第二半導體晶片。所述第一半導體晶片包括第一半導體基底、第一內連層、第一保護層、間隙填充層及第一導通孔,第一內連層位於第一半導體基底上,第一保護層覆蓋第一內連層,間隙填充層位於第一保護層上,第一導通孔嵌置在間隙填充層中且與第一內連層電性連接。所述第二半導體晶片嵌置在第一半導體晶片內且被間隙填充層及第一導通孔所環繞,其中第二半導體晶片包括第二半導體基底、第二內連層、第二保護層及第二導通孔,第二內連層位於第二半導體基底上,第二保護層位於第二內連層上,第二導通孔嵌置在第二保護層中且與第二內連層電性連接,其中第二半導體基底結合到第一保護層。
Description
本公開是涉及一種封裝結構,晶片結構及其製作方法。
半導體裝置及積體電路通常是在單個半導體晶圓上製造。可以在晶圓級下,對晶圓的晶粒進行加工並與其他半導體裝置或晶粒封裝在一起,且已經開發出用於晶圓級封裝(wafer level packaging,WLP)的各種技術。另外,此種封裝還可在進行切割(dicing)之後被整合到半導體基底或載體。因此,每一封裝內的導電端子與內部元件(例如,重佈線路結構)之間的電性連接的可靠性至關重要。
本公開實施例的一種晶片結構包括第一半導體晶片、第二半導體晶片及重佈線層。所述第一半導體晶片包括第一半導體基底、第一內連層、第一保護層、間隙填充層及多個第一導通孔,所述第一內連層位於所述第一半導體基底上,所述第一保護層覆蓋所述第一內連層,所述間隙填充層位於所述第一保護層上,所述多個第一導通孔嵌置在所述間隙填充層中且與所述第一內連層電性連接。所述第二半導體晶片嵌置在所述第一半導體晶片內且被所述間隙填充層及所述多個第一導通孔環繞,其中所述第二半導體晶片包括第二半導體基底、第二內連層、第二保護層及多個第二導通孔,所述第二內連層位於所述第二半導體基底上,所述第二保護層位於所述第二內連層上,所述多個第二導通孔嵌置在所述第二保護層中且與所述第二內連層電性連接,其中所述第二半導體基底結合到所述第一保護層。所述重佈線層位於所述第一半導體晶片的所述間隙填充層之上,其中所述重佈線層電性連接到所述多個第一導通孔及所述多個第二導通孔。
以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然,這些僅為實例且不旨在進行限制。舉例來說,以下說明中將第二特徵形成在第一特徵“之上”或第一特徵“上”可包括其中第二特徵與第一特徵被形成為直接接觸的實施例,且也可包括其中第二特徵與第一特徵之間可形成有附加特徵從而使得所述第二特徵與所述第一特徵可不直接接觸的實施例。另外,本公開可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的,而不是自身指示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“在…上(on)”、“在…之上(over)”、“上覆在…之上(overlying)”、“在…上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向),且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說,可包括測試結構以說明對三維(three-dimensional,3D)封裝或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試焊盤(test pad),以便能夠對3D封裝或3DIC進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法結合使用以提高良率並降低成本。
圖1A到圖1E是根據本公開一些示例性實施例的製作半導體晶片的方法中各個階段的示意性剖視圖。在示例性實施例中,闡述了製作第二半導體晶片SC2的方法,第二半導體晶片SC2將在之後的實施例中使用。參照圖1A,提供半導體晶圓WF(第二半導體晶圓),半導體晶圓WF具有多個第二半導體晶片SC2(通過切割線DL而分離的多個第二半導體晶片SC2)。如圖1A中所示,第二半導體晶片SC2中的每一者包括第二半導體基底201、第二內連層202、多個第二導電焊盤204及介電層206。在示例性實施例中,第二半導體基底201可為塊狀矽基底或絕緣體上矽(silicon-on-insulator,SOI)基底,且還包括形成在第二半導體基底201中的主動元件(例如,電晶體等)及視需要而定的被動元件(例如,電阻器、電容器、電感器等)。第二內連層202設置在第二半導體基底201上且可例如包括交替堆疊的多個金屬化層(頂部金屬化層202-TM及下部金屬化層202-LM)與層間介電層202A。第二導電焊盤204可為鋁焊盤、銅焊盤或其他合適的金屬焊盤。第二導電焊盤204例如設置在第二內連層202上且電性連接到第二內連層202(例如,連接到第二內連層202的頂部金屬化層202-TM)。介電層206可為氧化矽層、氮化矽層、氮氧化矽層或由任何合適的介電材料形成的介電層。在一些實施例中,介電層206環繞第二導電焊盤204,同時暴露出第二導電焊盤204的上表面。
參照圖1B,在下一步驟中,在第二內連層202上形成多個第二導通孔208,且形成第一保護部分210A以環繞所述多個第二導通孔208。在一些實施例中,首先在第二內連層202上形成第一保護部分210A。之後,將第一保護部分210A圖案化以形成開口,由此使第二導通孔208形成在所述開口內以電性連接到第二內連層202。在一些實施例中,第二導通孔208在實體上連接到第二內連層202的頂部金屬化層202-TM。在一些實施例中,可通過鍍覆(plating)形成第二導通孔208。在某些實施例中,可執行平坦化製程(例如化學機械拋光(chemical mechanical polishing,CMP))以使第二導通孔208的頂表面與第一保護部分210A的頂表面彼此共面。
參照圖1C,形成第二保護部分210B以覆蓋所述多個第二導通孔208且覆蓋第一保護部分210A。在一些實施例中,第一保護部分210A及第二保護部分210B構成第二保護層210。在一個示例性實施例中,第二保護層210的總厚度Tx為約20μm,本公開並非僅限於此。在一些實施例中,第一保護部分210A及第二保護部分210B可包含例如聚合物、介電材料、樹脂材料等材料。然而,本公開並非僅限於此,且可使用其他合適的保護材料。在某些實施例中,第一保護部分210A及第二保護部分210B(第二保護層210)是氧化物類膜。
參照圖1D,在下一步驟中,可執行薄化製程(thinning process)以對第二半導體基底201的背面進行薄化。舉例來說,在一個實施例中,可將晶圓結構上下顛倒,以用於對第二半導體基底201的背面進行薄化。在一些實施例中,執行薄化製程以使第二半導體晶片SC2的總高度減小到約40μm。然而,本公開並非僅限於此,且可根據要求來調整第二半導體晶片SC2的高度。
在一些實施例中,參照圖1E,在對第二半導體基底201(半導體晶圓WF)的背面進行薄化之後,可沿著切割線DL(在圖1D中示出)對半導體晶圓WF進行切割,以將所述多個第二半導體晶片SC2彼此分離。在某些實施例中,將半導體晶圓WF放置在用於晶粒鋸切(die saw)的切割膠帶DT上,從而可在切割膠帶DT上執行切割。至此,便可製作出示例性實施例的第二半導體晶片SC2。
圖2A到圖2D是根據本公開一些示例性實施例的製作晶片結構的方法中各個階段的示意性剖視圖。參照圖2A,提供半導體晶圓WF1,半導體晶圓WF1具有多個第一半導體晶片SC1。如圖2A中所示,第一半導體晶片SC1中的每一者包括第一半導體基底101、第一內連層102、多個第一導電焊盤104、介電層106、多個第一導電柱108及第一保護層110。在示例性實施例中,第一半導體基底101可為塊狀矽基底或絕緣體上矽(SOI)基底,且還包括形成在第一半導體基底101中的主動元件(例如,電晶體等)及視需要而定的被動元件(例如,電阻器、電容器、電感器等)。第一內連層102設置在第一半導體基底101上且可例如包括交替堆疊的多個金屬化層(頂部金屬化層102-TM及下部金屬化層102-LM)與層間介電層102A。第一導電焊盤104可為鋁焊盤、銅焊盤或其他合適的金屬焊盤。第一導電焊盤104例如電性連接到第一內連層102。第一導電柱108可通過鍍覆形成在第一內連層102上。在一些實施例中,第一導電柱108被形成為與第一導電焊盤104相鄰。介電層106可為氧化矽層、氮化矽層、氮氧化矽層或由任何合適的介電材料形成的介電層。在一些實施例中,介電層106可在環繞第一導電柱108的一些部分的同時蓋住第一導電焊盤104。在某些實施例中,第一保護層110覆蓋介電層106及第一內連層102,其中第一導電柱108的上表面被暴露出。第一保護層110包含例如聚合物、介電材料、樹脂材料等材料。然而,本公開並非僅限於此,且可使用其他合適的保護材料。在某些實施例中,保護層110是氧化物類膜(例如,氧化矽膜)。
如圖2A中所示,在提供半導體晶圓WF1之後,在第一半導體晶片SC1的第一保護層110上設置至少一個在圖1E中製備的第二半導體晶片SC2。在一些實施例中,第二半導體晶片SC2的第二半導體基底201在實體上接觸第一半導體晶片SC1的第一保護層110。在某些實施例中,半導體基底201通過熔融接合(fusion bonding)而直接結合到第一保護層110上。舉例來說,熔融接合可為氧化物-氧化物熔融接合或矽-氧化物熔融接合,本公開並非僅限於此。在熔融接合是氧化物-氧化物熔融接合的情形中,可在半導體基底201的背面上形成氧化物類膜,以用於結合到第一保護層110。本公開並非僅限於此。
參照圖2B,在下一步驟中,可在第一保護層110之上以及第二半導體晶片SC2之上共形地形成第一蝕刻終止層112。舉例來說,第一蝕刻終止層112可覆蓋第一保護層110的頂表面及第二半導體晶片SC2的頂表面,且還覆蓋第二半導體晶片SC2的側壁SW。在一些實施例中,第一蝕刻終止層112可由相對於上覆層或下方層具有高的蝕刻選擇性的材料形成,以終止及控制對這些層的蝕刻。在後續步驟中,在第一蝕刻終止層112之上形成間隙填充層114以覆蓋第一蝕刻終止層112。在某些實施例中,間隙填充層114形成在第一保護層110之上且覆蓋第二半導體晶片SC2。在某些實施例中,第一蝕刻終止層112位於第一保護層110與間隙填充層114之間(或夾置在第一保護層110與間隙填充層114之間)。在一些實施例中,間隙填充層114可為氧化物類介電材料層(例如,氧化矽),但本公開並非僅限於此。在某些實施例中,當第一保護層110及間隙填充層114二者皆由氧化物類材料製成時,則第一蝕刻終止層112可為例如氮化矽。
參照圖2C,在形成間隙填充層114之後,執行平坦化製程以移除第二保護層210的一些部分並且移除間隙填充層114的一些部分。在一些實施例中,是移除第二保護層210的至少第二保護部分210B。換句話說,在平坦化製程之後,僅保留第二保護層210的第一保護部分210A。在某些實施例中,所述平坦化製程還會移除第一蝕刻終止層112的一些部分,以使第一蝕刻終止層112的剩餘部分覆蓋第一保護層110的頂表面及第二半導體晶片SC2的側壁SW。在一些實施例中,通過機械研磨(mechanical grinding)製程及/或化學機械拋光(CMP)製程對第二保護層210及間隙填充層114進行研磨或拋光,直到顯露出第二導通孔208的頂表面208-TS為止。在平坦化或拋光製程之後,第二導通孔208的頂表面208-TS、第二保護層的頂表面210-TS、第一蝕刻終止層112的頂表面112-TS及間隙填充層114的頂表面114-TS彼此共面並齊平。
參照圖2D,在下一個步驟中,對間隙填充層114及蝕刻終止層112進行蝕刻,且在間隙填充層114及蝕刻終止層112中形成多個第一導通孔116。由於存在第一蝕刻終止層112,第一導通孔116可被形成為具有充足的均勻性。換句話說,由於間隙填充層114與蝕刻終止層112具有不同的蝕刻速率或蝕刻選擇性,因此對這些層的蝕刻可被適當地控制。在一些實施例中,第一導通孔116是嵌置在間隙填充層114中且與第一內連層102電性連接。在一些實施例中,第一導通孔116被形成為環繞第二半導體晶片SC2。在某些實施例中,第一導通孔116通過第一導電柱108電性連接到第一內連層102。另外,如圖2D中所示,第一蝕刻終止層112及間隙填充層114在實體上接觸第一導通孔116的側壁。換句話說,第一蝕刻終止層112及間隙填充層114環繞第一導通孔116。在形成第一導通孔116之後,第一導通孔116的頂表面116-TS與第二導通孔208的頂表面208-TS、第二保護層210的頂表面210-TS、第一蝕刻終止層112的頂表面112-TS及間隙填充層114的頂表面114-TS共面並齊平。之後,可沿著切割線DL(在圖2C中示出)對半導體晶圓WF1進行切割,以將所述多個第一半導體晶片SC1彼此分離。至此,便可完成根據本公開一些示例性實施例的晶片結構CS1。在所完成的晶片結構CS1(整合晶片結構)中,第二半導體晶片SC2是嵌置在第一半導體晶片SC1內,且被第一半導體晶片SC1的間隙填充層114及第一導通孔116所環繞。
另外,在示例性實施例中,第一半導體晶片SC1及第二半導體晶片SC2可選自以下晶片:應用專用積體電路(application-specific integrated circuit,ASIC)晶片、類比晶片(例如,無線射頻晶片)、數位晶片(例如,基頻晶片)、整合式被動元件(integrated passive device,IPD)、電壓調節器(voltage regulator)晶片、感測器晶片、記憶體晶片等。本公開並非僅限於此。舉例來說,第一半導體晶片SC1及第二半導體晶片SC2可為相同類型的晶片或可為不同類型的晶片。
圖3是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖3中所示的晶片結構CS1’相似於圖2A到圖2D中所示的晶片結構CS1。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於,在圖2C到圖2D中所述的切割製程之前,在圖3中還形成重佈線層118。舉例來說,在形成第一導通孔116之後,可在第一半導體晶片SC1的間隙填充層114之上及第二半導體晶片SC2之上形成重佈線層118。在一些實施例中,重佈線層118電性連接到所述多個第一導通孔116及所述多個第二導通孔208。換句話說,所述多個第一導通孔116及所述多個第二導通孔208通過重佈線層118而彼此電性連通。在一些實施例中,由於進行多晶片堆疊,重佈線層118可具有精細節距(例如,≦0.8μm)。
在一些實施例中,形成重佈線層118包括依序形成交替的一個或多個介電層118A與一個或多個導電層118B。在某些實施例中,導電層118B夾置在介電層118A之間。儘管本文中示出僅三層導電層118B及四層介電層118A,然而,本公開的範圍並不受本公開的實施例所限制。在其他實施例中,可根據產品要求來調整導電層118B及介電層118A的數目。在一些實施例中,導電層118B可電性連接到所述多個第一導通孔116及所述多個第二導通孔208。
在某些實施例中,介電層118A的材料可為可利用微影(photolithography)及/或蝕刻(etching)製程進行圖案化的聚醯亞胺、聚苯並噁唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)、氮化物(例如氮化矽)、氧化物(例如氧化矽)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)、其組合等。在一些實施例中,可通過例如旋轉塗布(spin-on coating)、化學氣相沉積(chemical vapor deposition,CVD)、等離子體增強型化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)等合適的製作技術來形成介電層118A的材料。本公開並非僅限於此。
在一些實施例中,導電層118B的材料可由通過電鍍(electroplating)或沉積形成的導電材料(例如鋁、鈦、銅、鎳、鎢及/或其合金)製成且可利用微影及蝕刻製程進行圖案化。在一些實施例中,導電層118B可為圖案化銅層或其他合適的圖案化金屬層。在本說明通篇中,用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅及含有少量例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等元素的銅合金。
在形成重佈線層118之後,可在導電層118B的最頂層的被暴露出的頂表面上設置多個導電焊盤118C以與導電球電性連接。在某些實施例中,導電焊盤118C是例如用於球安裝(ball mount)的球下金屬(under-ball metallurgy,UBM)圖案。如圖3中所示,導電焊盤118C形成在重佈線層118上且電性連接到重佈線層118。在一些實施例中,舉例來說,導電焊盤118C的材料可包括銅、鎳、鈦、鎢或其合金等,且可通過電鍍製程形成。導電焊盤118C的數目在本公開中不受限制,且可根據設計佈局來選擇。在一些替代性的實施例中,可省略導電焊盤118C。換句話說,可直接在重佈線層118上設置在後續步驟中形成的導電球120。
在形成導電焊盤118C之後,在導電焊盤118C上以及重佈線層118之上設置多個導電球120。在一些實施例中,可通過植球(ball placement)製程或回焊(reflow)製程將導電球120設置在導電焊盤118C上。在一些實施例中,導電球120是例如焊料球或球柵陣列(ball grid array,BGA)球。在一些實施例中,導電球120是例如控制塌陷高度晶片連接(controlled collapse chip connection,C4)凸塊或微凸塊。本公開並非僅限於此。在一些實施例中,導電球120通過導電焊盤118C連接到重佈線層118。在某些實施例中,導電球120中的一些導電球120可通過重佈線層118電性連接到第一導通孔116,而導電球120中的一些導電球120可通過重佈線層118電性連接到第二導通孔208。另外,在示例性實施例中,導電球120的數目並非僅限於本公開內容,且可根據導電焊盤118C的數目來指定並選擇。在形成重佈線層118及放置導電球120之後,可執行相同的切割製程(如圖2D中所述的切割製程)以將所述多個第一半導體晶片SC1彼此分離。至此,便可完成根據本公開一些示例性實施例的圖3中所示的晶片結構CS1’。
圖4是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖4中所示的晶片結構CS2相似於圖3中所示的晶片結構CS1’。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於第二導通孔208的連接。如圖3中所示,第二導通孔208在實體上連接到第二內連層202的頂部金屬化層202-TM。然而,本公開並非僅限於此。舉例來說,如圖4中所示,第二導通孔208可在實體上連接到任何一個下部金屬化層202-LM。
圖5是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖5中所示的晶片結構CS3相似於圖3中所示的晶片結構CS1’。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於第二導通孔208的連接。舉例來說,如圖5中所示,第二導通孔208在實體上連接到第二導電焊盤204。換句話說,導通孔208通過第二導電焊盤204電性連接到第二內連層202。這不同於圖3所示的實施例,在圖3所示的實施例中第二導電焊盤204是用作為虛設焊盤。
圖6是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖6中所示的晶片結構CS4相似於圖3中所示的晶片結構CS1’。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於第一導通孔116的連接。如圖3中所示,第一導通孔116通過第一導電柱108電性連接到第一內連層102。然而,本公開並非僅限於此。舉例來說,如圖6中所示,可省略第一導電柱108,且第一導通孔116可在實體上連接到第一內連層102的頂部金屬化層102-TM。在替代實施例中,第一導通孔116可在實體上連接到下部金屬化層102-LM中的任何一個下部金屬化層102-LM。
圖7是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖7中所示的晶片結構CS5相似於圖3中所示的晶片結構CS1’。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於將第二半導體晶片SC2結合在第一半導體晶片SC1的第一保護層110上的方式。如圖3中所示,第二半導體晶片SC2的半導體基底201通過熔融接合而直接結合到第一保護層110上。然而,本公開並非僅限於此。舉例來說,如圖7中所示,結合膜BF可進一步貼合到半導體基底201的背面,且第二半導體晶片SC2通過結合膜BF結合到第一保護層110上。在一些實施例中,結合膜BF可為用於熔融接合的任何材料。舉例來說,結合膜BF可為用於氧化物-氧化物熔融接合的氧化物類膜(例如,氧化矽膜)。在替代實施例中,結合膜BF可為例如晶粒貼合膜(die attach film)等粘合膜。本公開並非僅限於此。
圖8是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖8中所示的晶片結構CS6相似於圖3中所示的晶片結構CS1’。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於還包括第二蝕刻終止層113。舉例來說,可通過依序形成第一蝕刻終止層112、第一子層114-1、第二蝕刻終止層113及第二子層114-2來制作圖8中所示的結構,其中第一子層114-1及第二子層114-2構成間隙填充層114。在對這些層進行平坦化之後,可形成第一導通孔116以穿透第二子層114-2、第二蝕刻終止層113、第一子層114-1及第一蝕刻終止層112。在一些實施例中,第二蝕刻終止層113可由相對於上覆層或下方層具有高的蝕刻選擇性的材料形成,以用於終止及控制對這些層的蝕刻。在某些實施例中,當間隙填充層114的第一子層114-1及第二子層114-2二者皆由氧化物類材料所製成時,則第二蝕刻終止層113可為例如氮化矽。通過結合第一蝕刻終止層112使用第二蝕刻終止層113,第一導通孔116可被形成為具有充足的均勻性。
如圖8中所示,在已形成第二蝕刻終止層113及第一導通孔116之後,可執行形成重佈線層118及導電球120的相同的步驟來製作晶片結構CS6。舉例來說,在所完成的結構中,第二蝕刻終止層113位於間隙填充層114的第一子層114-1與第二子層114-2之間,且將第一子層114-1與第二子層114-2在實體上分開。另外,第一導通孔116的側壁在實體上接觸第二子層114-2、第二蝕刻終止層113、第一子層114-1及第一蝕刻終止層112。換句話說,第一導通孔116被第二子層114-2、第二蝕刻終止層113、第一子層114-1及第一蝕刻終止層112所環繞。
圖9是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖9中所示的晶片結構CS7相似於圖3中所示的晶片結構CS1’。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於還包括第三半導體晶片SC3。如圖9中所示,第三半導體晶片SC3結合到第一半導體晶片SC1的第一保護層110上,且位於第二半導體晶片SC2的旁邊。在示例性實施例中,第三半導體晶片SC3包括第三半導體基底301、第三內連層302、多個第三導電焊盤304、介電層306、多個第三導通孔308及第三保護層310。第三半導體晶片SC3的這些元件可相似於第二半導體晶片SC2的第二半導體基底201、第二內連層202、第二導電焊盤204、介電層206、第二導通孔208及第二保護層210,因此可參照第二半導體晶片SC2的詳細說明。簡單來說,第三內連層302位於第三半導體基底301上,第三保護層310位於第三內連層302上,且第三導通孔308嵌置在第三保護層310中且與第三內連層302電性連接。
在所示實施例中,第三半導體晶片SC3嵌置在第一半導體晶片SC1內且被間隙填充層114及第一導通孔116所環繞。另外,第三半導體晶片SC3的第三半導體基底301通過熔融接合而直接結合到第一保護層110。例如,可通過氧化物-氧化物熔融接合或矽-氧化物熔融接合。在一些實施例中,重佈線層118可電性連接到第三半導體晶片SC3的第三導通孔308。在一些實施例中,第一半導體晶片SC1及第二半導體晶片可通過重佈線層118電性連接到第三半導體晶片SC3。在某些實施例中,第一蝕刻終止層112還覆蓋第三半導體晶片SC3的側壁。
圖10是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖10中所示的晶片結構CS8相似於圖9中所示的晶片結構CS7。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於第三半導體晶片SC3的尺吋。如圖9中所示,第三半導體晶片SC3的尺吋實質上相同於第二半導體晶片SC2的尺吋。然而,本公開並非僅限於此。如圖10中所示,第三半導體晶片SC3的尺吋小於第二半導體晶片SC2的尺吋。換句話說,第二半導體晶片SC2與第三半導體晶片SC3可為不同類型的晶片。然而,本公開並非僅限於此,且可根據設計要求來適當地選擇不同尺吋的半導體晶片。
圖11是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。圖11中所示的晶片結構CS9相似於圖9中所示的晶片結構CS7。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於第三半導體晶片SC3的位置。如圖11中所示,第三半導體晶片SC3是位於第二半導體晶片SC2之上。在一些實施例中,可形成第二間隙填充層115(相似於第一間隙填充層114)以環繞第三半導體晶片SC3。在某些實施例中,輔助導通孔AxV(相似於第一導通孔116)可嵌置在第二間隙填充層115內。另外,輔助內連層AxI可位於第一間隙填充層114與第二間隙填充層115之間,以提供第一間隙填充層114與第二間隙填充層115之間中的電性連接。在一些實施例中,輔助內連層AxI包括交替堆疊的多個金屬化層AxI-1與多個層間介電層AxI-2。金屬化層AxI-1及層間介電層AxI-2的數目並非僅限於此,且可根據要求進行調整。
在一些實施例中,輔助內連層AxI與所述多個第一導通孔116、所述多個第二導通孔208及所述多個輔助導通孔AxV電性連接。在某些實施例中,第三半導體基底301通過熔融接合而結合到輔助內連層AxI的層間介電層AxI-2上。舉例來說,熔融接合可為氧化物-氧化物熔融接合及矽-氧化物熔融接合。本公開並非僅限於此。在某些實施例中,可在輔助內連層AxI上形成第二蝕刻終止層117(相似於第一蝕刻終止層112),第二蝕刻終止層117覆蓋第三半導體晶片SC3的側壁且覆蓋輔助內連層AxI的上表面。接著可將隨後形成的重佈線層118電性連接到第三導通孔308及輔助導通孔AxV。
圖12A到圖12G是根據本公開一些示例性實施例的製作封裝結構的方法中各個階段的示意性剖視圖。參照圖12A,提供載體402。在一些實施例中,載體402可為玻璃載體或任何適合為封裝結構的製造方法承載半導體晶圓或重構晶圓(reconstituted wafer)的載體。在一些實施例中,載體402塗布有剝離層404。剝離層404的材料可為適合將載體402相對於設置在載體402上的上方層或者任何晶圓進行結合及剝離的任何材料。
在一些實施例中,剝離層404可包括由介電材料(包括任何合適的聚合物類介電材料,例如苯並環丁烯(“BCB”)、聚苯並噁唑(“PBO”))製成的介電材料層。在替代實施例中,剝離層404可包括由當受熱時會失去其粘合性質的環氧類熱釋放材料(例如,光熱轉換(light-to-heat-conversion,LTHC)釋放塗布膜)製成的介電材料層。在另一個替代實施例中,剝離層404可包括由當暴露到紫外(ultra-violet,UV)光時會失去其粘合性質的紫外(UV)膠製成的介電材料層。在某些實施例中,剝離層404可以為液體形式而被分配並被固化,或可為層疊到載體402上的層疊膜,或者可為類似材料。剝離層404的與接觸載體402的底表面相對的頂表面可被整平且可具有高的共面程度。在某些實施例中,剝離層404是例如具有良好耐化學性(chemical resistance)的LTHC層,且此種層能夠通過應用激光輻射(laser irradiation)而在室溫下從載體402剝離,然而本公開並非僅限於此。
在替代實施例中,可在剝離層404上塗布緩衝層(未示出),其中剝離層404夾置在緩衝層與載體402之間,且緩衝層的頂表面還可提供高的共面程度。在一些實施例中,緩衝層可為介電材料層。在一些實施例中,緩衝層可為由聚醯亞胺、PBO、BCB或任何其他合適的聚合物類介電材料製成的聚合物層。在一些實施例中,緩衝層可為Ajinomoto Buildup Film (ABF)、阻焊劑(Solder Resist,SR)膜等。換句話說,緩衝層是可選的且可根據需要省略,因此本公開並非僅限於此。
如圖12A中進一步所示,在載體402之上形成重佈線層406。舉例來說,重佈線層406形成在剝離層404上,且形成重佈線層406包括依序形成交替的一個或多個介電層406A與一個或多個導電層406B。在一些實施例中,重佈線層406包括兩個介電層406A及一個導電層406B,如圖12A中所示,其中導電層406B夾置在介電層406A之間。然而,本公開並非僅限於此。重佈線層406中所包括的介電層406A及導電層406B的數目並非僅限於此,且可根據需要來指定並選擇。舉例來說,介電層406A及導電層406B的數目可為一個或多於一個。
在某些實施例中,介電層406A的材料可為利用微影及/或蝕刻製程進行圖案化的聚醯亞胺、聚苯並噁唑(PBO)、苯並環丁烯(BCB)、氮化物(例如氮化矽)、氧化物(例如氧化矽)、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻雜硼的磷矽酸鹽玻璃(BPSG)、其組合等。在一些實施例中,可通過例如旋轉塗布、化學氣相沉積(CVD)、等離子體增強型化學氣相沉積(PECVD)等合適的製作技術來形成介電層406A的材料。本公開並非僅限於此。在一些實施例中,導電層406B的材料可由通過電鍍或沉積形成的導電材料(例如鋁、鈦、銅、鎳、鎢及/或其合金)製成且可利用微影及蝕刻製程進行圖案化。在一些實施例中,導電層406B可為圖案化銅層或其他合適的圖案化金屬層。
參照圖12B,在形成重佈線層406之後,在重佈線層406上以及載體402之上提供至少一個在圖2D中獲得的晶片結構CS1及多個貫穿絕緣層孔408。在一些實施例中,貫穿絕緣層孔408是整合扇出型(integrated fan-out,“InFO”)穿孔。在一個實施例中,形成貫穿絕緣層孔408包括:形成具有開口的罩幕圖案(未示出);接著通過電鍍或沉積形成填滿所述開口的金屬材料(未示出);以及移除罩幕圖案以在重佈線層406上形成貫穿絕緣層孔408。在某些實施例中,貫穿絕緣層孔408填充到顯露出重佈線層406的導電層406B的通孔開口中,以使貫穿絕緣層孔408可電性連接到重佈線層406。在一些實施例中,罩幕圖案的材料可包括正性光阻或負性光阻。在一個實施例中,貫穿絕緣層孔408的材料可包括金屬材料,例如銅或銅合金等。然而,本公開並非僅限於此。
在替代實施例中,可通過如下方式形成貫穿絕緣層孔408:在重佈線層406上形成晶種層(未示出);形成具有開口的罩幕圖案,所述開口暴露出晶種層的一些部分;通過鍍覆在晶種層的被暴露出的部分上形成金屬材料以形成貫穿絕緣層孔408;移除罩幕圖案;以及接著移除晶種層的被貫穿絕緣層孔408暴露出的部分。舉例來說,晶種層可為鈦/銅複合層。為簡潔起見,在圖12B中示出僅兩個貫穿絕緣層孔408。然而應注意,貫穿絕緣層孔408的數目並非僅限於此,且可根據要求來選擇。
另外,在一些實施例中,拾取至少一個晶片結構CS1並將所述至少一個晶片結構CS1放置在重佈線層406上。在某些實施例中,採用將第一半導體晶片SC1的第一半導體基底101貼合到重佈線層406的介電層406A的方式將晶片結構CS1放置在重佈線層406上。舉例來說,第一半導體基底101通過晶粒貼合膜(未示出)或通過熔融接合而貼合到重佈線層406。在示例性實施例中,示出僅一個晶片結構CS1。然而應當注意,放置在重佈線層406上的晶片結構CS1的數目並非僅限於此,且此可根據設計要求進行調整。
在一些實施例中,當在重佈線層406上放置多於一個晶片結構CS1時,晶片結構CS1可被排列成陣列,且當晶片結構CS1被排列成陣列時,貫穿絕緣層孔408可被分類成群組。晶片結構CS1的數目可對應於貫穿絕緣層孔408的群組的數目。在示例性實施例中,在形成貫穿絕緣層孔408之後,可拾取晶片結構CS1並將晶片結構CS1放置在重佈線層406上。然而,本公開並非僅限於此。在一些替代實施例中,可在形成貫穿絕緣層孔408之前拾取晶片結構CS1並將晶片結構CS1放置在重佈線層406上。
參照圖12C,在下一步驟中,在重佈線層406上以及晶片結構CS1之上形成絕緣材料410。在一些實施例中,絕緣材料410通過例如壓縮模制(compression molding)製程形成且填滿晶片結構CS1與貫穿絕緣層孔408之間的間隙以包封晶片結構CS1。絕緣材料410還填滿相鄰的貫穿絕緣層孔408之間的間隙以包封貫穿絕緣層孔408。在此階段,間隙填充層114、第一導通孔116、第二導通孔208及第二保護層210被絕緣材料410包封並充分地保護。換句話說,晶片結構CS1的間隙填充層114、第一導通孔116、第二導通孔208及第二保護層210不被顯露出。
在一些實施例中,絕緣材料410包含聚合物(例如環氧樹脂、酚醛樹脂(phenolic resin)、含矽樹脂或其他合適的樹脂)、具有低電容率(permittivity,Dk)及低損耗角正切(loss tangent,Df)性質的介電材料或其他合適的材料。在替代實施例中,絕緣材料410可包含可接受的絕緣封裝體材料。在一些實施例中,絕緣材料410還可包含可被添加到絕緣材料410中來優化絕緣材料410的熱膨脹係數(coefficient of thermal expansion,CTE)的無機填料或無機化合物(例如,二氧化矽、粘土等)。本公開並非僅限於此。
參照圖12D,在一些實施例中,局部地移除絕緣材料410以暴露出貫穿絕緣層孔408、第一導通孔116及第二導通孔208。在一些實施例中,是通過平坦化步驟對絕緣材料410進行研磨或拋光。舉例來說,通過機械研磨製程及/或化學機械拋光(CMP)製程來執行所述平坦化步驟,直到顯露出第一導通孔116的頂表面116-TS及第二導通孔208的頂表面208-TS為止。在一些實施例中,可對貫穿絕緣層孔408局部地進行拋光,以使貫穿絕緣層孔408的頂表面408-TS與第一導通孔116的頂表面116-TS及第二導通孔208的頂表面208-TS齊平。換句話說,也可對貫穿絕緣層孔408、第一導通孔116及第二導通孔208進行輕微地研磨/拋光。
在所示實施例中,對絕緣材料410進行拋光以形成絕緣封裝體410’。在一些實施例中,絕緣封裝體410’的頂表面410-TS、貫穿絕緣層孔408的頂表面408-TS、第一導通孔116的頂表面116-TS、間隙填充層114的頂表面114-TS、第二導通孔208的頂表面208-TS及第二保護層210的頂表面210-TS彼此共面並齊平。在一些實施例中,在進行機械研磨或化學機械拋光(CMP)步驟之後,可視需要執行清潔步驟。舉例來說,執行清潔步驟以清潔並移除從平坦化步驟產生的殘餘物。然而,本公開並非僅限於此,且可通過任何其他合適的方法來執行平坦化步驟。
參照圖12E,在研磨/拋光步驟之後,在絕緣封裝體410’、貫穿絕緣層孔408上以及晶片結構CS1上形成重佈線層412。舉例來說,絕緣封裝體410’具有第一表面410-S1及與第一表面410-S1相對的第二表面410-S2,其中重佈線層412形成在第一表面410-S1上,且重佈線層406形成在絕緣封裝體410’的第二表面410-S2上。在一些實施例中,重佈線層412電性連接到貫穿絕緣層孔408,且分別通過第一導通孔116及第二導通孔208電性連接到第一半導體晶片SC1及第二半導體晶片SC2。在某些實施例中,重佈線層412將第一半導體晶片SC1的第一導通孔116電性連接到第二半導體晶片SC2的第二導通孔208。換句話說,第一半導體晶片SC1通過第一導通孔116、重佈線層412及第二導通孔208與第二半導體晶片SC2電性連接。在一些實施例中,晶片結構CS1通過重佈線層412電性連接到貫穿絕緣層孔408。
另外,在一些實施例中,形成重佈線層412包括依序形成交替的一個或多個介電層412A與一個或多個導電層412B。在某些實施例中,導電層412B夾置在介電層412A之間。儘管本文中示出僅三層導電層412B及四層介電層412A,然而,本公開的範圍並不受本公開的實施例限制。在其他實施例中,可根據產品要求來調整導電層412B及介電層412A的數目。在一些實施例中,導電層412B電性連接到第一半導體晶片SC1的第一導通孔116,且電性連接到第二半導體晶片SC2的第二導通孔208。另外,導電層412B電性連接到貫穿絕緣層孔408。在一些實施例中,重佈線層412的介電層412A及導電層412B的材料相似於針對重佈線層406所述的介電層406A及導電層406B的材料。因此,本文中將不再對介電層412A及導電層412B予以贅述。
在形成重佈線層412之後,可在導電層412B的最頂層的被暴露出的頂表面上設置多個導電焊盤412C以與導電球電性連接。在某些實施例中,導電焊盤412C是例如用於球安裝的球下金屬(UBM)圖案。如圖12E中所示,導電焊盤412C形成在重佈線層412上且電性連接到重佈線層412。在一些實施例中,舉例來說,導電焊盤412C的材料可包括銅、鎳、鈦、鎢或其合金等,且可通過電鍍製程形成。導電焊盤412C的數目在本公開中不受限制,且可根據設計佈局來選擇。在一些替代實施例中,可省略導電焊盤412C。換句話說,可直接在重佈線層412上設置在後續步驟中形成的導電球414。
在形成導電焊盤412C之後,在導電焊盤412C上以及重佈線層412之上設置多個導電球414。在一些實施例中,可通過植球製程或回焊製程將導電球414設置在導電焊盤412C上。在一些實施例中,導電球414是例如焊料球或球柵陣列(BGA)球。在一些實施例中,導電球414通過導電焊盤412C連接到重佈線層412。在某些實施例中,導電球414中的一些導電球414可通過重佈線層412電性連接到晶片結構CS1。另外,導電球414中的一些導電球414可通過重佈線層412電性連接到貫穿絕緣層孔408。導電球414的數目並非僅限於本公開內容,且可根據導電焊盤412C的數目來指定並選擇。另外,如圖12E中所示,可在重佈線層412上安裝一個或多個被動元件416。舉例來說,可通過焊接(soldering)製程將被動元件416安裝在重佈線層412的導電層412B上。本公開並非僅限於此。
參照圖12F,在形成重佈線層412並將導電球414及被動元件416放置在重佈線層412上之後,可將圖12E中所示的結構上下顛倒並貼合到由框架X2支撐的膠帶X1(例如,切割膠帶)上。如圖12F中所示,將載體402從重佈線層406剝離並分離。在一些實施例中,剝離製程包括在剝離層404(例如,LTHC釋放層)上投射光(例如雷射(laser light)或UV光),以使載體402可容易與剝離層404一起被移除。在剝離步驟期間,在剝離載體402及剝離層404之前,使用膠帶X1來固定封裝結構。在剝離製程之後,重佈線層406的背面表面406-BS被顯露出或暴露出。在某些實施例中,重佈線層406的介電層406A被顯露出或暴露出。
參照圖12G,在剝離製程之後,沿著切割線DL(在圖12F中示出)執行切割製程以將整個晶圓結構切分(切穿絕緣封裝體410’以及重佈線層406及412)成多個封裝結構PK1A。在示例性實施例中,切割製程是包括機械刀片鋸切(mechanical blade sawing)或雷射切分(laser cutting)的晶圓切割(wafer dicing)製程。在後續製程中,可例如將分離的封裝結構PK1A設置到線路基板上或根據要求設置到其他元件上。
圖13是根據本公開一些示例性實施例的疊層封裝(PoP)結構的示意性剖視圖。參照圖13,在製作第一封裝(例如圖12G中所示的封裝結構PK1A)之後,可在封裝結構PK1A(第一封裝)上堆疊第二封裝PK2,以形成疊層封裝(PoP)結構。如圖13中所示,第二封裝PK2電性連接到封裝結構PK1A(第一封裝)的導電層406B。在一些實施例中,第二封裝PK2具有基底510、安裝在基底510的一個表面(例如,頂表面)上且堆疊在彼此頂上的多個半導體晶片520。在一些實施例中,使用結合導線530來提供半導體晶片520與焊盤540(例如結合焊盤)之間的電性連接。在一些實施例中,形成絕緣封裝體560來包封半導體晶片520及結合導線530,以保護這些元件。在一些實施例中,可使用貫穿絕緣層孔(未示出)來提供焊盤540與導電焊盤550(例如結合焊盤)之間的電性連接,導電焊盤550位於基底510的另一表面(例如,底表面)上。在某些實施例中,導電焊盤550通過這些貫穿絕緣層孔(未示出)電性連接到半導體晶片520。在一些實施例中,封裝結構PK2的導電焊盤550電性連接到導電球570。另外,導電球570電性連接到封裝結構PK1A(第一封裝)中的重佈線層406的導電層406B。在一些實施例中,還提供底部填充膠580來填充在導電球570之間的空間中,以保護導電球570。在將第二封裝PK2堆疊在封裝結構PK1A(第一封裝)上並在第二封裝PK2與封裝結構PK1A(第一封裝)之間提供電性連接之後,可製作疊層封裝結構POP1。
圖14是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖14中所示的封裝結構PK1B相似於圖12G中所示的封裝結構PK1A,因此相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於從封裝結構PK1B省略重佈線層406。參照圖14,在一些實施例中,在絕緣封裝體410’的第二表面410-S2上設置介電層DI以代替重佈線層406。在某些實施例中,介電層DI具有顯露出貫穿絕緣層孔408的開口,而在介電層DI的開口中還設置有導電端子418且導電端子418連接到貫穿絕緣層孔408。換句話說,無需重佈線層406便能完成具有雙面端子的封裝結構PK1B。在替代實施例中,可省略導電端子418,且介電層DI可蓋住絕緣封裝體410’的背面(第二表面410-S2)及晶片結構CS1的背面。
圖15是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖15中所示的封裝結構PK1C相似於圖12G中所示的封裝結構PK1A,因此相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。實施例之間的不同之處在於還包括另一晶片結構CS8’。如圖15中所示,晶片結構CS8’位於晶片結構CS1的旁邊,且被絕緣封裝體410’包封。晶片結構CS8’是例如通過從圖10所示晶片結構CS8省略重佈線層118及位於重佈線層118上的元件而獲得的。另外,可使用重佈線層412代替重佈線層118,以提供對晶片結構CS8’的第一導通孔116、第二導通孔208及第三導通孔308的電性連接。
圖16是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。封裝結構PK1D是通過將圖3中所示的晶片結構CS1’安裝到基底600上而獲得的。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。參照圖16,提供基底600。在一些實施例中,基底600包括接觸焊盤610、接觸焊盤620、金屬化層630及通孔(未示出)。在一些實施例中,接觸焊盤610與接觸焊盤620分別分佈在基底600的兩個相對的側上,且被暴露出以與之後形成的元件/特徵電性連接。在一些實施例中,金屬化層630及通孔嵌置在基底600中且一同為基底600提供佈線功能,其中金屬化層630及通孔電性連接到接觸焊盤610及接觸焊盤620。換句話說,接觸焊盤610中的至少一些接觸焊盤610通過金屬化層630及通孔電性連接到接觸焊盤620中的一些接觸焊盤620。在一些實施例中,接觸焊盤610及接觸焊盤620可包括金屬焊盤或金屬合金焊盤。在一些實施例中,金屬化層630及通孔的材料可實質上相同於或相似於導電層118B或導電層406B的材料,且因此為簡潔起見本文中不再對其予以贅述。
在一些實施例中,如圖16中所示,通過在實體上連接導電球120與接觸焊盤610而將圖3中所繪示的晶片結構CS1’結合到基底600,以形成具有堆疊結構的封裝結構PK1D,其中晶片結構CS1’在實體上連接及電性連接到基底600。圖3中闡述了晶片結構CS1’的細節,且因此本文中不再對其予以贅述。在一些實施例中,基底600被稱為線路基板,例如有機柔性基底(organic flexible substrate)或印刷電路板(printed circuit board)。在此種實施例中,導電球120是例如晶片連接件或BGA球。
在一些實施例中,在基底600上分別形成多個導電端子640。如圖16中所示,舉例來說,導電端子640連接到基底600的接觸焊盤620。換句話說,導電端子640通過接觸焊盤620電性連接到基底600。導電端子640中的一些導電端子640通過接觸焊盤610及接觸焊盤620電性連接到晶片結構CS1’(例如,晶片結構CS1’中所包括的半導體晶片SC1/SC2)。在一些實施例中,導電端子640是例如焊料球或BGA球。在一些實施例中,通過利用倒裝晶片結合(flip chip bonding)在實體上連接導電球120與基底600的接觸焊盤610而將晶片結構CS1’結合到基底600。
圖17是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。封裝結構PK1E是通過將圖3中所示的晶片結構CS1’安裝到線路元件700及基底600上而獲得的。因此,相同的元件標號是用於表示相同或類似的元件,且於本文中將不再對其予以贅述。參照圖17,在一些實施例中,提供線路元件700。在一些實施例中,線路元件700包括核心部分710、多個通孔720、重佈線路結構730、重佈線路結構740、多個結合焊盤754a、多個結合焊盤754b、阻焊層752a及阻焊層752b。在一些實施例中,核心部分710可包括塊狀矽基底(例如單晶矽塊狀基底)、經摻雜的矽基底、未經摻雜的矽基底或SOI基底,其中經摻雜的矽基底的摻雜劑可為N型摻雜劑、P型摻雜劑或其組合。在一些實施例中,通孔720是穿透核心部分710的矽穿孔。在某些實施例中,在本公開中,線路元件700被稱為仲介層(參見圖17)。
在一些實施例中,重佈線路結構730與重佈線路結構740分別設置在核心部分710的兩個相對的側上,如圖17中所示。在一些實施例中,重佈線路結構730及/或重佈線路結構740電性連接到穿透核心部分710的通孔720。如圖17中所示,嵌置有通孔720的核心部分710位於重佈線路結構730與重佈線路結構740之間。重佈線路結構730與重佈線路結構740通過通孔720而彼此電性連接。
在一些實施例中,重佈線路結構730包括依序形成的交替的一個或多個介電層732與一個或多個金屬化層734,其中一個金屬化層734夾置在兩個介電層732之間。如圖17中所示,金屬化層734的最頂層的頂表面的一些部分分別被形成在介電層732的最頂層中的開口暴露出,以與其他導電特徵連接,且金屬化層734的最底層的底表面的一些部分分別被形成在介電層732的最底層中的開口暴露出,以與通孔720連接。重佈線路結構730中所包括的金屬化層及介電層的數目並非僅限於此,且可根據需要來指定並選擇。
在一些實施例中,重佈線路結構740包括依序形成的交替的一個或多個介電層742與一個或多個金屬化層744,其中一個金屬化層744夾置在兩個介電層742之間。如圖17中所示,金屬化層744的最頂層的頂表面的一些部分分別被形成在介電層742的最頂層中的開口暴露出,以與通孔720連接,且金屬化層744的最底層的底表面的一些部分分別被形成在介電層742的最底層中的開口暴露出,以與其他導電特徵連接。重佈線路結構740中所包括的金屬化層及介電層的數目並非僅限於此,且可根據需要來指定並選擇。
在某些實施例中,介電層732及介電層742的材料可為可利用微影及/或蝕刻製程進行圖案化的聚醯亞胺、PBO、BCB、氮化物(例如氮化矽)、氧化物(例如氧化矽)、PSG、BSG、BPSG、其組合等。在一些實施例中,通過例如旋轉塗布、CVD、PECVD等合適的製作技術來形成介電層732及介電層742。本公開並非僅限於此。在一個實施例中,介電層732的材料與介電層742的材料可為相同的。在替代實施例中,介電層732的材料與介電層742的材料可為不同的。
在某些實施例中,金屬化層734及金屬化層744的材料可由通過電鍍或沉積形成的導電材料(例如鋁、鈦、銅、鎳、鎢及/或其合金)製成且可利用微影及蝕刻製程進行圖案化。在一些實施例中,金屬化層734及金屬化層744可為圖案化銅層或其他合適的圖案化金屬層。在一個實施例中,金屬化層734的材料與金屬化層744的材料可為相同的。在替代實施例中,金屬化層734的材料與金屬化層744的材料可為不同的。
在一些實施例中,結合焊盤754a設置在重佈線路結構730的表面上且在實體上連接到金屬化層734的最頂層的頂表面的被形成在介電層732的最頂層中的開口暴露出的所述部分,其中結合焊盤754a通過形成在重佈線路結構730的上面設置有結合焊盤754a的表面上的阻焊層752a而在實體上彼此分開。結合焊盤754a通過重佈線路結構730電性連接到嵌置在核心部分710中的通孔720。
在一些實施例中,結合焊盤754b設置在重佈線路結構740的表面上且在實體上連接到金屬化層744的最底層的底表面的被形成在介電層742的最底層中的開口暴露出的所述部分,其中結合焊盤754b通過形成在重佈線路結構740的上面設置有結合焊盤754b的表面上的阻焊層752b而在實體上彼此分開。結合焊盤754b通過重佈線路結構740電性連接到嵌置在核心部分710中的通孔720。
如圖17中所示,在一些實施例中,結合焊盤754a電性連接到重佈線路結構730且結合焊盤754b電性連接到重佈線路結構740。在一些實施例中,結合焊盤754a及結合焊盤754b可包括凸塊下金屬(underbumpmetallurgy,UBM),然而本公開並非僅限於此。如圖17中所示,舉例來說,結合焊盤754a與結合焊盤754b通過通孔720、重佈線路結構730及重佈線路結構740而彼此電性連接。
在替代實施例中,可從線路元件700省略重佈線路結構730及重佈線路結構740中的一者或兩者,本公開並非僅限於此。也就是說,舉例來說,線路元件700可包括核心部分710、多個通孔720、多個結合焊盤754a、多個結合焊盤754b、阻焊層752a及阻焊層752b,其中結合焊盤754a與結合焊盤754b通過通孔720而彼此電性連接。
在一些實施例中,在結合焊盤754b上分別形成多個導電端子810。如圖17中所示,舉例來說,導電端子810在實體上連接到結合焊盤754b。換句話說,導電端子810通過結合焊盤754b電性連接到線路元件700。導電端子810中的一些導電端子810通過結合焊盤754b電性連接到結合焊盤754a中的一些結合焊盤754a。在一些實施例中,導電端子810是例如晶片連接件或BGA球。
仍參照圖17,在一些實施例中,提供圖3中所繪示的晶片結構CS1’並將晶片結構CS1’結合到線路元件700,且將線路元件700結合到基底600以形成具有堆疊結構的封裝結構PK1E。在圖3中闡述了晶片結構CS1’的細節,且在圖16中闡述了基底600的細節,且因此本文中不再對其予以贅述。在一些實施例中,通過連接導電球120與線路元件700的結合焊盤754a而使晶片結構CS1’在實體上連接到線路元件700,且通過連接導電端子810與基底600的接觸焊盤610而使線路元件700在實體上連接到基底600。換句話說,晶片結構CS1’通過導電球120及結合焊盤754a電性連接到線路元件700,線路元件700通過導電端子810及接觸焊盤610電性連接到基底600,以使晶片結構CS1’通過導電端子120、結合焊盤754a、導電端子810及接觸焊盤610電性連接到基底600。在此種實施例中,導電球120是例如微凸塊,而導電端子810是晶片連接件,且導電端子640是焊料球或BGA球。在某些實施例中,可通過基底上晶圓上晶片(chip on wafer on substrate,CoWoS)封裝製程形成圖17中所繪示的封裝結構PK1E。
在上述實施例中,晶片結構包括嵌置在第一半導體晶粒內的至少一個第二半導體晶片,其中第二半導體晶片被第一導通孔環繞。另外,可使用重佈線層將第一半導體晶片的第一導通孔電性連接到第二半導體晶片的第二導通孔。通過使用此種整合晶片結構,可縮短半導體晶片之間的連通路徑(晶粒連接之間的精細節距),且可實現更好的信號/功率傳輸。由於進行多晶片堆疊,晶片的導通孔之間的距離縮短,因此用於將晶片電性連接在一起的重佈線層也將具有精細節距。另外,可將晶片結構整合在不同的封裝類型或模組中,例如CoWos、倒裝晶片、InFO/扇出型晶圓級封裝(WLP)。綜上所述,晶片尺吋的設計會更加靈活,可容易地實現期望的厚度及晶片功能整合,且可改善封裝結構的性能及效率。
根據本公開的一些實施例,提供一種晶片結構,所述晶片結構包括第一半導體晶片、第二半導體晶片及重佈線層。所述第一半導體晶片包括第一半導體基底、第一內連層、第一保護層、間隙填充層及多個第一導通孔,所述第一內連層位於所述第一半導體基底上,所述第一保護層覆蓋所述第一內連層,所述間隙填充層位於所述第一保護層上,所述多個第一導通孔嵌置在所述間隙填充層中且與所述第一內連層電性連接。所述第二半導體晶片嵌置在所述第一半導體晶片內且被所述間隙填充層及所述多個第一導通孔環繞,其中所述第二半導體晶片包括第二半導體基底、第二內連層、第二保護層及多個第二導通孔,所述第二內連層位於所述第二半導體基底上,所述第二保護層位於所述第二內連層上,所述多個第二導通孔嵌置在所述第二保護層中且與所述第二內連層電性連接,其中所述第二半導體基底結合到所述第一保護層。所述重佈線層位於所述第一半導體晶片的所述間隙填充層之上,其中所述重佈線層電性連接到所述多個第一導通孔及所述多個第二導通孔。
在一些實施例中,所述第一半導體晶片還包括第一蝕刻終止層,所述第一蝕刻終止層位於所述第一保護層與所述間隙填充層之間且覆蓋所述第二半導體晶片的側壁。在一些實施例中,所述間隙填充層包括第一子層及與所述第一子層分開的第二子層,且所述第一半導體晶片還包括位於所述第一子層與所述第二子層之間的第二蝕刻終止層。在一些實施例中,所述多個第一導通孔在實體上接觸所述第一蝕刻終止層及所述第二蝕刻終止層。在一些實施例中,所述第二內連層包括頂部金屬化層及多個下部金屬化層,且所述第二半導體晶片包括位於所述頂部金屬化層上且電性連接到所述頂部金屬化層的多個第二導電焊盤,且所述第二保護層將所述多個第二導電焊盤與所述重佈線層隔開。在一些實施例中,所述多個第二導通孔在實體上連接到所述第二內連層的所述頂部金屬化層。在一些實施例中,所述多個第二導通孔在實體上連接到所述多個第二導電焊盤。在一些實施例中,所述的晶片結構還包括第三半導體晶片,所述第三半導體晶片嵌置在所述第一半導體晶片內且被所述間隙填充層及所述多個第一導通孔環繞,其中所述第三半導體晶片包括第三半導體基底、第三內連層、第三保護層及多個第三導通孔,所述第三內連層位於所述第三半導體基底上,所述第三保護層位於所述第三內連層上,所述多個第三導通孔嵌置在所述第三保護層中且與所述第三內連層電性連接,其中所述第三半導體基底結合到所述第一保護層。在一些實施例中,所述的晶片結構還包括:第三半導體晶片,位於所述第二半導體晶片之上;第二間隙填充層,環繞所述第三半導體晶片;多個輔助導通孔,嵌置在所述第二間隙填充層內;以及輔助內連層,位於所述第一間隙填充層與所述第二間隙填充層之間,其中所述輔助內連層與所述多個第一導通孔、所述多個第二導通孔及所述多個輔助導通孔電性連接。
根據本公開的一些其他實施例,提供一種封裝結構,所述封裝結構包括至少一個整合晶片結構、絕緣封裝體、多個貫穿絕緣層孔及重佈線層。所述整合晶片結構包括第一半導體晶片及第二半導體晶片。所述第一半導體晶片包括第一半導體基底、第一內連層、第一保護層、間隙填充層及多個第一導通孔,所述第一內連層位於所述第一半導體基底上,所述第一保護層覆蓋所述第一內連層,所述間隙填充層位於所述第一保護層上,所述多個第一導通孔嵌置在所述間隙填充層中且與所述第一內連層電性連接。所述第二半導體晶片嵌置在所述第一半導體晶片內且被所述間隙填充層及所述多個第一導通孔環繞,其中所述第二半導體晶片包括第二半導體基底、第二內連層、第二保護層及多個第二導通孔,所述第二內連層位於所述第二半導體基底上,所述第二保護層位於所述第二內連層上,所述多個第二導通孔嵌置在所述第二保護層中且與所述第二內連層電性連接,其中所述第二半導體基底結合到所述第一保護層。所述絕緣封裝體具有第一表面及與所述第一表面相對的第二表面,其中所述絕緣封裝體包封所述至少一個整合晶片結構。所述多個貫穿絕緣層孔嵌置在所述絕緣封裝體內且環繞所述至少一個整合晶片結構。所述重佈線層位於所述絕緣封裝體的所述第一表面之上且電性連接到所述多個第一導通孔、所述多個第二導通孔及所述多個貫穿絕緣層孔。
在一些實施例中,所述的封裝結構還包括背面重佈線層,所述背面重佈線層位於所述絕緣封裝體的所述第二表面之上且電性連接到所述多個貫穿絕緣層孔,其中所述至少一個整合晶片結構結合到所述背面重佈線層的介電層。在一些實施例中,所述第一半導體晶片還包括第一蝕刻終止層,所述第一蝕刻終止層位於所述第一保護層與所述間隙填充層之間且覆蓋所述第二半導體晶片的側壁。在一些實施例中,所述至少一個整合晶片結構還包括位於所述第一半導體晶片的所述第一保護層與所述第二半導體晶片的所述第二半導體基底之間的結合膜。在一些實施例中,所述第二內連層包括頂部金屬化層及多個下部金屬化層,所述第二半導體晶片包括位於所述頂部金屬化層上且電性連接到所述頂部金屬化層的多個第二導電焊盤,且所述多個第二導通孔在實體上連接到所述頂部金屬化層且與所述多個第二導電焊盤相鄰。在一些實施例中,所述至少一個整合晶片結構還包括:第三半導體晶片,位於所述第二半導體晶片之上;第二間隙填充層,環繞所述第三半導體晶片;多個輔助導通孔,嵌置在所述第二間隙填充層內;以及輔助內連層,位於所述第一間隙填充層與所述第二間隙填充層之間,其中所述輔助內連層與所述多個第一導通孔、所述多個第二導通孔及所述多個輔助導通孔電性連接。
在本公開的又一實施例中,闡述一種製作晶片結構的方法。所述方法包括以下步驟。提供半導體晶圓,所述半導體晶圓具有多個第一半導體晶片,其中所述第一半導體晶片中的每一者包括第一半導體基底、第一內連層及第一保護層,所述第一內連層位於所述第一半導體基底上,所述第一保護層覆蓋所述第一內連層。在所述第一半導體晶片中的每一者的所述第一保護層上設置至少一個第二半導體晶片,其中所述至少一個第二半導體晶片包括第二半導體基底、第二內連層、第二保護層及多個第二導通孔,所述第二內連層位於所述第二半導體基底上,所述第二保護層位於所述第二內連層上,所述多個第二導通孔嵌置在所述第二保護層中且與所述第二內連層電性連接。形成位於第一保護層之上且覆蓋所述至少一個第二半導體晶片的間隙填充層。執行平坦化製程來移除所述第二保護層的一些部分及所述間隙填充層的一些部分以顯露出所述多個第二導通孔。對所述間隙填充層進行蝕刻且在所述間隙填充層中形成多個第一導通孔。對所述半導體晶圓進行切割,以將所述多個第一半導體晶片分離而形成所述晶片結構。
在一些實施例中,所述的製作晶片結構的方法還包括:在形成所述間隙填充層之前,形成覆蓋所述第一保護層及所述第二半導體晶片的第一蝕刻終止層,其中所述平坦化製程還移除所述第一蝕刻終止層的一些部分以使所述第一蝕刻終止層的剩餘部分覆蓋所述第一保護層的頂表面及所述第二半導體晶片的側壁。在一些實施例中,形成所述第二半導體晶片的方法包括:提供具有多個所述第二半導體晶片的第二半導體晶圓,其中所述第二半導體晶片中的每一者包括所述第二半導體基底及所述第二內連層,所述第二內連層位於所述第二半導體基底上;在所述第二內連層上形成所述多個第二導通孔,且形成環繞所述多個第二導通孔的第一保護部分;形成覆蓋所述多個第二導通孔且位於所述第一保護部分之上的第二保護部分,其中所述第一保護部分及所述第二保護部分構成所述第二保護層;對所述第二半導體晶圓的背面進行薄化且執行切割製程以將所述多個第二半導體晶片分離。在一些實施例中,所述平坦化製程移除所述第二保護層的至少所述第二保護部分。在一些實施例中,所述第二半導體基底通過熔融接合而直接結合到所述第一保護層上。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解,他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
101:第一半導體基底
102:第一內連層
102A、202A、AxI-2:層間介電層
102-LM、202-LM:下部金屬化層
102-TM、202-TM:頂部金屬化層
104:第一導電焊盤
106、118A、206、306、406A、412A、732、742、DI:介電層
108:第一導電柱
110:第一保護層
112:第一蝕刻終止層
112-TS、114-TS、116-TS、208-TS、210-TS、408-TS、410-TS:頂表面
113、117:第二蝕刻終止層
114:間隙填充層/第一間隙填充層
114-1:第一子層
114-2:第二子層
115:第二間隙填充層
116:第一導通孔
118、406、412:重佈線層
118B、406B、412B:導電層
118C、412C、550:導電焊盤
120、414、570:導電球
201:第二半導體基底/半導體基底
202:第二內連層
204:第二導電焊盤
208:第二導通孔/導通孔
210:第二保護層
210A:第一保護部分
210B:第二保護部分
301:第三半導體基底
302:第三內連層
304:第三導電焊盤
308:第三導通孔
310:第三保護層
402:載體
404:剝離層
406-BS:背面表面
408:貫穿絕緣層孔
410:絕緣材料
410’、560:絕緣封裝體
410-S1:第一表面
410-S2:第二表面
416:被動元件
418、640、810:導電端子
510、600:基底
520:半導體晶片
530:結合導線
540:焊盤
580:底部填充膠
610、620:接觸焊盤
630、734、744、AxI-1:金屬化層
700:線路元件
710:核心部分
720:通孔
730、740:重佈線路結構
752a、752b:阻焊層
754a、754b:結合焊盤
AxI:輔助內連層
AxV:輔助導通孔
BF:結合膜
CS1、CS1’、CS2、CS3、CS4、CS5、CS6、CS7、CS8、CS8’、CS9:晶片結構
DL:切割線
DT:切割膠帶
PK1A:封裝結構/第一封裝
PK1B、PK1C、PK1D、PK1E:封裝結構
PK2:第二封裝/封裝結構
POP1:疊層封裝結構
SC1:第一半導體晶片
SC2:第二半導體晶片
SC3:第三半導體晶片
SW:側壁
Tx:總厚度
WF、WF1:半導體晶圓
X1:膠帶
X2:框架
結合附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的臨界尺寸(critical dimension)。
圖1A到圖1E是根據本公開一些示例性實施例的製作半導體晶片的方法中各個階段的示意性剖視圖。
圖2A到圖2D是根據本公開一些示例性實施例的製作晶片結構的方法中各個階段的示意性剖視圖。
圖3是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖4是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖5是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖6是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖7是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖8是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖9是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖10是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖11是根據本公開一些其他示例性實施例的晶片結構的示意性剖視圖。
圖12A到圖12G是根據本公開一些示例性實施例的製作封裝結構的方法中各個階段的示意性剖視圖。
圖13是根據本公開一些示例性實施例的疊層封裝(package-on-package,PoP)結構的示意性剖視圖。
圖14是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖15是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖16是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖17是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
101:第一半導體基底
102:第一內連層
102A:層間介電層
102-LM:下部金屬化層
102-TM:頂部金屬化層
104:第一導電焊盤
108:第一導電柱
116:第一導通孔
118:重佈線層
118A:介電層
118B:導電層
118C:導電焊盤
120:導電球
201:第二半導體基底/半導體基底
208:第二導通孔/導通孔
CS1’:晶片結構
SC1:第一半導體晶片
SC2:第二半導體晶片
Claims (1)
- 一種晶片結構,包括: 第一半導體晶片,包括第一半導體基底、第一內連層、第一保護層、間隙填充層及多個第一導通孔,所述第一內連層位於所述第一半導體基底上,所述第一保護層覆蓋所述第一內連層,所述間隙填充層位於所述第一保護層上,所述多個第一導通孔嵌置在所述間隙填充層中且與所述第一內連層電性連接; 第二半導體晶片,嵌置在所述第一半導體晶片內且被所述間隙填充層及所述多個第一導通孔所環繞,其中所述第二半導體晶片包括第二半導體基底、第二內連層、第二保護層及多個第二導通孔,所述第二內連層位於所述第二半導體基底上,所述第二保護層位於所述第二內連層上,所述多個第二導通孔嵌置在所述第二保護層中且與所述第二內連層電性連接,其中所述第二半導體基底結合到所述第一保護層;以及 重佈線層,位於所述第一半導體晶片的所述間隙填充層上,其中所述重佈線層電性連接到所述多個第一導通孔及所述多個第二導通孔。
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- 2019-09-26 CN CN201910916392.9A patent/CN112242383A/zh active Pending
- 2019-10-22 TW TW108137977A patent/TW202105666A/zh unknown
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2021
- 2021-06-03 US US17/338,660 patent/US20210296288A1/en active Pending
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TWI815356B (zh) * | 2021-04-07 | 2023-09-11 | 聯發科技股份有限公司 | 三維焊盤結構、互連結構和半導體封裝 |
TWI754586B (zh) * | 2021-05-04 | 2022-02-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
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US20210020602A1 (en) | 2021-01-21 |
US20210296288A1 (en) | 2021-09-23 |
CN112242383A (zh) | 2021-01-19 |
US11063019B2 (en) | 2021-07-13 |
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