CN113053827A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN113053827A
CN113053827A CN202011371843.4A CN202011371843A CN113053827A CN 113053827 A CN113053827 A CN 113053827A CN 202011371843 A CN202011371843 A CN 202011371843A CN 113053827 A CN113053827 A CN 113053827A
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China
Prior art keywords
interposer
die
molding material
substrate
forming
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CN202011371843.4A
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English (en)
Inventor
陈伟铭
丁国强
侯上勇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/919,298 external-priority patent/US11380611B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113053827A publication Critical patent/CN113053827A/zh
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Abstract

一种形成半导体结构的方法包括将第一管芯和第二管芯分别接合至第一中介层的第一侧和第二中介层的第一侧，其中第一中介层横向邻近第二中介层；用第一模制材料密封第一中介层和第二中介层；在与第一中介层的第一侧相对的第一中介层的第二侧中形成第一凹槽；在与第二中介层的第一侧相对的第二中介层的第二侧中形成第二凹槽；以及用第一介电材料填充第一凹槽和第二凹槽。本发明的实施例还涉及半导体结构。

Description

半导体结构及其形成方法
技术领域
本发明的实施例涉及半导体结构及其形成方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体行业经历了快速的增长。在大多数情况下，集成密度的提高来自最小部件尺寸的不断减小，这允许将更多的组件集成到给定区域中。
随着对缩小电子器件的需求的增长，出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装系统的示例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以提供高水平的集成和组件密度。另一个示例是衬底上晶圆上芯片(CoWoS)结构。在一些实施例中，为了形成CoWoS结构，将多个半导体芯片附接至晶圆，然后执行切割工艺以将晶圆分成多个中介层，其中每个中介层都附接有一个或多个半导体芯片。附接有半导体芯片的中介层称为晶圆上芯片(CoW)结构。然后将CoW结构附接至衬底(例如印刷电路板)以形成CoWoS结构。这些以及其他先进的封装技术使得能够生产具有增强的功能和较小占用面积的半导体器件。
发明内容
本发明的实施例提供了一种形成半导体结构的方法，所述方法包括：分别将第一管芯和第二管芯接合至第一中介层的第一侧和第二中介层的第一侧，其中，所述第一中介层横向邻近所述第二中介层；用第一模制材料密封所述第一中介层和所述第二中介层；在与所述第一中介层的所述第一侧相对的所述第一中介层的第二侧中形成第一凹槽；在与所述第二中介层的所述第一侧相对的所述第二中介层的第二侧中形成第二凹槽；以及用第一介电材料填充所述第一凹槽和所述第二凹槽。
本发明的另一实施例提供了一种形成半导体结构的方法，所述方法包括：将第一管芯和第二管芯分别附接至第一中介层和第二中介层，其中，在所述附接之后，所述第一管芯横向邻近所述第二管芯，并且所述第一中介层横向邻近所述第二中介层；用第一模制材料围绕所述第一中介层和所述第二中介层；在远离所述第一管芯的所述第一中介层的第一表面中形成第一凹槽；在远离所述第二管芯的所述第二中介层的第一表面中形成第二凹槽；以及用聚合物层填充所述第一凹槽和所述第二凹槽。
本发明的又一实施例提供了一种半导体结构，包括：多个中介层，彼此横向邻近并且具有衬底通孔(TSV)；第一模制材料，位于所述多个中介层周围；至少一个管芯，接合至并且电连接至所述多个中介层中的至少一个；以及介电层，位于远离所述至少一个管芯的所述多个中介层的背侧。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图9示出了实施例中的在制造的各个阶段处的晶圆上芯片(CoW)结构的截面图。
图10示出了另一实施例中的CoW结构的截面图。
图11示出了另一实施例中的CoW结构的截面图。
图12示出了另一实施例中的CoW结构的截面图。
图13至图17示出了另一实施例中的在制造的各个阶段处的CoW结构的截面图。
图18示出了一些实施例中的形成半导体结构的方法的流程图。
具体实施方式
以下公开提供了许多用于实现本发明的不同特征的不同的实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个示例中重复参考数字和/字母。在整个说明书中，除非另有声明，不同图中的相同参考数字指的是使用相同或类似的材料通过相同或类似的方法形成的相同或类似的组件。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间相对描述符可以同样地作相应地解释。
在一些实施例中，通过形成复合中介层以及将多个管芯附接至复合中介层来形成晶圆上芯片(CoW)结构。该复合中介层包括嵌入在第一模制材料中的第一中介层和第二中介层。可以可选地在第一模制材料上方以及在第一中介层和第二中介层上方形成第一再分布结构。在将多个管芯附接至复合中介层之后，在多个管芯周围形成第二模制材料。接下来，从远离管芯的一侧减薄第一中介层和第二中介层中的每个。在减薄工艺之后，对于第一中介层和第二中介层的每个，在远离管芯的一侧形成凹槽，其中该凹槽暴露相应中介层(第一中介层或第二中介层)中的通孔的端部。接下来，在凹槽中形成介电材料(例如，聚合物材料)。随后，在介电材料上方形成介电层，并且在介电层上方形成外部连接件，并且将外部连接件电耦合至第一中介层和第二中介层的通孔。
图1至图9示出了实施例中的在制造的各个阶段处的晶圆上芯片(CoW)结构100的截面图。参考图1，两个中介层110例如通过粘合层151附接至载体150。载体150可以由合适的材料制成，诸如硅、聚合物、聚合物复合物、金属箔、陶瓷、玻璃、玻璃环氧树脂、氧化铍、胶带或用于结构支撑的其他合适的材料。在一些实施例中，粘合层151沉积或层压在载体150上方。粘合层151可以是光敏的，并且可以通过在随后的载体脱粘工艺中将例如紫外(UV)光照射在载体150上而容易地与载体150分离。例如，粘合层151可以是光热转换(LTHC)涂层。
每个中介层110包括：衬底101、位于衬底101中的通孔103(也称为通孔、衬底通孔(TSV)或导电柱)、位于衬底101的第一表面101A上的再分布结构107以及位于再分布结构107上方并且电耦合至再分布结构107的导电焊盘109。图1还示出了形成在衬底101中(例如第一表面101A附近)的电子组件105。
衬底101可以是例如掺杂或未掺杂的硅衬底，或绝缘体上硅(SOI)衬底的有源层。然而，衬底101可以可选地是玻璃衬底、陶瓷衬底、聚合物衬底或可以提供合适的保护和/或互连功能的任何其他衬底。在所示的实施例中，衬底101是硅衬底(例如，体硅衬底)。
在一些实施例中，衬底101包括电子组件105，诸如电阻器、电容器、信号分配电路、设计为实现特定功能(例如，信号处理功能或逻辑功能)的电路、这些的组合等。这些电子组件可以是有源的、无源的、这些的组合等。在其他实施例中，衬底101中没有有源和无源电子组件。所有这样的组合完全旨在包括在本发明的范围内。在示出的实施例中，在衬底101中形成诸如深沟槽电容器(DTC)的电子组件105。可以形成并且并联连接多个DTC以提供大电容并且显著增大电容密度，允许各种器件的构建，诸如更高质量的电力传输网络(PDN)。
通孔103从衬底101的第一表面101A朝向但未到达衬底101的第二表面101B。在随后的衬底减薄工艺中，从第二表面101B减薄衬底101，使得通孔103在第二表面101B处暴露(例如，延伸穿过衬底101)。通孔103可以由合适的导电材料形成，诸如铜、钨、铝、合金、它们的组合等。可以在通孔103和衬底101之间形成阻挡层104(在图1中未示出，但是在图9中示出)。阻挡层104可以包括诸如氮化钛的合适的导电材料，但是可以可选地利用其他材料，诸如氮化钽、钛等。在一些实施例中，阻挡层104由诸如SiO2或SiN的介电材料形成。作为示例，通孔103的宽度(例如直径)在约2μm和约50μm之间。
仍参考图1，在每个中介层110上方形成再分布结构107。再分布结构107包括导电子组件，诸如形成在一个或多个介电层中的一层或多层导线和通孔。为简单起见，在图1中未分别示出再分布结构107的导电子组件和介电层。在一些实施例中，再分布结构107提供了通孔103、电子组件105和导电焊盘109之间的电连接。
在一些实施例中，再分布结构107的一个或多个介电层由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其他实施例中，介电层由以下材料形成：氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)或硼掺杂的磷硅酸盐玻璃(BPSG)等。一个或多个介电层可以通过任何可接受的沉积工艺形成，诸如旋涂、化学气相沉积(CVD)、层压等或它们的组合。
在一些实施例中，再分布结构107的导电子组件包括由诸如铜、钛、钨、铝等的合适的导电材料形成的导线和/或导电通孔。可以通过例如在介电层中形成开口以暴露下面的导电子组件，在介电层上方和开口中形成晶种层，在晶种层上方形成具有设计的图案的图案化的光刻胶，在设计的图案中和晶种层上方镀(例如电镀或化学镀)导电材料，以及去除光刻胶和晶种层的其上未形成导电材料的部分来形成导电子组件。形成再分布结构107的导电子组件的其他方法是可能的，并且完全旨在包括在本发明的范围内。
导电焊盘109形成在再分布结构107的导电子组件上方并且电耦合至再分布结构107的导电子组件。导电焊盘109可以是任何合适的类型，诸如微凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍化学镀钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb、这些的组合等。
在图1的示例中，再分布结构107形成为具有与衬底101相同的宽度W1，使得再分布结构107的侧壁与衬底101的相应侧壁对准。在一些实施例中，宽度W1在约1mm和约52mm之间。虽然图1示出了用于形成CoW结构100的两个中介层110，但是如本领域技术人员容易理解的，可以使用其他数量的中介层110来形成CoW结构100。
接下来，在图2中，模制材料108形成在中介层110周围的载体150上方，并且再分布结构112形成在模制材料108和中介层110上方。导电连接件114形成在再分布结构112上方。
作为示例，模制材料108可以包括环氧树脂、有机聚合物、添加或不添加二氧化硅基填料或玻璃填料的聚合物或其他材料。在一些实施例中，模制材料108包括液体模塑料(LMC)，LMC在被施加时是凝胶型液体。当施加时，模制材料108还可以包括液体或固体。可选地，模制材料108可以包括其他绝缘和/或密封材料。在一些实施例中，使用晶圆级模制工艺来施加模制材料108。可以使用例如压缩模制、传递模制、模制底部填充(MUF)或其他方法来模制模制材料108。
接下来，在一些实施例中，使用固化工艺来固化模制材料108。固化工艺可以包括使用退火过程或其他加热工艺将模制材料108加热到预定温度达预定时间段。固化工艺还可以包括紫外线(UV)曝光工艺、红外(IR)能量曝光工艺、它们的组合或它们与加热工艺的组合。可选地，可以使用其他方法来固化模制材料108。在一些实施例中，不包括固化工艺。
在形成模制材料108之后，可以执行平坦化工艺，诸如化学和机械平坦化(CMP)，以去除模制材料108的过量部分，使得模制材料108和导电焊盘109具有共面的上表面。如图2所示，模制材料108围绕中介层110并且与中介层110的侧壁物理接触。
接下来，再分布结构112形成在模制材料108的上表面上方并且电耦合至导电焊盘109。再分布结构112包括形成在一个或多个介电层113中的一层或多层导电子组件111(例如，导线和通孔)。再分布结构112的材料和形成方法可以与再分布结构107的材料和形成方法相同或类似，因此不再重复细节。在图2的示例中，再分布结构112形成为与模制材料108共末端(例如，具有相同的宽度)，使得再分布结构112的侧壁与模制材料108的相应侧壁对准。图2中的再分布结构112从左侧的中介层110连续地延伸至右侧的中介层110。
接下来，在再分布结构112上方形成导电连接件114，并且导电连接件114电耦合至再分布结构112的导电子组件111。导电连接件114可以是任何合适的类型，诸如微凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍化学镀钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb、这些的组合等。如图2所示，焊料区域115可以形成在导电连接件114上方。
在图2的示例中，中介层110、模制材料108、再分布结构112和导电连接件114形成复合中介层160，复合中介层160用作CoW结构100中的中介层。由于多个中介层110用于形成复合中介层160，所以每个中介层110也可以称为小芯片中介层。
接下来，在图3中，例如通过回流工艺将半导体管芯121(也称为管芯或集成电路(IC)管芯)附接至导电连接件114，使得管芯121的管芯连接件117接合至相应的导电连接件114。在一些实施例中，管芯121可以是不同类型的。例如，管芯121中的一个可以是逻辑管芯，而另一管芯121可以是存储器管芯。在一些实施例中，所有管芯121为相同类型。在图3的示例中，管芯121中的一个(例如，中间的管芯121A)与左侧的中介层110重叠，并且与右侧的中介层110重叠。换句话说，管芯121A的第一部分在左侧的中介层110的横向范围内，并且管芯121A的第二部分设置在右侧的中介层110的横向范围内。
每个管芯121包括衬底、形成在衬底中/上的电子组件(例如，晶体管、电阻器、电容器、二极管等)以及位于衬底上方的互连结构，互连结构连接电子组件以形成管芯121的功能电路。管芯121还包括管芯连接件117，管芯连接件117提供到管芯121的电路的电连接。
管芯121的衬底可以是掺杂或未掺杂的半导体衬底，或者是绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括半导体材料层，诸如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。可以使用的其他衬底包括多层衬底、梯度衬底或混合取向衬底。
管芯121的电子组件包括各种各样的有源器件(例如，晶体管)和无源器件(例如，电容器、电阻器、电感器)等。可以使用任何合适的方法在管芯121的衬底内或上形成管芯121的电子组件。管芯121的互连结构包括形成在一个或多个介电层中的一个或多个金属化层(例如，铜层)，并且用于连接各种电子组件以形成功能电路。在实施例中，互连结构由电介质和导电材料(例如，铜)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。
可以在管芯121的互连结构上方形成一个或多个钝化层，以便为下面的管芯121的结构提供一定程度的保护。钝化层可以由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅、低k电介质(诸如碳掺杂的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)、这些的组合等。钝化层可以通过诸如化学气相沉积(CVD)的工艺形成，但是可以利用任何合适的工艺。
导电焊盘可以形成在钝化层上方并且可以延伸穿过钝化层以与管芯121的互连结构电接触。导电焊盘可以包括铝，但是可以可选地使用其他材料，诸如铜。
在导电焊盘上形成管芯121的管芯连接件117，以提供用于电连接至管芯121的电路的导电区域。管芯连接件117可以是铜柱、诸如微凸块等的接触凸块，并且可以包括诸如铜、锡、银或其他合适材料的材料。
接下来，在图4中，在管芯121和复合中介层160的再分布结构112之间以及在相邻的管芯121之间形成底部填充材料119。在形成底部填充材料119之后，在管芯121周围的再分布结构112上方形成模制材料118。
底部填充材料119可以包括液态环氧树脂，该液态环氧树脂例如使用分配针或其他合适的分配工具分配在管芯121和再分布结构112之间的间隙中，然后固化以硬化。如图4所示，底部填充材料119填充管芯121和再分布结构112之间的间隙。在一些实施例中，管芯121附接至再分布结构112，使得相邻管芯121之间的间隙小于约10μm(例如，≤10μm)，使得分配的底部填充材料119能够通过毛细作用力来填充管芯121的侧壁之间的间隙。在其他实施例中，省略底部填充材料119。
接下来，在复合中介层160上方和管芯121周围形成模制材料118。模制材料118的材料和形成方法可以与模制材料108相同或类似，因此这里不再重复细节。在一些实施例中，未形成底部填充材料119，并且模制的底部填充(MUF)材料用作模制材料118，该MUF材料填充管芯121和复合中介层160之间的间隙，并且填充相邻管芯121之间的间隙。
接下来，在图5中，将图4的结构翻转，并且将管芯121例如通过粘合层152附接至载体153。载体153和粘合层152可以分别与载体150和粘合层151相同或类似，因此不再重复细节。接下来，通过载体脱粘工艺去除载体150。载体脱粘工艺可以使用任何合适的工艺(诸如蚀刻、研磨和机械剥离)来去除载体150。在一些实施例中，通过在载体150的表面上方照射激光或UV光来使载体150脱粘。激光或UV光破坏与载体150结合的粘合层151的化学键，然后可以容易地使载体150脱粘。可以通过载体脱粘工艺去除粘合层151。在一些实施例中，执行附加的清洁工艺以去除粘合层151。
在载体脱粘工艺之后，执行减薄工艺以减小衬底101的厚度和模制材料108的厚度。该减薄工艺可以是任何合适的工艺，诸如CMP工艺。从通过去除载体150而暴露的衬底101的第二表面101B执行减薄工艺。减薄工艺继续，直到暴露通孔103。因此，在减薄工艺之后，通孔103、衬底101和模制材料108在图5中具有共面的上表面。注意，由于减薄工艺，图5中的衬底101的第一表面101A和第二表面101B之间的距离(例如，衬底101的厚度)小于图1中的距离。
接下来，在图6中，在图5的结构上方形成图案化的掩模层125，诸如光刻胶层。形成图案化的掩模层125以覆盖(例如，完全覆盖)图6中的模制材料108的上表面。此外，图案化的掩模层125还覆盖位于图案化的掩模层125正下方的衬底101的部分(例如，与模制材料108物理接触的部分)。换句话说，除了覆盖模制材料108的上表面之外，图案化的掩模层125还与衬底101的部分重叠。在一些实施例中，在图案化的掩模层125的侧壁125C(与衬底101重叠)和最近的衬底的侧壁101S(与模制材料108接触)之间测得的距离W2在约0mm至约10mm之间(例如，0mm＜W2＜10mm)。
接下来，去除通过图案化的掩模层125的开口暴露的衬底101的部分(例如，上层)以在衬底101的第二表面101B处形成凹槽124。可以执行蚀刻工艺(诸如各向异性蚀刻)以形成凹槽124。蚀刻工艺可以使用对衬底101的材料具有选择性的蚀刻剂(例如，具有较高的蚀刻速率)，使得蚀刻衬底101而基本上不侵蚀通孔103和阻挡层104(见图9)。在蚀刻工艺完成之后，通孔103的端部由凹槽124暴露。换句话说，通孔103的端部延伸至凹槽124中。沿着图6的垂直方向在衬底101的第二表面101B和凹槽124的底部之间测量的每个凹槽124的深度D在约0μm和约10μm之间(例如，0μm＜D＜10μm)。
接下来，在图7中，在凹槽124中形成材料123(例如，介电材料)，并且去除图案化的掩模层125。在示例实施例中，材料123是聚合物材料，诸如聚酰亚胺，并且通过诸如旋涂的合适的形成方法形成。除了聚合物材料以外，其他合适的介电材料(诸如SiN或SiO2)也可以用于通过任何合适的形成方法(诸如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)等)形成材料123。材料123可以过度填充凹槽124，并且可以形成在模制材料108上方，因此，可以执行诸如CMP的平坦化工艺以去除材料123的过量部分，使得材料123、衬底101、通孔103和模制材料108在图7中具有共面的上表面。作为示例，在平坦化工艺之后，材料123的厚度T1可以在0μm和约5μm之间(例如，0μm＜T1＜5μm)。举个例子。如图7所示，材料123嵌入在衬底101(例如，硅衬底)中，并且具有的宽度W3(沿着水平方向测量)小于衬底101的宽度W1。在所示的实施例中，材料123覆盖(例如，围绕)通孔103的端部的侧壁。在一些实施例中，通过使用相对便宜的形成方法(例如，旋涂)形成材料123，避免了随后的隔离沉积工艺，诸如具有高真空度的CVD工艺以在通孔103周围形成SiN层，从而避免了高真空CVD工艺的较高成本。
接下来，在图8中，在材料123、衬底101和模制材料108上方形成再分布结构126，此后，在再分布结构126上方形成聚合物层128。外部连接件127形成在聚合物层128上方并且电耦合至通孔103。
在一些实施例中，再分布结构126包括一个或多个介电层以及使用与再分布结构112相同或类似的形成方法形成在一个或多个介电层中的导电子组件(例如，导线、通孔)。为简单起见，图8和后续附图可以将再分布结构126示出为单层，同时要理解，再分布结构126可以具有在一个或多个介电层中形成的一层或多层导电子组件。在一些实施例中，省略了再分布结构126，并且聚合物层128直接形成在(例如，接触)材料123上。聚合物层128由与材料123相同的聚合物材料形成，诸如聚酰亚胺，但是在一些实施例中，聚合物层128可以由与材料123不同的聚合物材料形成。聚合物层128可以用作CoW结构100的钝化层。作为示例，聚合物层128的厚度大于0μm，并且小于约20μm。
接下来，在聚合物层128上方形成外部连接件127。在所示的实施例中，外部连接件127延伸穿过聚合物层128，并且电耦合至通孔103。外部连接件127可以是例如微凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍化学镀钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb、这些的组合等。作为示例，外部连接件127的宽度(例如，直径)可以在约20μm至约300μm之间。如图8所示，焊料区域129可以形成在外部连接件127上方。
接下来，在图9中，例如通过载体脱粘工艺去除载体153和粘合层152，并形成晶圆上芯片(CoW)结构100。虽然未示出，但是如本领域技术人员容易理解的，可以执行切割工艺以将CoW结构100与在制造工艺期间和CoW结构100同时形成的其他CoW结构分离。然后，可以将CoW结构100的外部连接件127接合至衬底(例如，印刷电路板(PCB))上，以形成衬底上晶圆上芯片(CoWoS)结构。
图10示出了另一实施例中的CoW结构100A的截面图。CoW结构100A类似于图9的CoW结构100，但是图9中的聚合物层128和再分布结构126(如果形成)被再分布结构132代替。在一些实施例中，通过遵循图1至图9中的相同或类似的处理步骤，形成CoW结构100A，但是在图8的处理步骤中，代替聚合物层128和再分布结构126，形成再分布结构132(包括导电子组件131和一个或多个介电层133)。
图11示出了另一实施例中的CoW结构100B的截面图。CoW结构100B类似于图9的CoW结构100，但是CoW结构100B不具有形成在复合中介层160中的再分布结构112。在一些实施例中，通过遵循图1至图9中的相同或类似的处理步骤，形成CoW结构100B。但是在图2的处理步骤中，省略了再分布结构112，并且在相应的下面的导电焊盘109上直接形成导电连接件114。接下来，在用于CoW结构100B的与图3类似的处理中，管芯121的管芯连接件117接合至导电连接件114。
图12示出了在又另一实施例中的CoW结构100C的截面图。CoW结构100C类似于图10的CoW结构100A，但是管芯121的数量可以更少，并且CoW结构100C的模制材料118的宽度小于CoW结构100A的模制材料118的宽度。例如，在CoW结构100、100A和100B中，模制材料118和模制材料108具有相同的宽度，使得模制材料118的侧壁与模制材料108的相应侧壁对准。在结构100C中，模制材料118的左侧壁与模制材料108的左侧壁对准，而模制材料118的右侧壁与模制材料108的右侧壁未对准(例如，横向间隔开)。通过例如执行蚀刻工艺以去除模制材料118的部分(例如，图12中的右侧的部分)，可以形成CoW结构100C中的模制材料118的形状。可以使用合适的形成方法(例如注射模制工艺)来形成模制材料118，以直接具有图12所示的形状。CoW结构100C可以适用于光连接应用，其中形成在衬底101中的光波导由模制材料118暴露。
实施例可以实现优点。例如，通过在中介层110的衬底101中形成电子组件105，中介层110可以设计成包括用于实现不同功能的各种功能电路，而不是简单地起到电气路由的功能(例如，中介层中仅具有通孔和导线)。随着CoW结构的集成密度的增大，中介层的尺寸可以增大以容纳附接至中介层的管芯的数量。然而，大的中介层可能需要中介层的平面性的更高标准(因此更高的成本)，以避免与中介层的非平面性有关的问题，诸如冷接头和应力相关的结构故障。本发明允许使用多个较小的小芯片中介层110容易地形成大型复合中介层160，从而避免了与维持较大中介层的平面性相关的成本。另外，通过在中介层110中形成诸如DTC的电子组件105并且通过例如再分布结构112将所有中介层110中的DTC电耦合，可以大大增加在复合中介层160中形成的DTC的数量。作为另一示例，材料123的形成消除了执行高真空CVD工艺的需求，从而降低了制造成本。
图13至图17示出了另一实施例中的在制造的各个阶段处的CoW结构100D的截面图。CoW结构100D类似于CoW结构100，但是可以在不同的处理步骤中形成。
参考图13，例如通过粘合层152将半导体管芯121附接至载体153。接下来，在半导体管芯121周围的载体153上方形成模制材料118。可以执行平坦化工艺，诸如CMP，以在半导体管芯的管芯连接件117和模制材料118之间实现共面的上表面。
接下来，在图14中，将多个中介层110附接至管芯121。在所示的实施例中，通过焊料区域115将中介层110的导电焊盘109接合至管芯121的管芯连接件117。中介层110中的每个都在其衬底101中形成有通孔103。在图14中，通孔103不延伸穿过衬底101。在随后的衬底减薄工艺中，减薄衬底101，使得通孔103延伸穿过衬底101。
接下来，在图15中，在模制材料118上方和中介层110周围形成模制材料108。执行诸如研磨工艺的减薄工艺以减薄衬底101，使得在图15中，通孔103在衬底101的上表面处暴露。作为减薄工艺的结果，在衬底101和模制材料108之间实现共面的上表面。图15还示出了模制通孔106，可以是通过在模制材料108中形成开口(例如，使用激光钻孔工艺、光刻或蚀刻技术)以暴露相应的管芯连接件117，并且使用可接受的形成方法(诸如镀)用导电材料(例如，铜)填充开口来形成模制通孔106。作为非限制性示例，图13至图15示出了在两个单独的处理步骤中形成的模制材料(例如118和108)，在管芯121和中介层110周围形成模制材料的其他方式也是可以的并且完全旨在包括在本发明的范围内。在一些实施例中，在将管芯121附接至载体153之后，在形成模制材料(例如118)之前，将中介层110附接至管芯121。然后，在附接中介层110之后，执行单个模制工艺以形成围绕管芯121和中介层110的模制材料。
接下来，在图16中，在通孔103的侧壁周围(例如，接触)的衬底101中形成材料123。在一些实施例中，可以执行图6至图7中所示的处理以形成材料123。在形成之后，材料123、通孔103、衬底101和模制材料108具有共面的上表面。
接下来，在图17中，在模制材料108上方形成可选的再分布结构126。接下来，在模制材料108上方和再分布结构126(如果形成)上方形成聚合物层128。形成延伸穿过聚合物层128并且电耦合至通孔103的外部连接件127。可以在外部连接件127的顶部上形成焊料区域129。
图18示出了一些实施例中的形成半导体器件的方法1000的流程图。应该理解，图18所示的实施例方法仅仅是许多可能的实施例方法的示例。本领域普通技术人员将认识到许多变化、替代和修改。例如，可以添加、移除、替换、重新布置和重复如图18所示的各个处理框。
参考图18，在框1010处，将第一管芯和第二管芯分别接合至第一中介层的第一侧和第二中介层的第一侧，其中第一中介层横向邻近第二中介层。在框1020处，用第一模制材料密封第一中介层和第二中介层。在框1030处，在与第一中介层的第一侧相对的第一中介层的第二侧中形成第一凹槽。在框1040处，在与第二中介层的第一侧相对的第二中介层的第二侧中形成第二凹槽。在框1050处，用第一介电材料填充第一凹槽和第二凹槽。
根据实施例，一种形成半导体结构的方法包括：分别将第一管芯和第二管芯接合至第一中介层的第一侧和第二中介层的第一侧，其中，第一中介层横向邻近第二中介层；用第一模制材料密封第一中介层和第二中介层；在与第一中介层的第一侧相对的第一中介层的第二侧中形成第一凹槽；在与第二中介层的第一侧相对的第二中介层的第二侧中形成第二凹槽；以及用第一介电材料填充第一凹槽和第二凹槽。在实施例中，该方法还包括在接合第一管芯和第二管芯之前，将第一中介层和第二中介层附接至载体。在实施例中，该方法还包括在接合第一管芯和第二管芯之后，用第二模制材料密封第一管芯和第二管芯。在实施例中，该方法还包括用底部填充材料填充第一管芯和第二管芯之间的间隙。在实施例中，该方法还包括在接合第一管芯和第二管芯之前，将第一管芯和第二管芯附接至载体。在实施例中，第一模制材料还密封第一管芯和第二管芯。在实施例中，该方法还包括用第二模制材料密封第一管芯和第二管芯。在实施例中，该方法还包括在第一模制材料中形成通孔。在实施例中，第一介电材料是聚合物。在实施例中，该方法还包括在第一介电材料上形成导电连接件，其中该导电连接件电耦合至第一中介层中的第一导电柱。
根据实施例，一种形成半导体结构的方法包括：将第一管芯和第二管芯分别附接至第一中介层和第二中介层，其中，在附接之后，第一管芯横向邻近第二管芯，第一中介层横向邻近第二中介层，用第一模制材料围绕第一中介层和第二中介层；在远离第一管芯的第一中介层的第一表面中形成第一凹槽；在远离第二管芯的第二中介层的第一表面中形成第二凹槽；以及用聚合物层填充第一凹槽和第二凹槽。在实施例中，远离第一管芯的聚合物层的表面与第一中介层的第一表面和第二中介层的第一表面齐平。在实施例中，其中形成第一凹槽包括：在第一中介层的第一表面上形成图案化的掩模层，其中图案化的掩模层覆盖第一模制材料，覆盖与第一模制材料接触的第一中介层的第一部分，并且暴露第一中介层的第二部分；以及执行各向异性蚀刻工艺以去除第一中介层的第二部分的外层。在实施例中，第一凹槽的宽度形成为小于第一中介层的宽度，使得第一凹槽的侧壁与和第一模制材料接触的第一中介层的相应侧壁间隔开。在实施例中，第一中介层包括第一衬底和位于第一衬底中的第一衬底通孔(TSV)，其中在形成第一凹槽之后，第一TSV延伸至第一凹槽中。
根据实施例，一种半导体结构包括：多个中介层，彼此横向邻近并且具有衬底通孔(TSV)；第一模制材料，位于多个中介层周围；至少一个管芯，接合至并且电连接至多个中介层中的至少一个；以及介电层，位于远离至少一个管芯的多个中介层的背侧。在实施例中，半导体结构还包括：第二模制材料，位于至少一个管芯周围；以及底部填充材料，位于多个中介层和至少一个管芯之间。在实施例中，第一模制材料围绕至少一个管芯。在实施例中，半导体结构还包括位于第一模制材料中的通孔，其中通孔电连接至至少一个管芯。在实施例中，介电层是聚合物层，其中半导体结构还包括位于介电层上的外部连接件。
前面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同配置不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体结构的方法，所述方法包括：
分别将第一管芯和第二管芯接合至第一中介层的第一侧和第二中介层的第一侧，其中，所述第一中介层横向邻近所述第二中介层；
用第一模制材料密封所述第一中介层和所述第二中介层；
在与所述第一中介层的所述第一侧相对的所述第一中介层的第二侧中形成第一凹槽；
在与所述第二中介层的所述第一侧相对的所述第二中介层的第二侧中形成第二凹槽；以及
用第一介电材料填充所述第一凹槽和所述第二凹槽。
2.根据权利要求1所述的方法，还包括：在接合所述第一管芯和所述第二管芯之前，将所述第一中介层和所述第二中介层附接至载体。
3.根据权利要求2所述的方法，还包括：在接合所述第一管芯和所述第二管芯之后，用第二模制材料密封所述第一管芯和所述第二管芯。
4.根据权利要求3所述的方法，还包括用底部填充材料填充所述第一管芯和所述第二管芯之间的间隙。
5.根据权利要求1所述的方法，还包括：在接合所述第一管芯和所述第二管芯之前，将所述第一管芯和所述第二管芯附接至载体。
6.根据权利要求5所述的方法，其中，所述第一模制材料还密封所述第一管芯和所述第二管芯。
7.根据权利要求5所述的方法，还包括用第二模制材料密封所述第一管芯和所述第二管芯。
8.根据权利要求5所述的方法，还包括在所述第一模制材料中形成通孔。
9.一种形成半导体结构的方法，所述方法包括：
将第一管芯和第二管芯分别附接至第一中介层和第二中介层，其中，在所述附接之后，所述第一管芯横向邻近所述第二管芯，并且所述第一中介层横向邻近所述第二中介层；
用第一模制材料围绕所述第一中介层和所述第二中介层；
在远离所述第一管芯的所述第一中介层的第一表面中形成第一凹槽；
在远离所述第二管芯的所述第二中介层的第一表面中形成第二凹槽；以及
用聚合物层填充所述第一凹槽和所述第二凹槽。
10.一种半导体结构，包括：
多个中介层，彼此横向邻近并且具有衬底通孔(TSV)；
第一模制材料，位于所述多个中介层周围；
至少一个管芯，接合至并且电连接至所述多个中介层中的至少一个；以及
介电层，位于远离所述至少一个管芯的所述多个中介层的背侧。
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