WO2022012476A1 - Mems器件晶圆级封装方法及封装结构 - Google Patents

Mems器件晶圆级封装方法及封装结构 Download PDF

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Publication number
WO2022012476A1
WO2022012476A1 PCT/CN2021/105828 CN2021105828W WO2022012476A1 WO 2022012476 A1 WO2022012476 A1 WO 2022012476A1 CN 2021105828 W CN2021105828 W CN 2021105828W WO 2022012476 A1 WO2022012476 A1 WO 2022012476A1
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WIPO (PCT)
Prior art keywords
electrical connection
wafer
cover
chip
connection portion
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Application number
PCT/CN2021/105828
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English (en)
French (fr)
Inventor
黄河
刘孟彬
向阳辉
Original Assignee
中芯集成电路（宁波）有限公司上海分公司
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Publication of WO2022012476A1 publication Critical patent/WO2022012476A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a wafer-level packaging method and packaging structure of a MEMS device.
  • advanced packaging methods mainly adopt the three-dimensional stacking mode of wafer-level system packaging (wafer level package system in package, WLPSIP), compared with the traditional system package, the wafer level system package is to complete the packaging integration process on the wafer, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, batch Sub-manufacturing and other advantages can significantly reduce workload and equipment requirements.
  • wafer level package system in package WLPSIP
  • Embodiments of the present invention provide a wafer-level packaging method and packaging structure for a MEMS device, so as to improve the compatibility and yield of obtained products while realizing wafer-level packaging.
  • an embodiment of the present invention provides a wafer-level packaging method for a MEMS device, including: providing a device wafer in which a first chip and a first chip electrically connected to the first chip are formed. an electrical connection; providing a cover in which an interconnect structure is formed, the interconnect structure including a second electrical connection; on a first surface of the device wafer or a first surface of the cover forming a wall, the area enclosed by the wall is a cavity; after forming the wall, bonding the cover and the device wafer, the first chip corresponds to the cavity, the first chip
  • the electrical connection part is opposite to the second electrical connection part, and both are located at least partially outside the enclosure wall, forming an electrical connection cavity, and the electrical connection cavity has an opening; a first conductive block is formed to electrically connect the first electrical connection a connection part and the second electrical connection part.
  • an embodiment of the present invention further provides a MEMS device packaging structure, including: a device substrate, in which a first chip and a first chip electrically connected to the first chip are formed. an electrical connection part; a cover, an interconnection structure is formed in the cover, and the interconnection structure includes a second electrical connection part; a fence is located between the device substrate and the cover, the first chip and the The cavities enclosed by the enclosure wall correspond to each other, the first electrical connection part and the second electrical connection part are opposite to each other, and both are at least partially located outside the enclosure wall; the first conductive block is electrically connected to the first electrical connection part. a connection part and the second electrical connection part.
  • the wafer-level packaging method for a MEMS device provided by the embodiment of the present invention utilizes a cover having an interconnection structure to bond with the MEMS device wafer, which can realize The MEMS device is interconnected with an external signal, and the device wafer and the cover are connected through a fence, which provides a generation space for the first conductive block that electrically connects the first electrical connection part and the second electrical connection part of the cover, and works for the MEMS device
  • the region provides a cavity working environment and improves the performance of the device.
  • the first electrical connection part of the device wafer is electrically connected to the second electrical connection part of the cover by an electroplating process, and the MEMS is electrically led out to the top of the cover, which avoids the TSV process and saves the process.
  • the cost reduces the difficulty of packaging the wafer-level system in the three-dimensional stacking mode, and improves the yield of the product.
  • the provided cover includes a release layer located between the substrate and the dielectric layer.
  • the substrate may be a process for interconnecting structures.
  • the existence of the release layer can be used after the processing of the interconnect structure or the bonding of the cover and the device wafer is completed.
  • the release of the release layer removes the substrate, improves the convenience of substrate removal, and can also achieve accurate control of substrate removal, avoiding the device caused by the low accuracy of thickness control when removing the substrate by grinding. damage and improve product yield.
  • 1 to 8 are schematic structural diagrams corresponding to each step in an embodiment of the wafer level packaging method of the present invention.
  • 9 to 10 are schematic structural diagrams corresponding to some steps in another embodiment of the wafer level packaging method of the present invention.
  • Wafer-level system packaging mainly includes two important processes of physical connection and electrical connection.
  • the most typical packaging method can be: 1) three-dimensionally stack the upper and lower bare chips on the substrate by curing glue, and use the wire bond process to wire the lead pads of the two bare chips to the substrate; 2 ) The upper and lower bare chips are three-dimensionally stacked on the substrate by curing glue, and wire The bonding process leads the lead pads of the upper bare chip to the lead pads of the lower bare chip, and then leads the lead pads of the lower bare chip to the substrate; 3) Through the bump welding prefabricated on the surface of the upper bare chip ) or prefabricated bump soldering on the lower bare chip surface to achieve flip-chip soldering, and use wire Bond the lead pads of the lower bare chip to the substrate; 4) Flip-chip bonding is realized by bump welding prefabricated on the surface of the upper bare chip or bump welding prefabricated on the surface of the lower bare chip, and using prefabricated bump welding on the surface of the lower bare chip A through
  • the bump flip-chip bonding process has been used more and more, especially the high-density system integration package based on the through-silicon via interconnection process and the micro-bump flip-chip bonding.
  • the TSV structure prefabricated in the lower bare chip will connect the lead pads of the lower bare chip to the backside of the lower bare chip, and with the development trend of integrated circuits, the complexity of integrated circuit design continues to increase, and the metal interconnection
  • the layout of the structure is correspondingly more and more complicated, thereby increasing the difficulty of the TSV process, and even the problem that the TSV structure cannot be formed due to the blocking effect of the functional structure (eg, metal interconnect structure) in the lower bare chip.
  • an embodiment of the present invention provides a wafer-level packaging method for a MEMS device, which can realize the interconnection between the MEMS device and an external signal by using a cover having an interconnection structure to bond with the MEMS device wafer. And the device wafer and the cover are connected by the fence, which provides a generation space for the first conductive block that electrically connects the first electrical connection part and the second electrical connection part of the cover, and provides a cavity working environment for the working area of the MEMS device, Improve device performance.
  • 1 to 8 are schematic structural diagrams corresponding to each step in an embodiment of the wafer level packaging method of the present invention.
  • a device wafer 100 is provided in which a first chip 110 and a first electrical connection portion 120 electrically connected to the first chip 110 are formed.
  • the wafer-level packaging method is used for realizing wafer-level system packaging, and the device wafer 100 is used for bonding with the chip to be integrated in the subsequent process.
  • the device wafer 100 is a MEMS device wafer.
  • the device wafer 100 is fabricated by using an integrated circuit fabrication technology.
  • the device wafer 100 includes a substrate.
  • the substrate is a silicon substrate.
  • the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or an insulator other types of substrates such as germanium substrates.
  • the device wafer 100 is formed with a first chip 110 and a first electrical connection part 120 .
  • the first electrical connection part 120 is located on the device wafer 100 .
  • the first surface of the first electrical connection part 120 is exposed; in addition, the first electrical connection part 120 does not cover the first chip 110 to provide a basis for forming the cavity working environment of the first chip 110 in the subsequent process. , the first chip 110 is exposed.
  • the surface of the first electrical connection portion 120 protrudes from the surface of the first chip 110 and is electrically connected to the internal structure of the first chip 110 .
  • the surface of the first electrical connection part 120 may be the same surface as the surface of the first chip 110 , or the surface of the first electrical connection part 120 may be lower than the surface of the first chip 110 .
  • the device wafer 100 includes a front side of the wafer and a back side of the wafer, and the first electrical connection portion 120 is located on the front side of the wafer, that is, the first electrical connection portion 120 is exposed from the front side of the wafer.
  • the backside of the wafer refers to the bottom surface of the substrate in the device wafer 100 .
  • the exposed position of the first electrical connection portion 120 can be protected by a dielectric layer (not marked) to prevent short circuits, and in the wafer-level packaging method of the MEMS device, the dielectric layer is etched to expose the exposed position The first electrical connection portion 120 is described.
  • this embodiment is described by taking as an example that the device wafer 100 has three first chips 110 formed therein.
  • the number of the first chips 110 is not limited to three.
  • the number of the first electrical connection parts 120 electrically connected to the same first chip 110 is two, so as to realize the input and output of the signals of the first chip 110 .
  • the number of the electrically connected first electrical connection parts 120 may be plural.
  • each first chip 110 of the same device wafer 100 may be the same type of chip with the same function, or may be a chip with different functions, and each first chip 110 of the same device wafer 100 may specifically be It includes at least one of a bulk acoustic wave filter, a surface acoustic wave filter, a solid-state assembly resonator, a microphone and a fingerprint identification device.
  • a cover 300 is provided, and an interconnect structure 331 is formed in the cover 300 , and the interconnect structure 331 includes a second electrical connection portion 331 a.
  • the cover 300 is a part of the to-be-integrated structure of the wafer level package, wherein the interconnect structure 331 is formed, and the position of the first electrical connection part 120 on the wafer plane is changed while realizing the packaging of the device wafer 100 .
  • the cover 300 is fabricated by using an integrated circuit manufacturing technology, and the second electrical connection portion 331a is located on the first surface of the cover 300, that is, the second electrical connection portion 331a is exposed.
  • the exposed position of the second electrical connection portion 331a can be protected by a dielectric layer (not marked) to prevent short circuits, and in the wafer-level packaging method of the MEMS device, the dielectric layer is etched to expose all the parts.
  • the second electrical connection portion 331a is described, and the surface of the second electrical connection portion 331a is lower than the surface of the dielectric layer, that is, a groove is formed.
  • the cover 300 may include a substrate 310.
  • the substrate 310 is a silicon substrate.
  • the material of the substrate may also be germanium, silicon germanium, silicon carbide, or arsenide.
  • Other materials such as gallium, indium gallium or glass, and the substrate can also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
  • the cap may not include the substrate, but only include the dielectric layer formed with the interconnect structure.
  • the cover 300 is obtained through the following steps: providing a substrate 310 ; forming a release layer 320 on the substrate 310 , the release layer 320 covering the substrate 310 ; forming on the release layer 320 A dielectric layer 330 in which an interconnect structure 331 is formed.
  • the step of forming the cap 300 may further include, after forming the interconnect structure 331 in the dielectric layer 330 , releasing the release layer 320 and removing the substrate 310 . That is, the capping cap 300 includes only the dielectric layer on which the interconnection structure 331 is formed.
  • the substrate 310 provides support for the fabrication of the interconnect structures 331 of the cap 300 .
  • the release layer 320 facilitates the removal of the substrate 310.
  • the release layer 320 is a germanium release layer; in other embodiments, the release layer material is at least one of carbon and a pyrolysis film; When the substrate is light-transmitting glass, the material of the release layer can also be a photolysis film.
  • the dielectric layer 330 provides a forming space for the interconnect structure 331. As shown in FIG. 2, a dielectric material layer is first deposited on the release layer 320, and then etching and filling are performed at the corresponding positions of the dielectric material layer to form the interconnect structure. 331.
  • the material of the dielectric layer 330 is high-resistance silicon, and the material of the interconnection structure 331 is copper, and the resistivity of copper is relatively low.
  • the interconnection structure 331 is formed in the interconnection structure hole, and the filling of copper is good, thereby improving the formation quality of the interconnection structure 331 in the interconnection structure hole.
  • the material of the dielectric layer can also be other materials with higher resistance, and the material of the interconnect structure can also be other applicable conductive materials, such as: nickel, zinc, tin, gold, tungsten, magnesium .
  • the interconnection structure further includes a third electrical connection portion that is electrically connected to the second electrical connection portion, and the third electrical connection portion and the second electrical connection portion are respectively located on two opposite surfaces of the cover.
  • the cover 300 includes a substrate 310 and a release layer 320 , and the third electrical connection part and the second electrical connection part are respectively located on two opposite surfaces of the cover, which means that the interconnect structure 331 can It includes a second electrical connection portion 331a located on the first surface of the dielectric layer 330, and a third electrical connection portion 331c located on the second surface of the dielectric layer 330.
  • the second electrical connection portion 331a and the third electrical connection portion 331c can also be electrically connected.
  • the plug 331b of the electrical connection portion 331c includes a redistribution layer layer, RDL) structure (not shown in the figure), the first surface of the dielectric layer 330 is opposite to the second surface of the dielectric layer 330 .
  • the cover only includes a dielectric layer formed with an interconnect structure, then the third electrical connection portion and the second electrical connection portion are located on two opposite surfaces of the dielectric layer, that is, on two opposite surfaces of the cover, respectively. a surface.
  • a thinning process may be performed after the processing of the interconnect structure 311 or the wafer-level packaging of the MEMS device is completed.
  • the release layer 320 is first formed on the substrate 310, and then the dielectric layer 330 is formed on the release layer 320.
  • the substrate 310 can provide support for the processing of the interconnect structure 331, or simultaneously provide the cover 300 and the device wafer.
  • the presence of the release layer 320 can remove the liner by releasing the release layer 320 after the processing of the interconnect structure 331 or the bonding of the cover 300 and the device wafer 100 is completed.
  • the bottom 310 can improve the convenience of removing the substrate 310, and can also realize the accurate control of the substrate 310 removal, and avoid the damage to the device caused by the low thickness control accuracy caused by the removal of the substrate 310 by grinding. , improve the product yield.
  • the dielectric layer may also be directly formed on the substrate, thereby forming the interconnect structure.
  • the cap 300 may be a wafer-level cap, that is, the cap 300 has the size of a wafer, and the number of the interconnect structures 331 of the cap 300 is the same as the number of the first electrical connection parts 110 of the device wafer 100 .
  • the number of the first chips 110 of the device wafer 100 is three, and the number of the first electrical connection parts 120 electrically connected to each of the first chips 110 is two.
  • the number of interconnect structures 331 of the cover 300 is correspondingly six. But the number of interconnect structures 331 is not limited to six.
  • wafer-level packaging can be achieved through one-time bonding, which can simplify the processing process and improve the packaging speed.
  • the cover 300 may be a chip-level cover, and the providing of the cover described herein includes providing a plurality of chip-level covers, and the number of the chip-level covers may be the same as that of the first chip 110 of the device wafer 100 .
  • the number is the same as the number of the first chips 110 of the device wafer 100 .
  • the number of the second electrical connection parts 331 a of each chip level cap is the same as the number of the first electrical connection parts of each first chip 110 . 120 is the same amount.
  • the structures of the chip-level caps may be the same, or may be different on the basis of ensuring subsequent bonding and packaging requirements;
  • chip-level caps with different structures may be selected to realize the transfer interconnection of different first chips 110 .
  • a plurality of discrete chip-level caps can be obtained by dicing the wafer-level caps.
  • a wall 200 is formed on the first surface of the device wafer 100 , and the area enclosed by the wall 200 is a cavity 210 .
  • a support is formed between the device wafer 100 and the cover 300 to provide space for the electrical connection of the first electrical connection portion 120 and the second electrical connection portion 331a.
  • the area enclosed by the wall 200 is the cavity 210 , which corresponds to the position of the first chip 110 of the device wafer 100 , and provides an active space for the first chip to improve the performance of the first chip.
  • the surrounding wall 200 may be formed on a part of the surface of the first electrical connection structure 120 and the edge of the first chip 110 .
  • it can also be formed only on a part of the surface of the first electrical connection structure 120 , so that the surrounding walls 200 can be formed on the plurality of first electrical connection structures 120 in the same step, thereby improving the packaging. efficiency, while avoiding occupying the area corresponding to the first chip 110 to form an unsealed cavity 210 .
  • the material of the enclosure wall 200 may be a dry film (Dry Film). Dry film is a sticky photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. After exposure and development, patterns can be formed in the dry film light.
  • Dry film is a sticky photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. After exposure and development, patterns can be formed in the dry film light.
  • the material of the wall 200 may be metal. First, a metal layer is deposited on the first surface of the device wafer 100 , and then the metal layer is etched. A dielectric layer is deposited on the first surface of the first electrical connection structure 120 , a part of the surface of the first electrical connection structure 120 close to the first chip 100 and the dielectric layer on the edge of the first chip 110 are etched to form filling holes, metal is filled in the filling holes, and the remaining parts are removed A dielectric layer is formed to obtain an enclosure; in other embodiments, the material of the enclosure may also be a photosensitive material, so that patterning can be achieved through a photolithography process, thereby reducing damage to electrodes or external interconnect lines.
  • the thickness of the enclosure wall 200 should not be too small or too large. If the thickness is too small, the height of the enclosure wall 200 is likely to be insufficient, so that a sufficient filling space for the electrical connection material of the first electrical connection portion 120 and the second electrical connection portion 331a cannot be provided, which increases the difficulty of filling the subsequent conductive material therein. It also cannot provide enough space for the cavity 210, and cannot meet the requirements of the first chip 110 for the movable space; if the thickness is too large, the thickness of the subsequently formed package structure will be too large, which is not conducive to the miniaturization of the device. developing. Therefore, in this embodiment, the thickness of the wall 200 ranges from 5 microns to 50 microns.
  • the cover 300 is bonded to the device wafer 100 , the first chip 110 corresponds to the cavity 210 , and the first electrical connection portion 120 Opposite to the second electrical connection portion 331 a and at least partially located outside the enclosure wall 200 , an electrical connection cavity 400 is formed.
  • the enclosure wall 200 After the enclosure wall 200 is formed, by bonding the cover 300 on the enclosure wall 200 , the system integration of the cover 300 and the device wafer 100 is realized. Furthermore, the first surface of the cover 300 is bonded to the enclosure wall 200 so that the second electrical connection portion 331a faces the first electrical connection portion 120 to realize the electrical connection between the first electrical connection portion 120 and the second electrical connection portion 331a.
  • an electrical connection cavity 400 is formed between the first electrical connection portion 120 and the second electrical connection portion 331a, and the electrical connection cavity 400 is used to fill the electrical connection material.
  • the material of the enclosure wall 200 is dry film, and the cover 300 can be bonded to the device wafer 100 by adhering the cover 300 to the enclosure wall 200 .
  • the material of the wall 200 is metal, and the bonding between the cover 300 and the device wafer 100 is realized by metal-to-metal bonding.
  • the cover 300 is a wafer-level cover. After the cover 300 is bonded to the device wafer 100 , in addition to the electrical connection cavity 400 located at the edge, in order to facilitate subsequent filling of electrical connection materials The cover 300 may be cut.
  • the opening 600 communicates with the electrical connection cavity 400 , so that the filling electrical connection material enters the electrical connection cavity 400 through the opening 600 to realize the electrical connection between the first electrical connection part 120 and the second electrical connection part 331 a.
  • a laser cutting process may be used to cut the cover 300 along the cutting path to form the opening 600 ; in other embodiments, a knife cutting process may also be used to cut the cover 300 along the cutting path to form the opening 600 .
  • the cover is a chip-level cover, and when the cover is bonded to the device wafer, each chip-level cover is bonded to each first chip, and the chip-level cover is bonded to the first chip.
  • the electrical connection cavity between the first electrical connection part and the second electrical connection part is an unsealed cavity, and an opening is directly formed, so that the electrical connection material can be filled into the electrical connection cavity.
  • a first conductive block 410 is formed to electrically connect the first electrical connection portion 120 and the second electrical connection portion 331 a.
  • the first electrical connection portion 120 and the second electrical connection portion 331 a are electrically connected through the first conductive block 410 , so as to realize the interconnection package between the cover 300 and the device wafer 100 , and to connect the electrical properties of the device wafer 100 . Lead out, and then prepare for the subsequent packaging process. For example, the electrical connection between the first chip 110 and other substrates (eg, circuit boards) can be achieved subsequently through the second conductive blocks 420 (shown in FIG. 7 ).
  • an electroplating process can be used to fill the electrical connection material from the boundary of the opening 600 into the electrical connection cavity 400 to form the first conductive block 410 , and the first conductive block 410 in the electrical connection cavity 400 is electrically connected to the first electrical connection.
  • Both the part 120 and the second electrical connection part 331a are in contact, so the electrical connection between the first electrical connection part 120 and the second electrical connection part 331a can be realized.
  • a good filling effect can be achieved in the electrical connection cavity 400, thereby improving the reliability of the electrical connection.
  • the electroplating process is electroless electroplating (ie, electroless plating).
  • the bonded cover 300 and the device wafer 100 are placed in a solution containing metal ions (eg, electroless silver plating, nickel plating, copper plating, etc.) without powering on.
  • metal ions eg, electroless silver plating, nickel plating, copper plating, etc.
  • the strong reducing agent reduces metal ions to metal and is deposited on the surfaces of the first electrical connection portion 120 and the second electrical connection portion 331a to form a dense metal plating layer.
  • the metal plating layer fills the electrical connection cavity 400. is full, thereby forming the first conductive block 410 . Therefore, the material of the first conductive block 410 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten and magnesium.
  • a bumping process may also be used to form solder bumps on the first electrical connection part or the second electrical connection part as the first electrical connection block.
  • the release layer 320 is released and the substrate 310 is removed.
  • the release layer 320 is released after the bonding of the cover 300 and the device wafer 100 is completed, which can reduce the thickness requirement for the dielectric layer 330 of the cover 300 and reduce the difficulty of bonding.
  • the opening 600 is formed first and then the release layer 320 is released, which can enlarge the etching area or the heating area of the release layer 320 , improve the removal speed of the release layer 320 , and improve the processing efficiency.
  • the substrate 310 is a silicon substrate, and the release layer 320 is a germanium release layer; the release layer 320 can be etched through a wet etching process to realize the release layer 320 and the substrate 310 of removal.
  • the release layer and the substrate can be removed by heating, when the material of the release layer is a photolytic film and the substrate is a transparent glass At the same time, the removal of the release layer and the substrate can be achieved by means of illumination.
  • the release layer and the substrate can also be removed first, and then the opening 600 can be formed by cutting.
  • the interconnect structure 331 may include a second electrical connection part 331 a located on the first surface of the dielectric layer 330 (ie, the first surface of the cap 300 ), a third electrical connection part 331 a located on the second surface of the dielectric layer 330
  • the electrical connection portion 331c, and the plug 331b electrically connecting the second electrical connection portion 331a and the third electrical connection portion 331c, after removing the release layer 320 and the substrate 310, the third electrical connection portion 331c is exposed to the second Therefore, while the first conductive block 410 is formed by electroplating, the second conductive block 420 is also formed on the surface of the third electrical connection part 331c to realize subsequent electrical connection with other substrates (eg, circuit boards).
  • the formation of the first conductive block 410 and the second conductive block 420 can be realized by one-time electroplating, which can simplify the process flow and improve the process efficiency.
  • the second conductive block may also be formed by implanting balls on the third electrical connection portion, and the second conductive block and the first conductive block may be generated separately.
  • the cover 300 having the interconnection structure 330 is used to bond the wafer device 100, and the first electrical connection of the device wafer 100 is made by an electroplating process.
  • the part 120 is electrically connected to the second electrical connection part 331a of the cover 300, so that the connection points of the first electrical connection parts 120 of the first chips 110 of the device wafer 100 can be rewired in the plane direction of the device wafer 100, thereby improving the performance of the device wafer 100.
  • connection portion 331a provides a space for the generation of the first conductive block 410, and the electrical connection between the three-dimensionally stacked components is realized through the electroplating process, omitting the use of the through-silicon via interconnect technology, and reducing the number of wafers in the three-dimensional three-dimensional stacking mode.
  • the difficulty of level system packaging can improve the yield of products, and the device wafer 100 and the cover 300 are connected through the wall 200, and a cavity 210 can also be formed at a position corresponding to the first chip 110 to provide the first chip 110. Moveable space to improve device performance.
  • the method further includes: filling the opening 600 with an injection molding agent to form the encapsulation layer 500 .
  • the encapsulation layer 500 is used to protect and insulate the first conductive block 410 . Therefore, the material of the encapsulation layer 500 is an insulating material. In this embodiment, the material of the encapsulation layer 500 is epoxy resin. In other embodiments, the material of the encapsulation layer includes one or both of a dielectric material and a plastic encapsulation material, wherein the dielectric material may be silicon oxide, nitrogen Silicon or other dielectric materials.
  • the encapsulation layer 500 can further protect and insulate the second conductive block 420, and in order to satisfy the protection of the second conductive block 420 and facilitate the connection between the second conductive block 420 and other circuits at the same time
  • the encapsulation layer 500 may cover part of the second conductive block 420 .
  • the encapsulation layer 500 may completely cover the top surface of the second conductive block 420, or be flush with the top surface of the second conductive block 420, for this purpose, the encapsulation layer may be planarized until the second conductive block 420 is exposed. Conductive block 420 . In other embodiments, after the encapsulation layer is formed, the encapsulation layer above the second conductive block may be etched to expose the second conductive block.
  • the method further includes: cutting the device wafer 100 bonded with the interconnect structure 331 , and separating each of the device wafers 100 .
  • the first chip 110 is
  • the device wafer 100 bonded with the interconnect structure 331 is cut to obtain each first chip 110 having the interconnect structure 331 .
  • the cutting process for cutting the device wafer 100 may be either a knife cutting process or a laser cutting process.
  • 9 to 10 are schematic structural diagrams corresponding to each step in another embodiment of the wafer level packaging method of the present invention.
  • an enclosure wall 200 is formed on the first surface of the cover 300 , and the enclosure wall 200 The enclosed area is the cavity 210 .
  • a wall 200 is formed on the first surface of the cover 300 , and the area enclosed by the wall 200 is the cavity 210 .
  • the enclosure wall 200 For the specific description of the enclosure wall 200, please refer to the foregoing content, which will not be repeated here. It should be noted that, when the cavity 210 enclosed by the wall 200 is subsequently bonded to the device wafer 100, the cavity needs to correspond to the first chip 110, and the wall 200 will not completely cover the second electrical connection part 331a to ensure subsequent electrical connection with the first electrical connection part 120 .
  • the enclosure wall 200 is formed on each cover chip, and then each of the cover chips with the enclosure wall 200 formed thereon is bonded to the device wafer 100 .
  • the cover 300 is bonded to the device wafer 100 , the first chip 110 corresponds to the cavity 210 , and the first electrical connection portion 120 Opposite to the second electrical connection portion 331 a and at least partially located outside the enclosure wall 200 .
  • the cover 300 formed with the enclosure wall 200 is bonded to the device wafer 100, so that the first chip 110 corresponds to the cavity 210, and the first electrical connection portion 120 and the second electrical connection portion 331a are opposite to each other , and are at least partially located outside the enclosure wall 200 .
  • the present invention also provides a MEMS device packaging structure, comprising: a device substrate, wherein a first chip and a first electrical connection part electrically connected to the first chip are formed in the device substrate; a cover, An interconnection structure is formed in the cover, and the interconnection structure includes a second electrical connection part; a surrounding wall is located between the device substrate and the cover, and a space enclosed by the first chip and the surrounding wall is formed. corresponding to the cavity, the first electrical connection part and the second electrical connection part are opposite to each other, and both are at least partially located outside the enclosure; a first conductive block is electrically connected to the first electrical connection part and the second electrical connection part electrical connection.
  • FIG. 8 is a schematic structural diagram of an embodiment of the MEMS device packaging structure of the present invention.
  • the MEMS device packaging structure uses the device wafer 100 as the device substrate and the dielectric layer 330 forming the interconnect structure 331 as the cover, including: the device wafer 100, in which the device wafer 100 is A first chip 110 and a first electrical connection part 120 electrically connected to the first chip 110 are formed; a cover, an interconnection structure 331 is formed in the cover, and the interconnection structure 331 includes a second electrical connection part 331a ; Wall 200, located between the device wafer 100 and the cover, the first chip 110 corresponds to the cavity surrounded by the wall 200, the first electrical connection 120 and the first
  • the two electrical connection portions 331a are opposite to each other, and both are at least partially located outside the enclosure wall 200; the first conductive block 410 is electrically connected to the first electrical connection portion 120 and the second electrical connection portion 331a.
  • the device wafer 100 is a MEMS device wafer.
  • the device wafer 100 is fabricated by using an integrated circuit fabrication technology.
  • the device wafer 100 includes a substrate.
  • the substrate is a silicon substrate.
  • the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or an insulator other types of substrates such as germanium substrates.
  • the exposed position of the first electrical connection portion 120 can be protected by a dielectric layer (not shown) to prevent short circuits, and in the MEMS device wafer level packaging method, the first electrical connection is exposed by etching the dielectric layer. Section 120.
  • this embodiment is described by taking as an example that the device wafer 100 has three first chips 110 formed therein.
  • the number of the first chips 110 is not limited to three.
  • the number of the first electrical connection parts 120 electrically connected to the same first chip 110 is two, so as to realize the input and output of the signals of the first chip 110 .
  • the number of the electrically connected first electrical connection parts 120 may be plural.
  • Each first chip 110 of the same device wafer 100 may be a chip of the same type with the same function, or may be a chip with different functions, and each first chip 110 of the same device wafer 100 may specifically include: a bulk acoustic wave filter at least one of a device, a surface acoustic wave filter, a solid-state mounted resonator, a microphone, and a fingerprint identification device.
  • the cap may be a wafer-level cap, that is, the cap has the size of a wafer, and the number of the interconnect structures 331 of the cap is the same as the number of the first electrical connection portions 110 of the device wafer 100 .
  • the number of the first chips 110 of the device wafer 100 is three, and the number of the first electrical connection parts 120 electrically connected to each of the first chips 110 is two.
  • the number of interconnect structures 331 of the cover is correspondingly six. But the number of interconnect structures 331 is not limited to six.
  • the packaging process can realize wafer-level packaging through one-time bonding, which can simplify the processing process and improve the packaging speed.
  • the cover when the device substrate is a device wafer, the cover may also be a chip-level cover, so that chip-level covers with different structures can be selected to achieve different interconnection requirements.
  • the device substrate may also be a MEMS device chip
  • the MEMS device packaging structure is a MEMS device chip-level packaging structure
  • the cover is also a chip-level cover, and other structures are the same as the device wafer. It is similar in shape and will not be repeated here.
  • the cover is a part of the package structure, in which the interconnect structure 331 is formed to change the position of the first electrical connection part 120 on the wafer plane while realizing the package of the device wafer 100 .
  • the cover is made of integrated circuit manufacturing technology, and the exposed position of the second electrical connection portion 331a can be protected by a dielectric layer (not marked) to prevent short circuits, and in the wafer-level packaging method of MEMS devices, the dielectric layer is Etching is performed to expose the second electrical connection portion 331a, and the surface of the second electrical connection portion 331a is lower than the surface of the dielectric layer, that is, grooves are formed.
  • the material of the interconnection structure 331 is copper, and the resistivity of copper is low. By selecting the copper material, it is beneficial to improve the electrical conductivity of the interconnection structure 331; Preferably, the formation quality of the interconnect structure 331 in the interconnect structure hole is improved.
  • the material of the interconnect structure may also be other applicable conductive materials, such as nickel, zinc, tin, gold, tungsten, and magnesium.
  • the material of the enclosure wall 200 may be a dry film (Dry Film). Dry film is a sticky photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. After exposure and development, patterns can be formed in the dry film light.
  • Dry film is a sticky photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. After exposure and development, patterns can be formed in the dry film light.
  • the material of the wall 200 may be metal.
  • a metal layer is first deposited on the first surface of the device wafer 100, and then the metal layer is etched, and the remaining metal layer is used as the wall, or
  • a dielectric layer is deposited on the first surface of the device wafer 100, a part of the surface of the first electrical connection structure 120 close to the first chip 100 and the dielectric layer on the edge of the first chip 110 are etched to form filling holes, and metal is filled in the filling holes, And remove the remaining dielectric layer to obtain a fence; in other embodiments, the material of the fence can also be a photosensitive material, so that patterning can be achieved through a photolithography process, thereby reducing damage to electrodes or external interconnect lines.
  • the thickness of the enclosure wall 200 should not be too small or too large. If the thickness is too small, the height of the enclosure wall 200 is likely to be insufficient, so that a sufficient filling space for the electrical connection material of the first electrical connection portion 120 and the second electrical connection portion 331a cannot be provided, which increases the difficulty of filling the subsequent conductive material therein. It also cannot provide enough space for the cavity 210, and cannot meet the requirements of the first chip 110 for the movable space; if the thickness is too large, the thickness of the subsequently formed package structure will be too large, which is not conducive to the miniaturization of the device. developing. Therefore, in this embodiment, the thickness of the wall 200 ranges from 5 microns to 50 microns.
  • the material of the first conductive block 410 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.
  • the first conductive block can be generated by an electroplating process, and the electroplating process can be electroless plating (ie, chemical plating).
  • the bonded cap and device substrate are placed in a solution containing metal ions (for example, electroless silver plating, nickel plating, copper plating, etc.) without energization.
  • the reducing agent reduces metal ions to metal and is deposited on the surfaces of the first electrical connection portion 120 and the second electrical connection portion 331a to form a dense metal plating layer. 5 ) is filled, thereby forming the first conductive block 410 .
  • the interconnection structure 331 may include a second electrical connection portion 331a and a third electrical connection portion 331c respectively located on two opposite surfaces of the cover, and the plug 331b that electrically connects the second electrical connection portion 331a and the third electrical connection portion 331c, of course, a redistribution layer may also be included therein.
  • layer, RDL) structure (not shown in the figure), and the MEMS device packaging structure also includes.
  • the second conductive block 420 is electrically connected to the third electrical connection portion 331c.
  • the material of the second conductive block 420 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten and magnesium, and the second conductive block 420 can realize the connection between the first chip 110 and other circuits.
  • the MEMS device packaging structure provided by the embodiment of the present invention further includes an encapsulation layer 500, and the encapsulation layer 500 covers at least the surface of the first conductive block.
  • the encapsulation layer 500 is used to protect and insulate the first conductive block 410 . Therefore, the material of the encapsulation layer 500 is an insulating material. In this embodiment, the material of the encapsulation layer 500 is epoxy resin. In other embodiments, the material of the encapsulation layer includes one or both of a dielectric material and a plastic encapsulation material, wherein the dielectric material may be silicon oxide, nitrogen Silicon or other dielectric materials.
  • the encapsulation layer 500 can also realize the protection and insulation of the second conductive block 420, and in order to satisfy the protection of the second conductive block 420 and facilitate the connection between the second conductive block 420 and other circuits at the same time
  • the encapsulation layer 500 may cover part of the second conductive block 420 .
  • the encapsulation layer 500 may completely cover the top surface of the second conductive block 420, or be flush with the top surface of the second conductive block 420, for this purpose, the encapsulation layer may be planarized until the second conductive block 420 is exposed. Conductive block 420 . In other embodiments, after the encapsulation layer 500 is formed, the encapsulation layer above the second conductive block may be etched to expose the second conductive block.
  • the MEMS device package structure provided by the embodiment of the present invention includes a cap and a MEMS device substrate that are bonded to each other with an interconnection structure, and the first electrical connection part of the device substrate and the second electrical connection part of the cap pass through the A conductive block is electrically connected, which can realize the interconnection between the MEMS device and the external signal, and the device substrate and the cover are connected through the fence, which provides a cavity working environment for the working area of the MEMS device and improves the performance of the device.

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Abstract

一种MEMS器件晶圆级封装方法及封装结构，方法包括：提供器件晶圆（100），器件晶圆中形成有第一芯片（110）、与第一芯片电连接的第一电连接部（120）；提供封盖（300），封盖中形成有互连结构（331），互连结构包括第二电连接部（331a）；在器件晶圆的第一表面或封盖的第一表面形成围墙（200），围墙围成的区域为空腔（210）；形成围墙后，键合封盖与器件晶圆，第一芯片与空腔相对应，第一电连接部和第二电连接部相对，且均至少部分位于围墙外，形成电连接空腔（400），电连接空腔具有开口（600）；形成第一导电块（410），以电连接第一电连接部和第二电连接部。该MEMS器件晶圆级封装方法及封装结构，可以提高所得产品的兼容性和成品率。

Description

MEMS器件晶圆级封装方法及封装结构 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种MEMS器件晶圆级封装方法及封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装(Ball Grid Array，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、晶圆级封装(Wafer Level Package ，WLP)、三维封装(3D) 和系统封装(System in Package，SiP)等，而采用不同形式的三维立体堆叠模式的系统集成封装已经得到越来越多的应用。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用三维立体堆叠模式的晶圆级系统封装（wafer level package system in package，WLPSIP），与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
在晶圆级系统封装工艺中，不仅需要将两片裸芯片键合在一起以实现物理连接，同时还需要连接其互连引线，从而实现电性连接。
 技术问题
本发明实施例提供一种MEMS器件晶圆级封装方法及封装结构，以在实现晶圆级封装的同时，提高所得产品的兼容性和成品率。
 技术解决方案
为解决上述问题，本发明实施例提供一种MEMS器件晶圆级封装方法，包括：提供器件晶圆，所述器件晶圆中形成有第一芯片、与所述第一芯片电连接的第一电连接部；提供封盖，所述封盖中形成有互连结构，所述互连结构包括第二电连接部；在所述器件晶圆的第一表面或所述封盖的第一表面形成围墙，所述围墙围成的区域为空腔；形成所述围墙后，键合所述封盖与所述器件晶圆，所述第一芯片与所述空腔相对应，所述第一电连接部和所述第二电连接部相对，且均至少部分位于所述围墙外，形成电连接空腔，电连接空腔具有开口；形成第一导电块，以电连接所述第一电连接部和所述第二电连接部。
相应地，为解决上述问题，本发明实施例还提供一种MEMS器件封装结构，包括：器件衬底，所述器件衬底中形成有第一芯片、与所述第一芯片电连接的第一电连接部；封盖，封盖中形成有互连结构，所述互连结构包括第二电连接部；围墙，位于所述器件衬底和所述封盖之间，所述第一芯片与所述围墙围成的空腔相对应，所述第一电连接部和所述第二电连接部相对，且均至少部分位于所述围墙外；第一导电块，电连接所述第一电连接部和所述第二电连接部。
 有益效果
与现有技术相比，本发明的技术方案具有以下优点：本发明实施例所提供的MEMS器件晶圆级封装方法，利用具有互连结构的封盖与MEMS器件晶圆进行键合，可以实现MEMS器件与外接信号互连，并且器件晶圆和封盖通过围墙连接，为电连接第一电连接部与封盖的第二电连接部的第一导电块提供了生成空间，为MEMS器件工作区提供空腔工作环境，提高器件的性能。
可选方案中，利用电镀工艺使器件晶圆的第一电连接部与封盖的第二电连接部电连接，将MEMS电性引出到封盖顶，避免了硅通孔TSV工艺，节省制程成本，降低了三维立体堆叠模式的晶圆级系统封装的难度，提高产品的成品率。
可选方案中，本发明实施例所提供的MEMS器件晶圆级封装方法，所提供的封盖包括位于衬底和介质层之间的释放层，一方面，衬底可以为互连结构的加工提供支撑，或者同时为封盖和器件晶圆的键合提供支撑；另一方面，释放层的存在，可以在完成互连结构的加工，或者完成封盖与器件晶圆的键合后，通过释放层的释放去除衬底，提高衬底去除的方便性，还可以实现衬底去除的准确控制，避免由于通过磨削的方式去除衬底时所造成的厚度控制准确度较低对器件所造成的损伤，提高产品的成品率。
 附图说明
图1至图8是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
图9至图10是本发明晶圆级封装方法另一实施例中部分步骤对应的结构示意图。
 本发明的实施方式
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺。其中，最典型的封装方式可以是：1）通过固化胶将上下裸芯片立体堆叠至基板上，并采用引线互连（wire bond）工艺将两个裸芯片的引线焊盘引线至基板上；2）通过固化胶将上下裸芯片立体堆叠至基板上，并采用wire bond工艺将上裸芯片的引线焊盘引线至下裸芯片的引线焊盘上，再将下裸芯片的引线焊盘引线至基板上；3）通过预制于上裸芯片表面的凸点焊（bump）或预制于下裸芯片表面的凸点焊实现倒装焊接，并采用wire bond将下裸芯片的引线焊盘引线至基板上；4）通过预制于上裸芯片表面的凸点焊或预制于下裸芯片表面的凸点焊实现倒装焊接，并采用预制于下裸芯片内的硅通孔互连（TSV）结构将下裸芯片的引线焊盘连至下裸芯片的背面。
其中，凸点倒装焊接工艺得到越来越多的应用，尤其是基于硅通孔互连工艺以及微凸点倒装焊的高密度系统集成封装。然而，由于预制于下裸芯片内的TSV结构会将下裸芯片的引线焊盘连至下裸芯片的背面，且随着集成电路的发展趋势，集成电路设计的复杂度不断提高，金属互连结构的布局相应越来越复杂，从而导致TSV工艺的难度增大，甚至出现因下裸芯片中的功能结构（例如，金属互连结构）的阻挡作用，无法形成TSV结构的问题。
为了解决所述技术问题，本发明实施例提供了一种MEMS器件晶圆级封装方法，利用具有互连结构的封盖与MEMS器件晶圆进行键合，可以实现MEMS器件与外接信号互连，并且器件晶圆和封盖通过围墙连接，为电连接第一电连接部与封盖的第二电连接部的第一导电块提供了生成空间，同时为MEMS器件工作区提供空腔工作环境，提高器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1至图8是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
参考图1，提供器件晶圆100，所述器件晶圆100中形成有第一芯片110、与所述第一芯片110电连接的第一电连接部120。
所述晶圆级封装方法用于实现晶圆级系统封装，器件晶圆100用于在后续工艺中与待集成芯片进行键合。当然，器件晶圆100为MEMS器件晶圆。所述器件晶圆100采用集成电路制作技术所制成。本实施例中，器件晶圆100包括衬底。作为一种示例，所述衬底为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
器件晶圆100中形成有第一芯片110和第一电连接部120，当然，为实现在后续工艺中与待集成芯片的电连接部进行电连接，第一电连接部120位于器件晶圆100的第一表面，即第一电连接部120的表面裸露，；另外，为在后续工艺中形成第一芯片110的空腔工作环境提供基础，第一电连接部120并未覆盖第一芯片110，暴露出第一芯片110。
其中，第一电连接部120的表面凸出于第一芯片110的表面，与第一芯片110的内部结构电连接。在其他实施例中，第一电连接部120的表面可以与第一芯片110的表面为同一表面，或者第一电连接部120的表面低于第一芯片110的表面。
本实施例中，器件晶圆100包括相对的晶圆正面和晶圆背面，第一电连接部120位于晶圆正面，即晶圆正面露出第一电连接部120。其中，晶圆背面指的是器件晶圆100中衬底的底部表面。
需要说明的是，第一电连接部120露出的位置可以利用介质层（未标示）进行保护以防止短路，且在MEMS器件晶圆级封装方法中，再通过对介质层进行刻蚀以暴露所述第一电连接部120。
还需要说明的是，为了便于图示，本实施例以器件晶圆100中形成有三个第一芯片110为例进行说明。但所述第一芯片110的数量不仅限于三个。另外，为了便于图示，与同一个第一芯片110电连接的第一电连接部120的数量为两个，以实现第一芯片110的信号的输入和输出，当然与同一个第一芯片110电连接的第一电连接部120的数量可以为多个。
可以理解的是，同一个器件晶圆100的各个第一芯片110可以为相同类型具有相同功能的芯片，也可以为具有不同功能的芯片，同一个器件晶圆100的各个第一芯片110具体可以包括：体声波滤波器、表面声波滤波器、固态装配谐振器、麦克风和指纹识别器件中的至少一种。
请参考图2，提供封盖300，所述封盖300中形成有互连结构331，所述互连结构331包括第二电连接部331a。
封盖300作为晶圆级封装的待集成结构的一部分，其中形成有互连结构331，在实现对器件晶圆100的封装的同时改变第一电连接部120在晶圆平面的位置。
封盖300采用集成电路制作技术所制成，第二电连接部331a位于封盖300的第一表面，即第二电连接部331a被裸露。
需要说明的是，第二电连接部331a露出的位置可以利用介质层（未标示）进行保护以防止短路，且在MEMS器件晶圆级封装方法中，再通过对介质层进行刻蚀以暴露所述第二电连接部331a，而第二电连接部331a的表面低于介质层的表面，即形成有凹槽。
封盖300可以包括衬底310，本实施例中，所述衬底310为硅衬底，在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓、镓化铟或玻璃等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。在其他实施例中，封盖也可以不包括衬底，仅包括形成有互连结构的介质层。
本实施例中，封盖300通过以下步骤获取：提供衬底310；在所述衬底310上形成释放层320，所述释放层320覆盖所述衬底310；在所述释放层320上形成介质层330，在所述介质层330中形成互连结构331。
在其他实施例中，形成封盖300的步骤还可以包括，在所述介质层330中形成所述互连结构331之后，释放所述释放层320，去除所述衬底310。即封盖300为仅包括形成有互连结构331的介质层。
衬底310为封盖300的互连结构331的制作提供支撑。对封盖300的衬底的描述，可结合参考前述的相关描述，在此不再赘述。释放层320为衬底310的去除提供方便，本实施例中，所述释放层320为锗释放层；在其他实施例中，所述释放层材料为碳和热解膜中的至少一种；当衬底为透光玻璃时，所述释放层材料还可以为光解膜。
介质层330提供了互连结构331的成型空间，如图2所示，首先在释放层320上沉积一层介质材料层，然后在介质材料层的对应位置进行刻蚀和填充，形成互连结构331。
本实施例中，介质层330的材料为高阻硅，互连结构331的材料为铜，铜的电阻率较低，通过选取铜材料，有利于提高互连结构331的导电性能；而且，互连结构331形成于互连结构孔中，铜的填充性较好，从而提高互连结构331在互连结构孔内的形成质量。在其他实施例中，介质层的材料还可以为其他具有较高电阻的材料，而互连结构的材料也可以为其他可适用的导电材料，比如：镍、锌、锡、金、钨、镁。
容易理解的是，为实现互连，互连结构还包括与第二电连接部电连接的第三电连接部，第三电连接部与第二电连接部分别位于封盖相对的两个表面。本实施例中，如图2所示，封盖300包括衬底310和释放层320，第三电连接部与第二电连接部分别位于封盖相对的两个表面是指互连结构331可以包括位于介质层330的第一表面的第二电连接部331a，位于介质层330的第二表面的第三电连接部331c，当然，其中还可以包括电连接第二电连接部331a和第三电连接部331c的插塞331b，包括再布线层（redistribution layer，RDL）结构（图中未示出），介质层330的第一表面与介质层330的第二表面相对。在其他实施例中，封盖仅包括形成有互连结构的介质层，那么第三电连接部与第二电连接部分别位于介质层的两个相对的表面，即分别位于封盖相对的两个表面。
为减小MEMS器件晶圆级封装后的封装结构的厚度，在完成互连结构311的加工或者MEMS器件晶圆级封装后，可以进行减薄处理。而在衬底310上先形成释放层320，再在释放层320上形成介质层330，一方面，衬底310可以为互连结构331的加工提供支撑，或者同时为封盖300和器件晶圆100的键合提供支撑；另一方面，释放层320的存在，可以在完成互连结构331的加工，或者完成封盖300与器件晶圆100的键合后，通过释放层320的释放去除衬底310，提高衬底310去除的方便性，还可以实现衬底310去除的准确控制，避免由于通过磨削的方式去除衬底310时所造成的厚度控制准确度较低对器件所造成的损伤，提高产品的成品率。
在其他实施例中，也可以直接在衬底上形成介质层，进而形成互连结构。
封盖300可以为晶圆级封盖，即封盖300具有晶圆大小，则封盖300的互连结构331的数量与器件晶圆100的第一电连接部110的数量相同。
本实施例中，以器件晶圆100的所述第一芯片110的数量为三个，与每个第一芯片110电连接的第一电连接部120的数量为两个为例进行说明，封盖300的互连结构331的数量相应为六个。但互连结构331的数量不仅限于六个。
当封盖300为晶圆级封盖时，通过一次键合既可以实现晶圆级的封装，可以简化处理工艺，提高封装速度。
在其他实施例中，封盖300可以为芯片级封盖，则本文所述的提供封盖包括提供多个芯片级封盖，芯片级封盖的数量可以与器件晶圆100的第一芯片110的数量相同，也可以与器件晶圆100的第一芯片110的数量不同，当然，每个芯片级封盖的第二电连接部331a的数量与每个第一芯片110的第一电连接部120的数量相同。
当器件晶圆100的各个第一芯片110的结构相同时，各个芯片级封盖的结构可以相同，也可以在保证后续键合以及封装要求的基础上有所不同；当器件晶圆100的各个第一芯片110的结构相同时，可以选择具有不同结构的芯片级封盖，以实现不同第一芯片110的转接互连。
可以通过对晶圆级封盖进行切割的方式，获得多个分立的芯片级封盖。
请参考图3，在所述器件晶圆100的第一表面形成围墙200，所述围墙200围成的区域为空腔210。
通过在器件晶圆100的第一表面形成围墙200，在器件晶圆100和封盖300之间形成支撑，为第一电连接部120和第二电连接部331a的电连接提供空间。
围墙200所围成的区域为空腔210，与器件晶圆100的第一芯片110的位置相对应，为第一芯片提供活动空间，提高第一芯片的性能。
本实施例中，围墙200可以形成于第一电连接结构120的部分表面以及第一芯片110的边缘。当然也可以只形成于第一电连接结构120部分表面上，第一电连接结构120的部分表面，从而能够在同一步骤中，在多个第一电连接结构120上形成围墙200，从而提高封装效率，同时避免占用第一芯片110对应的区域，形成不密闭的空腔210。
本实施例中，围墙200的材料可以为干膜（Dry Film）。干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，经曝光显影处理，即可在干膜光内形成图形。
在另一种实施例中，围墙200的材料可以为金属，首先在器件晶圆100的第一表面沉积金属层，然后刻蚀金属层，以剩余的金属层为围墙，或者在器件晶圆100的第一表面沉积介质层，刻蚀第一电连接结构120靠近第一芯片100的部分表面以及第一芯片110的边缘的介质层，形成填充孔，在填充孔内填充金属，并去除剩余的介质层，得到围墙；在其他实施例中，围墙的材料还可以为光敏材料，从而能够通过光刻工艺实现图形化，从而能够降低对电极或外接互连线的损伤。
需要说明的是，围墙200的厚度不宜过小，也不宜过大。如果厚度过小，则容易导致围墙200的高度不足，从而不能提供足够的第一电连接部120和第二电连接部331a的电连接材料的填充空间，增加后续导电材料填充于其中的难度，也不能提供最够的空腔210的空间，不能满足第一芯片110对于可动空间的要求；如果厚度过大，则相应会导致后续所形成封装结构的厚度过大，不利于器件小型化的发展。为此，本实施例中，围墙200的厚度范围为5微米-50微米。
请参考图4，形成所述围墙200后，键合所述封盖300与所述器件晶圆100，所述第一芯片110与所述空腔210相对应，所述第一电连接部120和所述第二电连接部331a相对，且均至少部分位于所述围墙200外，形成电连接空腔400。
形成围墙200后，通过将封盖300键合于围墙200上，实现封盖300与器件晶圆100的系统集成。而且，将封盖300的第一表面键合于围墙200，以便于第二电连接部331a朝向第一电连接部120，实现第一电连接部120与第二电连接部331a的电连接。
本实施例中，将封盖300键合于围墙200后，第一电连接部120和第二电连接部331a之间形成电连接空腔400，电连接空腔400用于填充电连接材料，第一电连接部120与第二电连接部331a的电连接。
在本实施例中，围墙200的材料为干膜，将封盖300粘于围墙200即可实现封盖300和器件晶圆100的键合。在其他实施例中，围墙200的材料为金属，则利用金属与金属的键合实现封盖300和器件晶圆100的键合。
在本实施例中，封盖300为晶圆级封盖，将封盖300与器件晶圆100键合后，除了位于边缘位置的电连接空腔400，为方便后续进行电连接材料的填充还可以对封盖300进行切割。
具体地，请参考图5，沿切割道切割所述封盖300，形成用于填充电连接材料的开口600。
开口600与电连接空腔400连通，以便填充电连接材料经过开口600进入电连接空腔400，实现第一电连接部120与第二电连接部331a的电连接。
本实施例中，可以采用激光切割工艺，沿切割道切割封盖300，形成开口600；其他实施例中，还可以采用刀切割工艺，沿切割道切割封盖300，形成开口600。
其他实施例中，封盖为芯片级封盖，将封盖与器件晶圆键合时，将各个芯片级封盖分别与各个第一芯片键合，将芯片级封盖与第一芯片键合后，第一电连接部和第二电连接部之间的电连接空腔为不密封空腔，直接形成有开口，从而可以填充电连接材料进入电连接空腔。
请参考图6和图7，形成第一导电块410，以电连接所述第一电连接部120和所述第二电连接部331a。
通过第一导电块410电连接所述第一电连接部120和所述第二电连接部331a，从而实现封盖300和器件晶圆100的互连封装，并将器件晶圆100的电性引出，进而为后续的封装制程做准备。例如，后续能够通过第二导电块420（示于图7中），实现第一芯片110与其他基板（例如，电路板）的电连接。
具体地，可以利用电镀工艺，使电连接材料从开口600的边界填充至电连接空腔400中，形成第一导电块410，电连接空腔400中的第一导电块410与第一电连接部120和所述第二电连接部331a均相接触，因此可以实现第一电连接部120和所述第二电连接部331a的电连接。通过电镀工艺，可在电连接空腔400中实现良好的填充效果，进而提高电连接的可靠性。
本实施例中，电镀工艺为无极电镀（即化学镀）。具体地，键合后的封盖300和器件晶圆100放置到含有金属离子的溶液（例如，化学镀银、镀镍、镀铜等溶液）中，不需要通电，根据氧化还原反应原理，利用强还原剂使金属离子还原成金属而沉积在第一电连接部120和所述第二电连接部331a的表面，形成致密金属镀层，经过一段反应时间之后，金属镀层将电连接空腔400填满，从而形成第一导电块410。因此，第一导电块410的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。
在其他实施例中，也可以利用凸块（bumping）工艺在第一电连接部或第二电连接部上形成焊料凸点，作为第一电连接块。
如图6所示，在本实施例中，键合所述封盖300与所述器件晶圆100，并切割形成开口600后，释放所述释放层320，去除所述衬底310。
在完成封盖300与所述器件晶圆100的键合后再释放所述释放层320，可以降低对于封盖300的介质层330的厚度要求，降低键合难度。
首先形成开口600再释放所述释放层320，可以扩大释放层320的刻蚀面积或者受热面积，提高释放层320去除的速度，提高加工效率。
如前所述，本实施例中，衬底310为硅衬底，所述释放层320为锗释放层；可以通过湿法刻蚀工艺，刻蚀释放层320，实现释放层320和衬底310的去除。在其他实施例中，当释放层的材料为热解膜时，可以通过加热的方式实现释放层和衬底的去除，当释放层的材料为光解膜时，且衬底为透光的玻璃时，可以通过光照的方式实现释放层和衬底的去除。
当然，在另一种具体实施方式中，还可以首先进行释放层和衬底的去除，再切割形成开口600。
如图7所示，由于互连结构331可以包括位于介质层330的第一表面（即封盖300的第一表面）的第二电连接部331a，位于介质层330的第二表面的第三电连接部331c，以及电连接第二电连接部331a和第三电连接部331c的插塞331b，去除释放层320和衬底310后，第三电连接部331c裸露于介质层330的第二表面，从而电镀形成第一导电块410的同时，还在第三电连接部331c的表面形成第二导电块420，以便实现后续与其他基板（例如，电路板）的电连接。
这样，通过一次电镀，就可以实现第一导电块410和第二导电块420的生成，可以简化工艺流程，提高工艺效率。
在其他实施例中，还可以通过在第三电连接部上植球形成第二导电块，并且第二导电块和第一导电块可以分别生成。
从而，本发明实施例所提供的MEMS器件晶圆级封装方法，利用具有互连结构330的封盖300与晶圆器件100进行键合，并利用电镀工艺使器件晶圆100的第一电连接部120与封盖300的第二电连接部331a电连接，可以实现器件晶圆100的各个第一芯片110的第一电连接部120的连接点在器件晶圆100平面方向的重新布线，提高器件晶圆100的第一芯片110与其他芯片的连接的灵活性和兼容性；并且器件晶圆100和封盖300通过围墙200连接，为第一电连接部120与封盖300的第二电连接部331a电连接提供了第一导电块410的生成空间，通过电镀工艺实现立体堆叠的部件之间的电连接，省略了硅通孔互连技术的使用，降低了三维立体堆叠模式的晶圆级系统封装的难度，可以提高产品的成品率，并且器件晶圆100和封盖300通过围墙200连接，还可以在与第一芯片110相对应的位置形成空腔210，为第一芯片110提供可动空间，提高器件的性能。
在另一种具体实施方式中，请参考图8，在电镀形成第一导电块410的步骤之后还包括：利用注塑剂填充开口600，形成封装层500。
封装层500用于实现对第一导电块410的保护和绝缘。因此，封装层500的材料为绝缘材料。本实施例中，封装层500的材料为环氧树脂，其他实施例中，封装层的材料包括介电材料和塑封材料中的一种或两种，其中，介电材料可以为氧化硅、氮化硅或者其他介电材料。
当形成第二导电块420时，封装层500还可以实现对于第二导电块420的保护和绝缘，而为了同时满足对第二导电块420的保护和以及方便第二导电块420与其他电路的连接，如图8所示，封装层500可以覆盖部分第二导电块420。
在其他实施例中，封装层500还可以完全覆盖第二导电块420的顶面，或者与第二导电块420的顶面齐平，为此可以对封装层进行平坦化处理，直至露出第二导电块420。在其他实施例中，也可以在形成封装层后，刻蚀第二导电块上方的封装层，从而露出第二导电块。
进一步地，所述填充形成所述第一导电块410的开口600之后还包括：将键合有所述互连结构331的器件晶圆100进行切割，分离所述器件晶圆100的各个所述第一芯片110。
将键合有所述互连结构331的器件晶圆100进行切割，得到具有互连结构331的各个第一芯片110。
对器件晶圆100进行切割的切割工艺既可以为刀切割工艺，也可以为激光切割工艺。
图9至图10是本发明晶圆级封装方法另一实施例中各步骤对应的结构示意图。
本发明实施例与前述实施例的相同之处在此不再赘述，本发明实施例与前述实施例的不同之处在于：在所述封盖300的第一表面形成围墙200，所述围墙200围成的区域为空腔210。
请参考图9，在所述封盖300的第一表面形成围墙200，所述围墙200围成的区域为空腔210。
关于围墙200的具体描述请参考前述内容，在此不再赘述。需要说明的是，围墙200所围成的空腔210，在后续与器件晶圆100键合时，需要使空腔与第一芯片110相对应，并且围墙200的不会完全覆盖第二电连接部331a，以保证后续与第一电连接部120的电连接。
当然，当封盖300为封盖芯片时，围墙200在各个封盖芯片上形成，再将各个形成有围墙200的封盖芯片与器件晶圆100进行键合。
请参考图10，形成所述围墙200后，键合所述封盖300与所述器件晶圆100，所述第一芯片110与所述空腔210相对应，所述第一电连接部120和所述第二电连接部331a相对，且均至少部分位于所述围墙200外。
将形成有围墙200的封盖300与器件晶圆100进行键合，使第一芯片110与所述空腔210相对应，所述第一电连接部120和所述第二电连接部331a相对，且均至少部分位于所述围墙200外。
此步骤的具体内容请参考图4的描述，在此不再赘述。
后续制程与前述实施例相同，在此不再赘述。对本实施例所述封装方法的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
相应的，本发明还提供一种MEMS器件封装结构，包括：器件衬底，所述器件衬底中形成有第一芯片、与所述第一芯片电连接的第一电连接部；封盖，封盖中形成有互连结构，所述互连结构包括第二电连接部；围墙，位于所述器件衬底和所述封盖之间，所述第一芯片与所述围墙围成的空腔相对应，所述第一电连接部和所述第二电连接部相对，且均至少部分位于所述围墙外；第一导电块，电连接所述第一电连接部和所述第二电连接部。
图8是本发明MEMS器件封装结构一实施例的结构示意图。
本发明实施例所提供的MEMS器件封装结构，以器件晶圆100为器件衬底，以形成互连结构331的介质层330为封盖，包括：器件晶圆100，所述器件晶圆100中形成有第一芯片110、与所述第一芯片110电连接的第一电连接部120；封盖，封盖中形成有互连结构331，所述互连结构331包括第二电连接部331a；围墙200，位于所述器件晶圆100和所述封盖之间，所述第一芯片110与所述围墙200围成的空腔相对应，所述第一电连接部120和所述第二电连接部331a相对，且均至少部分位于所述围墙200外；第一导电块410，电连接所述第一电连接部120和所述第二电连接部331a。
具体地，器件晶圆100为MEMS器件晶圆。所述器件晶圆100采用集成电路制作技术所制成。
本实施例中，器件晶圆100包括衬底。作为一种示例，所述衬底为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
第一电连接部120露出的位置可以利用介质层（未标示）进行保护以防止短路，且在MEMS器件晶圆级封装方法中，再通过对介质层进行刻蚀以暴露所述第一电连接部120。
还需要说明的是，为了便于图示，本实施例以器件晶圆100中形成有三个第一芯片110为例进行说明。但所述第一芯片110的数量不仅限于三个。另外，为了便于图示，与同一个第一芯片110电连接的第一电连接部120的数量为两个，以实现第一芯片110的信号的输入和输出，当然与同一个第一芯片110电连接的第一电连接部120的数量可以为多个。
同一个器件晶圆100的各个第一芯片110可以为相同类型具有相同功能的芯片，也可以为具有不同功能的芯片，同一个器件晶圆100的各个第一芯片110具体可以包括：体声波滤波器、表面声波滤波器、固态装配谐振器、麦克风和指纹识别器件中的至少一种。
封盖可以为晶圆级封盖，即封盖具有晶圆大小，则封盖的互连结构331的数量与器件晶圆100的第一电连接部110的数量相同。
本实施例中，以器件晶圆100的所述第一芯片110的数量为三个，与每个第一芯片110电连接的第一电连接部120的数量为两个为例进行说明，封盖的互连结构331的数量相应为六个。但互连结构331的数量不仅限于六个。
当封盖为晶圆级封盖时，封装过程可以通过一次键合实现晶圆级的封装，可以简化处理工艺，提高封装速度。
在其他实施例中，当器件衬底为器件晶圆时，封盖还可以为芯片级封盖，从而可以选择具有不同结构的芯片级封盖，实现不同的互连要求。
在另一种具体实施方式中，器件衬底还可以为MEMS器件芯片，MEMS器件封装结构为MEMS器件芯片级封装结构，与其对应的，封盖也为芯片级封盖，其他结构与器件晶圆形似，在此不再赘述。
封盖作为封装结构的一部分，其中形成有互连结构331，在实现对器件晶圆100的封装的同时改变第一电连接部120在晶圆平面的位置。
封盖采用集成电路制作技术所制成，第二电连接部331a露出的位置可以利用介质层（未标示）进行保护以防止短路，且在MEMS器件晶圆级封装方法中，再通过对介质层进行刻蚀以暴露所述第二电连接部331a，而第二电连接部331a的表面低于介质层的表面，即形成有凹槽。
互连结构331的材料为铜，铜的电阻率较低，通过选取铜材料，有利于提高互连结构331的导电性能；而且，互连结构331形成于互连结构孔中，铜的填充性较好，从而提高互连结构331在互连结构孔内的形成质量。在其他实施例中，互连结构的材料也可以为其他可适用的导电材料，比如：镍、锌、锡、金、钨、镁。
本实施例中，围墙200的材料可以为干膜（Dry Film）。干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，经曝光显影处理，即可在干膜光内形成图形。
在另一种实施例中，围墙200的材料可以为金属，封装过程中，首先在器件晶圆100的第一表面沉积金属层，然后刻蚀金属层，以剩余的金属层为围墙，或者在器件晶圆100的第一表面沉积介质层，刻蚀第一电连接结构120靠近第一芯片100的部分表面以及第一芯片110的边缘的介质层，形成填充孔，在填充孔内填充金属，并去除剩余的介质层，得到围墙；在其他实施例中，围墙的材料还可以为光敏材料，从而能够通过光刻工艺实现图形化，从而能够降低对电极或外接互连线的损伤。
需要说明的是，围墙200的厚度不宜过小，也不宜过大。如果厚度过小，则容易导致围墙200的高度不足，从而不能提供足够的第一电连接部120和第二电连接部331a的电连接材料的填充空间，增加后续导电材料填充于其中的难度，也不能提供最够的空腔210的空间，不能满足第一芯片110对于可动空间的要求；如果厚度过大，则相应会导致后续所形成封装结构的厚度过大，不利于器件小型化的发展。为此，本实施例中，围墙200的厚度范围为5微米-50微米。
第一导电块410的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种，第一导电块可以通过电镀工艺生成，电镀工艺可以为无极电镀（即化学镀）。具体地，将键合后的封盖和器件衬底放置到含有金属离子的溶液（例如，化学镀银、镀镍、镀铜等溶液）中，不需要通电，根据氧化还原反应原理，利用强还原剂使金属离子还原成金属而沉积在第一电连接部120和所述第二电连接部331a的表面，形成致密金属镀层，经过一段反应时间之后，金属镀层将电连接空腔400（示于图5中）填满，从而形成第一导电块410。
在另一种具体实施方式中，本发明实施例所提供的MEMS器件封装结构，互连结构331可以包括分别位于封盖相对的两表面的第二电连接部331a和第三电连接部331c，以及电连接第二电连接部331a和第三电连接部331c的插塞331b，当然，其中还可以包括再布线层（redistribution layer，RDL）结构（图中未示出），MEMS器件封装结构还包括。
第二导电块420，所述第二导电块420电连接所述第三电连接部331c。第二导电块420的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种，所述第二导电块420可以实现第一芯片110与其他电路的连接。
在另一种具体实施方式中，本发明实施例所提供的MEMS器件封装结构，还包括封装层500，所述封装层500至少覆盖所述第一导电块的表面。
封装层500用于实现对第一导电块410的保护和绝缘。因此，封装层500的材料为绝缘材料。本实施例中，封装层500的材料为环氧树脂，其他实施例中，封装层的材料包括介电材料和塑封材料中的一种或两种，其中，介电材料可以为氧化硅、氮化硅或者其他介电材料。
当具有第二导电块420时，封装层500还可以实现对于第二导电块420的保护和绝缘，而为了同时满足对第二导电块420的保护和以及方便第二导电块420与其他电路的连接，封装层500可以覆盖部分第二导电块420。
在其他实施例中，封装层500还可以完全覆盖第二导电块420的顶面，或者与第二导电块420的顶面齐平，为此可以对封装层进行平坦化处理，直至露出第二导电块420。在其他实施例中，也可以在形成封装层500后，刻蚀第二导电块上方的封装层，从而露出第二导电块。
本发明实施例所提供的MEMS器件封装结构，包括相互键合的具有互连结构的封盖与MEMS器件衬底，器件衬底的第一电连接部与封盖的第二电连接部通过第一导电块电连接，可以实现MEMS器件与外接信号互连，并且器件衬底和封盖通过围墙连接，为MEMS器件工作区提供空腔工作环境，提高器件的性能。
对所公开的实施例的上述说明，使本领域技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其他实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是符合与本文所公开的原理和新颖特点相一致的最宽的范围。
虽然本发明实施例披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种变动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种MEMS器件晶圆级封装方法，其特征在于，包括：
    提供器件晶圆，所述器件晶圆中形成有第一芯片、与所述第一芯片电连接的第一电连接部；
    提供封盖，所述封盖中形成有互连结构，所述互连结构包括第二电连接部；
    在所述器件晶圆的第一表面或所述封盖的第一表面形成围墙，所述围墙围成的区域为空腔；
    形成所述围墙后，键合所述封盖与所述器件晶圆，所述第一芯片与所述空腔相对应，所述第一电连接部和所述第二电连接部相对，且均至少部分位于所述围墙外，形成电连接空腔，电连接空腔具有开口；
    形成第一导电块，以电连接所述第一电连接部和所述第二电连接部。
  2. 如权利要求1所述的MEMS器件晶圆级封装方法，其特征在于，所述封盖的形成步骤包括：
    提供衬底；
    在所述衬底上形成释放层，所述释放层覆盖所述衬底；
    在所述释放层上形成介质层，在所述介质层中形成互连结构；
    在所述介质层中形成所述互连结构的步骤之后，还包括：
    释放所述释放层，去除所述衬底。
  3. 如权利要求2所述的MEMS器件晶圆级封装方法，其特征在于，所述释放层的材料包括锗、碳、热解膜和光解膜中的至少一种。
  4. 如权利要求1所述的晶圆级封装方法，其特征在于，所述封盖包括芯片级封盖；
    所述键合所述封盖与所述器件晶圆的步骤包括：
    键合各个所述芯片级封盖和所述第一芯片。
  5. 如权利要求1所述的MEMS器件晶圆级封装方法，其特征在于，所述封盖包括晶圆级封盖；
    所述键合所述封盖与所述器件晶圆之后还包括：
    沿切割道切割所述封盖。
  6. 如权利要求1所述的MEMS器件晶圆级封装方法，其特征在于，所述互连结构还包括与所述第二电连接部电连接的第三电连接部，所述第三电连接部与所述第二电连接部分别位于所述封盖相对的两个表面；
    所述MEMS器件晶圆级封装方法还包括：
    形成所述第一导电块的同时形成与所述第三电连接部电连接的第二导电块，或者在所述第三电连接部上植球形成第二导电块。
  7. 如权利要求1所述的MEMS器件晶圆级封装方法，其特征在于，所述围墙的材料包括干膜或金属。
  8. 如权利要求1-7任一项所述的MEMS器件晶圆级封装方法，其特征在于，所述形成第一导电块的步骤之后还包括：
    填充各所述开口，形成封装层。
  9. 如权利要求8所述的MEMS器件晶圆级封装方法，其特征在于，所述填充形成所述第一导电块的开口之后还包括：
    将键合有所述互连结构的器件晶圆进行切割，分离所述器件晶圆的各个所述第一芯片。
  10. 如权利要求1-7任一项所述的MEMS器件晶圆级封装方法，其特征在于，形成所述第一导电块的工艺为电镀工艺。
  11. 如权利要求1-7任一项所述的MEMS器件晶圆级封装方法，其特征在于，所述第一导电块的材料为铜、镍、锌、锡、金、钨和镁中的一种或多种。
  12. 如权利要求1-7任一项所述的MEMS器件晶圆级封装方法，其特征在于，所述MEMS器件包括体声波滤波器、表面声波滤波器、固态装配谐振器、麦克风和指纹识别器件中的至少一种。
  13. 如权利要求1-7任一项所述的MEMS器件晶圆级封装方法，其特征在于，所述围墙的厚度范围为5微米-50微米。
  14. 一种MEMS器件封装结构，其特征在于，包括：
    器件衬底，所述器件衬底中形成有第一芯片、与所述第一芯片电连接的第一电连接部；
    封盖，封盖中形成有互连结构，所述互连结构包括第二电连接部；
    围墙，位于所述器件衬底和所述封盖之间，所述第一芯片与所述围墙围成的空腔相对应，所述第一电连接部和所述第二电连接部相对，且均至少部分位于所述围墙外；
    第一导电块，电连接所述第一电连接部和所述第二电连接部。
  15. 如权利要求14所述的MEMS器件封装结构，其特征在于，所述互连结构还包括与所述第二电连接部电连接的第三电连接部，所述第三电连接部与所述第二电连接部分别位于所述封盖相对的两个表面；
    MEMS器件封装结构还包括： 第二导电块，所述第二导电块电连接所述第三电连接部。
  16. 如权利要求14或15所述的MEMS器件封装结构，其特征在于，所述封盖包括晶圆级封盖或芯片级封盖。
  17. 如权利要求14或15所述的MEMS器件封装结构，其特征在于，所述围墙的厚度范围为5微米-50微米。
  18. 如权利要求14或15所述的MEMS器件封装结构，其特征在于，第一导电块的材料为铜、镍、锌、锡、金、钨和镁中的一种或多种。
  19. 如权利要求14或15所述的MEMS器件封装结构，其特征在于，还包括封装层，所述封装层至少覆盖所述第一导电块的表面。
  20. 如权利要求14或15所述的MEMS器件封装结构，其特征在于，所述MEMS器件包括体声波滤波器、表面声波滤波器、固态装配谐振器、麦克风、指纹识别器件。
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