TWI727469B - 封裝體及其形成方法 - Google Patents

封裝體及其形成方法 Download PDF

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TWI727469B
TWI727469B TW108137880A TW108137880A TWI727469B TW I727469 B TWI727469 B TW I727469B TW 108137880 A TW108137880 A TW 108137880A TW 108137880 A TW108137880 A TW 108137880A TW I727469 B TWI727469 B TW I727469B
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package
core frame
core
component
dielectric
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TW108137880A
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TW202107641A (zh
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吳俊毅
余振華
劉重希
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台灣積體電路製造股份有限公司
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Abstract

一種形成封裝體的方法，包含將封裝組件置放在載體上 方。封裝組件包含裝置晶粒。核心框架置放於載體上方。核心框架形成環繞封裝組件的環。方法更包含將核心框架及封裝組件包封在包封體中，在核心框架及封裝組件上方形成多個重佈線，以及經由所述多個重佈線在所述第一封裝組件上方形成多個電連接器，所述多個電連接器經由所述多個重佈線電耦合至所述第一封裝組件。

Description

封裝體及其形成方法
本發明實施例是有關於一種封裝體及其形成方法。
高效能計算(High-Performance Computing；HPC)封裝體正越來越多地用於要求效能的應用，諸如人工智能(Artificial Intelligence；AI)應用。HPC封裝體的尺寸亦日益變大。較大尺寸造成封裝體具有明顯翹曲。
一種HPC封裝體可包含接合至封裝基底的封裝體。為控制翹曲，封裝基底的厚度增加以提高抗翹曲性。然而，此解決方案導致HPC封裝體中的電路徑更長，並導致IR降(IR drop)增大，此可嚴重降低HPC封裝體的效能。
根據本發明的實施例，一種形成封裝體的方法，包括：將第一封裝組件置放在載體上方，其中所述第一封裝組件包括裝置晶粒；將核心框架置放在所述載體上方，其中所述核心框架形 成環繞所述第一封裝組件的環；將所述核心框架及所述第一封裝組件包封在包封體中；在所述核心框架及所述第一封裝組件上方形成多個重佈線；以及經由所述多個重佈線在所述第一封裝組件上方形成多個電連接器，所述多個電連接器經由所述多個重佈線電耦合至所述第一封裝組件。
根據本發明的實施例，一種形成封裝體的方法，包括：將核心框架置放在載體上方，其中所述核心框架包括核心介電質以及位於所述核心介電質的相對側上的第一金屬板及第二金屬板；將封裝組件置放在所述核心框架中的開口中及所述載體上方，其中所述封裝組件包括裝置晶粒；將所述核心框架及所述封裝組件包封在包封體中；以及在所述核心框架及所述封裝組件上方形成多個重佈線，其中所述多個重佈線電連接至所述封裝組件，且電解耦於所述核心框架。
根據本發明的實施例，一種封裝體，包括封裝組件、核心框架、包封體、多個介電質層以及多個重佈線。封裝組件包括裝置晶粒於其中。核心框架形成環繞所述封裝組件的環。包封體包封所述封裝組件及所述核心框架於其中。多個介電質層位於所述包封體上方。多個重佈線位於多個介電質層中，其中所述多個重佈線電連接至所述封裝組件，且電解耦於所述核心框架。
20、64:載體
22、66:釋放膜
23、68:晶粒貼合膜
24、58:封裝組件
26:核心框架
28:開口
30:金屬板
32、72:核心介電質
34、82、122:包封體
36:前側重佈結構
38、71、78、118:介電質層
40、74、76、116:重佈線
42:金屬墊
44:獨立被動裝置
46:電容器
48、84:電連接器
50、86:重構晶圓
60、60'、61:封裝體
62:金屬環
63:黏著膜
70:帶芯基底
73:電鍍穿孔
88:切割道
100:系統晶片晶粒
102、112:金屬凸塊
104、114:表面介電質層
108:高頻寬記憶體堆疊
110:記憶體晶粒
120:互連結構
124:導電特徵
200:製程流程
202、204、206、208、210、212、214、216、218、220:製程
S1、S2:間距
T1、T2:厚度
當結合隨附圖式閱讀以下具體實施方式時會最佳地理解 本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見，任意地增加或減小各種特徵的尺寸。
圖1、圖2A、圖2B、圖3A、圖3B以及圖4至圖10說明根據一些實施例在封裝體形成中的中間階段的橫截面視圖及透視圖。
圖11A與圖11B說明根據一些實施例的分別置放於圓形載體與長方形載體上的封裝體及核心框架的頂視圖。
圖12至圖15說明根據一些實施例的在封裝體形成中的中間階段的橫截面圖。
圖16說明根據一些實施例的用於形成封裝體的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露內容。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包括第一特徵及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成使得第一特徵及第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複圖式元件符號及/或字母。此重複為出於簡單及清楚之目的，且自身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，可在本文中使用空間相對術語，諸如「在...之下」、「在...下方」、「下部」、「上覆」、「上部」以及類似術語，以描述如諸圖中所說明的一個元件或特徵與另一(一些)元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例提供一種封裝體以及其形成方法。根據一些實施例說明封裝體形成中的中間階段。論述一些實施例的一些變型。本文中論述的實施例將提供使得能夠製備或使用本揭露內容的主題的實例，且本領域的技術人員將易於理解在屬於不同實施例的所設想範疇內的情況下可進行的修改。貫穿各視圖及說明性實施例，相同的參考標號用以指代相同元件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
根據本揭露內容的一些實施例，封裝組件安置於由核心框架環繞的開口中。核心框架及封裝組件包封在包封體(諸如模製化合物)中。重佈線(Redistribution line；RDL)自包封體開始形成，以電連接至封裝組件。核心框架提供機械支撐物且減少翹曲，而核心框架並不包含用於電佈線功能的穿透核心框架的電鍍穿孔(Plating Through-Hole；PTH)(PTH為導電管道)。因此，當提供機械支撐物時，核心框架的厚度並不造成所得封裝體中的 電訊號及功率的IR降的升高。
圖1、圖2A、圖2B、圖3A、圖3B以及圖4至圖10說明根據本揭露內容的一些實施例的在封裝體形成中的中間階段的橫截面圖。對應製程亦示意性地反映於圖16中所示的製程流程200中。
圖1說明載體20與形成於載體20上方的釋放膜22。載體20可為玻璃載體、陶瓷載體或類似者。根據本揭露內容的一些實施例，如圖11A所示，載體20具有圓形俯視圖形狀。載體20可具有典型矽晶圓的大小，其可具有8吋直徑、12吋直徑或大於12吋直徑。根據本揭露內容的替代性實施例，如圖11B所示，載體20具有長方形俯視圖形狀。
返回參考圖1，釋放膜22形成於載體20上。釋放膜22可由聚合物類材料(諸如，光熱轉換(Light-To-Heat-Conversion；LTHC)材料)形成，其可連同載體20一起自將在後續製程中形成的上覆結構移除。根據本揭露內容的一些實施例，釋放膜22由環氧類熱釋放材料形成。根據本揭露內容的一些實施例，晶粒貼合膜(Die-Attach Film；DAF)23形成於釋放膜22上方。DAF 23為黏著膜，且可經塗佈或疊層。根據替代實施例，單獨的DAF形成於貼合至釋放膜22上方的組件下方，而非形成晶圓大小的DAF。
圖2A及圖2B說明封裝組件24例如經由DAF 23置放在釋放膜22上方。將各別製程說明為圖16中所展示的製程流程200 中的製程202。封裝組件24可為經由封裝製程形成的封裝體，其可包含邏輯晶粒(諸如計算晶粒)、記憶體晶粒(諸如動態隨機存取記憶體(Dynamic Random Access Memory；DRAM))晶粒或靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒、光子晶粒、封裝體(包含已封裝的裝置晶粒)、輸入輸出(Input-output；IO)晶粒、數位晶粒、類比晶粒、表面安裝被動裝置或類似者。在封裝組件24中的晶粒可包封於一或多個包封體(諸如模製化合物、底填充物或類似者)中。封裝組件24亦可為裝置晶粒。根據本揭露內容的一些實施例，封裝組件24為高效能計算(HPC)封裝體，其可用於要求性能的應用，例如人工智能(AI)應用。圖2A說明封裝組件24的實例，且封裝組件24可具有其他結構。
根據本揭露內容的一些實施例，封裝組件24包含系統晶片(System-on-Chip；SoC)晶粒100，其為包含多個裝置晶粒的封裝體，所述多個裝置晶粒接合在一起以形成系統。SoC晶粒100中的裝置晶粒並不詳細展示。SoC晶粒100可包含表面處的金屬凸塊102，且金屬凸塊102可嵌入於表面介電質層104中。根據本揭露內容的一些實施例，表面介電質層104由諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或類似者的聚合物形成。金屬凸塊102可由銅、鎳、鈀、金、其複合層及/或其合金形成。
封裝組件24亦可包含多個高頻寬記憶體 (High-Bandwidth Memory；HBM)堆疊108，其中多個HBM堆疊108中的每一者包含堆疊在一起以形成記憶體堆疊的多個記憶體晶粒110。記憶體晶粒110可為DRAM晶粒、SRAM晶粒或其他類型的記憶體晶粒。SoC晶粒100中的裝置晶粒並不詳細展示。HBM堆疊108可包含表面處的金屬凸塊112，且金屬凸塊112可嵌入於HBM堆疊108的表面介電質層114或包封體122中。根據本揭露內容的一些實施例，表面介電質層114由聚合物(諸如PBO、聚醯亞胺、BCB或類似者)形成。金屬凸塊112亦可由銅、鎳、鈀、金、其複合層及/或其合金形成。
根據本揭露內容的一些實施例，封裝組件24的形成包含將多個SoC晶粒100及多個HBM堆疊108置放至另一載體(未圖示)上，將多個SoC晶粒100及多個HBM堆疊108包封於包封體122中，且執行平坦化製程，諸如化學機械研磨(Chemical Mechanical Polish；CMP)製程或機械研磨製程，直至金屬凸塊102及金屬凸塊112暴露。隨後互連結構120形成於SoC晶粒100、HBM堆疊108以及包封體122上方。互連結構120包含介電質層118及介電質層118中的RDL 116。表面導電特徵(諸如金屬墊、金屬柱或類似者)124形成於封裝組件24的上表面處。因此，重構晶圓形成，其包含多個SoC晶粒100及多個HBM堆疊108。然後可執行單體化製程，以將重構晶圓鋸穿成多個封裝組件24。
根據替代實施例，互連結構120可預先形成為封裝基底條(帶芯或無芯)、插入件(interposer)晶圓(具有穿透對應基底 的通孔)或類似者，而非在包封多個SoC晶粒100及多個HBM堆疊108之後逐層形成。當互連結構120為插入件時，其可包含半導體基底(諸如矽基底)，且通孔穿透半導體基底以互連半導體基底的相對側上的導電特徵。對應封裝組件24的形成可包含將多個SoC晶粒100及多個HBM堆疊108接合至插入件晶圓或封裝基底條上，所述插入件晶圓或封裝基底條中分別包含多個插入件及多個封裝基底。SoC晶粒100與HBM堆疊108隨後包封在包封體122中。隨後執行單體化製程以形成多個封裝組件24。
圖2B說明圖2A中所示的結構示意性透視圖，其中說明封裝組件24、載體20、釋放膜22以及DAF 23。
圖3A及圖3B說明核心框架26在載體20上的置放。將各別製程說明為圖16中所展示的製程流程200中的製程204。核心框架26亦可經由DAF 23貼合至載體20。根據替代實施例，替代形成所有SoC管芯100及HBM堆疊108都貼合至其上的晶圓級DAF，封裝組件24與HBM堆疊108中的每一者可在其下方具有單獨的DAF，且單獨的DAF可具有與對應上覆封裝組件24及HBM堆疊108相同的形狀及大小。同樣地，當不使用晶圓級DAF時，DAF亦可貼合至核心框架26的底部以用於黏著。如圖3B中所示，核心框架26可形成矩形環，其中具有貫通開口28，且封裝組件24位於開口28中。根據本揭露內容的一些實施例，核心框架26具有相似結構，且可由與帶芯封裝基底中的核心框架相同的材料形成。然而，核心框架26不同於常規帶芯封裝基底，原因在 於核心框架26在帶芯封裝基底中不含電鍍穿孔(Plating Through-Hole；PTH)。PTH為穿透核心介電質的導電(諸如金屬，例如可包含銅)管道，且用於在核心介電質的相對側上傳導電訊號及電力。另外，核心框架26可包含位於核心介電質32的相對側上的金屬板30，其中金屬板30為不含孔及裂縫的毯覆式金屬板，此不同於常規帶芯封裝基底中的圖案化RDL。金屬板30具有提供結構支撐的功能，從而提高核心框架26的抗翹曲性。
根據本揭露內容的一些實施例，核心介電質32包括纖維玻璃。核心介電質32亦可包含環氧化物、樹脂、預浸體(其包括環氧化物、樹脂及/或纖維玻璃)、樹脂塗佈銅(resin coated Copper；RCC)、玻璃、模製化合物、塑料(諸如聚氯乙烯(PolyVinylChloride；PVC)、丙烯腈、丁二烯&苯乙烯(Butadiene&Styrene；ABS)、聚丙烯(Polypropylene；PP)、聚乙烯(Polyethylene；PE)、聚苯乙烯(PolyStyrene；PS)、聚甲基丙烯酸甲酯(Polymethyl Methacrylate；PMMA)、聚對苯二甲酸伸乙酯(Polyethylene Terephthalate；PET)、聚碳酸酯(Polycarbonates；PC)、聚苯硫醚(Polyphenylene sulfide；PPS)、撓性聚醯亞胺、其組合以及其多層。金屬板30可由銅、鎳、鎢或類似者或其合金形成。根據一些實施例，無導電特徵形成於多個金屬板30之間。
圖11A及圖11B說明根據一些實施例的所置放封裝組件24及核心框架26的頂視圖。參考圖11A，載體20為具有圓形俯視圖形狀的載體晶圓。釋放膜22及DAF 23亦可具有圓形俯視圖 形狀。多個核心框架26經置放為包括多列及多行的陣列。多個核心框架26彼此間隔開。封裝組件24置放於多個核心框架26中的每一者的開口28中。
參考圖11B，載體20具有長方形俯視圖形狀。釋放膜22及DAF 23亦可具有長方形俯視圖形狀。多個核心框架26經置放為包括多列及多行的陣列。多個核心框架26亦彼此間隔開。封裝組件24置放於多個核心框架26中的每一者的開口28中。在整個描述中，圖11A及圖11B中所示的載體20皆稱為呈晶圓形式，其上可置放多個晶粒/封裝體。
根據本揭露內容的替代性實施例，在載體20上方置放剛性環，而非置放核心框架26。剛性環可由剛性材料形成，剛性材料可由金屬(諸如銅、不鏽鋼或類似者)或金屬合金形成。根據一些實施例，剛性環可由陶瓷形成。剛性環可具有與核心框架26相同的大小以及相同的俯視圖形狀。
隨後，如圖4中所示，封裝組件24及核心框架26被包封在包封體34中。將各別製程說明為圖16中所展示的製程流程200中的製程206。包封體34填充鄰近的多個核心框架26之間的間隙以及開口28的剩餘部分。包封體34可包含模製化合物、模製底填充料、環氧化物及/或樹脂。包封體34的上表面比核心框架26及封裝組件24的頂端高。包封體34可包含基質材料以及基質材料中的填充劑顆粒，所述基質材料可為聚合物、樹脂、環氧化物及/或類似者。填充劑顆粒可為SiO2、Al2O3、二氧化矽或類似者 的介電顆粒，且可具有球形形狀。此外，球形填充劑顆粒可具有多個不同的直徑。
隨後，執行平坦化製程(諸如CMP製程或機械研磨製程)以薄化包封體34，直至導電特徵124暴露。將各別製程說明為圖16中所展示的製程流程200中的製程208。所得結構展示於圖5中。由於平坦化製程，核心框架26的頂端可與導電特徵124及包封體34的頂部表面齊平(共面)或低於所述導電特徵及所述包封體的所述頂部表面。根據本揭露內容的一些實施例，包封體34包含交疊核心框架26的層。根據本揭露內容的替代性實施例，核心框架26的頂部表面在平坦化製程之後暴露。
圖6說明前側重佈結構36的形成，所述前側重佈結構包含多個介電質層38、RDL 40以及金屬墊42。金屬墊42為前側重佈結構36的頂部表面部分，且經暴露。將各別製程說明為圖16中所展示的製程流程200中的製程210。根據本揭露內容的一些實施例，介電質層38由聚合物(諸如PBO、聚醯亞胺或類似者)形成。介電質層38以及RDL 40的對應層的形成製程可包含形成介電質層38，且接著圖案化介電質層38以形成通孔開口，下伏導電特徵(諸如導電特徵124或下伏RDL 40)經由所述通孔開口暴露。根據介電質層38由感光性材料(諸如PBO或聚醯亞胺)形成的一些實施例，通孔開口的形成涉及使用微影罩幕(未展示)的曝光製程(photo exposure process)及顯影製程。根據本揭露內容的替代性實施例，介電質層38由無機介電材料(諸如氮化矽、氧化 矽或類似者)形成，所述無機介電材料可經由沈積製程(諸如化學氣相沈積(Chemical Vapor Deposition；CVD)製程、原子層沈積(Atomic Layer Deposition；ALD)製程、電漿增強型化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition；PECVD)製程或其他可適用的沈積製程)形成。所沈積介電質層38經蝕刻以形成通孔開口。晶種層隨後沈積為毯覆層。舉例而言，晶種層可包含鈦子層及在鈦子層上方的銅子層，所述層可經由物理氣相沈積(Physical Vapor Deposition；PVD)形成。可由光阻形成的電鍍罩幕(未圖示)隨後形成且圖案化以顯露下伏金屬晶種層。執行電鍍製程以電鍍金屬材料。電鍍罩幕隨後移除，接著進行蝕刻製程以移除未由鍍覆材料覆蓋的金屬晶種層的部分。鍍覆材料及晶種層的下伏剩餘部分形成RDL 40。
前側重佈結構36可包含5個至9個或大於9個RDL層40。根據本揭露內容的一些實施例，RDL的線寬可小於約3微米或將近約2微米。因此，RDL層40的數量可降低以滿足佈線要求。
如圖6中所示，作為所得封裝體的一部分的核心框架26具有為所得封裝體提供機械支撐的功能。由於核心框架26的厚度可與封裝組件24及記憶體堆疊108的厚度一樣大，所述封裝組件及所述記憶體堆疊具有多個堆疊晶粒的厚度，因此核心框架26可提供顯著的機械支撐以減少翹曲，而不會導致電路徑的不利增加，因為所述核心框架不在電路徑的中間。效果類似於將帶芯封裝基底的芯移出佈線路徑以與封裝組件24在相同層級，使得其提供機 械支撐的功能保持不變，而不會導致電路徑長度的增加。
圖7說明將獨立被動裝置(Independent Passive Device；IPD)44及電容器46接合至金屬墊42。將各別製程說明為圖16中所展示的製程流程200中的製程212。IPD 44可為電感器、電阻器、電容器或類似者。電容器46可為多層陶瓷電容器(Multi-Layer Ceramic Capacitor；MLCC)，且可用作電力儲存器。如圖7中所示，在電容器46與封裝組件24之間的利用所儲存電力的電路徑為短的，此是因為在電容器46與封裝組件24之間不存在核心。根據本揭露內容的一些實施例，封裝組件24為對效能要求高的HPC封裝體。由於電容器46與封裝組件24之間的電路徑為短的，電容器46可提供電力以滿足封裝組件24的電湧(surge)要求，而無顯著的IR下降與時延(latency)。
圖8說明電連接器48的形成。將各別製程說明為圖16中所展示的製程流程200中的製程214。電連接器48的形成可包含將焊料球置放於金屬墊42的暴露部分上且接著回焊焊料球，且因此電連接器48為焊料區。根據本揭露內容的替代性實施例，電連接器48的形成包含執行鍍覆步驟以形成金屬墊42上方的焊料層，且接著回焊經鍍覆焊料層。電連接器48亦可包含非焊料金屬柱或非焊料金屬柱上方的亦可經由鍍覆形成的金屬柱及焊料蓋。貫穿描述，上覆於DAF 23的結構及組件組合地稱為重構晶圓50。
隨後，將重構晶圓50置放在貼合至切割框架(未展示)的載帶(未展示)上。根據本揭露內容的一些實施例，電連接器 48與載帶接觸。然後，重構晶圓50自載體20剝離。根據本揭露內容的一些實施例中，為剝離重構晶圓50，將光束投射在釋放膜22上，且光穿過透明載體20。根據本揭露內容的一些實施例，光包含雷射束，所述雷射束掃描穿過整個釋放膜22。
由於光暴露(諸如雷射掃描)，載體20可自DAF 23脫離，且因此重構晶圓50自載體20剝離(卸下)。在光暴露期間，釋放膜22回應於由光暴露所產生的熱量而分解，從而允許載體20與上覆結構分離。隨後例如經由電漿清潔步驟來移除釋放膜22的殘餘物。DAF 23亦可經移除。所得重構晶圓50展示於圖9中。若使用單獨DAF，而非毯覆式DAF。單獨DAF可經由研磨移除，或可保持不移除。在此情況下，核心框架26與封裝組件24交疊對應DAF，所述對應DAF具有與上覆核心框架26及封裝組件24相同的大小及俯視圖形狀。單獨DAF可在包封體34中，且可具有與包封體34的底表面共面的底表面。
在單體化製程中，重構晶圓50接著可經單體化，所述單體化製程可使用晶粒鋸割製程執行。將各別製程說明為圖16中所展示的製程流程200中的製程216。舉例而言，鋸片可用於鋸穿包封體34及介電質層38以將重構晶圓50分成多個相同的封裝體60中，所述封裝體各自具有根據一些實例所說明的結構。在所得封裝體60中，核心框架26可藉由一些包封體34與封裝體60的最近邊緣間隔開。
圖10說明實例封裝體60。根據本揭露內容的一些實施例， 介電質層38的厚度T1可在約5微米與約100微米範圍內。核心框架26的厚度T2可在約20微米與約2,000微米之間的範圍內。厚度T2亦可等於或稍小於(例如大於約80%及小於100%)封裝組件24的厚度，且可等於或稍小於SoC晶粒100及記憶體堆疊108的厚度。間隔S1為核心框架26的邊緣與封裝體60的對應最近邊緣之間的空間，所述空間可在約10微米與約3,000微米之間的範圍內。核心框架26與封裝組件24之間的間距S2可在約10微米與約3,000微米之間的範圍內。
圖10進一步說明將封裝體60接合至封裝組件58上以形成封裝體61。將各別製程說明為圖16中所展示的製程流程200中的製程218。根據本揭露內容的一些實施例，封裝組件58包括印刷電路板、其他封裝體或類似者。根據本揭露內容的一些實施例，金屬環62經由黏著膜63貼合至封裝體60的頂部表面。將各別製程說明為圖16中所展示的製程流程200中的製程220。金屬環62可提供進一步的機械支撐以減少封裝體61的翹曲。根據替代實施例，無金屬環62經貼合。金屬環62可具有與核心框架26(圖3B)相似的形狀。金屬環62的外邊緣可與封裝體60的外邊緣齊平。
圖12至圖15說明根據本揭露內容的替代性實施例的封裝體形成的中間階段的橫截面圖。除非另有指定，否則這些實施例中的組件的材料及形成製程基本上與由在圖1、圖2A、圖2B、圖3A、圖3B以及圖4至圖10中展示的前述實施例中的相似參考 標號表示的相似組件相同。關於圖12至圖15中展示的組件的形成製程及材料的細節可因此在對前述實施例的論述中發現。這些實施例的初始步驟基本上與圖1、圖2A、圖2B、圖3A、3B圖以及圖4至圖8中所展示的相同。應理解，圖12至圖15中所示的製程說明其中重構晶圓50已鋸割開為多個封裝體60的製程。
參考圖12，根據本揭露內容的一些實施例，封裝體60置放於載體64上，釋放膜66及DAF 68形成於所述封裝體上方。載體64、釋放膜66以及DAF 68可由分別與載體20、釋放膜22以及DAF 23相似的材料形成且具有與其相似的功能及相似的形狀。舉例而言，載體64可具有如圖11A中所示的圓形俯視圖形狀或具有如圖11B中所示的長方形俯視圖形狀。隨後多個封裝體60(以其中一者來說明)置放於DAF 68上，且可以行及列形式置放。多個核心基底70(以其中一者來說明)經由電連接器48接合至對應的下伏封裝體60。
根據本揭露內容的一些實施例，帶芯封裝基底70可包含核心介電質72，其中PTH 73穿透核心介電質層72。核心介電質72可由與核心框架26中的核心介電質32相似的材料形成。PTH 73為金屬管，其中介電質區域75填充由PTH 73環繞的區域。RDL 74與RDL 76形成於核心介電質72的相對側上，且經由PTH 73互連。焊料區域48穿透介電質層71以接觸RDL 74，且一些RDL 76經由介電質層78中的多個開口暴露。根據本揭露內容的一些實施例，多個帶芯封裝基底70中的每一者具有各側(上方或下方)核心介 電質72上的RDL的單層。根據其他實施例，存在大於一個在帶芯介電質72的各側上的RDL層。帶芯封裝基底70的熱膨脹係數(Coefficient of Thermal Expansion；CTE)接近(且可高於)將接合至其上的封裝組件58(圖15)的CTE，且低於前側重佈結構36的CTE。因此，帶芯封裝基底70在封裝組件58與前側重佈結構36之間用作緩衝器以降低及吸收壓力。
圖13說明根據一些實施例的包封體82中的上述形成結構的包封，所述包封體可為模製化合物、模製底填充物或類似者。包封可經由暴露模製(expose molding)執行，因此RDL 76不由包封體82覆蓋。包封體82延伸至封裝體60的側壁。包封體34及包封體82可由相同或不同類型的材料(包含基質材料的材料及填充劑顆粒的材料)形成。不管材料的原料如何，由於包封體34已經鋸割及平坦化，鋸割及平坦化的填料顆粒具有部分球形形狀，因此包封體34與包封體82之間的介面為可識別的。
根據本揭露內容的一些實施例，如圖13中所示，已自重構晶圓50(圖8)鋸割的封裝體60用於圖12至圖15中所展示的封裝製程。根據其他實施例，替代將重構晶圓50鋸割開，而將帶芯基底70接合至重構晶圓50，繼之以封裝製程與鋸割製程。因此，包封體82並不延伸至與封裝體60相同層級。相反地，包封體82的整體位於封裝體60上方。
圖14說明電連接器84的形成，所述電連接器可為焊料區域、金屬柱等。在DAF 68上方的所得結構稱為重構晶圓86。 隨後，例如藉由投射光束以分解釋放膜66而自載體64剝離重構晶圓86。單體化製程隨後沿著切割道88執行，因此形成多個相同封裝體60'。
一個封裝體60'展示圖15中。圖15亦說明封裝體60'至封裝組件58的接合，所述封裝組件58可為印刷電路板、其他封裝體或類似者。
在以上所說明的實施例中，根據本發明的一些實施例論述一些製程及特徵以形成三維(three-dimensional；3D)封裝體。亦可包含其他特徵及製程。舉例而言，可包含測試結構以幫助對3D封裝體或3DIC裝置進行校驗測試。測試結構可包含例如形成於重佈層中或基底上的測試墊，所述測試墊允許測試3D封裝體或3DIC、使用探針及/或探測卡以及類似操作。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭露的結構及方法可結合併入有對已知良好晶粒的中間驗證的測試方法而使用，以提高良率及降低成本。
本揭露內容的實施例具有一些有利特徵。本揭露內容的實施例適合於大型封裝體的形成，例如，經常用於HPC應用的具有80公釐×80公釐或大於80公釐×80公釐的尺寸的大型封裝體。大型封裝體經常受嚴重翹曲問題的影響。藉由封裝與HPC封裝體位於相同層級的核心框架，核心的厚度並不影響電訊號與電力的佈線長度。舉例而言，對於80公釐×80公釐大小的封裝體，翹曲可自2,434奈米(若不使用核心框架)減小至200奈米(若使用核 心框架)。對於尺寸為53.5公釐×53.5公釐的封裝體，翹曲可自942奈米(若不使用芯框架)減小至148奈米(若使用核心框架)。舉例而言，對於尺寸為44公釐×44公釐的封裝體，翹曲可自386奈米(若不使用核心框架)減小至139奈米(若使用核心框架)。由於核心框架與封裝組件(諸如HPC封裝體)置放於相同層級，所得封裝體的性能亦不受核心框架厚度影響。此外，所得封裝體可由薄及短的RDL形成，且因此封裝體的訊號完整性得以改良。
根據本揭露內容的一些實施例，方法包括：將第一封裝組件置放在載體上方，其中第一封裝組件包括裝置晶粒；將核心框架置放在載體上方，其中核心框架形成環繞第一封裝組件的環；將核心框架及第一封裝組件包封在包封體中；在核心框架及第一封裝組件上方形成多個重佈線；以及經由多個重佈線形成在第一封裝組件上方形成多個電連接器，多個電連接器經由多個重佈線電耦合至第一封裝組件。在一實施例中，方法更包括在包封之後，平面化包封體直至第一封裝組件的多個導電特徵顯露。在實施例中，核心框架包括核心介電質及核心介電質的相對側上的多個金屬板。在實施例中，核心框架不含穿透核心介電質的導電管道。在實施例中，裝置晶粒包括SoC晶粒及包封SoC晶粒於其中的額外包封體。在一實施例中，方法更包括：執行晶粒鋸割以形成封裝體，其中第一封裝組件在封裝體中；以及經由多個電連接器將第二封裝組件接合至封裝體，其中第二封裝組件包含：附加核心介電質；多個附加導電管道，穿透附加核心介電質；以及多個附 加重佈線，位於附加核心介電質的相對側上且經由多個附加導電管道互連。在一實施例中，方法更包括：執行晶粒鋸割製程以形成封裝體，其中第一封裝組件在封裝體中；以及將金屬環貼合至封裝體。在一實施例中，方法更包括將被動裝置接合至多個重佈線，其中被動裝置與電連接器在相同層級中。
根據本揭露內容的一些實施例方法包括：將核心框架置放在載體上方，其中核心框架包括：核心介電質；以及第一金屬板與第二金屬板，位於核心介電質的相對側上；將封裝組件置放在核心框架中的開口中及載體上方，其中封裝組件包括裝置晶粒；將核心框架及封裝組件包封在包封體中；以及在核心框架及封裝組件上方形成多個重佈線，其中多個重佈線電連接至封裝組件，且電解耦(decouple)於核心框架。在一實施例中，方法更包括形成在多個重佈線上方且電耦合至多個重佈線的多個焊料區域，其中所有的多個焊料區域電解耦於核心框架。在一實施例中，第一金屬板及第二金屬板為其中無孔的毯覆式金屬板。在一實施例中，方法更包括在包封之後，執行平面化製程以顯露封裝組件的多個頂部導電特徵，其中平面化製程在核心框架顯露之前停止。在實施例中，方法更包括形成在包封體及封裝組件上方且與包封體及封裝組件接觸的介電質層，其中多個重佈線的底部層延伸至介電質層中，其中介電質層藉由包封體的層與核心框架間隔開。在一實施例中，方法更包括執行晶粒鋸割製程，以形成包括封裝組件、核心框架以及包封體的一部分的封裝體，其中晶粒鋸割製程並不 切穿核心框架。
根據本揭露內容的一些實施例，封裝體包括：封裝組件，包括裝置晶粒於其中；核心框架，形成環繞封裝組件的環；包封體，包封封裝組件及核心框架於其中；多個介電質層，位於包封體上方；以及多個重佈線，位於多個介電質層中，其中多個重佈線電連接至封裝組件且電解耦於核心框架。在一實施例中，核心框架包括：核心介電質；以及第一金屬板與第二金屬板，位於核心介電質的相對側上。在一實施例中，第一金屬板及第二金屬板為其中不含孔的毯覆式金屬板。在一實施例中，核心框架不含穿透核心介電質的導電特徵。在一實施例中，核心介電質包括纖維玻璃。在一實施例中，封裝體更包括接合至封裝組件的封裝基底，其中封裝基底包括：附加核心介電質；多個附加導電管道，穿透附加核心介電質；以及多個附加重佈線，位於核心介電質的相對側上且經由多個附加導電管道互連。
前文概述若干實施例的特徵以使得所屬領域中具通常知識者可更佳地理解本揭露內容的態樣。在本領域的技術人員應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且本領域的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
202、204、206、208、210、212、214、216、218、220:製程

Claims (10)

  1. 一種形成封裝體的方法，包括：將第一封裝組件置放在載體上方，其中所述第一封裝組件包括裝置晶粒；將核心框架置放在所述載體上方，其中所述核心框架形成環繞所述第一封裝組件的環；將所述核心框架及所述第一封裝組件包封在包封體中；在所述核心框架及所述第一封裝組件上方形成多個重佈線；經由所述多個重佈線在所述第一封裝組件上方形成多個電連接器，所述多個電連接器經由所述多個重佈線電耦合至所述第一封裝組件；執行晶粒鋸割製程以形成封裝體，其中所述第一封裝組件在所述封裝體中；以及將金屬環貼合至所述封裝體。
  2. 如申請專利範圍第1項所述的方法，其中所述裝置晶粒包括系統晶片晶粒以及包封所述系統晶片晶粒於其中的額外包封體。
  3. 如申請專利範圍第1項所述的方法，更包括：經由所述多個電連接器將第二封裝組件接合至所述封裝體，其中所述第二封裝組件包括：附加核心介電質；多個附加導電管道，穿透所述附加核心介電質；以及 多個附加重佈線，位於所述附加核心介電質的相對側上且經由所述多個附加導電管道互連。
  4. 一種形成封裝體的方法，包括：將核心框架置放在載體上方，其中所述核心框架包括：核心介電質；以及第一金屬板及第二金屬板，位於所述核心介電質的相對側上；將封裝組件置放在所述核心框架中的開口中及所述載體上方，其中所述封裝組件包括裝置晶粒；將所述核心框架及所述封裝組件包封在包封體中；以及在所述核心框架及所述封裝組件上方形成多個重佈線，其中所述多個重佈線電連接至所述封裝組件，且電解耦於所述核心框架。
  5. 如申請專利範圍第4項所述的方法，更包括在所述包封之後，執行平面化製程以顯露所述封裝組件的多個頂部導電特徵，其中在所述核心框架顯露前停止所述平面化製程。
  6. 如申請專利範圍第4項所述的方法，更包括執行晶粒鋸割製程，以形成包括所述封裝組件、所述核心框架以及所述包封體的一部分的封裝體，其中所述晶粒鋸割製程並不切穿所述核心框架。
  7. 一種封裝體，包括：封裝組件，包括裝置晶粒於其中； 核心框架，形成環繞所述封裝組件的環；包封體，包封所述封裝組件及所述核心框架於其中；多個介電質層，位於所述包封體上方；以及多個重佈線，位於多個介電質層中，其中所述多個重佈線電連接至所述封裝組件，且電解耦於所述核心框架。
  8. 如申請專利範圍第7項所述的封裝體，其中所述核心框架包括：核心介電質；以及第一金屬板及第二金屬板，位於所述核心介電質的相對側上。
  9. 如申請專利範圍第8項所述的封裝體，其中所述第一金屬板及所述第二金屬板為其中不含孔的毯覆式金屬板。
  10. 如申請專利範圍第8項所述的封裝體，其中所述核心框架不含穿透所述核心介電質的導電特徵。
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