TW201926602A - 扇出型半導體封裝 - Google Patents

扇出型半導體封裝 Download PDF

Info

Publication number
TW201926602A
TW201926602A TW107119317A TW107119317A TW201926602A TW 201926602 A TW201926602 A TW 201926602A TW 107119317 A TW107119317 A TW 107119317A TW 107119317 A TW107119317 A TW 107119317A TW 201926602 A TW201926602 A TW 201926602A
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
fan
semiconductor package
disposed
item
Prior art date
Application number
TW107119317A
Other languages
English (en)
Other versions
TWI676247B (zh
Inventor
曺正鉉
許榮植
白龍浩
Original Assignee
南韓商三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW201926602A publication Critical patent/TW201926602A/zh
Application granted granted Critical
Publication of TWI676247B publication Critical patent/TWI676247B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32265—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1088—Arrangements to limit the height of the assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一種扇出型半導體封裝包括：第一連接構件，具有貫穿孔；半導體晶片，設置於所述貫穿孔中且包括主動面及與所述主動面相對的非主動面，所述主動面上設置有連接墊；第二連接構件，設置於所述半導體晶片的所述主動面上且包括電性連接至所述半導體晶片的重佈線層；以及包封體，對所述半導體晶片進行包封且具有設置於所述半導體晶片的所述非主動面上方的空腔。

Description

扇出型半導體封裝
本揭露是有關於一種半導體封裝，且更具體而言是有關於一種電性連接結構可朝半導體晶片所設置的區域之外延伸的扇出型半導體封裝。 [相關申請案的交叉參照]
本申請案主張2017年11月29日在韓國智慧財產局中申請的韓國專利申請案第10-2017-0162144號的優先權的權益，所述韓國專利申請案的揭露內容以全文引用的方式併入本文中。
半導體晶片相關技術發展中的重要近期趨勢為縮小半導體晶片的尺寸。因此，在封裝技術領域中，隨著對小型尺寸半導體晶片等的需求快速增加，亟需實施包括多個引腳（pin）的小型尺寸（compact size）半導體封裝。
扇出型半導體封裝即為一種滿足上述技術需求而提出的半導體封裝技術。此種扇出型封裝具有小型尺寸，並可容許藉由朝半導體晶片所設置的區域之外對連接端子進行重新分佈而實施多個引腳。
此種半導體封裝可以同時對多個半導體晶片或被動元件等進行封裝的多晶片封裝（multichip package）的形式實施，且在此種情形中，所述封裝的厚度及大小可增大。
本揭露的態樣可提供適合於薄度（thinness）及高積集度（high integration）的一種扇出型半導體封裝。
根據本揭露的態樣，一種扇出型半導體封裝可包括：第一連接構件，具有貫穿孔；第一半導體晶片，設置於所述貫穿孔中且包括主動面及與所述主動面相對的非主動面，所述主動面上設置有連接墊；第二連接構件，設置於所述第一半導體晶片的所述主動面上，且包括電性連接至所述半導體晶片的重佈線層；以及包封體，對所述第一半導體晶片進行包封，且具有設置於所述半導體晶片的所述非主動面上方的空腔。
所述扇出型半導體封裝可更包括設置於所述第一半導體晶片的所述非主動層上的黏合層。
所述空腔具有的寬度可大於所述半導體晶片的寬度。
所述扇出型半導體封裝可更包括與所述第一半導體晶片並排地設置於所述貫穿孔中的第二半導體晶片。
所述扇出型半導體封裝可更包括被設置成相鄰於所述第一半導體晶片且具有藉由所述空腔而暴露出的上表面的被動元件。
所述扇出型半導體封裝可更包括設置於所述第一連接構件上以覆蓋所述空腔的印刷電路板。
所述扇出型半導體封裝可更包括設置於所述印刷電路板的下表面上且定位於所述空腔中的附加半導體晶片。
扇出型半導體封裝可更包括設置於所述印刷電路板的上表面上的附加半導體晶片。
所述扇出型半導體封裝可更包括設置於所述印刷電路板的下表面上且定位於所述空腔中的被動元件。
所述扇出型半導體封裝可更包括嵌入所述印刷電路板中的附加半導體晶片。
所述扇出型半導體封裝可更包括設置於所述印刷電路板的下表面上且定位於所述空腔中的被動元件。
所述印刷電路板可為天線或感測器板。
所述扇出型半導體封裝可更包括設置於所述第一半導體晶片的所述非主動面上且定位於所述空腔中的附加半導體晶片。
所述扇出型半導體封裝可更包括設置於所述第一連接構件上且電性連接至所述附加半導體晶片的第三連接構件。
所述扇出型半導體封裝可更包括導電焊線及模製部分，所述導電焊線連接至所述附加半導體晶片，所述模製部分對所述導電焊線進行包封。
所述扇出型半導體封裝可更包括附加半導體晶片及模製部分，所述附加半導體晶片設置於所述第一連接構件上且定位於所述空腔上，所述模製部分對所述附加半導體晶片進行包封。
所述附加半導體晶片可為微機電系統（micro electro mechanical system，MEMS）元件，且所述空腔可處於真空狀態。
所述扇出型半導體封裝可更包括設置於所述空腔中且接合至所述第一半導體晶片的熱輻射部分。
在下文中，將參照所附圖式闡述本揭露中的各例示性實施例。在所附圖式中，為清晰起見，可誇大或縮小各組件的形狀、尺寸等。
電子裝置
圖1為示出電子裝置系統的實例的方塊示意圖。
參照圖1，電子裝置1000中可容置主板1010。主板1010可包括物理連接或電性連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件以形成各種訊號線1090。
晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體（例如動態隨機存取記憶體（dynamic random access memory，DRAM））、非揮發性記憶體（例如唯讀記憶體（read only memory，ROM））、快閃記憶體等；應用處理器晶片，例如中央處理器（例如中央處理單元（central processing unit，CPU））、圖形處理器（例如圖形處理單元（graphics processing unit，GPU））、數位訊號處理器、密碼處理器（cryptographic processor）、微處理器、微控制器等；以及邏輯晶片，例如類比至數位轉換器（analog-to-digital converter，ADC）、應用專用積體電路（application-specific integrated circuit，ASIC）等。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。
網路相關組件1030可包括例如以下協定：無線保真（wireless fidelity，Wi-Fi）（電氣及電子工程師學會（Institute of Electrical And Electronics Engineers，IEEE）802.11家族等）、全球互通微波存取（worldwide interoperability for microwave access，WiMAX）（IEEE 802.16家族等）、IEEE 802.20、長期演進（long term evolution，LTE）、僅支援資料的演進（evolution data only，Ev-DO）、高速封包存取+（high speed packet access +，HSPA+）、高速下行封包存取+（high speed downlink packet access +，HSDPA+）、高速上行封包存取+（high speed uplink packet access +，HSUPA+）、增強型資料GSM環境（enhanced data GSM environment，EDGE）、全球行動通訊系統（global system for mobile communications，GSM）、全球定位系統（global positioning system，GPS）、通用封包無線電服務（general packet radio service，GPRS）、分碼多重存取（code division multiple access，CDMA）、分時多重存取（time division multiple access，TDMA）、數位增強型無線電訊（digital enhanced cordless telecommunications，DECT）、藍芽、3G協定、4G協定及5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括各種其他無線標準或協定或者有線標準或協定。另外，網路相關組件1030可與以上所述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器（ferrite inductor）、功率電感器（power inductor）、鐵氧體珠粒（ferrite beads）、低溫共燒陶瓷（low temperature co-firing ceramic，LTCC）、電磁干擾（electromagnetic interference，EMI）濾波器、多層陶瓷電容器（multilayer ceramic capacitor，MLCC）等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動組件等。另外，其他組件1040可與以上所述的晶片相關組件1020或網路相關組件1030一起彼此組合。
視電子裝置1000的類型而定，電子裝置1000可包括可物理連接至或電性連接至主板1010的其他組件，或可不物理連接至或不電性連接至主板1010的其他組件。該些其他組件可包括例如照相機1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器（未繪示）、視訊編解碼器（未繪示）、功率放大器（未繪示）、羅盤（未繪示）、加速度計（未繪示）、陀螺儀（未繪示）、揚聲器（未繪示）、大容量儲存單元（例如硬碟驅動機）（未繪示）、光碟（compact disk，CD）驅動機（未繪示）、數位多功能光碟（digital versatile disk，DVD）驅動機（未繪示）等。然而，該些其他組件並非僅限於此，而是視電子裝置1000的類型等而定亦可包括用於各種目的的其他組件。
電子裝置1000可為智慧型電話、個人數位助理（personal digital assistant，PDA）、數位攝影機、數位照相機（digital still camera）、網路系統、電腦、監視器、平板個人電腦（personal computer，PC）、筆記型個人電腦、隨身型易網機個人電腦（netbook PC）、電視、視訊遊戲機（video game machine）、智慧型手錶、汽車等。然而，電子裝置1000並非僅限於此，而是亦可為處理資料的任何其他電子裝置。
圖2為示出電子裝置的實例的立體示意圖。
參照圖2，半導體封裝可於如上所述的各種電子裝置1000中使用於各種目的。舉例而言，母板1110可容置於智慧型電話1100的本體1101中，且各種組件1120可物理連接至或電性連接至母板1110。另外，可物理連接至或電性連接至主板1010或可不物理連接至或不電性連接至主板1010的其他組件（例如照相機1130）可容置於本體1101中。電子組件1120中的一些電子組件可為晶片相關組件，且半導體封裝100可為例如晶片相關組件中的應用處理器，但並非僅限於此。所述電子裝置不必僅限於智慧型電話1100，而是可為如上所述的其他電子裝置。
半導體封裝
一般而言，半導體晶片中整合了諸多精密的電路。然而，半導體晶片自身不能充當已完成的半導體產品，且可能因外部物理性或化學性影響而受損。因此，半導體晶片無法單獨使用，但可封裝於電子裝置等中且在電子裝置等中以封裝狀態使用。
此處，由於半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異，因而需要半導體封裝。詳言之，半導體晶片的連接墊的尺寸及半導體晶片的連接墊之間的間隔極為精密，但電子裝置中所使用的主板的組件安裝墊的尺寸及主板的組件安裝墊之間的間隔顯著大於半導體晶片的連接墊的尺寸及間隔。因此，可能難以將半導體晶片直接安裝於主板上，而需要用於緩衝半導體晶片與主板之間的電路寬度差異的封裝技術。
視半導體封裝的結構及目的而定，藉由封裝技術製造的半導體封裝可分類為扇入型半導體封裝或扇出型半導體封裝。
在下文中，將參照圖式更詳細地闡述扇入型半導體封裝及扇出型半導體封裝。
扇入型 半導體封裝
圖3A及圖3B為示出扇入型半導體封裝在封裝前及封裝後狀態的剖面示意圖。
圖4為示出扇入型半導體封裝的封裝製程的剖面示意圖。
參照所述圖式，半導體晶片2220可例如是處於裸露狀態下的積體電路（integrated circuit，IC），半導體晶片2220包括：本體2221，包括矽（Si）、鍺（Ge）、砷化鎵（GaAs）等；連接墊2222，形成於本體2221的一個表面上且包括例如鋁（Al）等導電材料；以及鈍化層2223，其例如是氧化物膜、氮化物膜等，且形成於本體2221的一個表面上且覆蓋連接墊2222的至少一部分。在此種情形中，由於連接墊2222在尺寸上為顯著小的，因此可能難以將積體電路（IC）安裝於中級印刷電路板（printed circuit board，PCB）上以及電子裝置的主板等上。
因此，連接構件2240可視半導體晶片2220的尺寸而形成在半導體晶片2220上，以對連接墊2222進行重新分佈。連接構件2240可藉由以下步驟形成：利用例如感光成像介電（photo imagable dielectric，PID）樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241，形成敞開連接墊2222的通孔孔洞2243h，並接著形成配線圖案2242及通孔2243。接著，可形成保護連接構件2240的鈍化層2250，可形成開口2251，並可形成凸塊下金屬層2260等。亦即，可藉由一系列製程來製造包括例如半導體晶片2220、連接構件2240、鈍化層2250及凸塊下金屬層2260的扇入型半導體封裝2200。
如上所述，扇入型半導體封裝可具有半導體晶片的所有連接墊（例如輸入/輸出（input/output，I/O）端子）均設置於半導體晶片內的一種封裝形式，且可具有優異的電性特性並可利用低成本進行生產。因此，諸多安裝於智慧型電話中的元件已以扇入型半導體封裝的形式製造而出。詳言之，已開發出諸多安裝於智慧型電話中的元件，其在具有小型尺寸時仍可以實施快速的訊號傳遞。
然而，由於在扇入型半導體封裝中所有I/O端子皆需要設置於半導體晶片內，因此扇入型半導體封裝的空間限制大。因此，難以將此種結構應用於具有大量I/O端子的半導體晶片或具有小型尺寸的半導體晶片。另外，由於以上所述的缺點，扇入型半導體封裝無法在電子裝置的主板上直接安裝並使用。原因在於，即使藉由重佈線製程增大半導體晶片的I/O端子的尺寸及半導體晶片的各I/O端子之間的間隔，在此種情形中，半導體晶片的I/O端子的尺寸及半導體晶片的各I/O端子之間的間隔仍不足以使扇入型半導體封裝直接安裝於電子裝置的主板上。
圖5為示出扇入型半導體封裝安裝於中介基板上且最終安裝於電子裝置的主板上之情形的剖面示意圖。
圖6為示出扇入型半導體封裝嵌入中介基板中且最終安裝於電子裝置的主板上之情形的剖面示意圖。
參照圖5及圖6，在扇入型半導體封裝2200中，半導體晶片2220的連接墊2222（即，I/O端子）可經由中介基板2301重新分佈，且扇入型半導體封裝2200可在其安裝於中介基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此種情形中，可藉由底部填充樹脂2280等來固定焊球2270等，且半導體晶片2220的外側可利用模製材料2290等覆蓋。或者，扇入型半導體封裝2200可嵌入單獨的中介基板2302中，半導體晶片2220的連接墊2222（即，I/O端子）可在扇入型半導體封裝2200嵌入中介基板2302中的狀態下由中介基板2302重新分佈，且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。
如上所述，可能難以在電子裝置的主板上直接安裝並使用扇入型半導體封裝。因此，扇入型半導體封裝可安裝於單獨的中介基板上，並接著藉由封裝製程安裝於電子裝置的主板上，或者扇入型半導體封裝可在扇入型半導體封裝嵌入中介基板中的狀態下在電子裝置的主板上安裝並使用。
扇出型 半導體封裝
圖7為示出扇出型半導體封裝的剖面示意圖。
參照圖7，在扇出型半導體封裝2100中，舉例而言，半導體晶片2120的外側可由包封體2130保護，且半導體晶片2120的連接墊2122可藉由連接構件2140而朝半導體晶片2120之外進行重新分佈。在此種情形中，在連接構件2104上可進一步形成鈍化層2202，且在鈍化層2202的開口中可進一步形成凸塊下金屬層2106。在凸塊下金屬層2160上可進一步形成焊球2170。半導體晶片2120可為包括本體2121、連接墊2122、鈍化層（未繪示）等的積體電路（IC）。連接構件2140可包括絕緣層2141、形成於絕緣層2141上的重佈線層2142以及將連接墊2122與重佈線層2142彼此電性連接的通孔2143。
如上所述，扇出型半導體封裝可具有一種形式，其中半導體晶片的I/O端子藉由形成於半導體晶片上的連接構件而朝半導體晶片之外進行重佈線並朝半導體晶片之外進行設置。如上所述，在扇入型半導體封裝中，半導體晶片的所有I/O端子皆需要設置於半導體晶片內。因此，當半導體晶片的尺寸減小時，須減小球的尺寸及間距，進而使得標準化球佈局（standardized ball layout）無法在扇入型半導體封裝中使用。另一方面，扇出型半導體封裝具有一種形式，其中半導體晶片的I/O端子藉由形成於半導體晶片上的連接構件而朝半導體晶片之外進行重新分佈並朝半導體晶片之外進行設置，如上所述。因此，即使在半導體晶片的尺寸減小的情形中，標準化球佈局亦可照樣用於扇出型半導體封裝中，進而使得扇出型半導體封裝無須使用單獨的中介基板即可安裝於電子裝置的主板上，如下所述。
圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的剖面示意圖。
參照圖8，扇出型半導體封裝2100可經由焊球2170等安裝於電子裝置的主板2500上。亦即，如上所述，扇出型半導體封裝2100包括連接構件2140，連接構件2140形成於半導體晶片2120上且能夠將連接墊2122重新分佈至半導體晶片2120的尺寸之外的扇出區，進而使得標準化球佈局可照樣用於扇出型半導體封裝2100中。因此，扇出型半導體封裝2100無須使用單獨的中介基板等即可安裝於電子裝置的主板2500上。
如上所述，由於扇出型半導體封裝無須使用單獨的中介基板即可安裝於電子裝置的主板上，因此扇出型半導體封裝可在其厚度小於使用中介基板的扇入型半導體封裝的厚度的情況下實施。因此，可使扇出型半導體封裝小型化且薄化。另外，扇出型半導體封裝具有優異的熱特性及電性特性，進而使得扇出型半導體封裝尤其適合用於行動產品。因此，扇出型半導體封裝可被實施成較使用印刷電路板（PCB）的一般疊層封裝（package-on-package，POP）類型更小型的形式，且可解決因翹曲（warpage）現象出現而產生的問題。
同時，扇出型半導體封裝指代一種封裝技術，如上所述用於將半導體晶片安裝於電子裝置的主板等上且保護半導體晶片免受外部影響，且其與例如中介基板等的印刷電路板（PCB）在概念上是不同的，印刷電路板具有與扇出型半導體封裝的規格、目的不同的規格、目的等，且有扇入型半導體封裝嵌入其中。
在下文中，將參照圖式闡述根據本揭露中的例示性實施例的一種扇出型半導體封裝。
圖9為示出扇出型半導體封裝的實例的剖面示意圖。圖10示出圖9的扇出型半導體封裝的經修改實例。
參照圖式，根據本揭露中的例示性實施例的扇出型半導體封裝100可包括第一連接構件111、半導體晶片120、包封體130及第二連接構件140，第一連接構件111具有貫穿孔110H。包封體130可具有空腔C以暴露出半導體晶片120的一個表面。空腔C可為由包封體130的上外表面131與包封體130的中間內表面132之間的台階S所形成的包封體130的凹陷部（recess）。包封體130可未覆蓋半導體晶片120的非主動面。包封體130可覆蓋半導體晶片的側表面。在將黏合層160貼附至半導體晶片120的非主動面的情形中，包封體130的中間內表面132與黏合層160的上表面可實質上彼此共面，且空腔C可暴露出黏合層160的整個上表面。在存在此種黏合層的情形中，包封體130的中間內表面132與半導體晶片120的非主動面可實質上彼此共面，且空腔C可暴露出半導體晶片120的整個非主動面。「實質上」或「近似」意指考慮到由製造過程所造成的容差/誤差/變動以界定相應的關係。除以上所述組件之外，扇出型半導體封裝100可包括鈍化層150、電性連接結構170等。
第一連接構件110可視特定材料而定來進一步改善扇出型半導體封裝100的剛性，且可用於確保包封體130的厚度均勻性。當如以下將闡述的例示性實施例中一樣貫通配線（through-wirings）等形成於第一連接構件110中時，扇出型半導體封裝100可作為疊層封裝（POP）型封裝使用。根據本揭露，第一連接構件110可包括貫穿孔110H，且半導體晶片120可設置於貫穿孔110H中。半導體晶片120的側表面可被第一連接構件110環繞。然而，此種形式僅為實例，並可經由各式修改以具有其他形式，且第一連接構件110可依此種形式而執行另一功能。必要時，可省略第一連接構件110，但第一連接構件110可更有利於在扇出型半導體封裝100包括第一連接構件110時確保板級可靠性（board level reliability）。
可使用絕緣材料作為形成第一連接構件111的絕緣層的材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維（或玻璃布，或玻璃纖維布）等的核心材料中的樹脂，例如預浸體（prepreg）、味之素構成膜（Ajinomoto Build up Film，ABF）、FR-4或雙馬來醯亞胺三嗪（Bismaleimide Triazine，BT）等。此種第一連接構件110可當作支撐構件。
同時，如圖10的經修改實例中所示，第一連接構件111可包括貫通配線112及113。在此種情形中，扇出型半導體封裝100可作為POP型封裝使用。詳言之，第一連接構件111可包括配線層113及連接至配線層113的導電通孔112。儘管圖10示出配線層113僅形成於第一連接構件111的絕緣層的上表面及下表面上，然而配線層113亦可形成於所述絕緣層中。
半導體晶片120可為設置為將數百至數百萬個或更多數量的元件整合於單一晶片中的積體電路（IC）。在此種情形中，舉例而言，所述積體電路可為處理器晶片（更具體而言，應用處理器（AP）），例如中央處理器（比如CPU）、圖形處理器（比如GPU）、場域可程式閘陣列（field programmable gate array，FPGA）、數位訊號處理器、密碼處理器、微處理器或微控制器等，但並非僅限於此。亦即，所述積體電路可為邏輯晶片，例如類比至數位轉換器或應用專用積體電路（ASIC）等，或可為記憶體晶片，例如揮發性記憶體（比如DRAM）、非揮發性記憶體（比如ROM）或快閃記憶體等。另外，上述元件亦可彼此組合而設置。
半導體晶片120可以主動晶圓為基礎而形成。在此種情形中，本體的基材（base material）可為矽（Si）、鍺（Ge）或砷化鎵（GaAs）等。在本體上可形成各種電路。連接墊可將半導體晶片120電性連接至其他組件。半導體晶片的連接墊120P中的每一者的材料可為例如鋁（Al）等的導電材料。半導體晶片120可為裸晶粒（bare die），必要時可進一步在半導體晶片120的主動面上形成重佈線層（未繪示），並可將凸塊（未繪示）等連接至連接墊120P。
包封體130可保護第一連接構件110、半導體晶片120等。包封體130的包封形式不受特別限制，但可為包封體130環繞第一連接構件110的至少一部分、半導體晶片120的至少一部分等的形式。包封體130可填充貫穿孔110H的壁表面與半導體晶片120的側表面之間的空間，且因此充當黏合劑且減少半導體晶片120的彎曲（buckling）情況。根據本例示性實施例，包封體130可具有空腔C以暴露出半導體晶片120的非主動面（圖9中的上表面）。由於半導體晶片120的非主動面被暴露出，因此扇出型半導體封裝100的熱輻射效能可改善。此外，如下所述，空腔C用作用於半導體晶片、被動元件、熱輻射結構、真空等的區域，進而使得可有效地實施具有高積集程度的扇出型半導體封裝100。對於此種積體結構，黏合層160可設置於半導體晶片120的非主動面上。黏合層160的材料可為各種材料。舉例而言，可使用具有優異黏合效能的聚合物、雙面膠等。另外，為達成高效的佈局，空腔C的寬度可大於如圖9中所示半導體晶片的寬度。
包封體130的材料不受特別限制。舉例而言，可使用絕緣材料作為包封體130的材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維（或玻璃布，或玻璃纖維布）等的核心材料中的樹脂，例如預浸體、味之素構成膜（ABF）、FR-4或雙馬來醯亞胺三嗪（BT）等。或者，亦可使用感光成像介電（PID）樹脂作為所述絕緣材料。
第二連接構件140可對半導體晶片120的連接墊120P進行重新分佈。半導體晶片120的數十至數百萬個具有各種功能的連接墊120P可藉由第二連接構件140進行重新分佈，且可視功能而藉由電性連接結構170與外部進行物理連接或電性連接。為此，第二連接構件140可包括絕緣層141、重佈線層142及導電通孔143。然而，必要時，重佈線層142的數量、絕緣層的數量及通孔143的數量可有所改變。
可使用例如PID材料作為絕緣層141中所包括的絕緣材料。當絕緣層141具有感光性質時，絕緣層141可被形成為具有較小的厚度，且可更容易地達成通孔143的精密間距。絕緣層141可為包括絕緣樹脂及無機填料的感光絕緣層。當絕緣層141為多層時，絕緣層141的材料可為彼此相同，且必要時亦可為彼此不同。當絕緣層141為多層時，絕緣層121可視製程而彼此整合，進而使得各絕緣層之間的邊界亦可為不明顯。可形成較圖式中所示絕緣層的數量大的絕緣層。
重佈線層142可用於對半導體晶片120的連接墊120P進行重新分佈，且重佈線層142的材料可為導電材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。重佈線層142可視對應層的設計而執行各種功能。舉例而言，重佈線層142可包括接地圖案、訊號圖案等。此處，訊號圖案可包括除接地圖案、電源圖案等之外的各種訊號，例如資料訊號等。另外，重佈線層142可包括通孔接墊圖案、連接端子接墊圖案等。
通孔143可將形成於不同層上的重佈線層142或連接墊等彼此電性連接，從而在扇出型半導體封裝100中形成電性通路。通孔143中的每一者的材料可為導電材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。通孔143中的每一者可利用導電材料完全填充，或者導電材料亦可沿著通孔中的每一者的壁形成。另外，通孔143中的每一者可具有在相關技術中已知的所有形狀，例如錐形、圓柱形等。
鈍化層150可保護第二連接構件140免受外部物理性或化學性損傷等。鈍化層150可具有開口以暴露出第二連接構件140的重佈線層142的至少一部分。在鈍化層150中形成的開口之數量可為數十至數千個。鈍化層150的材料不受特定限制。舉例而言，可使用絕緣材料作為鈍化層150的材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維（或玻璃布，或玻璃纖維布）等的核心材料中的樹脂，例如預浸體、味之素構成膜（ABF）、FR-4或雙馬來醯亞胺三嗪（BT）等。或者，亦可使用阻焊劑（solder resist）。
電性連接結構170可在外部物理連接或電性連接扇出型半導體封裝100。舉例而言，扇出型半導體封裝100可藉由電性連接結構170安裝於電子裝置的主板上。電性連接結構170中的每一者可由例如焊料等的導電材料形成。然而，此僅為實例，而電性連接結構170中的每一者的材料並不特別限定於此。電性連接結構170中的每一者可為接腳（land）、球、引腳等。電性連接結構170可形成為多層結構或單層結構。當電性連接結構170形成為多層結構時，電性連接結構170可包括銅（Cu）柱及焊料。當電性連接結構170形成為單層結構時，電性連接結構170可包括錫-銀焊料或銅（Cu）。然而，此僅為實例，且電性連接結構170並非僅限於此。
電性連接結構170的數量、間隔、設置形式等不受特別限制，但可由熟習此項技術者視設計細節而定充分修改。舉例而言，電性連接結構170可根據連接墊的數量而設置為數十至數千的數量，亦或可設置為數十至數千或更多的數量或是數十至數千或更少的數量。當電性連接結構170為焊球時，電性連接結構170可覆蓋延伸至鈍化層150的一個表面上的側表面，而連接可靠性可更加優異。
電性連接結構170中的至少一者可設置於扇出區中。所述扇出區為半導體晶片120所設置的區域之外的區域。扇出型封裝具有的可靠性可高於扇入型封裝的可靠性，可實施多個I/O端子，且可輕易地執行三維內連線（3D interconnection）。另外，相較於球柵陣列（ball grid array，BGA）封裝或接腳柵陣列（land grid array，LGA）封裝等，扇出型封裝可被製造成具有較小的厚度，且可具有價格競爭力。
在下文中，將參照圖11至圖21闡述根據經修改實例的扇出型半導體封裝。將主要著墨於圍繞空腔C設置的元件等。
根據圖11的例示性實施例，扇出型半導體封裝可包括彼此平行地設置的第一半導體晶片120與第二半導體晶片121，且第一半導體晶片120的暴露出的非主動面上可設置有黏合層160且第二半導體晶片121的暴露出的非主動面上可設置有黏合層161。扇出型半導體封裝可實施於對多個半導體晶片120及121進行封裝的多晶片封裝中，藉此改善所述扇出型半導體封裝的效能。在此種情形中，必要時，半導體晶片120及121的數量可進一步增大。
圖12的例示性實施例示出將被動元件122設置成相鄰於半導體晶片120的結構。被動元件122可為電容器、電感器或電阻器等，且必要時亦可使用相同種類或其他種類的多個被動元件。被動元件122可被設置成相鄰於半導體晶片120，且被動元件122的上表面可以與半導體晶片120相同的方式藉由空腔C暴露出。然而，不同於半導體晶片120，黏合層160可不設置於被動元件122的暴露出的表面上。
接下來，圖13的例示性實施例示出將印刷電路板180設置於第一連接構件111上的結構。印刷電路板180可為覆蓋空腔的結構。作為實例，印刷電路板180可藉由電性連接結構171連接至第一連接構件111的配線層113及導電通孔112。印刷電路板180可為天線板或感測器板，且除此之外，亦可使用執行各種功能的板。另外，附加半導體晶片123可設置於印刷電路板180的下表面上以定位於包封體130的空腔中。如此一來，可藉由調整上面安裝有半導體晶片123的印刷電路板180的佈局方向來實施具有改善的空間效率的多晶片結構。因此，可使扇出型半導體封裝小型化且薄化，且扇出型半導體封裝中所包括的電性連接結構170中的每一者的間距可減小。同時，儘管圖13示出不將附加半導體晶片123接合至半導體晶片120的形式，然而亦可藉由黏合層160來形成將附加半導體晶片123與半導體晶片120彼此接合的結構。
圖14的例示性實施例示出將附加半導體晶片124設置於印刷電路板180的上表面（即，不指向空腔的表面）上的結構，且被動元件125設置於印刷電路板180的下表面上以定位於包封體130的空腔中。在此種情形中，如所示形式中一樣，多個被動元件125可形成及設置於空腔中，藉此改善空間效率。同時，儘管圖14示出不將被動元件125接合至半導體晶片120的形式，然而亦可藉由黏合層160來形成將被動元件125與半導體晶片120彼此接合的結構。
作為半導體晶片124的佈局的另一實例，如圖15的例示性實施例中一樣，附加半導體晶片124可嵌入印刷電路板182中。在此種情形中，被動元件125可設置於印刷電路板182的下表面上以定位於包封體130的空腔中。
接下來，圖16的例示性實施例示出對多個半導體晶片120及126進行層壓的堆疊結構。附加半導體晶片126可定位於半導體晶片120的非主動面上以定位於空腔中，且可藉由黏合層162來形成將附加半導體晶片126與半導體晶片120彼此接合的接合結構。在此種情形中，可對半導體層120及附加半導體層126中的每一者的非主動面施加黏合層162，且半導體晶片120與附加半導體晶片126可接著彼此接合。第三連接構件147可設置於第一連接構件111上以電性連接至附加半導體晶片126等，且可包括絕緣層144、配線層145及導電通孔146。在此種情形中，第三連接構件147可以與第二連接構件140相同的方式來實施。另外，第三連接構件147上可形成保護第三連接構件147的鈍化層151。
作為半導體晶片的堆疊結構的另一實例，圖17的例示性實施例示出可用於照相機模組等中的感測器封裝結構。附加半導體晶片127可為包括感測區127a的感測器封裝，且為使用半導體晶片120作為感測器封裝，半導體晶片120可為應用專用積體電路（ASIC）或記憶體等。如所示，附加半導體晶片127可藉由導電焊線W連接至配線層113。另外，由絕緣材料形成的模製部分152可被形成為對導電焊線W進行包封。在此種情形中，模製部分152的一部分可被移除以暴露出感測區127a。
作為另一實例，圖18的例示性實施例示出將多個半導體晶片128a及128b設置於空腔中的結構。在此種情形中，半導體晶片128a及128b中的每一者可藉由導電焊線W連接至配線層113，且模製部分152可對半導體晶片128a及128b以及導電焊線W進行包封。在此種情形中，模製部分152可填充包封體130的空腔的其餘區。
具有空腔的扇出型半導體封裝可應用於執行與以上所述功能不同的功能的元件。圖19的例示性實施例示出附加半導體晶片129是微機電系統（MEMS）元件的一種情形，且此種MEMS元件可為根據壓力變化來產生電性訊號的壓電封裝（piezoelectric package）等。黏合層160及半導體晶片120可被包封體130局部地覆蓋。另外，為使得MEMS元件能夠有效地運作，包封體130的空腔可處於真空狀態V。為實施真空區V，空腔中可設置密封層163。此種真空區V可充當用於傳統MEMS元件中的矽頂蓋（silicon cap）。另外，為穩定地安裝附加半導體晶片129，可使用黏合層164。不同於圖19的使用導電焊線W來實施電性連接結構的例示性實施例，電性連接結構亦可如圖20的例示性實施例中一樣直接彼此連接。詳言之，附加半導體晶片129可具有接墊P，接墊P被設置成指向空腔且可藉由電性連接結構172連接至配線層113等。
接下來，圖21的例示性實施例示出將熱輻射部分183而非半導體晶片或被動元件設置於空腔中以使熱輻射效應（heat radiation effect）最大化的結構。熱輻射部分183可形成於空腔中且接合至半導體晶片120，且可由例如銀（Ag）、鋁（Al）、銅（Cu）或鎳（Ni）等金屬或石墨烯等形成。為進一步改善熱輻射效應，熱輻射部分183可填充整個空腔，且可延伸至第一連接構件111的上部分以連接至配線層113。
在下文中，將參照圖22至圖25闡述基於形成空腔的方法來製造扇出型半導體封裝的製程的實例。
首先，可製備框架200，可形成貫穿孔H，且可形成第一連接構件111。儘管圖22僅示出第一連接構件111的絕緣層，然而第一連接構件111中亦可包括以上所述的配線層、導電通孔等。接下來，可將膠帶201貼附至第一連接構件111，且此是為設置半導體晶片等。
接下來，如圖23中所示，可設置犧牲層210且可接著在犧牲層210上設置半導體晶片120。在此種情形中，可藉由黏合層160將犧牲層210與半導體晶片120彼此接合。犧牲層210可為將在後續製程中被移除以形成空腔的區域，且可由例如銅（Cu）區塊等形成。在設置半導體晶片120之後，可形成包封體130且可接著移除膠帶201。
接下來，如圖24中所示，可形成能夠執行重佈線功能的第二連接構件。為此，可在包封體130中形成孔洞，且可形成導電通孔143以填充所述孔洞。另外，可藉由以下步驟獲得第二連接構件：形成重佈線層142及絕緣層141，且視需要接著重覆進行形成絕緣層141的孔洞的製程及填充導電通孔143的製程。
接下來，如圖25中所示，可形成鈍化層150且可接著移除犧牲層以在包封體130中形成空腔C。當移除犧牲層210時，可施加能夠對銅等進行選擇性蝕刻的蝕刻劑，且為在此種製程期間保護其他組件，可形成保護層202。
在本文中，下側、下部分、下表面等是用來指涉相對於圖式的橫截面的一個朝向扇出型半導體封裝之安裝表面的方向，而上側、上部分、上表面等是用來指涉與所述方向相反的一個方向。然而，定義這些方向是為了方便闡釋，且本申請專利範圍並不受上述定義之方向特別限制。
在說明中，組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及在兩個組件之間的直接連接。另外，「電性連接」意指包括物理連接及物理斷接的概念。可理解，當以「第一」及「第二」等用語來指代元件時，所述元件並不因此受到限制。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的，且可能並不限制所述元件的順序或重要性。在一些情形中，在不背離本文中所提出的申請專利範圍的範圍的條件下，第一元件可被稱作第二元件。相似地，第二元件亦可被稱作第一元件。
本文中所使用的用語「例示性實施例」並非指稱同一例示性實施例，而是為強調與另一例示性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而，本文中所提供的例示性實施例被視為能夠藉由彼此整體組合或部分組合而實施。舉例而言，即使並未在另一例示性實施例中闡述在特定例示性實施例中闡述的一個元件，除非在另一例示性實施例中提供了相反或矛盾的說明，否則所述元件亦可被理解為與另一例示性實施例相關的說明。
使用本文中所使用的用語僅為了闡述例示性實施例而非限制本揭露。在此種情形中，除非在上下文中另有解釋，否則單數形式包括多數形式。
如上所述，根據本揭露中的例示性實施例，扇出型半導體封裝可被薄化且高度積體。
儘管以上已示出及闡述例示性實施例，然而對於熟習此項技術者而言應顯而易見，在不背離如由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出潤飾及變動。
100、2100‧‧‧半導體封裝
110H、H‧‧‧貫穿孔
111‧‧‧第一連接構件
112、143、146‧‧‧通孔
113、145‧‧‧配線層
120P、2122、2222‧‧‧連接墊
122、125‧‧‧被動元件
120、121、123、124、126、127、128a、128b、129、2120、2220‧‧‧半導體晶片
127a‧‧‧感測區
130、2130‧‧‧包封體
131‧‧‧上外表面
132‧‧‧中間內表面
140‧‧‧第二連接構件
141、144、2141、2241‧‧‧絕緣層
142、2142‧‧‧重佈線層
147‧‧‧第三連接構件
150、151、2150、2223、2250‧‧‧鈍化層
152‧‧‧模製部分
160、161、162、164‧‧‧黏合層
163‧‧‧密封層
170、171、172‧‧‧電性連接結構
180、182‧‧‧印刷電路板
183‧‧‧熱輻射部分
200‧‧‧框架
201‧‧‧膠帶
202‧‧‧保護層
210‧‧‧犧牲層
1000‧‧‧電子裝置
1010、2500‧‧‧主板
1020‧‧‧晶片相關組件
1030‧‧‧網路相關組件
1040‧‧‧其他組件
1050、1130‧‧‧照相機
1060‧‧‧天線
1070‧‧‧顯示器裝置
1080‧‧‧電池
1090‧‧‧訊號線
1100‧‧‧智慧型電話
1101、2121、2221‧‧‧本體
1110‧‧‧母板
1120‧‧‧組件
2140、2240‧‧‧連接構件
2143、2243‧‧‧通孔
2160、2260‧‧‧凸塊下金屬層
2170、2270‧‧‧焊球
2200‧‧‧扇入型半導體封裝
2242‧‧‧配線圖案
2243h‧‧‧通孔孔洞
2251‧‧‧開口
2280‧‧‧底部填充樹脂
2290‧‧‧模製材料
2301、2302‧‧‧中介基板
C‧‧‧空腔
P‧‧‧接墊
S‧‧‧台階
V‧‧‧真空狀態
V‧‧‧真空區
W‧‧‧導電焊線
藉由結合所附圖式閱讀以下詳細說明，將更清楚地理解本揭露的上述及其他樣態、特徵及其他優點，在所附圖式中： 圖1為示出電子裝置系統的實例的方塊示意圖。 圖2為示出電子裝置的實例的立體示意圖。 圖3A及圖3B為示出扇入型半導體封裝在封裝前及封裝後狀態的剖面示意圖。 圖4為示出扇入型半導體封裝的封裝製程的剖面示意圖。 圖5為示出扇入型半導體封裝安裝於中介基板（interposer substrate）上且最終安裝於電子裝置的主板上之情形的剖面示意圖。 圖6為示出扇入型半導體封裝嵌入中介基板中且最終安裝於電子裝置的主板上之情形的剖面示意圖。 圖7為示出扇出型半導體封裝的剖面示意圖。 圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的剖面示意圖。 圖9為示出扇出型半導體封裝的實例的剖面示意圖。 圖10示出圖9的扇出型半導體封裝的經修改實例。 圖11至圖21示意性地示出根據經修改實例中的每一者的扇出型半導體封裝。 圖22至圖25示出製造扇出型半導體封裝的製程的實例。

Claims (20)

  1. 一種扇出型半導體封裝，包括： 第一連接構件，具有貫穿孔； 第一半導體晶片，設置於所述貫穿孔中且包括主動面及與所述主動面相對的非主動面，所述主動面上設置有連接墊； 第二連接構件，設置於所述半導體晶片的所述主動面上且包括電性連接至所述第一半導體晶片的重佈線層；以及 包封體，對所述第一半導體晶片進行包封且具有設置於所述半導體晶片的所述非主動面上方的空腔。
  2. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 黏合層，設置於所述第一半導體晶片的所述非主動層上。
  3. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述空腔具有的寬度大於所述第一半導體晶片的寬度。
  4. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 第二半導體晶片，與所述第一半導體晶片並排地設置於所述貫穿孔中。
  5. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 被動元件，被設置成相鄰於所述第一半導體晶片且具有藉由所述空腔而暴露出的上表面。
  6. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 印刷電路板，設置於所述第一連接構件上以覆蓋所述空腔。
  7. 如申請專利範圍第6項所述的扇出型半導體封裝，更包括： 附加半導體晶片，設置於所述印刷電路板的下表面上且定位於所述空腔中。
  8. 如申請專利範圍第6項所述的扇出型半導體封裝，更包括： 附加半導體晶片，設置於所述印刷電路板的上表面上。
  9. 如申請專利範圍第8項所述的扇出型半導體封裝，更包括： 被動元件，設置於所述印刷電路板的下表面上且定位於所述空腔中。
  10. 如申請專利範圍第6項所述的扇出型半導體封裝，更包括： 附加半導體晶片，嵌入所述印刷電路板中。
  11. 如申請專利範圍第10項所述的扇出型半導體封裝，更包括： 被動元件，設置於所述印刷電路板的下表面上且定位於所述空腔中。
  12. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述印刷電路板是天線或感測器板。
  13. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 附加半導體晶片，設置於所述第一半導體晶片的所述非主動面上且定位於所述空腔中。
  14. 如申請專利範圍第13項所述的扇出型半導體封裝，更包括： 第三連接構件，設置於所述第一連接構件上且電性連接至所述附加半導體晶片。
  15. 如申請專利範圍第13項所述的扇出型半導體封裝，更包括： 導電焊線，連接至所述附加半導體晶片；以及 模製部分，對所述導電焊線進行包封。
  16. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 附加半導體晶片，設置於所述第一連接構件上且定位於所述空腔上；以及 模製部分，對所述附加半導體晶片進行包封。
  17. 如申請專利範圍第16項所述的扇出型半導體封裝，其中所述附加半導體晶片是微機電系統（MEMS）元件，且 所述空腔處於真空狀態。
  18. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 熱輻射部分，設置於所述空腔中且接合至所述第一半導體晶片。
  19. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述包封體未覆蓋所述半導體晶片的所述非主動面。
  20. 一種扇出型半導體封裝，包括： 第一連接構件，具有貫穿孔； 半導體晶片，設置於所述貫穿孔中且包括主動面及與所述主動面相對的非主動面，所述主動面上設置有連接墊； 第二連接構件，設置於所述半導體晶片的所述主動面上且包括電性連接至所述半導體晶片的重佈線層； 黏合層，設置於所述半導體晶片的所述非主動面上；以及 包封體，對所述第一半導體晶片的側表面進行包封，且所述包封體所具有的上表面具有相對於所述黏合層的台階。
TW107119317A 2017-11-29 2018-06-05 扇出型半導體封裝 TWI676247B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2017-0162144 2017-11-29
KR1020170162144A KR102073956B1 (ko) 2017-11-29 2017-11-29 팬-아웃 반도체 패키지
??10-2017-0162144 2017-11-29

Publications (2)

Publication Number Publication Date
TW201926602A true TW201926602A (zh) 2019-07-01
TWI676247B TWI676247B (zh) 2019-11-01

Family

ID=66633560

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107119317A TWI676247B (zh) 2017-11-29 2018-06-05 扇出型半導體封裝

Country Status (3)

Country Link
US (1) US10832986B2 (zh)
KR (1) KR102073956B1 (zh)
TW (1) TWI676247B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI727469B (zh) * 2019-07-31 2021-05-11 台灣積體電路製造股份有限公司 封裝體及其形成方法
TWI767521B (zh) * 2020-03-19 2022-06-11 日商鎧俠股份有限公司 半導體裝置、檢查用元件及檢查裝置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102586794B1 (ko) * 2018-06-08 2023-10-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20200211980A1 (en) * 2018-12-27 2020-07-02 Powertech Technology Inc. Fan-out package with warpage reduction and manufacturing method thereof
KR20210104364A (ko) 2020-02-17 2021-08-25 삼성전자주식회사 반도체 패키지
CN113035813B (zh) * 2021-03-02 2022-07-19 华进半导体封装先导技术研发中心有限公司 一种芯片封装结构及芯片封装方法
KR20220164946A (ko) * 2021-06-07 2022-12-14 삼성전자주식회사 반도체 패키지

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745897B2 (en) 2005-05-27 2010-06-29 Aptina Imaging Corporation Methods for packaging an image sensor and a packaged image sensor
KR20080038719A (ko) * 2006-10-31 2008-05-07 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR101486420B1 (ko) 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
JP5588137B2 (ja) * 2009-09-14 2014-09-10 新光電気工業株式会社 半導体装置の製造方法
US20110175218A1 (en) * 2010-01-18 2011-07-21 Shiann-Ming Liou Package assembly having a semiconductor substrate
KR101261482B1 (ko) * 2011-08-03 2013-05-10 하나 마이크론(주) 반도체 적층 패키지 및 이를 제조하는 제조 방법
US8866287B2 (en) 2012-09-29 2014-10-21 Intel Corporation Embedded structures for package-on-package architecture
US9082743B2 (en) 2013-08-02 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packages with heat dissipation structures
US9584889B2 (en) * 2013-08-27 2017-02-28 Infineon Technologies Ag System and method for packaged MEMS device having embedding arrangement, MEMS die, and grille
US9252135B2 (en) 2014-02-13 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9754897B2 (en) * 2014-06-02 2017-09-05 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits
US10453785B2 (en) * 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
CN107039369A (zh) * 2015-01-23 2017-08-11 三星半导体(中国)研究开发有限公司 封装、包括该封装的封装堆叠结构及其制造方法
CN104868872A (zh) 2015-04-21 2015-08-26 江苏长电科技股份有限公司 声表面波滤波器封装结构
KR20170043427A (ko) * 2015-10-13 2017-04-21 삼성전기주식회사 전자부품 패키지 및 그 제조방법
US10566289B2 (en) 2015-10-13 2020-02-18 Samsung Electronics Co., Ltd. Fan-out semiconductor package and manufacturing method thereof
KR101944007B1 (ko) * 2015-12-16 2019-01-31 주식회사 네패스 반도체 패키지 및 그 제조방법
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI727469B (zh) * 2019-07-31 2021-05-11 台灣積體電路製造股份有限公司 封裝體及其形成方法
US11251099B2 (en) 2019-07-31 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of packages using embedded core frame
US11984374B2 (en) 2019-07-31 2024-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of packages using embedded core frame
TWI767521B (zh) * 2020-03-19 2022-06-11 日商鎧俠股份有限公司 半導體裝置、檢查用元件及檢查裝置

Also Published As

Publication number Publication date
US20190164863A1 (en) 2019-05-30
US10832986B2 (en) 2020-11-10
TWI676247B (zh) 2019-11-01
KR20190063219A (ko) 2019-06-07
KR102073956B1 (ko) 2020-02-05

Similar Documents

Publication Publication Date Title
US10886192B2 (en) Semiconductor package
TWI684255B (zh) 扇出型半導體封裝
TWI689069B (zh) 扇出型半導體封裝
TWI651821B (zh) 扇出型半導體封裝
TWI645526B (zh) 扇出型半導體裝置
TWI651818B (zh) 扇出型半導體封裝
TWI676247B (zh) 扇出型半導體封裝
TWI689073B (zh) 扇出型半導體封裝
TWI702704B (zh) 扇出型半導體封裝
TW201917839A (zh) 扇出型半導體封裝
TW201917831A (zh) 扇出型半導體封裝
TW201926587A (zh) 扇出型半導體封裝
US20190189589A1 (en) Fan-out semiconductor package
US20190139920A1 (en) Fan-out semiconductor package
TW201921619A (zh) 扇出型半導體封裝
TWI707411B (zh) 半導體封裝的連接系統
TWI684251B (zh) 扇出型感測器封裝
TW201929107A (zh) 半導體封裝及堆疊型被動組件模組
US10541221B2 (en) Fan-out semiconductor package
TW201937672A (zh) 扇出型半導體封裝
TW201926604A (zh) 扇出型半導體封裝
TW201926593A (zh) 扇出型半導體封裝
TW201816902A (zh) 扇出型半導體封裝以及製造扇出型半導體封裝的方法
TW202042357A (zh) 半導體封裝
TW201929183A (zh) 扇出型半導體封裝