TWI689073B - 扇出型半導體封裝 - Google Patents

扇出型半導體封裝 Download PDF

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TWI689073B
TWI689073B TW107118372A TW107118372A TWI689073B TW I689073 B TWI689073 B TW I689073B TW 107118372 A TW107118372 A TW 107118372A TW 107118372 A TW107118372 A TW 107118372A TW I689073 B TWI689073 B TW I689073B
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Taiwan
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layer
fan
semiconductor package
metal bump
item
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TW107118372A
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English (en)
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TW201919184A (zh
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李楨日
李政昊
金鎭洙
趙俸紸
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南韓商三星電子股份有限公司
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Abstract

一種扇出型半導體封裝包括：框架，包括絕緣層、配線層及連接通孔層，且具有凹陷部分，所述凹陷部分具有終止元件層；半導體晶片，具有連接墊且設置於凹陷部分中，以使非主動面連接至終止元件層；第一金屬凸塊，設置於連接墊上；第二金屬凸塊，設置於配線層中的最上層側配線層上；包封體，覆蓋框架、半導體晶片及第一金屬凸塊及第二金屬凸塊中的每一者的至少一部分且填充凹陷部分的至少一部分；以及連接構件，設置於框架上及半導體晶片的主動面上，且包括藉由第一金屬凸塊及第二金屬凸塊電性連接至連接墊及最上層配線層的重佈線層。

Description

扇出型半導體封裝
本揭露是有關於一種半導體封裝，且更具體而言，有關於一種電性連接結構可朝向半導體晶片所設置的區域之外延伸的扇出型半導體封裝。
[相關申請案的交叉參照]
本申請案主張2017年11月3日在韓國智慧財產局中申請的韓國專利申請案第10-2017-0146195號的優先權的權益，所述韓國專利申請案的揭露內容以全文引用的方式併入本文中。
半導體晶片相關技術發展中的重要近期趨勢為縮小半導體晶片的尺寸。因此，在封裝技術領域中，隨著對小型尺寸半導體晶片等的需求快速增加，亟需實施包括多個引腳(pin)的小型尺寸(compact size)半導體封裝。
扇出型半導體封裝即一種為滿足上述技術需求而提出的半導體封裝技術。此種扇出型封裝具有小型尺寸，並可容許藉由朝半導體晶片所設置的區域之外對連接端子進行重新分佈而實施多個引腳。
本揭露的態樣可提供一種扇出型半導體封裝，在所述扇出型半導體封裝中設置有包括盲凹陷部分(blind recess portion)的框架且半導體晶片設置於所述凹陷部分中，且因此儘管使用研磨製程(grinding process)，仍可解決例如銅(Cu)毛邊(copper burring)等問題。
根據本揭露的態樣，可提供一種扇出型半導體封裝，在所述扇出型半導體封裝中設置有具有藉由終止元件層(stopper layer)而形成的盲凹陷部分的框架，半導體晶片設置於所述凹陷部分中，且所述框架的配線層上及所述半導體晶片的連接墊上設置有金屬凸塊。
根據本揭露的態樣，一種扇出型半導體封裝可包括：框架，包括多個絕緣層、設置於所述多個絕緣層上的多個配線層及貫穿所述多個絕緣層且將所述多個配線層彼此電性連接的多個連接通孔層，且具有凹陷部分，所述凹陷部分的底表面上設置有終止元件層；半導體晶片，具有連接墊、主動面及與所述主動面相對的非主動面且設置於所述凹陷部分中，以使所述非主動面連接至所述終止元件層，所述主動面上設置有所述連接墊；第一金屬凸塊，設置於所述半導體晶片的所述連接墊上；第二金屬凸塊，設置於所述多個配線層中的最上層配線層上；包封體，覆蓋所述框架、所述半導體晶片及所述第一金屬凸塊及所述第二金屬凸塊 中的每一者的至少一部分且填充所述凹陷部分的至少一部分；以及連接構件，設置於所述框架上及所述半導體晶片的所述主動面上，且包括藉由所述第一金屬凸塊及所述第二金屬凸塊電性連接至所述連接墊及所述最上層配線層的重佈線層。
100、2100:扇出型半導體封裝
110、110’:框架
110H:凹陷部分
111a、111b、111c、141a、141b、141c、201、2141、2241:絕緣層
112a、112b、112c、112d、112d’:配線層
112aM:終止元件層
112B、120B:金屬凸塊
113a、113b、113c:連接通孔層
120、120’、2120、2220:半導體晶片
120B’:銅柱
120P、120P’、2122、2222:連接墊
125:黏合構件
130、2130:包封體
140、2140、2240:連接構件
142a、142b、142c、2142:重佈線層
143a1、143a2、143b、143c:連接通孔
151:第一鈍化層
152:第二鈍化層
160、2160、2260:凸塊下金屬層
170:電性連接結構
200:載體膜
202:金屬層
250:乾膜
1000:電子裝置
1010、1110、2500:主板
1020:晶片相關組件
1030:網路相關組件
1040:其他組件
1050、1130:照相機模組
1060:天線
1070:顯示器裝置
1080:電池
1090:訊號線
1100:智慧型電話
1101、2121、2221:本體
1120:電子組件
1121:半導體封裝
2143、2243:通孔
2150、2223、2250:鈍化層
2170、2270:焊球
2200:扇入型半導體封裝
2242:配線圖案
2243h:通孔孔洞
2251:開口
2280:底部填充樹脂
2290:模製材料
2301、2302:BGA基板
I-I’:線
藉由結合所附圖式閱讀以下詳細說明，將更清楚地理解本揭露的上述及其他樣態、特徵及優點，在附圖中：圖1為示出電子裝置系統的實例的方塊示意圖。
圖2為示出電子裝置的實例的立體示意圖。
圖3A及圖3B為示出扇入型半導體封裝在封裝前及封裝後狀態的剖面示意圖。
圖4為示出扇入型半導體封裝的封裝製程的剖面示意圖。
圖5為示出扇入型半導體封裝安裝於球柵陣列(ball grid array，BGA)基板上且最終安裝於電子裝置的主板上之情形的剖面示意圖。
圖6為示出扇入型半導體封裝嵌入BGA基板中且最終安裝於電子裝置的主板上之情形的剖面示意圖。
圖7為示出扇出型半導體封裝的剖面示意圖。
圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的剖面示意圖。
圖9為示出扇出型半導體封裝的實例的剖面示意圖。
圖10為沿圖9的扇出型半導體封裝的線I-I’所截取的平面示 意圖。
圖11至圖15為示出製造圖9的扇出型半導體封裝的製程的示意圖。
圖16為示出當不形成金屬凸塊時的研磨製程的剖面示意圖。
圖17為示出因圖16的研磨製程而產生的銅毛邊的平面示意圖。
在下文中，將參照所附圖式闡述本揭露中的各例示性實施例。在所附圖式中，為清晰起見，可誇大或縮小各組件的形狀、尺寸等。
在本文中，下側、下部分、下表面等是用來指涉相對於圖式的橫截面的一個朝向扇出型半導體封裝之安裝表面的方向，而上側、上部分、上表面等是用來指涉與所述方向相反的一個方向。然而，定義該些方向是為了方便闡釋，且本申請專利範圍並不受上述定義之方向特別限制。
在說明中，組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及在兩個組件之間的直接連接。另外，「電性連接」的概念包括物理連接及物理斷接。可理解，當以例如「第一」及「第二」等用語來指代元件時，所述元件並不因此受到限制。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的，且可能並不限制所述元件的順序或重要性。在一 些情形中，在不背離本文中所提出的申請專利範圍的範圍的條件下，第一元件可被稱作第二元件。相似地，第二元件亦可被稱作第一元件。
本文中所使用的用語「例示性實施例」並非指稱同一例示性實施例，而是為強調與另一例示性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而，本文中所提供的例示性實施例被視為能夠藉由彼此整體組合或部分組合而實施。舉例而言，即使並未在另一例示性實施例中闡述在特定例示性實施例中闡述的一個元件，除非在另一例示性實施例中提供了相反或矛盾的說明，否則所述元件亦可被理解為與另一例示性實施例相關的說明。
使用本文中所使用的用語僅為了闡述例示性實施例而非限制本揭露。在此種情形中，除非在上下文中另有解釋，否則單數形式包括多數形式。
電子裝置
圖1為示出電子裝置系統的實例的方塊示意圖。
參照圖1，電子裝置1000中可容置主板1010。主板1010可包括物理連接或電性連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件以形成各種訊號線1090。
晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory，DRAM))、非揮發性記憶體(例如唯讀記憶體(read only memory，ROM))或快閃記憶體等；應用處理器晶片，例如中央處理器(例如中央處理單元(central processing unit，CPU))、圖形處理器(例如圖形處理單元(graphics processing unit，GPU))、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器或微控制器等；以及邏輯晶片，例如類比至數位轉換器(analog-to-digital converter，ADC)或應用專用積體電路(application-specific integrated circuit，ASIC)等。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。
網路相關組件1030可包括例如以下協定：無線保真(wireless fidelity，Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers，IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access，WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution，LTE)、僅支援資料的演進(evolution data only，Ev-DO)、高速封包存取+(high speed packet access +，HSPA+)、高速下行封包存取+(high speed downlink packet access +，HSDPA+)、高速上行封包存取+(high speed uplink packet access +，HSUPA+)、增強型資料GSM環境(enhanced data GSM environment，EDGE)、全球行動通訊系統(global system for mobile communications，GSM)、全球定位系統(global positioning system，GPS)、通用封 包無線電服務(general packet radio service，GPRS)、分碼多重存取(code division multiple access，CDMA)、分時多重存取(time division multiple access，TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications，DECT)、藍芽、3G協定、4G協定及5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括多種其他無線標準或協定或者有線標準或協定。另外，網路相關組件1030可與以上所述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器(power inductor)、鐵氧體珠粒(ferrite beads)、低溫共燒陶瓷(low temperature co-fired ceramic，LTCC)、電磁干擾(electromagnetic interference，EMI)濾波器或多層陶瓷電容器(multilayer ceramic capacitor，MLCC)等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動組件等。另外，其他組件1040可與以上所述的晶片相關組件1020或網路相關組件1030一起彼此組合。
視電子裝置1000的類型而定，電子裝置1000可包括可物理連接至或電性連接至主板1010的其他組件，或可不物理連接至或不電性連接至主板1010的其他組件。該些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器(未繪示)、視訊編解碼器(未繪示)、功率放大器(未繪示)、羅盤(未繪示)、加速度計(未繪示)、陀螺儀(未繪 示)、揚聲器(未繪示)、大容量儲存單元(例如硬碟驅動機)(未繪示)、光碟(compact disk，CD)驅動機(未繪示)、數位多功能光碟(digital versatile disk，DVD)驅動機(未繪示)等。然而，該些其他組件並非僅限於此，而是視電子裝置1000的類型等而定亦可包括各種用途的其他組件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant，PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(tablet PC)、筆記型PC(laptop PC)、隨身型易網機PC(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶或汽車組件等。然而，電子裝置1000並非僅限於此，而是亦可為處理資料的任何其他電子裝置。
圖2為示出電子裝置的實例的立體示意圖。
參照圖2，半導體封裝可於如上所述的各種電子裝置1000中使用於各種目的。舉例而言，主板1110可容置於智慧型電話1100的本體1101中，且各種電子組件1120可物理連接至或電性連接至主板1110。另外，可物理連接至或電性連接至主板1110或可不物理連接至或不電性連接至主板1110的其他組件(例如照相機模組1130)可容置於本體1101中。電子組件1120中的一些電子組件可為晶片相關組件，例如半導體封裝1121，但並非僅限於此。所述電子裝置不必僅限於智慧型電話1100，而是可為如上所述的其他電子裝置。
半導體封裝
一般而言，半導體晶片中整合了諸多精密的電路。然而，半導體晶片自身不能充當已完成的半導體產品，且可能因外部物理性或化學性影響而受損。因此，半導體晶片無法單獨使用，但可封裝於電子裝置等中且在電子裝置等中以封裝狀態使用。
此處，由於半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異，因而需要半導體封裝。詳言之，半導體晶片的連接墊的尺寸及半導體晶片的連接墊之間的間隔極為精密，但電子裝置中所使用的主板的組件安裝墊的尺寸及主板的組件安裝墊之間的間隔顯著大於半導體晶片的連接墊的大小及間隔。因此，可能難以將半導體晶片直接安裝於主板上，而需要用於緩衝半導體晶片與主板之間的電路寬度差異的封裝技術。
視半導體封裝的結構及目的而定，由封裝技術製造的半導體封裝可分類為扇入型半導體封裝或扇出型半導體封裝。
在下文中，將參照圖式更詳細地闡述扇入型半導體封裝及扇出型半導體封裝。
扇入型半導體封裝
圖3A及圖3B為示出扇入型半導體封裝在封裝前及封裝後狀態的剖面示意圖。
圖4為示出扇入型半導體封裝的封裝製程的剖面示意圖。
參照圖3A、圖3B及圖4，半導體晶片2220可例如是處 於裸露狀態下的積體電路(integrated circuit，IC)，半導體晶片2220包括：本體2221，包括矽(Si)、鍺(Ge)或砷化鎵(GaAs)等；連接墊2222，形成於本體2221的一個表面上且包括例如鋁(Al)等導電材料；以及鈍化層2223，其例如是氧化物膜、氮化物膜等，且形成於本體2221的一個表面上且覆蓋連接墊2222的至少一部分。在此種情形中，由於連接墊2222在尺寸上可能為顯著小的，因此可能難以將積體電路(IC)安裝於中級印刷電路板(printed circuit board，PCB)上以及電子裝置的主板等上。
因此，可視半導體晶片2220的尺寸而定，在半導體晶片2220上形成連接構件2240以對連接墊2222進行重新分佈。連接構件2240可藉由以下步驟來形成：利用例如感光成像介電(photoimagable dielectric，PID)樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241，形成外露連接墊2222的通孔孔洞2243h，並接著形成配線圖案2242及通孔2243。接著，可形成保護連接構件2240的鈍化層2250，可形成開口2251，並可形成凸塊下金屬層2260等。亦即，可藉由一系列製程來製造包括例如半導體晶片2220、連接構件2240、鈍化層2250及凸塊下金屬層2260的扇入型半導體封裝2200。
如上所述，扇入型半導體封裝可具有半導體晶片的所有連接墊(例如輸入/輸出(input/output，I/O)端子)均設置於半導體晶片內的一種封裝形式，且可具有優異的電性特性並可利用低成本進行生產。因此，諸多安裝於智慧型電話中的元件已以扇入 型半導體封裝的形式製造而出。詳言之，已開發出諸多安裝於智慧型電話中的元件以實施快速的訊號傳送並同時具有小型尺寸。
然而，由於在扇入型半導體封裝中所有I/O端子皆需要設置於半導體晶片內，因此扇入型半導體封裝的空間限制顯著。因此，難以將此種結構應用於具有大量I/O端子的半導體晶片或具有小型尺寸的半導體晶片。另外，由於以上所述的缺點，扇入型半導體封裝無法在電子裝置的主板上直接安裝並使用。原因在於，即使藉由重佈線製程增大半導體晶片的I/O端子的尺寸及半導體晶片的各I/O端子之間的間隔，半導體晶片的I/O端子的尺寸及半導體晶片的各I/O端子之間的間隔仍不足以讓扇入型半導體封裝直接安裝於電子裝置的主板上。
圖5為示出扇入型半導體封裝安裝於球柵陣列(BGA)基板上且最終安裝於電子裝置的主板上之情形的剖面示意圖。
圖6為示出扇入型半導體封裝嵌入BGA基板中且最終安裝於電子裝置的主板上之情形的剖面示意圖。
參照圖5及圖6，在扇入型半導體封裝2200中，半導體晶片2220的連接墊2222(即，I/O端子)可經由BGA基板2301進行重新分佈，且扇入型半導體封裝2200可在其安裝於BGA基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此種情形中，可藉由底部填充樹脂2280等來固定焊球2270等，且半導體晶片2220的外側可被模製材料2290等覆蓋。或者，扇入型半導體封裝2200可嵌入單獨的BGA基板2302中，半導體晶片 2220的連接墊2222(即，I/O端子)可在扇入型半導體封裝2200嵌入BGA基板2302中的狀態下，由BGA基板2302進行重新分佈，且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。
如上所述，可能難以在電子裝置的主板上直接安裝並使用扇入型半導體封裝。因此，扇入型半導體封裝可安裝於單獨的BGA基板上，並接著藉由封裝製程安裝於電子裝置的主板上，或者扇入型半導體封裝可在扇入型半導體封裝嵌入BGA基板中的狀態下在電子裝置的主板上安裝並使用。
扇出型半導體封裝
圖7為示出扇出型半導體封裝的剖面示意圖。
參照圖7，在扇出型半導體封裝2100中，舉例而言，半導體晶片2120的外側可由包封體2130保護，且半導體晶片2120的連接墊2122可藉由連接構件2140而朝半導體晶片2120之外進行重新分佈。在此種情形中，在連接構件2140上可進一步形成鈍化層2150，且在鈍化層2150的開口中可進一步形成凸塊下金屬層2160。在凸塊下金屬層2160上可進一步形成焊球2170。半導體晶片2120可為包括本體2121、連接墊2122、鈍化層(未繪示)等的積體電路(IC)。連接構件2140可包括絕緣層2141、形成於絕緣層2141上的重佈線層2142以及將連接墊2122與重佈線層2142彼此電性連接的通孔2143。
如上所述，扇出型半導體封裝可具有一種形式，其中半 導體晶片的I/O端子藉由形成於半導體晶片上的連接構件而朝半導體晶片之外進行重新分佈並朝半導體晶片之外進行設置。如上所述，在扇入型半導體封裝中，半導體晶片的所有I/O端子皆需要設置於半導體晶片內。因此，當半導體晶片的尺寸減小時，須減小球的尺寸及間距，進而使得標準化球佈局(standardized ball layout)無法在扇入型半導體封裝中使用。另一方面，扇出型半導體封裝具有一種形式，其中半導體晶片的I/O端子藉由形成於半導體晶片上的連接構件而朝半導體晶片之外進行重新分佈並朝半導體晶片之外進行設置，如上所述。因此，即使在半導體晶片的尺寸減小的情形中，標準化球佈局亦可照樣用於扇出型半導體封裝中，進而使得扇出型半導體封裝無須使用單獨的BGA基板即可安裝於電子裝置的主板上，如下所述。
圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的剖面示意圖。
參照圖8，扇出型半導體封裝2100可經由焊球2170等安裝於電子裝置的主板2500上。亦即，如上所述，扇出型半導體封裝2100包括連接構件2140，連接構件2140形成於半導體晶片2120上且能夠將連接墊2122重新分佈至半導體晶片2120的尺寸之外的扇出區，進而使得標準化球佈局可照樣用於扇出型半導體封裝2100中。因此，扇出型半導體封裝2100無須使用單獨的BGA基板等即可安裝於電子裝置的主板2500上。
如上所述，由於扇出型半導體封裝無須使用單獨的BGA 基板即可安裝於電子裝置的主板上，因此扇出型半導體封裝可在厚度小於使用BGA基板的扇入型半導體封裝的厚度的情況下實施。因此，可使扇出型半導體封裝小型化且薄化。另外，扇出型半導體封裝具有優異的熱特性及電性特性，進而使得扇出型半導體封裝尤其適宜用於行動產品。因此，扇出型半導體封裝可被實施成較使用印刷電路板(PCB)的一般疊層封裝(package-on-package，POP)類型更小型的形式，且可解決因翹曲(warpage)現象出現而產生的問題。
同時，扇出型半導體封裝意指一種封裝技術，如上所述用於將半導體晶片安裝於電子裝置的主板等上且保護半導體晶片免受外部影響，且其與例如BGA基板等的印刷電路板(PCB)在概念上是不同的，印刷電路板具有與扇出型半導體封裝的規格、目的不同的規格、目的等，且有扇入型半導體封裝嵌入其中。
在下文中，將參照圖式闡述設置有具有藉由終止元件層而形成的盲凹陷部分的框架的一種扇出型半導體封裝。
圖9為示出扇出型半導體封裝的實例的剖面示意圖。
圖10為沿圖9的扇出型半導體封裝的線I-I’所截取的平面示意圖。
參照圖9及圖10，根據本揭露中的例示性實施例的扇出型半導體封裝100可包括：框架110，具有凹陷部分110H，凹陷部分110H具有被終止元件層112aM覆蓋的第一表面以及與所述第一表面相對的第二表面為敞露的盲形式(blind form)；半導體晶 片120，具有主動面及與所述主動面相對的非主動面且設置於凹陷部分110H中以使所述非主動面貼附至終止元件層112aM，所述主動面上設置有連接墊120P；包封體130，包封框架110及半導體晶片120中的每一者的至少一部分且填充凹陷部分110H的至少一部分；以及連接構件140，設置於框架110、包封體130以及半導體晶片120的主動面上。另外，根據例示性實施例的扇出型半導體封裝100可更包括：第一鈍化層151，設置於連接構件140上且具有暴露出連接構件140的重佈線層142c的至少一部分的開口；第二鈍化層152，設置於框架110上且具有暴露出框架110的配線層112c的至少一部分的開口；凸塊下金屬層160，設置於第一鈍化層151的開口中且電性連接至暴露出的重佈線層142c；以及電性連接結構170，設置於凸塊下金屬層160上且必要時經由凸塊下金屬層160電性連接至暴露出的重佈線層142c。
同時，框架110可包括經由連接通孔層113a、113b及113c彼此電性連接的配線層112a、112b、112c及112d，連接構件140可包括經由連接通孔143a1、143a2、143b及143c彼此電性連接的重佈線層142a、142b及142c，且半導體晶片120的連接墊120P可電性連接至配線層112a、112b、112c及112d以及重佈線層142a、142b及142c。在此種情形中，重佈線層142a可經由例如銅(Cu)柱(copper post)等金屬凸塊120B及112B分別電性連接至連接墊120P及配線層112d。更詳言之，重佈線層142a可經由連接通孔143a1及143a2以及分別連接至連接通孔143a1及 143a2的金屬凸塊120B及112B而電性連接至連接墊120P及配線層112d。
同時，當設置有具有呈盲形式的凹陷部分的框架且半導體晶片設置於所述凹陷部分中並接著被包封時，一般提前在所述半導體晶片的連接墊上形成銅柱等，並執行研磨製程以形成用於形成連接構件的平坦表面。在此種情形中，如圖16中所示，當不向框架110’中引入單獨的金屬凸塊時，執行研磨製程以使框架110’的配線層112d’的表面及形成於半導體晶片120’的連接墊120P’上的銅柱120B’暴露出。然而，由於配線層112d’的表面具有較銅柱120B’的表面的表面積大的表面積，因此在研磨製程中構成配線層112d’的銅(Cu)可能將蔓延。因此，如圖17中所示，銅(Cu)殘留物可能變成異物且黏著至研磨輪，從而使加工性(processability)降低。另外，在此種製程中產生的銅毛邊可能產生所未預期的電性短路。
另一方面，在根據例示性實施例的扇出型半導體封裝100中，金屬凸塊120B可形成於連接墊120P上，且金屬凸塊112B亦可形成於框架110的配線層112d上。金屬凸塊120B及112B可為具有矩形橫截面形狀的銅柱。在此種情形中，如自以下將闡述的製程看出，在研磨製程中金屬凸塊120B及112B的表面可被暴露出，且在研磨製程中配線層112d可不被研磨。由於金屬凸塊112B的表面一般具有較配線層112d的表面的表面積小的表面積，因此即使在研磨製程中金屬凸塊112B的表面被研磨，產生銅 殘留物的情況仍可顯著減少。因此，黏著至研磨輪的異物可減少，進而使得加工性可改善。
在下文中，將更詳細闡述根據例示性實施例的扇出型半導體封裝100中所包括的各個組件。
框架110可視特定材料而定改善扇出型半導體封裝100的剛性，且可用於確保包封體130的厚度均勻性。另外，框架110可包括配線層112a、112b、112c及112d以及連接通孔層113a、113b及113c，且因此充當連接構件。框架110可包括設置於半導體晶片120的非主動面上的配線層112c，且因此在不執行形成單獨的背側配線層(separate backside wiring layer)的製程的情況下為半導體晶片120提供背側配線層。框架110可具有使用終止元件層112aM作為終止元件而形成且具有盲形式的凹陷部分110H，且半導體晶片120的非主動面可藉由例如晶粒貼附膜(die attach film，DAF)等任何習知黏合構件125貼附至終止元件層112aM。凹陷部分110H可藉由如下所述的噴砂製程(sandblast process)形成。在此種情形中，凹陷部分110H可具有錐形。亦即，凹陷部分110H的壁可具有相對於終止元件層112aM的預定斜度(gradient)。在此種情形中，對齊半導體晶片120的製程可更簡單，且因此半導體晶片120的良率(yield)可提高。
框架110可包括第一絕緣層111a；第一配線層112a及第二配線層112b，分別設置於第一絕緣層111a的第一表面及第二表面上；第二絕緣層111b，設置於第一絕緣層111a的第一表面上 且覆蓋第一配線層112a；第三配線層112c，設置於第二絕緣層111b上；第三絕緣層111c，設置於第一絕緣層111a的第二表面上且覆蓋第二配線層112b；以及第四配線層112d，設置於第三絕緣層111c上。另外，框架110可包括：第一連接通孔層113a，貫穿第一絕緣層111a且將第一配線層112a與第二配線層112b彼此電性連接；第二連接通孔層113b，貫穿第二絕緣層111b且將第一配線層112a與第三配線層112c彼此電性連接；以及第三連接通孔層113c，貫穿第三絕緣層111c且將第二配線層112b與第四配線層112d彼此電性連接。第一配線層至第四配線層112a、112b、112c及112d可彼此電性連接，且可電性連接至半導體晶片120的連接墊120P。凹陷部分110H可貫穿第一絕緣層111a及第三絕緣層111c，但可不貫穿第二絕緣層111b。終止元件層112aM可設置於第一絕緣層111a的第一表面上且被第二絕緣層111b覆蓋。
終止元件層112aM可為包括例如銅(Cu)等金屬的金屬板。或者，終止元件層112aM可包括對於噴砂製程的蝕刻速率低於金屬的蝕刻速率的材料。舉例而言，可使用乾膜光阻作為終止元件層。終止元件層112aM的第一表面可被第二絕緣層覆蓋，且終止元件層112aM的與所述第一表面相對的第二表面的至少一部分可藉由凹陷部分110H暴露出。終止元件層112aM的接觸第一絕緣層111a的邊緣區的厚度可大於終止元件層112aM的藉由凹陷部分110H而自第一絕緣層111a暴露出的區域的厚度。原因在於，暴露出的區域的部分亦可在噴砂製程中被移除。
絕緣層111a、111b及111c中的每一者的材料可為絕緣材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維(或玻璃布，或玻璃纖維布)等的核心材料中的樹脂，例如預浸體(prepreg)、味之素構成膜(Ajinomoto Build up Film，ABF)、FR-4或雙馬來醯亞胺三嗪(Bismaleimide Triazine，BT)等。當使用具有高剛性的材料(例如包括玻璃纖維等的預浸體)作為絕緣層111a、111b及111c中的每一者的材料時，框架110可用作為用於控制扇出型半導體封裝100的翹曲的支撐構件。
第一絕緣層111a具有的厚度可大於第二絕緣層111b及第三絕緣層111c的厚度。第一絕緣層111a可為相對較厚以維持剛性，且為了形成數量較多的配線層112c及112d，第二絕緣層111b及第三絕緣層111c可被引入。第一絕緣層111a可包括不同於第二絕緣層111b及第三絕緣層111c的絕緣材料的絕緣材料。舉例而言，第一絕緣層111a可例如為將絕緣樹脂與無機填料一起浸入玻璃纖維中的預浸體，且第二絕緣層111b及第三絕緣層111c可為包括無機填料及絕緣樹脂的ABF或PID膜。然而，第一絕緣層111a的材料以及第二絕緣層111b及第三絕緣層111c的材料並非僅限於此。相似地，貫穿第一絕緣層111a的第一連接通孔層113a具有的直徑可大於分別貫穿第二絕緣層111b及第三絕緣層111c的第二連 接通孔層113b及第三連接通孔層113c的直徑。
配線層112a、112b、112c及112d可與重佈線層142a、142b及142c一起對半導體晶片120的連接墊120P進行重新分佈。配線層112a、112b、112c及112d中的每一者的材料可為導電材料，諸如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。配線層112a、112b、112c及112d可視對應層的設計而執行各種功能。舉例而言，配線層112a、112b、112c及112d可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。此處，訊號(S)圖案可包括除接地(GND)圖案、電源(PWR)圖案等之外的各種訊號，例如資料訊號等。另外，配線層112a、112b、112c及112d可包括各種接墊圖案等。
配線層112a、112b、112c及112d的厚度可大於連接構件140的重佈線層142a、142b及142c的厚度。由於框架110是使用基板製程製造而成，因此配線層112a、112b、112c及112d可形成為具有相對較大的厚度，但由於連接構件140是使用半導體製程製造而成，因此重佈線層142a、142b及142c可形成為具有相對較小的厚度。
連接通孔層113a、113b及113c可將形成於不同層上的配線層112a、112b、112c及112d彼此電性連接，從而在框架110中形成電性通路(electrical path)。連接通孔層113a、113b及113c中的每一者的材料可為導電材料。連接通孔層113a、113b及113c中的每一者可利用導電材料完全填充，或者導電材料亦可沿著通 孔孔洞中的每一者的壁形成。第一連接通孔層113a可具有圓柱形或沙漏形，且第二連接通孔層113b及第三連接通孔層113c可具有錐形。在此種情形中，相對於第一絕緣層111a，第二連接通孔層113b與第三連接通孔層113c可具有方向彼此相反的錐形。
半導體晶片120可為以數百至數百萬個或更多數量的元件整合於單一晶片中提供的積體電路(IC)。半導體晶片120可例如為處理器晶片(更具體而言，應用處理器(AP))，例如中央處理器(例如CPU)、圖形處理器(例如GPU)、現場可程式閘陣列(field programmable gate array，FPGA)、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器或微控制器等，但並非僅限於此。
半導體晶片120可以主動晶圓為基礎而形成。在此種情形中，半導體晶片120的本體的基材(base material)可為矽(Si)、鍺(Ge)或砷化鎵(GaAs)等。在本體上可形成各種電路。連接墊120P可將半導體晶片120電性連接至其他組件。連接墊120P中的每一者的材料可為例如鋁(Al)等的導電材料。本體上可形成暴露出連接墊120P的鈍化層，所述鈍化層例如是氧化物膜、氮化物膜等，且可為氧化物層與氮化物層所構成的雙層。亦可在其他需要的位置中進一步設置絕緣層等。半導體晶片120可為裸晶粒，但必要時可更包括形成於半導體晶片120的主動面上的重佈線層。
包封體130可保護框架110、半導體晶片120等。包封 體130的包封形式不受特別限制，但可為包封體130環繞框架110的至少一部分、半導體晶片120的至少一部分等的形式。舉例而言，包封體130可覆蓋框架110的至少一部分，且可填充凹陷部分110H的壁與半導體晶片120的側表面之間的空間。包封體130可填充凹陷部分110H，藉以充當黏合劑，並視特定材料而定減少半導體晶片120的彎曲(buckling)情況。連接至重佈線層142a的金屬凸塊120B及112B的表面可設置於與包封體130的接觸絕緣層141a的表面的水平高度相同的水平高度上。相同的水平高度的概念可包括輕微誤差。
包封體130的材料不受特別限制。舉例而言，可使用絕緣材料作為包封體130的材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維(或玻璃布，或玻璃纖維布)等的核心材料中的樹脂，例如預浸體、ABF、FR-4或BT等。或者，亦可使用感光成像包封體(photoimagable encapsulant，PIE)樹脂作為絕緣材料。
連接構件140可對半導體晶片120的連接墊120P進行重佈線，且可將框架110的配線層112a、112b、112c及112d電性連接至半導體晶片120的連接墊120P。數十至數百萬個具有各種功能的連接墊120P可藉由連接構件140進行重新分佈，且可視功能而通過電性連接結構170來與外部進行物理連接或電性連接。
連接構件140可包括：第一絕緣層141a，設置於框架110、包封體130及半導體晶片120的主動面上；第一重佈線層142a，設置於第一絕緣層141a上；第一連接通孔143a1及143a2，貫穿第一絕緣層141a且將第一重佈線層142a電性連接至金屬凸塊120B及112B；第二絕緣層141b，設置於第一絕緣層141a上且覆蓋第一重佈線層142a；第二重佈線層142b，設置於第二絕緣層141b上；第二連接通孔143b，貫穿第二絕緣層141b且將第一重佈線層142a與第二重佈線層142b彼此電性連接；第三絕緣層141c，設置於第二絕緣層111b上且覆蓋第二重佈線層142b；第三重佈線層142c，設置於第三絕緣層141c上；以及第三連接通孔143c，貫穿第三絕緣層141c且將第二重佈線層142b與第三重佈線層142c彼此電性連接。連接構件140的絕緣層、重佈線層、通孔層的數量可大於或小於圖式中所示出的數量。
絕緣層141a、141b及141c中的每一者的材料可為絕緣材料。在此種情形中，除如上所述的絕緣材料之外，亦可使用例如感光成像介電(PID)樹脂等感光絕緣材料作為絕緣材料。亦即，絕緣層141a、141b及141c可為感光絕緣層。當絕緣層141a、141b及141c具有感光性質時，絕緣層141a、141b及141c可形成為具有較小的厚度，且可更容易達成連接通孔143a1、143a2、143b及143c的精密間距。絕緣層141a、141b及141c可為包括絕緣樹脂及無機填料的感光絕緣層。當絕緣層141a、141b及141c為多層時，絕緣層141a、141b及141c的材料可為彼此相同，必要時亦 可為彼此不同。當絕緣層141a、141b及141c為多層時，絕緣層141a、141b及141c可視製程而彼此整合，進而使得絕緣層之間的邊界亦可為不明顯。
重佈線層142a、142b及142c可用於對連接墊120P實質上進行重新分佈。重佈線層142a、142b及142c中的每一者的材料可為導電材料，例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。重佈線層142a、142b及142c可視對應層的設計而執行各種功能。舉例而言，重佈線層142a、142b及142c可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。此處，訊號(S)圖案可包括除接地(GND)圖案、電源(PWR)圖案等之外的各種訊號，例如資料訊號等。另外，重佈線層142a、142b及142c可包括各種接墊圖案等。
連接通孔143a1、143a2、143b及143c可將形成於不同層上的重佈線層142a、142b及142c、金屬凸塊120B及112B等彼此電性連接，從而在扇出型半導體封裝100中形成電性通路。連接通孔143a1、143a2、143b、143c中的每一者的材料可為導電材料，例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。連接通孔143a1、143a2、143b及143c中的每一者可利用導電材料完全填充，或者導電材料亦可沿著通孔孔洞中的每一者的壁形成。另外，連接通孔143a1、143a2、143b及143c中的每一者可具有錐形等。第1-1連接通孔143a1中的每一者具有的高度可等於第1-2連接通孔143a2中的每 一者的高度。
重佈線層142a可經由例如銅(Cu)柱等金屬凸塊120B及112B電性連接至連接墊120P及配線層112d。更詳言之，重佈線層142a可經由連接通孔143a1及143a2以及分別連接至連接通孔143a1及143a2的金屬凸塊120B及112B而電性連接至連接墊120P及配線層112d。亦即，金屬凸塊120B可形成於連接墊120P上，且金屬凸塊112B亦可形成於框架110的配線層112d上。金屬凸塊120B及112B可為具有矩形橫截面形狀的銅柱。在此種情形中，如自以下將闡述的製程看出，在研磨製程中金屬凸塊120B及112B的表面可被暴露出，且在研磨製程中配線層112d可不被研磨。由於金屬凸塊112B的表面一般具有較配線層112d的表面的表面積小的表面積，因此即使在研磨製程中金屬凸塊112B的表面被研磨，產生銅殘留物的情況仍可顯著減少。因此，黏著至研磨輪的異物可減少，進而使得加工性可改善。
第一鈍化層151可保護連接構件140免受外部物理性或化學性損傷。第一鈍化層151可具有暴露出連接構件140的第三重佈線層142c的至少一部分的開口。在第一鈍化層151中形成的開口的數量可為數十至數百萬個。第一鈍化層151的材料不受特別限制。舉例而言，可使用絕緣材料作為第一鈍化層151的材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料 一起浸入例如玻璃纖維(或玻璃布，或玻璃纖維布)等的核心材料中的樹脂，例如預浸體、ABF、FR-4或BT等。或者，亦可使用阻焊劑(solder resist)。
第二鈍化層152可保護框架110免受外部物理性或化學性損傷。第二鈍化層152可具有暴露出框架110的第三配線層112c的至少一部分的開口。在第二鈍化層152中形成的開口的數量可為數十至數百萬個。第二鈍化層152的材料不受特別限制。舉例而言，可使用絕緣材料作為第二鈍化層152的材料。在此種情形中，所述絕緣材料可為熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料混合的樹脂或是將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維(或玻璃布，或玻璃纖維布)等的核心材料中的樹脂，例如預浸體、ABF、FR-4或BT等。或者，亦可使用阻焊劑。
凸塊下金屬層160可改善電性連接結構170的連接可靠性，藉以改善扇出型半導體封裝100的板級(board level)可靠性。凸塊下金屬層160可連接至經由第一鈍化層151的開口而暴露出的連接構件140的重佈線層142c。可藉由任何習知金屬化方法，使用任何習知導電材料(例如金屬)以在第一鈍化層151的開口中形成凸塊下金屬層160，但並非僅限於此。
電性連接結構170可在外部物理連接及/或電性連接扇出型半導體封裝100。舉例而言，扇出型半導體封裝100可經由電性連接結構170安裝於電子裝置的主板上。電性連接結構170中 的每一者可由例如焊料等導電材料形成。然而，此僅為實例，且電性連接結構170中的每一者的材料並不特別限定於此。電性連接結構170中的每一者可為接腳(land)、球或引腳等。電性連接結構170可形成為多層結構或單層結構。當電性連接結構170形成為多層結構時，電性連接結構170可包括銅(Cu)柱及焊料。當電性連接結構170形成為單層結構時，電性連接結構170可包括錫-銀焊料或銅(Cu)。然而，此僅為實例，且電性連接結構170並非僅限於此。
電性連接結構170的數量、間隔、佈置形式等不受特別限制，而是可視設計細節而以適合方式修改。舉例而言，電性連接結構170可根據連接墊120P的數量而設置為數十至數千的數量，亦或可設置為數十至數千或更多的數量或是數十至數千或更少的數量。當電性連接結構170為焊球時，電性連接結構170可覆蓋凸塊下金屬層160延伸至第一鈍化層151的一個表面上的側表面，且連接可靠性可更為優異。
電性連接結構170中的至少一者可設置於扇出區中。所述扇出區指代半導體晶片120所設置的區域之外的區域。扇出型封裝相較於扇入型封裝而言可具有優異的可靠性，可實施多個輸入/輸出(I/O)端子，且可有利於三維內連線(3D interconnection)。另外，相較於球柵陣列(BGA)封裝、接腳柵陣列(land grid array，LGA)封裝等，扇出型封裝可被製造成具有較小的厚度，且可具有價格競爭力。
同時，儘管圖式中未繪示，必要時，為了散熱或阻擋電磁波，凹陷部分110H的壁上可形成金屬薄膜。另外，必要時，凹陷部分110H中可設置執行彼此相同或彼此不同的功能的多個半導體晶片120。另外，必要時，凹陷部分110H中可設置單獨的被動組件，例如電感器或電容器等。另外，必要時，第一鈍化層151及第二鈍化層152的表面上可設置被動組件，例如包括電感器或電容器等的表面安裝技術(surface mounting technology，SMT)組件。
圖11至圖15為示出製造圖9的扇出型半導體封裝的製程的示意圖。
首先，參照圖11，可使用覆銅層壓板(copper clad laminate，CCL)等製備第一絕緣層111a，且可藉由適合的鍍覆製程在第一絕緣層111a上及第一絕緣層111a中形成第一配線層112a及第二配線層112b、終止元件層112aM及第一連接通孔層113a。可使用機械鑽孔(mechanical drill)或雷射鑽孔(laser drill)等形成第一連接通孔層113a的通孔孔洞。接著，可分別在第一絕緣層111a的相對兩表面上形成第二絕緣層111b與第三絕緣層111c。可藉由層壓ABF等並接著將所述ABF等硬化來形成第二絕緣層111b及第三絕緣層111c。接著，可藉由適合的鍍覆製程在第二絕緣層111b及第三絕緣層111c上以及第二絕緣層111b及第三絕緣層111c中分別形成第三配線層112c及第四配線層112d以及第二連接通孔層113b及第三連接通孔層113c。亦可使用機械鑽孔或雷射 鑽孔等形成第二連接通孔層113b的通孔孔洞及第三連接通孔層113c的通孔孔洞。可在第三絕緣層111c上形成圖案化乾膜250。可在藉由一系列製程而製備的框架110的第一表面上形成第二鈍化層152，且可將包括絕緣層201及金屬層202的載體膜200(例如可拆載體膜(detachable carrier film，DCF))貼附至第二鈍化層152。可使用GCP材料引入第二鈍化層152。另外，可將例如乾膜光阻(dry film photoresist，DFR)等乾膜250貼附至框架110的第二表面。
接著，參照圖12，可藉由例如(舉例而言)噴砂製程等適合的製程來形成貫穿第一絕緣層111a及第三絕緣層111c的凹陷部分110H。在此種情形中，終止元件層112aM可充當終止元件。所形成的凹陷部分110H可具有錐形。在形成凹陷部分110H之後，可移除乾膜250。
接著，參照圖13，可將半導體晶片120設置於凹陷部分110H中，以使非主動面貼附至終止元件層112aM。可使用例如DAF等任何習知黏合構件125將非主動面貼附至終止元件層112aM。同時，可在連接墊120P上形成有例如銅柱等金屬凸塊120B的狀態下貼附半導體晶片120。另外，可在框架110的第四配線層112d上形成例如銅柱等金屬凸塊112B。接著，可使用包封體130包封框架110的至少一部分及半導體晶片120的至少一部分。可藉由層壓ABF等並接著將所述ABF等硬化來形成包封體130。包封體130可覆蓋相應的金屬凸塊120B及112B。
接著，參照圖14，可對包封體130進行研磨以使金屬凸塊120B及112B的表面暴露出。包封體130的表面可藉由研磨而變為平坦的，且金屬凸塊120B及112B的表面可自包封體130暴露出。亦即，在研磨製程中可不對第四配線層112d進行研磨。由於金屬凸塊120B及112B的表面一般具有較配線層112d的表面的表面積小的表面積，因此即使在研磨製程中金屬凸塊120B及112B的表面被研磨，產生銅殘留物的情況仍可顯著減少。因此，黏著至研磨輪的異物可減少，進而使得加工性可改善。
接著，參照圖15，可對包封體130施加PID且接著將所述PID硬化以形成第一絕緣層141a，且可藉由鍍覆製程在第一絕緣層141a上及第一絕緣層141a中形成第一重佈線層142a以及第一連接通孔143a1及143a2。可藉由使用曝光及顯影的微影法(photolithography method)形成通孔孔洞。接著，可視設計而形成第二絕緣層141b與第三絕緣層141c、第二重佈線層142b與第三重佈線層142c以及第二連接通孔143b與第三連接通孔143c。可藉由一系列製程形成連接構件140。接著，可藉由層壓ABF等並接著將所述ABF等硬化來在連接構件140上形成第一鈍化層151，且可移除載體膜200。接著，可藉由任何習知金屬化方法形成凸塊下金屬層160，且可藉由迴焊製程(reflow process)、使用焊球等形成電性連接結構170。可使用一系列製程製造根據例示性實施例的扇出型半導體封裝100。
如上所述，根據本揭露中的例示性實施例，可提供一種 扇出型半導體封裝，在所述扇出型半導體封裝中設置有包括盲凹陷部分的框架且半導體晶片設置於所述凹陷部分中，且因此儘管使用研磨製程，仍可解決例如銅(Cu)毛邊等問題。
儘管以上已示出並闡述例示性實施例，然而對於熟習此項技術者而言應顯而易見，在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出潤飾及變動。
100‧‧‧扇出型半導體封裝
110‧‧‧框架
110H‧‧‧凹陷部分
111a、111b、111c、141a、141b、141c‧‧‧絕緣層
112a、112b、112c、112d‧‧‧配線層
112aM‧‧‧終止元件層
112B、120B‧‧‧金屬凸塊
113a、113b、113c‧‧‧連接通孔層
120‧‧‧半導體晶片
120P‧‧‧連接墊
125‧‧‧黏合構件
130‧‧‧包封體
140‧‧‧連接構件
142a、142b、142c‧‧‧重佈線層
143a1、143a2、143b、143c‧‧‧連接通孔
151‧‧‧第一鈍化層
152‧‧‧第二鈍化層
160‧‧‧凸塊下金屬層
170‧‧‧電性連接結構
I-I’‧‧‧線

Claims (22)

  1. 一種扇出型半導體封裝，包括：框架，包括：多個絕緣層；多個配線層，設置於所述多個絕緣層上；以及多個連接通孔層，貫穿所述多個絕緣層且將所述多個配線層彼此電性連接，且所述框架具有凹陷部分，所述凹陷部分的底表面上設置有終止元件層；半導體晶片，具有連接墊；主動面，上面設置有所述連接墊；以及非主動面，與所述主動面相對，且所述半導體晶片設置於所述凹陷部分中，以使所述非主動面連接至所述終止元件層；第一金屬凸塊，設置於所述半導體晶片的所述連接墊上；第二金屬凸塊，設置於所述多個配線層中的最上層配線層上；包封體，覆蓋所述框架、所述半導體晶片、所述第一金屬凸塊及所述第二金屬凸塊中的每一者的至少一部分且填充所述凹陷部分的至少一部分；以及連接構件，設置於所述框架上及所述半導體晶片的所述主動面上，且包括藉由所述第一金屬凸塊及所述第二金屬凸塊電性連 接至所述連接墊及所述最上層配線層的重佈線層，其中所述第一金屬凸塊及所述第二金屬凸塊與所述連接構件的第一連接通孔及第二連接通孔接觸，且所述第一金屬凸塊及所述第二金屬凸塊分別經由所述第一連接通孔及所述第二連接通孔連接至所述重佈線層。
  2. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一金屬凸塊及所述第二金屬凸塊中的每一者的上表面與所述包封體的上表面共面。
  3. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一金屬凸塊及所述第二金屬凸塊是銅(Cu)柱。
  4. 如申請專利範圍第3項所述的扇出型半導體封裝，其中所述第一金屬凸塊及所述第二金屬凸塊中的每一者具有矩形橫截面形狀。
  5. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述多個絕緣層包括核心絕緣層、設置於所述核心絕緣層的下表面上的一或多個第一積層絕緣層及設置於所述核心絕緣層的上表面上的一或多個第二積層絕緣層，且所述核心絕緣層所具有的厚度大於所述第一積層絕緣層及所述第二積層絕緣層中的每一者的厚度。
  6. 如申請專利範圍第5項所述的扇出型半導體封裝，其中所述第一積層絕緣層的數量與所述第二積層絕緣層的數量彼此相同。
  7. 如申請專利範圍第5項所述的扇出型半導體封裝，其中所述凹陷部分貫穿至少所述核心絕緣層且貫穿所述一或多個第一積層絕緣層及所述一或多個第二積層絕緣層中的至少一者。
  8. 如申請專利範圍第5項所述的扇出型半導體封裝，其中貫穿所述第一積層絕緣層的第一連接通孔層與貫穿所述第二積層絕緣層的第二連接通孔層在彼此相反的方向上呈錐形。
  9. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述終止元件層的藉由所述凹陷部分而暴露出的區域所具有的厚度小於所述終止元件層的未被暴露出的邊緣區的厚度。
  10. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述凹陷部分的壁呈錐形。
  11. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述半導體晶片的所述非主動面藉由黏合構件貼附至所述終止元件層。
  12. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述終止元件層是金屬層，所述多個配線層中的至少一者包括接地，且所述金屬層電性連接至所述接地。
  13. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述終止元件層具有較所述半導體晶片的所述非主動面的平面面積大的平面面積。
  14. 如申請專利範圍第1項所述的扇出型半導體封裝，其 中所述凹陷部分的所述底表面具有較所述半導體晶片的所述非主動面的平面面積大的平面面積。
  15. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括：第一鈍化層，設置於所述連接構件上且具有暴露出所述重佈線層的至少一部分的開口；凸塊下金屬層，設置於所述第一鈍化層的所述開口中且連接至暴露出的所述重佈線層的至少一部分；以及電性連接結構，設置於所述第一鈍化層上且連接至所述凸塊下金屬層。
  16. 如申請專利範圍第15項所述的扇出型半導體封裝，更包括第二鈍化層，所述第二鈍化層設置於所述框架之下且具有暴露出所述多個配線層中的最下側配線層的至少一部分的開口。
  17. 一種扇出型半導體封裝，包括：框架，具有凹陷部且具有設置於所述框架的上表面及下表面中的每一者上的配線層，在所述凹陷部的底表面上設置有終止元件層；半導體晶片，具有主動面及非主動面且設置於所述凹陷部中，使得所述非主動面接觸所述終止元件層，所述主動面包括連接墊；第一金屬凸塊，設置於所述半導體晶片的所述連接墊上；第二金屬凸塊，設置於在所述框架上設置的最上層配線層 上；以及包封體，覆蓋所述框架、所述半導體晶片、所述第一金屬凸塊及所述第二金屬凸塊的至少多個部分，且填充所述凹陷部的至少一部分，且其中所述終止元件層是金屬層，所述配線層中的至少一者包括接地，且所述金屬層電性連接至所述接地。
  18. 如申請專利範圍第17項所述的扇出型半導體封裝，其中所述第一金屬凸塊及所述第二金屬凸塊中的每一者具有矩形橫截面形狀。
  19. 如申請專利範圍第17項所述的扇出型半導體封裝，其中所述第一金屬凸塊及所述第二金屬凸塊中的每一者的上表面與所述包封體的上表面共面。
  20. 如申請專利範圍第17項所述的扇出型半導體封裝，更包括：連接構件，設置於所述框架上及所述半導體晶片的所述主動面上，所述連接構件包括藉由所述第一金屬凸塊及所述第二金屬凸塊電性連接至所述連接墊及所述最上層配線層的重佈線層。
  21. 如申請專利範圍第17項所述的扇出型半導體封裝，其中所述配線層中的至少一者設置在低於所述終止元件層的水平高度上。
  22. 一種扇出型半導體封裝，包括： 框架，具有凹陷部且具有設置於所述框架的上表面及下表面中的每一者上的配線層，在所述凹陷部的底表面上設置有終止元件層；半導體晶片，具有主動面及非主動面且設置於所述凹陷部中，使得所述非主動面接觸所述終止元件層，所述主動面包括連接墊；第一金屬凸塊，設置於所述半導體晶片的所述連接墊上；第二金屬凸塊，設置於在所述框架上設置的最上層配線層上；以及包封體，覆蓋所述框架、所述半導體晶片、所述第一金屬凸塊及所述第二金屬凸塊的至少多個部分，且填充所述凹陷部的至少一部分，其中所述終止元件層的藉由所述凹陷部分而暴露出的區域所具有的厚度小於所述終止元件層的未被暴露出的邊緣區的厚度。
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