TW201721771A - 整合式扇出封裝及製造方法 - Google Patents

整合式扇出封裝及製造方法 Download PDF

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TW201721771A
TW201721771A TW105122581A TW105122581A TW201721771A TW 201721771 A TW201721771 A TW 201721771A TW 105122581 A TW105122581 A TW 105122581A TW 105122581 A TW105122581 A TW 105122581A TW 201721771 A TW201721771 A TW 201721771A
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Taiwan
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device die
die
top surface
package
conductive member
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TW105122581A
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TWI616956B (zh
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余振華
蔡豪益
余國寵
郭庭豪
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括自第一裝置晶粒之第一導電墊形成一貫穿通路。該第一導電墊位於該第一裝置晶粒之一頂表面處。第二裝置晶粒黏附至該第一裝置晶粒之該頂表面。該第二裝置晶粒具有一表面導電構件。該第二裝置晶粒及該貫穿通路包封於一包封材料中。平坦化該包封材料以顯露該貫穿通路及該表面導電構件。在該貫穿通路及該表面導電構件上方形成重佈線並電性耦接至該貫穿通路及該表面導電構件。

Description

整合式扇出封裝及製造方法 優先權主張及交叉參考
本申請案主張以下臨時申請之美國專利申請案之權益：2015年9月21日申請且標題為「Integrated fan-out Package and the methods of manufacturing」的申請案第62/221,443號，該申請案特此以引用的方式併入本文中。
本揭露係關於整合式扇出封裝及製造方法。
堆疊式晶粒常用於三維(3D)積體電路中。經由晶粒之堆疊，減少包裝之佔據面積(尺寸架構)。此外，經由堆疊式晶粒之形成顯著簡化晶粒中之金屬線佈線。
在一些應用中，複數個晶粒經堆疊以形成晶粒堆疊，其中該複數個晶粒包括貫穿基板通路(Through-Substrate Vias,TSV，有時稱為貫穿矽通路)。經堆疊晶粒之總計數有時可達到八個或八個以上。當形成此類晶粒堆疊時，首先將第一晶粒經由倒裝晶片接合至封裝基板上，其中焊料區域/焊球經回焊以將該第一晶粒結合至該封裝基板。將第一底膠填充施配至該第一晶粒與該封裝基板之間的間隙中。接著固化該第一底膠填充。接著執行測試，以確保該第一晶粒適當地連接至該封裝基板，且該第一晶粒及該封裝基板如所需起作用。
接下來，將第二晶粒經由倒裝晶片接合至該第一晶粒上，其中焊料區域/焊球經回焊以將該第二晶粒結合至該第一晶粒。將第二底膠填充施配至該第二晶粒與該第一晶粒之間的間隙中。接著固化該第二底膠填充。接著執行測試，以確保該第二晶粒適當地連接至該第一晶粒及該封裝基板，且該第一晶粒、該第二晶粒及該封裝基板如所需起作用。接下來，經由與用於接合該第一晶粒及該第二晶粒的相同處理步驟將第三晶粒接合至該第二晶粒上。重複此等處理直至接合全部晶粒。
本揭露的實施例具有一些有利特徵。藉由在較低層位晶粒之金屬墊上直接形成貫穿通路，並不使用封裝基板，且所得封裝薄。藉由使用DAF之邏輯晶粒及記憶體晶粒的熱解耦防止記憶體晶粒遭受由在邏輯晶粒中產生之熱引起的效能降級。封裝之俯視圖區得以最小化。可由相同包封製程(encapsulating process)包封較高層位晶粒及較低層位晶粒，且因此減小封裝之成本及翹曲。
根據本揭露之一些實施例，一種方法包括自第一裝置晶粒之第一導電墊形成貫穿通路。第一導電墊在第一裝置晶粒之頂表面處。將第二裝置晶粒黏附至第一裝置晶粒之頂表面。第二裝置晶粒具有表面導電構件。將第二裝置晶粒及貫穿通路包封於包封材料中。平坦化包封材料以顯露貫穿通路及表面導電構件。在貫穿通路及表面導電構件上方形成重佈線，且使該等該重佈線電性耦接至貫穿通路及表面導電構件。
根據本揭露之一些實施例，一種方法包括在第一裝置晶粒之第一導電墊上形成第一貫穿通路，在第二裝置晶粒之第二導電墊上形成第二貫穿通路，將第一裝置晶粒及第二裝置晶粒置放在載體上方，且將第三裝置晶粒黏附至第一裝置晶粒之頂表面及第二裝置晶粒之頂表 面。該方法進一步包括將第三裝置晶粒、第一貫穿通路及第二貫穿通路包封於包封材料中，平坦化包封材料以顯露第一貫穿通路、第二貫穿通路及第三裝置晶粒之表面導電構件，及在第一貫穿通路、第二貫穿通路及第三裝置晶粒上方形成重佈線且使重佈線電性耦接至第一貫穿通路、第二貫穿通路及第三裝置晶粒。
根據本揭露之一些實施例，一種方法包括在第一裝置晶粒之頂表面上形成第一貫穿通路，在第二裝置晶粒之頂表面上形成第二貫穿通路，將第一裝置晶粒及第二裝置晶粒置放在載體上方，且將第三裝置晶粒黏附至第一裝置晶粒之頂表面及第二裝置晶粒之頂表面。第三裝置晶粒在第一貫穿通路與第二貫穿通路之間。第一裝置晶粒之前表面及第二裝置晶粒之前表面面向第三裝置晶粒之背表面。該方法進一步包括在相同包封製程將第一裝置晶粒、第二裝置晶粒、第三裝置晶粒、第一貫穿通路及第二貫穿通路包封於包封材料中。平面化包封材料以顯露第一貫穿通路、第二貫穿通路及第三裝置晶粒之表面導電構件。在第一貫穿通路、第二貫穿通路及第三裝置晶粒之表面導電構件上方形成重佈線，且使該等重佈線電性耦接至第一貫穿通路、第二貫穿通路及第三裝置晶粒之表面導電構件。
2‧‧‧晶圓
4‧‧‧晶圓
10‧‧‧裝置晶粒
10A‧‧‧頂表面
10B‧‧‧背表面
12‧‧‧金屬墊
14‧‧‧貫穿通路
14A‧‧‧貫穿通路
14B‧‧‧貫穿通路
15‧‧‧開口
16‧‧‧光阻
20‧‧‧裝置晶粒
20-1‧‧‧裝置晶粒
20-2‧‧‧裝置晶粒
20-3‧‧‧裝置晶粒
20-4‧‧‧裝置晶粒
20-1-L‧‧‧裝置晶粒20-1之下部部分
20-1-U‧‧‧裝置晶粒20-1之上部部分
20-2-L‧‧‧裝置晶粒20-2之下部部分
20-2-U‧‧‧裝置晶粒20-2之上部部分
22‧‧‧晶粒附接膜(DAF)
24‧‧‧金屬墊
24A‧‧‧金屬墊
24B‧‧‧金屬墊
26‧‧‧表面介電層
28‧‧‧金屬柱
30‧‧‧包封材料
30A‧‧‧第一包封材料
30B‧‧‧第二包封材料
32‧‧‧介電層
34‧‧‧重佈層(RDL)
36‧‧‧電連接器
38‧‧‧複合晶圓
39‧‧‧整合被動元件(IPD)
40‧‧‧封裝
41‧‧‧裝置晶粒
44‧‧‧黏著膜
46‧‧‧載體
50‧‧‧晶粒附接膜(DAF)
52‧‧‧金屬柱
54‧‧‧蓋
56‧‧‧熱界面材料(TIM)
58‧‧‧球形填充劑
60‧‧‧球形填充劑
200‧‧‧處理流程
202‧‧‧步驟
204‧‧‧步驟
206‧‧‧步驟
208‧‧‧步驟
210‧‧‧步驟
212‧‧‧步驟
當結合附圖閱讀時，自以下詳細描述最好地理解本揭露之態樣。應注意，根據業界中之標準實務，各種構件未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種構件之尺寸。
圖1A至圖1I說明根據一些實施例之扇出封裝的形成中之中間階段的剖面圖。
圖2A至圖2I說明根據一些實施例之扇出封裝的形成中之中間階段的剖面圖。
圖3A至圖3J說明根據一些實施例之扇出封裝的形成中之中間階 段的剖面圖。
圖4A至圖4J說明根據一些實施例之扇出封裝的形成中之中間階段的剖面圖。
圖5至圖10說明根據一些實施例之扇出封裝的剖面圖。
圖11說明根據一些實施例之扇出封裝的俯視圖。
圖12說明根據一些實施例之用於形成扇出封裝的處理流程。
以下揭示內容提供用於實施本揭露之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件在第二構件上方或上之形成可包括第一構件與第二構件直接接觸地形成之實施例，且亦可包括額外構件可在第一構件與第二構件之間形成使得第一構件與第二構件可不直接接觸之實施例。另外，本揭露可能在各種實例中重複參考數字及/或字母。此重複係出於簡單及清晰之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
另外，本文中為易於描述而可能使用諸如「下伏」、「下方」、「下部」、「上覆」、「上部」及其類似者等空間相對術語，以描述如諸圖中所說明的一個元件或構件與另一或多個元件或構件的關係。除諸圖中所描繪之定向以外，空間相對術語意欲涵蓋在使用或操作中之裝置的不同定向。設備可以其他方式定向(旋轉90度或位於其他定向)，且本文中所使用之空間相對描述詞同樣可相應地進行解釋。
根據各種實施例來提供整合式扇出封裝及形成該等整合式扇出封裝的方法。說明形成扇出封裝之中間階段。論述一些實施例之一些變化。貫穿各視圖及說明性實施例，相同的參考標號用以指明相同元件。
圖1A至圖1I說明根據一些實施例之扇出封裝的形成中之中間階 段的剖面圖。於如圖12中所示之處理流程200中亦示意性地說明圖1A至圖1I中所展示之步驟。在後續論述中，參看圖12中之處理步驟而論述圖1A至圖1I中所展示之處理步驟。
參看圖1A，提供裝置晶粒10(其為具有複數個裝置晶粒的各別晶圓2之一部分)。根據本揭露之一些實施例，裝置晶粒10為邏輯晶粒，其可為中央處理單元(CPU)晶粒、微控制單元(MCU)晶粒、輸入-輸出(IO)晶粒、基頻(BB)晶粒或應用處理器(AP)晶粒。儘管未展示，但裝置晶粒10可包括半導體基板，其中在半導體基板之頂表面處形成諸如電晶體及/或二極體之主動裝置。另外，金屬線及通路(未展示)形成於裝置晶粒10之互連結構(未展示)中以互連裝置晶粒10中之積體電路裝置，該互連結構在半導體基板上方。
金屬墊12形成於裝置晶粒10之頂表面10A處。裝置晶粒10之頂表面10A亦稱作前表面。裝置晶粒10具有背表面10B，背表面10B亦可為裝置晶粒10中之各別半導體基板的背表面。金屬墊12可為鋁墊、銅墊、鋁銅墊或其類似者。金屬墊12可形成於裝置晶粒10之第一表面區域中，且裝置晶粒10之第二表面區域中未形成金屬墊。舉例而言，根據如圖1A中所展示之一些例示性實施例，右表面區域中具有金屬墊12，且左表面區域不具有金屬墊。
圖1B及圖1C說明貫穿通路14之形成。各別步驟說明為圖12中所展示之處理步驟中的步驟202。根據一些實施例，如圖1B中所示，光阻16形成於晶圓2上方，且接著經圖案化以形成開口15，經由開口15暴露金屬墊12中之每一者的一部分。接著在開口15中鍍覆貫穿通路14。接著移除光阻16，從而產生圖1C中之結構。根據本揭露之一些實施例，在鍍覆之前並未在晶圓2上形成晶種層。根據替代性實施例，在形成光阻16之前形成晶種層(未展示)，且在晶種層上鍍覆貫穿通路14。在移除光阻16之後，以蝕刻製程移除晶種層的不在貫穿通路 14正下方之部分。晶種層之剩餘部分因此變成貫穿通路14之底部部分。
接下來，參看圖1D，裝置晶粒20經由晶粒附接膜(Die-Attach Film,DAF)22黏附至裝置晶粒10。各別步驟說明為如圖12中所展示之處理步驟的步驟204。裝置晶粒20之背表面黏附至裝置晶粒10之前表面10A，且因此對應晶粒堆疊為正面至背面堆疊(face-to-back stacking)。根據本揭露之一些實施例，裝置晶粒20為記憶體晶粒，記憶體晶粒可為負AND(NAND)晶粒、靜態隨機存取記憶體(SRAM)晶粒、低IO雙倍資料速率(DDR)晶粒或其類似者。儘管未展示，但裝置晶粒20可為單一記憶體晶粒或堆疊式記憶體晶粒。又，裝置晶粒20亦可包括半導體基板，其中諸如電晶體及/或二極體之主動裝置形成於半導體基板之頂表面處。另外，金屬線及通路(未展示)形成於裝置晶粒20之互連結構中，以互連裝置晶粒20中之積體電路裝置。裝置晶粒20之背表面亦可為裝置晶粒20中之半導體基板的背表面。
圖11說明裝置晶粒10之例示性俯視圖及對應上覆裝置晶粒20及貫穿通路14。根據一些例示性實施例，裝置晶粒20與裝置晶粒10之拐角區域重疊，其中貫穿通路14鄰近於裝置晶粒20之兩個側壁。根據替代性實施例，裝置晶粒20與裝置晶粒10之中心區域重疊，且貫穿通路14圍繞裝置晶粒20。亦可使用其他佈置方案佈置裝置晶粒20及貫穿通路14。
DAF 22為黏著膜，且可由聚合物形成。根據本揭露之一些實施例，DAF 22具有可低於約0.5W/m*K之低熱導率。
返回參看圖1D，裝置晶粒20包括在表面介電層26中形成的導電柱28，導電柱28可為金屬柱。金屬柱28可由銅、鎳、鈀、金、其多層及/或其合金形成。表面介電層26可由聚苯并唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或其類似者形成。金屬柱28下方可駐留金屬墊24， 金屬墊24可由銅、鋁或其他金屬形成。
參看圖1E，在裝置晶粒20及貫穿通路14上包封包封材料30。各別步驟說明為圖12中所展示之處理步驟中的步驟206。包封材料30作為流體而施配，且接著(例如)以熱固化製程加以壓縮及固化。包封材料30填充裝置晶粒20與貫穿通路14之間的間隙。包封材料30可包括模塑料、成型底膠填充、環氧樹脂或樹脂。在包封製程之後，包封材料30之頂表面高於金屬柱28及貫穿通路14之頂端。
接下來，執行諸如機械研磨、化學機械拋光(CMP)及/或兩者之組合的平坦化步驟，以平面化包封材料30、貫穿通路14、表面介電層26及金屬柱28。各別步驟亦說明為圖12中所展示之處理步驟中的步驟206。亦在圖1E中展示所得結構。歸因於平坦化，貫穿通路14之頂表面與金屬柱28之頂表面齊平(共面)，且與包封材料30之頂表面齊平(共面)。
參看圖1F，在包封材料30、貫穿通路14及金屬柱28上方形成一或多個介電層32及各別重佈層(Redistribution Layers,RDL)34。各別步驟說明為圖12中所展示之處理步驟中的步驟208。根據本揭露之一些實施例，介電層32係由諸如PBO、聚醯亞胺、BCB或其類似者之聚合物形成。
形成RDL 34而電性耦接至金屬柱28及貫穿通路14。應注意，貫穿全部圖對RDL 34的說明係示意性的。舉例而言，RDL 34實際上經圖案化為由(多個)各別介電層彼此分離的複數個離散部分。RDL 34之離散部分中之每一者連接至各別下伏金屬柱28及/或貫穿通路14。RDL 34亦可將一些金屬柱28互連至各別貫穿通路14。RDL 34可包括金屬跡線(金屬線)及在金屬跡線下方且連接至金屬跡線的通路。根據本揭露之一些實施例，經由鍍覆製程形成RDL 34，其中RDL 34中之每一者包括晶種層(未展示)及在該晶種層上方的鍍覆金屬材料。晶種 層與鍍覆金屬材料可由相同材料或不同材料形成。
圖1G說明裝置晶粒10之背面研磨，自其背面(所說明之底面)研磨裝置晶粒10。各別步驟說明為圖12中所展示之處理步驟中的步驟210。因此，裝置晶粒10之厚度自厚度T1(圖1F)減小至如圖1G中所示之厚度T2。
圖1H說明根據本揭露之一些例示性實施例的電連接器36之形成。各別步驟說明為圖12中所展示之處理步驟中的步驟212。電連接器36電性耦接至RDL 34、金屬柱28及/或貫穿通路14。電連接器36之形成可包括在RDL 34上方置放焊球且接著對焊球進行回焊。根據本揭露之替代性實施例，電連接器36之形成包括執行鍍覆步驟以在RDL 34上方形成焊料區域及接著對該焊料區域進行回焊。電連接器36亦可包括金屬柱或金屬柱加焊蓋(其亦可經由鍍覆形成)。
此外，整合被動元件(Integrated Passive Device,IPD)39可接合至RDL 34。IPD 39可用於調諧所得封裝之效能，且可包括(例如)電容器。根據替代性實施例，並不接合IPD 39。貫穿描述，包含裝置晶粒10及20、貫穿通路14、包封材料30、RDL 34及介電層32的組合結構將稱作複合晶圓38，複合晶圓38為包含複數個裝置晶粒10及20的複合晶圓。
在後續步驟中，將複合晶圓38鋸切分開成複數個封裝40，每一封裝40包含裝置晶粒10中之一者、裝置晶粒20中之一者及對應貫穿通路14。根據一些實施例，封裝40因此係以單一包封(成型)製程形成，但封裝40包括堆疊在一起之兩層裝置晶粒。此不同於習知晶粒堆疊製程，在習知晶粒堆疊製程中，使用兩個包封製程包封兩層裝置晶粒。此外，未在封裝40中使用封裝基板。此引起封裝40之厚度的有利減小，且因此封裝40適合於需要極薄封裝的行動應用。
根據一些實施例，儘管封裝40因為RDL 34延伸超出裝置晶粒20 之邊緣而為扇出封裝，但封裝40之佔據面積(俯視圖區)與裝置晶粒10之俯視圖區相同，從而使得裝置晶粒10之俯視圖區適於安置全部電連接器36。因此，封裝40之俯視圖區小。此外，金屬墊12與電連接器36之間距離小，從而導致所得封裝40之電效能的改良。
另外，可為邏輯晶粒之裝置晶粒10通常相較於諸如裝置晶粒20之記憶體裝置晶粒產生更多熱。記憶體晶粒因熱而遭受嚴重效能降級。根據本揭露之實施例，具有低熱導率之DAF 22用以減少傳導至裝置晶粒20的在裝置晶粒10中產生之熱。確切而言，裝置晶粒10中之熱可經由貫穿通路14傳導至電連接器36。貫穿通路14中之一些亦可設計為未用於裝置晶粒10與電連接器36之間的電連接的虛設通路。虛設貫穿通路14能夠以電氣方式浮動，且用於將裝置晶粒10中之熱傳導至電連接器36。
圖2A至圖4J說明根據一些實施例之扇出封裝的形成中之中間階段的剖面圖。除非另有指定，否則在此等實施例中之組件的材料及形成方法基本上與由與圖1A至圖1I中所展示之實施例中之相同參考數字表示的相同組件相同。因此，可經由圖1A至圖1H中所展示之實施例的論述而發現或實現關於圖2A至圖4J(及圖5至圖10中之實施例)中所展示組件的形成過程及材料之細節。
在圖2A及圖2B中展示一些實施例之初始步驟，該等初始步驟基本上與圖1A至圖1C中所展示之處理步驟相同。在裝置晶粒10之金屬墊12上形成貫穿通路14。接下來，將晶圓2鋸切為個別裝置晶粒10。
參看圖2C，裝置晶粒10經由黏著膜44黏附至載體46。根據本揭露之一些實施例，載體46為玻璃載體。儘管展示一個裝置晶粒10，但存在置放於載體46上的複數個裝置晶粒10，且裝置晶粒10可佈置為陣列。裝置晶粒20接著經由DAF 22黏附至裝置晶粒10之前表面，如圖2D中所展示。在後續步驟中，如圖2E中所展示，施配包封材料30以 封裝裝置晶粒10及20。不同於如圖1E中所示之實施例，亦包封裝置晶粒10。因為以單一包封製程達成裝置晶粒10及20之封裝，故在包封材料30之上部部分(用於包封裝置晶粒20)與底部部分(用於包封裝置晶粒10)之間不存在可辨別界面。
在後續步驟中，如圖2F中所展示，在包封材料30上方形成介電層32及RDL 34，其中RDL 34電性耦接至金屬柱28及貫穿通路14。根據一些例示性實施例，RDL 34擴展超出裝置晶粒10及20兩者之邊緣。因此，圖2F中所展示之實施例(相比於圖1F)可用於裝置晶粒10之俯視圖區不足夠大來容納全部電連接器36(圖2I)，且因此RDL 34需要自裝置晶粒10扇出的實施例中。
接下來，使載體46自上覆結構脫膠，從而產生圖2G中所展示之結構。接著可執行背面研磨以移除黏著膜44且使裝置晶粒10變薄，且在圖2H中展示所得結構。在圖2I中，IPD 39可(或可不)接合至RDL 34。將所得複合晶圓38(其包括裝置晶粒10、裝置晶粒20、包封材料30、貫穿通路14、RDL 34及介電層32)鋸切為個別封裝40。
圖3A至圖3J說明根據一些實施例之扇出封裝40的形成。參看圖3A，形成晶圓4，其中包括裝置晶粒20。在裝置晶粒20之前表面20A處形成導電墊(諸如金屬墊)24。裝置晶粒20具有背表面20B，背表面20B亦可為裝置晶粒中的各別半導體基板(未展示)之背表面。接下來，參看圖3B，形成貫穿通路14，其中形成過程可類似於圖1B及圖1C中所展示之過程。接著將晶圓4鋸切為個別裝置晶粒20。
參看圖3C，選取裝置晶粒20(包括20-1及20-2)且將其置放於載體46及上覆黏著膜44上。黏著層44可由光熱轉換(LTHC)材料形成。此外，DAF 50可用以將裝置晶粒20黏附至黏著膜44。裝置晶粒20-1與20-2之間的距離為選定的，以使得裝置晶粒20-1上方之貫穿通路14與裝置晶粒20-2上方之貫穿通路14之間的空間足夠大以容納裝置晶粒10 (圖3D)。根據本揭露之一些實施例，裝置晶粒20-1與20-2等同於彼此，且裝置晶粒20-1相對於裝置晶粒20-2旋轉180度(在俯視圖中)。根據替代性實施例，裝置晶粒20-1與20-2部分等同於彼此，其中(裝置晶粒20-1之)下部部分20-1-L(諸如主動裝置及互連結構(未展示))等同於裝置晶粒20-2之下部部分20-2-L。然而，上部部分20-1-U及20-2-U(其包括頂部重佈層(未展示))彼此不同，以使得裝置晶粒20-1中之導電墊24集中在裝置晶粒20-1之左側上，且裝置晶粒20-2中之導電墊24集中在裝置晶粒20-2之右側上。根據本揭露之替代性實施例，裝置晶粒20-1與20-2為不同類型之晶粒，且具有不同結構。根據本揭露之替代性實施例，裝置晶粒20可包括兩個以上晶粒，諸如四個晶粒，且裝置晶粒10可包括一個以上晶粒，諸如兩個晶粒，以取決於設計需要用於多個邏輯及多個記憶體晶片之整合。
接下來，參看圖3D，裝置晶粒10置放在裝置晶粒20上方，且經由DAF 22黏附至裝置晶粒20之前表面。裝置晶粒10之一部分亦與裝置晶粒20之間的間隙重疊。根據一些實施例，裝置晶粒10包括在金屬墊12上方之金屬柱52，其中無介電層圍繞金屬柱52。根據替代性實施例，存在與金屬柱52處在相同層位且圍繞金屬柱52的介電層(未展示)。根據其他替代實施例，在金屬墊12上方未形成金屬柱，且金屬墊12為裝置晶粒10之頂部導電構件。
圖3E說明裝置晶粒10及20以及貫穿通路14於包封材料30中之包封，接著為機械研磨、化學機械拋光(CMP)及/或兩者之組合以暴露金屬柱52及貫穿通路14。在後續步驟中，形成介電層32及RDL 34，且將RDL 34電性耦接至金屬柱52及貫穿通路14，如圖3F中所展示。接下來，可將裝置晶粒41接合至RDL 34(圖3G)，且形成電連接器36以連接至RDL 34(圖3H)。裝置晶粒41可包括穿過裝置晶粒41中之半導體基板的貫穿通路(有時被稱作貫穿矽通路或貫穿基板通路)。根據一 些實施例，亦可將IPD接合至RDL 34。
接著使載體46自上覆結構脫膠，且在圖3I中展示所得結構。在後續步驟中，自背面研磨裝置晶粒20-1及20-2，且經由研磨移除DAF50。在圖3J中展示所得結構。圖3J進一步說明蓋54(例如)經由熱界面材料(Thermal Interface Material,TIM)56至裝置晶粒20之附接。TIM 56具有高於DAF 22(圖1I、圖2I及圖3J)之熱導率的熱導率。舉例而言，TIM 56之熱導率可能高於約1W/m*K或甚至更高。蓋54可由具有良好熱導率的材料形成。根據一些例示性實施例，蓋54包括金屬，諸如鋁、銅、鋁/銅合金、不鏽鋼或其類似者。
圖4A至圖4J說明根據一些實施例之封裝40(圖4J)的形成。此等實施例基本上與圖3A至圖3J中所展示之實施例相同，惟裝置晶粒10不具有在金屬墊12上方形成的金屬柱52(圖3J)除外。下文提供對形成過程的簡要論述。可在圖3A至圖3J中之實施例中發現此等實施例之細節，且不在本文中重複此等細節。
圖4A至圖4C中所展示之步驟基本上與圖3A至圖3C中所展示之步驟相同。接下來，如圖4D中所展示，裝置晶粒10黏附至裝置晶粒20(包括20-1及20-2)。裝置晶粒10將金屬墊12包括為頂表面導電構件，且在金屬墊12上方未形成金屬柱。亦在裝置晶粒20-1正上方之貫穿通路14與裝置晶粒20-2正上方之貫穿通路14之間置放裝置10。
圖4E說明包封材料30在暴露金屬墊12及貫穿通路14的同時之直接形成(無需平坦化)。圖4F至圖4J中所展示之處理步驟基本上與圖3F至圖3J中所展示之處理步驟相同，且細節不在本文中重複。
圖5至圖10說明根據本揭露之一些實施例而形成的封裝。可自圖1A至圖4J中之實施例理解形成過程。圖5中所展示之封裝40類似於圖1I中所展示之封裝，惟以下情況除外：在圖5中，未形成金屬柱，且金屬墊24為晶粒20之頂部導電構件。RDL 34包括與金屬墊24實體接 觸之通路。
圖6中所展示之封裝40類似於圖2I中所展示之封裝，惟以下情況除外：在圖6中，未形成金屬柱，且金屬墊24為晶粒20之頂部導電構件。RDL 34包括與金屬墊24實體接觸之通路。
圖7說明封裝40，其類似於圖2I中之封裝40，惟裝置晶粒20部分地自裝置晶粒10偏移除外。在部分偏移之情況下，裝置晶粒20之第一部分與包封材料30之一部分重疊，且不與裝置晶粒10之任何部分重疊。裝置晶粒20之第二部分與裝置晶粒10之一部分重疊。裝置晶粒20之該第一部分因此懸浮，而無裝置晶粒10在下方之支撐。裝置晶粒20相對於裝置晶粒10之部分偏移有利地減小裝置晶粒10與20之重疊區。因此，裝置晶粒10之頂表面區域的增加之百分比可用於形成金屬墊12及貫穿通路14，而非正由裝置晶粒20重疊。然而，根據一些實施例，裝置晶粒20自裝置晶粒10之偏移並不導致封裝40之尺寸架構(俯視圖區)的非所需增大。舉例而言，當封裝40之俯視圖區由適配全部電連接器36所需的區域判定時，只要裝置晶粒10及20之總佔據面積區域不超出適配全部電連接器36所需的區域，裝置晶粒20自裝置晶粒10之部分偏移將不會引起尺寸架構(俯視圖區)之增大。圖8說明類似於圖7中所展示之封裝的封裝40，惟未在金屬墊24上方形成金屬柱除外。
圖9說明根據一些實施例之封裝40，其中存在自各別裝置晶粒10部分偏移的兩個裝置晶粒10及兩個裝置晶粒20。每一裝置晶粒10具有與各別下伏裝置晶粒20之一部分重疊的第一部分，及自各別下伏裝置晶粒20偏移的第二部分。貫穿通路14直接形成於裝置晶粒20中之每一者的金屬墊24上。
圖10說明根據一些實施例之封裝40，其中存在四個裝置晶粒20(包括20-3及20-4)及一個裝置晶粒10。四個裝置晶粒20包括兩個較高層位裝置晶粒20-4，及在較高層位裝置晶粒20-4下方的兩個較低層位 裝置晶粒20-3。較高層位裝置晶粒20-4中之每一者具有與各別下伏較低層位裝置晶粒20-3之一部分重疊的第一部分，及自各別下伏較低層位裝置晶粒20-3偏移的第二部分。四個裝置晶粒20以第一包封製程包封於第一包封材料30A中。
裝置晶粒10在較高層位裝置晶粒20-4上方，且以第二包封製程包封於第二包封材料30B中。裝置晶粒10自兩個較高層位裝置晶粒20-4皆部分偏移。舉例而言，裝置晶粒10具有與較高層位裝置晶粒20-4之部分重疊的第一部分，及與較高層位裝置晶粒20-4之間的間隙重疊的第二部分。
包封材料30A與30B可彼此相同或彼此不同。貫穿通路14A直接形成於較低層位裝置晶粒20-3之金屬墊24A上。貫穿通路14B中之一些直接形成於較高層位裝置晶粒20-4之金屬墊24B上。歸因於對包封材料30A之頂表面執行的CMP，包封材料30A與30B之界面可自彼此辨別，此使得包封材料30A中的球形填充劑58中之一些經研磨以具有平面(而非球面)頂表面。另一方面，在包封材料30B中且與包封材料30A接觸的球形填充劑60仍然具有圓形。另外，歸因於貫穿通路14A及14B之形成過程的本質，貫穿通路14A及14B中之每一者可具有大於各別底部寬度的頂部寬度。貫穿通路14B至各別下伏貫穿通路14A之過渡亦將展示不連續性，且貫穿通路14A之頂部寬度可能大於各別上覆貫穿通路14B之底部寬度。
在圖9及圖10中，較高層位晶粒自較低層位晶粒之部分偏移導致可用於形成金屬墊及貫穿通路的較低層位晶粒20-3之表面積的有利增大。另一方面，因為較低層位晶粒20-3佔據封裝40之大部分俯視圖區，故封裝40之翹曲不嚴重。
前文概述若干實施例之特徵以使得熟習此項技術者可較好地理解本揭露之態樣。熟習此項技術者應理解，其可易於使用本揭露作為 設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露之精神及範疇，且其可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、替代及更改。
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Claims (10)

  1. 一種方法，其包含：自一第一裝置晶粒之一第一導電墊形成一貫穿通路，其中該第一導電墊位於該第一裝置晶粒之一頂表面處；將一第二裝置晶粒黏附至該第一裝置晶粒之該頂表面，其中該第二裝置晶粒包含一表面導電構件；將該第二裝置晶粒及該貫穿通路包封於一包封材料中；平坦化該包封材料以顯露該貫穿通路及該表面導電構件；及在該貫穿通路及該表面導電構件上方形成重佈線並電性耦接至該貫穿通路及該表面導電構件。
  2. 如請求項1之方法，其中該包封材料具有對準至該第一裝置晶粒之各別邊緣的邊緣。
  3. 如請求項1之方法，其中該包封材料擴展超出該第一裝置晶粒之各別邊緣，其中該包封材料之一底表面與該第一裝置晶粒之一底表面共面。
  4. 如請求項1之方法，其中該第二裝置晶粒包含：與該第一裝置晶粒之一部分重疊的一第一部分；及與該包封材料之一部分重疊的一第二部分。
  5. 如請求項4之方法，其進一步包含與該第一裝置晶粒共面的一第三裝置晶粒，其中該第二裝置晶粒進一步包含與該第三裝置晶粒之一部分重疊的一第三部分。
  6. 如請求項5之方法，其中該第一裝置晶粒包含一第一下部部分及在該第一下部部分上方之一第一上部部分，其中該第一下部部分包含第一主動裝置，且該第一上部部分包含一第一佈線層，其中該第二裝置晶粒包含一第二下部部分及在該第二下部部分 上方之一第二上部部分，其中該第二下部部分包含主動裝置，且該第二上部部分包含一第二佈線層，其中該第一下部部分等同於該第二下部部分，且該第一上部部分不同於該第二上部部分。
  7. 如請求項4之方法，其中該第一裝置晶粒包封於該包封材料中，且該第一裝置晶粒與該第二裝置晶粒係於一相同包封製程包封。
  8. 如請求項1之方法，其中該第二裝置晶粒之該表面導電構件為一金屬柱。
  9. 一種方法，其包含：在一第一裝置晶粒之一第一導電墊上形成一第一貫穿通路；在一第二裝置晶粒之一第二導電墊上形成一第二貫穿通路；將該第一裝置晶粒及該第二裝置晶粒置放於一載體上方；將一第三裝置晶粒黏附至該第一裝置晶粒之一頂表面及該第二裝置晶粒之一頂表面；將該第三裝置晶粒、該第一貫穿通路及該第二貫穿通路包封於一包封材料中；平坦化該包封材料以顯露該第一貫穿通路、該第二貫穿通路及該第三裝置晶粒之一表面構件；及在該第一貫穿通路、該第二貫穿通路及該第三裝置晶粒上方形成重佈線並電性耦接至該第一貫穿通路、該第二貫穿通路及該第三裝置晶粒。
  10. 一種方法，其包含：在一第一裝置晶粒之一頂表面上形成一第一貫穿通路；在一第二裝置晶粒之一頂表面上形成一第二貫穿通路；將該第一裝置晶粒及該第二裝置晶粒置放於一載體上方； 將一第三裝置晶粒黏附至該第一裝置晶粒之該頂表面及該第二裝置晶粒之該頂表面，其中該第三裝置晶粒在該第一貫穿通路與該第二貫穿通路之間，且該第一裝置晶粒之一前表面及該第二裝置晶粒之一前表面面向該第三裝置晶粒之一背表面；在一相同包封製程，將該第一裝置晶粒、該第二裝置晶粒、該第三裝置晶粒、該第一貫穿通路及該第二貫穿通路包封於一包封材料中；平坦化該包封材料以顯露該第一貫穿通路、該第二貫穿通路及該第三裝置晶粒之一表面導電構件；及在該第一貫穿通路、該第二貫穿通路及該第三裝置晶粒之該表面導電構件上方形成重佈線並電性耦接至該第一貫穿通路、該第二貫穿通路及該第三裝置晶粒之該表面導電構件。
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US11532529B2 (en) 2022-12-20
US20170084555A1 (en) 2017-03-23
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US10049953B2 (en) 2018-08-14
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US10269674B2 (en) 2019-04-23
CN106548948B (zh) 2020-01-14
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