WO2022037754A1 - A method for manufacturing a die assembly - Google Patents

A method for manufacturing a die assembly Download PDF

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Publication number
WO2022037754A1
WO2022037754A1 PCT/EP2020/072972 EP2020072972W WO2022037754A1 WO 2022037754 A1 WO2022037754 A1 WO 2022037754A1 EP 2020072972 W EP2020072972 W EP 2020072972W WO 2022037754 A1 WO2022037754 A1 WO 2022037754A1
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WIPO (PCT)
Prior art keywords
die
primary
dies
layer
producing
Prior art date
Application number
PCT/EP2020/072972
Other languages
French (fr)
Inventor
Wu Chen
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to EP20760405.9A priority Critical patent/EP4189741A1/en
Priority to PCT/EP2020/072972 priority patent/WO2022037754A1/en
Publication of WO2022037754A1 publication Critical patent/WO2022037754A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
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    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the present disclosure relates to the field of die stacking. More specifically, the present disclosure relates to a method for manufacturing a die assembly with a plurality of dies in a three-dimensional arrangement.
  • 3D stacks using state-of-the-art 3D integration schemes are not scalable for future products due to their requirements of high system density and high bandwidth.
  • Quilt Packaging differs from conventional packaging methods in that interconnecting nodules are fabricated at the wafer level and are lithographically defined, enabling self-aligning nodules that can be assembled easily and precisely at sub-micron scales using commercial microelectronic pick and place equipment.
  • embodiments disclosed herein provide an integration process to fabricate three-dimensional die stacks using die edge connections. While the approach of using side wall of a die stack has not been widely used due to design and manufacturing challenges, embodiments disclosed herein provide a new possibility and an integration process of using the side wall of a die, thus opening a new dimension in die stacking.
  • an improved manufacturing method allowing for manufacturing a die assembly with a plurality of dies in a three-dimensional arrangement efficiently.
  • producing the carrier wafer further comprises depositing a filling material on the substrate layer and the plurality of primary dies bonded thereto for embedding, i.e. burying, the plurality of primary dies in the filling material.
  • producing the carrier wafer further comprises polishing a top surface of the filling material for revealing within the filling material a respective contact surface of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer.
  • the rough sidewall surface of each primary die can be smoothened.
  • producing the carrier wafer further comprises providing a dielectric material layer on the top surface of the filling material, wherein the dielectric material layer defines a respective through-hole above the contact surface of each of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer, wherein each through-hole in the dielectric material layer above the contact surface of each of the plurality of electrically conductive protrusions is filled with a metallic material for forming a plurality of metal vias.
  • providing the dielectric material layer on the top surface of the filling material comprises: depositing the dielectric material layer on the top surface of the filling material and the respective contact surface of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer; etching a respective through-hole in the dielectric material layer above the contact surface of each of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer; and depositing the metallic material in each of the plurality of through-holes in the dielectric material layer above the contact surface of each of the plurality of electrically conductive protrusions for producing the plurality of metal vias.
  • producing the carrier wafer further comprises providing a plurality of metal pads on top of each of the plurality of metal vias, wherein each of the plurality of metal pads is electrically connected to a respective electrically conductive protrusion of each primary die of the plurality of primary dies bonded to the support layer of the carrier wafer.
  • providing the plurality of metal pads on top of each of the plurality of metal vias comprises depositing a metallic material on top of each of the plurality of metal vias to produce the plurality of metal pads.
  • a wiring layer of a die comprising a metal pad, a metal via and an electrically conductive protrusion is provided, allowing efficiently connecting the BEOL layer of the die with a BEOL layer of another die orthogonally.
  • the wiring layer is able to produce a fine pitch bump with a size smaller than 40 pm.
  • bonding the one or more secondary dies to the tertiary die for producing the die assembly comprises bonding one or more electrical conductive protrusions arranged on a top surface of and electrically connected to a BEOL, i.e. metallization, layer of the tertiary die with the plurality of metal pads of the one or more secondary dies.
  • bonding the one or more secondary dies to the tertiary die for producing the die assembly further comprises depositing a respective solder bump on top of each of the plurality of metal pads of the one or more secondary dies and bonding the one or more electrical conductive protrusions arranged on the top surface of and electrically connected to the BEOL, i.e. metallization, layer of the tertiary die with the plurality of solder bumps of the one or more secondary dies.
  • fine bumps such as with a size smaller than 40 pm can be used to bond a die to another die orthogonally for obtaining a die assembly.
  • bonding the one or more secondary dies to the tertiary die for producing the die assembly comprises bonding using a thermal compression bonding.
  • an improved die assembly which achieves high system density, high bandwidth, reduced power consumption and increased functionality.
  • Figure 2 shows a schematic diagram illustrating that a plurality of electrically conducting protrusions are arranged on a top surface of and electrically connected to a back-end-of- line (BEOL) layer on a wafer in an embodiment
  • BEOL back-end-of- line
  • Figure 3 shows a schematic diagram illustrating dicing a wafer for producing a plurality of primary dies in an embodiment
  • Figure 7 shows a schematic diagram illustrating depositing a dielectric material layer on the top surface of a filling material in an embodiment
  • Figure 8 shows a schematic diagram illustrating etching a plurality of through-holes in a dielectric material in an embodiment
  • Figure 9 shows a schematic diagram illustrating depositing a metallic material in each of a plurality of through-holes in a dielectric material layer in an embodiment
  • Figure 10 shows a schematic diagram illustrating depositing a metallic material on top of each of a plurality of metal vias to form a plurality of metal pads in an embodiment
  • Figure 11 shows a schematic diagram illustrating dicing a carrier wafer for obtaining a plurality of secondary dies in an embodiment
  • Figure 12 also shows a schematic diagram illustrating dicing a carrier wafer for obtaining a plurality of secondary dies in an embodiment
  • Figure 13 shows a schematic diagram illustrating bonding a plurality of secondary dies to a tertiary die for obtaining a die assembly in an embodiment
  • Figure 14 shows a schematic diagram illustrating depositing a solder bump on top of each of a plurality of metal pads of each of a plurality of secondary dies.
  • a corresponding method may include one step to perform the functionality of the one or plurality of units (e.g. one step performing the functionality of the one or plurality of units, or a plurality of steps each performing the functionality of one or more of the plurality of units), even if such one or plurality of steps are not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless specifically noted otherwise.
  • Figure 1 shows a schematic diagram illustrating a method 100 for manufacturing a die assembly with a plurality of dies in a three-dimensional (3D) arrangement.
  • the method 100 comprises the following steps: a step of producing a plurality of primary dies by dicing 101 a wafer, wherein each primary die comprises a base layer, a back-end- of-line, BEOL, layer and a plurality of electrically conductive protrusions, each of the electrically conductive protrusions providing part of the top surface and being electrically connected to the BEOL layer; a further step 103 of producing a carrier wafer by bonding a cut face of each primary die to a substrate layer; a further step 105 of producing a plurality of secondary dies by dicing the carrier wafer, wherein each secondary die comprises one or more primary dies; and a further step 107 of producing the die assembly by bonding one or more of the secondary dies to a tertiary die, thereby producing an electrical connection from the BEOL layer of each primary die in each of the one or more secondary dies to a BEOL layer of the tertiary die via the plurality of electrically conductive protrusions of that
  • Figure 2 provides a schematic cross-sectional view of an example of a wafer 200.
  • the wafer 200 can be produced from a raw wafer (e.g. crystalline silicon) in one more processing steps. These processing steps, which are not the object of the present disclosure, may include operations such as ion implantation, layer deposition, etching, and so on.
  • the wafer 200 thus produced comprises a base layer 201 (e.g. a silicon layer) and a back-end-of-line (BEOL) layer 203 formed on top of the base layer 201 .
  • a plurality of electrically conductive protrusions 205a, 205b, 205c are formed on top of the BEOL layer 203.
  • Further electrically conductive protrusions are formed in front of and behind each of the protrusions 205a, 205b, 205c in cross-sections parallel to the cross section shown in the figure.
  • the protrusions 205a, 205b, 205c shown in the figure are representative of a larger, two-dimensional array of protrusions formed on the BEOL layer 203.
  • the electrically conductive protrusions are electrically connected to the BEOL layer 203 of the wafer 200.
  • “Electrically connected” means in direct material contact or connected via material having a high electrical conductivity.
  • the electrically conducting protrusions are made of copper.
  • the BEOL layer 203 is a metallization layer which interconnects devices (not shown) such as transistors, capacitors, or/and resistors that may be formed on the wafer 200.
  • FIG. 3 shows a schematic cross-sectional view of the wafer 200 after a step of dicing. More specifically, the wafer 200 has been diced (i.e. cut into pieces) so as to produce a plurality of primary dies 301 a-c.
  • Each primary die 301 a-c comprises a portion of the base layer 201 , a portion of the BEOL layer 203 and a subset of the plurality of electrically conductive protrusions 205a-c.
  • Each of the electrically conductive protrusions 205a-c provides a part of the top surface of the respective primary die 301 a-c and, as already described above, is electrically connected to the BEOL layer 203.
  • Figure 4 shows a schematic diagram illustrating a step of bonding a respective cut edge of the plurality of primary dies 301 a-c to a substrate layer 401 by a temporary bonding material 403 for forming a carrier wafer 400 according to an embodiment.
  • Figure 5 shows a schematic diagram illustrating a step of depositing a filling material 501 on the substrate layer 401 and the plurality of primary dies 301 a-c bonded thereto, thereby embedding the plurality of primary dies 301 a-c in the filling material 501 according to an embodiment.
  • Figure 6 shows a schematic diagram illustrating a step of polishing a top surface of the filling material 501 according to an embodiment for revealing within the filling material 501 a respective contact surface of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400.
  • Figure 7 shows a schematic diagram illustrating a step of depositing a dielectric material layer 701 on the top surface of the filling material 501 and the respective contact surface of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400.
  • Figure 8 shows a schematic diagram illustrating a step of etching a respective through- hole 801 a-c in the dielectric material layer 701 above the contact surface of each of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400.
  • Figure 9 shows a schematic diagram illustrating a step of depositing metallic material in each of the plurality of through-holes 801 a-c in the dielectric material layer 701 above the contact surface of each of the plurality of electrically conductive protrusions 205a-c, thereby forming the plurality of metal vias 901 a-c.
  • the metallic material is copper.
  • Figure 10 shows a schematic diagram illustrating a step of providing a plurality of metal pads 1001 a-c on top of each of the plurality of metal vias 901 a-c according to an embodiment.
  • the plurality of metal pads 1001 a-c are provided by depositing a metallic material on top of each of the plurality of metal vias 901 a-c.
  • Each of the plurality of metal pads 1001 a-c is electrically connected to a respective electrically conductive protrusion 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the support layer 401 of the carrier wafer 400.
  • the metallic material is copper.
  • Figure 11 shows a schematic diagram illustrating a step of dicing the carrier wafer 400 into a plurality of secondary dies 110Oa-c according to an embodiment.
  • each secondary die 1100a-c comprises one of the primary dies 301 a-c.
  • Figure 12 shows a schematic diagram illustrating a step of dicing the carrier wafer 400 into a plurality of secondary dies 1200a, b according to a further embodiment.
  • the secondary die 1200a comprises two primary dies, while the secondary die 1200b comprises only one primary die.
  • Figure 13 shows a schematic diagram illustrating a step of bonding the plurality of secondary dies 110Oa-c to a tertiary die 1301 according to an embodiment.
  • the plurality of secondary dies 110Oa-c are bonded to the tertiary die 1301 in such a way that an electrical connection from the BEOL layer 203 of each primary die 301 a-c in each of the plurality secondary dies 110Oa-c to a BEOL layer 1303 of the tertiary die 1301 is produced via the plurality of electrically conductive protrusions 205a-c of that primary die 301 a-c.
  • one or more electrical conductive protrusions 1305a-c arranged on a top surface of and electrically connected to the BEOL layer 1303 of the tertiary die 1301 may be bonded with the plurality of metal pads 901 a-c of the plurality of secondary dies 110Oa-c.
  • the BEOL layer 203 of the plurality of primary dies 301 a-c may be electrically connected via the plurality of electrically conducting protrusions 205a-c with the BEOL layer 1303 of the tertiary die 1301.
  • bonding the plurality of secondary dies 1100a-c, 1200a,b to the tertiary die 1301 for obtaining the die assembly comprises bonding using a thermal compression bonding.
  • Figure 14 shows a schematic diagram illustrating a step of depositing a respective solder bump 1401 a-c on top of each of the plurality of metal pads 1001 a-c of the secondary dies 1100a-c according to an embodiment.
  • bonding the plurality of secondary dies 1100a-c to the tertiary die 1301 may further comprise depositing the respective solder bump 1401 a-c on top of each of the plurality of metal pads 1001 a-c of the secondary dies 1100a-c and bonding the one or more electrical conductive protrusions 1305a-c arranged on the top surface of and electrically connected to the BEOL layer 1303 of the tertiary die 1301 with the plurality of solder bumps 1401a-c of the plurality of secondary dies 1100a-c.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A method (100) for manufacturing a die assembly is described. The method (100) comprises: producing a plurality of primary dies by dicing (101) a wafer, wherein each primary die comprises a base layer, a back-end-of-line, BEOL, layer and a plurality of electrically conductive protrusions being electrically connected to the BEOL layer; producing a carrier wafer by bonding (103) each primary die to a substrate layer; producing a plurality of secondary dies by dicing (105) the carrier wafer; and producing the die assembly by bonding (107) one or more of the secondary dies to a tertiary die, thereby producing an electrical connection from the BEOL layer of each primary die in each of the one or more secondary dies to a BEOL layer of the tertiary die via the plurality of electrically conductive protrusions of that primary die.

Description

DESCRIPTION
A METHOD FOR MANUFACTURING A DIE ASSEMBLY
TECHNICAL FIELD
Generally, the present disclosure relates to the field of die stacking. More specifically, the present disclosure relates to a method for manufacturing a die assembly with a plurality of dies in a three-dimensional arrangement.
BACKGROUND
A three-dimensional integrated circuit (3D IC) has emerged as a viable solution for meeting electronic device requirements such as high performance, increased functionality, low power consumption, and a small footprint.
However, three-dimensional (3D) stacks using state-of-the-art 3D integration schemes are not scalable for future products due to their requirements of high system density and high bandwidth.
There are several methods for manufacturing and designing a new three-dimensional integrated circuit. For instance, in the publication, "Vertical laser assisted bonding for advanced 3.5D chip packaging", Andrej Kolbasow et. al., 2019 IEEE 69th Electronic Components and Technology Conference, a laser-assisted bonding process is used for vertically bonded components at the sides of a chip stack. The bonding system performing the task is the conventional “Laplace-Bonder” available from PacTech. The optic imaging system as well as the tooling have been redesigned and adapted to fulfill the requirements of a 45° orientation. A special transfer station allows for the handover of the horizontally stored chip to the 45° tilted tool. A vacuum is created inside the tool to fix the chip to its bottom. Prior to the bonding process, the chip had been prepared with solder depots of 80pm size via solder jetting. During the bonding, the laser hits the surface of the chip at an incident angle of 45°.
In the publication, "Orthogonal Quilt Packaging 3D Integration for High-Energy Particle Detectors", Jason Kulick et. al., 2019 IEEE 69th Electronic Components and Technology Conference, multiple chips are joined (or “quilted”) together via nodules to form a monolithic-like “meta-chip” called a “quilt,” which performs mechanically and electrically as a single chip. Quilt packaging (QP) differs from conventional packaging methods in that interconnecting nodules are fabricated at the wafer level and are lithographically defined, enabling self-aligning nodules that can be assembled easily and precisely at sub-micron scales using commercial microelectronic pick and place equipment.
However, processing sidewall metal pads at the wafer surface is very challenging. In addition, bonding steps require a special tool to heat the die vertically, thus conventional bump processes and materials cannot be applied.
In light of the above, there is still a need for an improved method for manufacturing a die assembly in the new three-dimensional arrangement efficiently.
SUMMARY
It is an object to provide an improved method for manufacturing a die assembly with a plurality of dies in a three-dimensional arrangement efficiently.
The foregoing and other objects are achieved by the subject matter of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.
Generally, embodiments disclosed herein provide an integration process to fabricate three-dimensional die stacks using die edge connections. While the approach of using side wall of a die stack has not been widely used due to design and manufacturing challenges, embodiments disclosed herein provide a new possibility and an integration process of using the side wall of a die, thus opening a new dimension in die stacking.
More specifically, according to a first aspect a method for manufacturing a die assembly with a plurality of dies in a three-dimensional, i.e. horizontal and vertical, arrangement is provided. The method comprises the following steps: producing a plurality of primary dies by dicing a wafer, wherein each primary die comprises a base layer, a back-end-of-line, BEOL, layer and a plurality of electrically conductive protrusions, wherein the electrically conductive protrusions provide part of a top surface of the respective primary die and are electrically connected to the BEOL layer; producing a carrier wafer by bonding a cut face of each primary die to a substrate layer; producing a plurality of secondary dies by dicing the carrier wafer, wherein each secondary die comprises one or more primary dies; and producing the die assembly by bonding one or more of the secondary dies to a tertiary die, thereby producing an electrical connection from the BEOL layer of each primary die in each of the one or more secondary dies to a BEOL layer of the tertiary die via the plurality of electrically conductive protrusions of that primary die.
Thus, an improved manufacturing method is provided, allowing for manufacturing a die assembly with a plurality of dies in a three-dimensional arrangement efficiently.
In a further possible implementation form of the first aspect, producing the carrier wafer further comprises depositing a filling material on the substrate layer and the plurality of primary dies bonded thereto for embedding, i.e. burying, the plurality of primary dies in the filling material.
In a further possible implementation form of the first aspect, producing the carrier wafer further comprises polishing a top surface of the filling material for revealing within the filling material a respective contact surface of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer. Thus, the rough sidewall surface of each primary die can be smoothened.
In a further possible implementation form of the first aspect, producing the carrier wafer further comprises providing a dielectric material layer on the top surface of the filling material, wherein the dielectric material layer defines a respective through-hole above the contact surface of each of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer, wherein each through-hole in the dielectric material layer above the contact surface of each of the plurality of electrically conductive protrusions is filled with a metallic material for forming a plurality of metal vias. In a further possible implementation form of the first aspect, providing the dielectric material layer on the top surface of the filling material comprises: depositing the dielectric material layer on the top surface of the filling material and the respective contact surface of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer; etching a respective through-hole in the dielectric material layer above the contact surface of each of the plurality of electrically conductive protrusions of each primary die of the plurality of primary dies bonded to the substrate layer of the carrier wafer; and depositing the metallic material in each of the plurality of through-holes in the dielectric material layer above the contact surface of each of the plurality of electrically conductive protrusions for producing the plurality of metal vias.
In a further possible implementation form of the first aspect, producing the carrier wafer further comprises providing a plurality of metal pads on top of each of the plurality of metal vias, wherein each of the plurality of metal pads is electrically connected to a respective electrically conductive protrusion of each primary die of the plurality of primary dies bonded to the support layer of the carrier wafer.
In a further possible implementation form of the first aspect, providing the plurality of metal pads on top of each of the plurality of metal vias comprises depositing a metallic material on top of each of the plurality of metal vias to produce the plurality of metal pads.
Thus, a wiring layer of a die comprising a metal pad, a metal via and an electrically conductive protrusion is provided, allowing efficiently connecting the BEOL layer of the die with a BEOL layer of another die orthogonally. The wiring layer is able to produce a fine pitch bump with a size smaller than 40 pm.
In a further possible implementation form of the first aspect, bonding the one or more secondary dies to the tertiary die for producing the die assembly comprises bonding one or more electrical conductive protrusions arranged on a top surface of and electrically connected to a BEOL, i.e. metallization, layer of the tertiary die with the plurality of metal pads of the one or more secondary dies.
Thus, a BEOL layer of a die can be bonded orthogonally with a BEOL layer of another die efficiently. Such bonding provides good electrical contacts and mitigates overlay errors to the metal pads. In a further possible implementation form of the first aspect, bonding the one or more secondary dies to the tertiary die for producing the die assembly further comprises depositing a respective solder bump on top of each of the plurality of metal pads of the one or more secondary dies and bonding the one or more electrical conductive protrusions arranged on the top surface of and electrically connected to the BEOL, i.e. metallization, layer of the tertiary die with the plurality of solder bumps of the one or more secondary dies.
Thus, fine bumps such as with a size smaller than 40 pm can be used to bond a die to another die orthogonally for obtaining a die assembly.
In a further possible implementation form of the first aspect, bonding the one or more secondary dies to the tertiary die for producing the die assembly comprises bonding using a thermal compression bonding.
In this respect, bonding steps do not require a special tool to heat the die vertically and conventional bump processes and materials can be applied. Thus, the one or more secondary dies and the tertiary die can be bonded efficiently.
According to a second aspect, the invention relates to a die assembly manufactured by a method according to the first aspect of the invention.
Thus, an improved die assembly is provided, which achieves high system density, high bandwidth, reduced power consumption and increased functionality.
Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following, embodiments of the present disclosure are described in more detail with reference to the attached figures and drawings, wherein: Figure 1 shows a schematic diagram illustrating a method for manufacturing a die assembly with a plurality of dies in a three-dimensional (3D) arrangement according to an embodiment;
Figure 2 shows a schematic diagram illustrating that a plurality of electrically conducting protrusions are arranged on a top surface of and electrically connected to a back-end-of- line (BEOL) layer on a wafer in an embodiment;
Figure 3 shows a schematic diagram illustrating dicing a wafer for producing a plurality of primary dies in an embodiment;
Figure 4 shows a schematic diagram illustrating bonding a cut edge of a plurality of primary dies to a substrate layer in an embodiment;
Figure 5 shows a schematic diagram illustrating depositing a filling material on a substrate layer in an embodiment;
Figure 6 shows a schematic diagram illustrating polishing a top surface of a filling material for revealing within the filling material a contact surface of a plurality of electrically conductive protrusions of each die of a plurality of dies in an embodiment;
Figure 7 shows a schematic diagram illustrating depositing a dielectric material layer on the top surface of a filling material in an embodiment;
Figure 8 shows a schematic diagram illustrating etching a plurality of through-holes in a dielectric material in an embodiment;
Figure 9 shows a schematic diagram illustrating depositing a metallic material in each of a plurality of through-holes in a dielectric material layer in an embodiment;
Figure 10 shows a schematic diagram illustrating depositing a metallic material on top of each of a plurality of metal vias to form a plurality of metal pads in an embodiment;
Figure 11 shows a schematic diagram illustrating dicing a carrier wafer for obtaining a plurality of secondary dies in an embodiment; Figure 12 also shows a schematic diagram illustrating dicing a carrier wafer for obtaining a plurality of secondary dies in an embodiment;
Figure 13 shows a schematic diagram illustrating bonding a plurality of secondary dies to a tertiary die for obtaining a die assembly in an embodiment; and
Figure 14 shows a schematic diagram illustrating depositing a solder bump on top of each of a plurality of metal pads of each of a plurality of secondary dies.
In the various figures, identical reference signs will be used for identical or at least functionally equivalent features.
DETAILED DESCRIPTION OF EMBODIMENTS
In the following description, reference is made to the accompanying figures, which form part of the disclosure, and which shows, by way of illustration, specific aspects of embodiments of the present disclosure or specific aspects in which embodiments of the present disclosure may be used. It is understood that embodiments of the present disclosure may be used in other aspects and comprise structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.
For instance, it is to be understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if one or a plurality of specific method steps are described, a corresponding device may include one or a plurality of units, e.g. functional units, to perform the described one or plurality of method steps (e.g. one unit performing the one or plurality of steps, or a plurality of units each performing one or more of the plurality of steps), even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a specific apparatus is described based on one or a plurality of units, e.g. functional units, a corresponding method may include one step to perform the functionality of the one or plurality of units (e.g. one step performing the functionality of the one or plurality of units, or a plurality of steps each performing the functionality of one or more of the plurality of units), even if such one or plurality of steps are not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless specifically noted otherwise.
Figure 1 shows a schematic diagram illustrating a method 100 for manufacturing a die assembly with a plurality of dies in a three-dimensional (3D) arrangement.
The method 100 comprises the following steps: a step of producing a plurality of primary dies by dicing 101 a wafer, wherein each primary die comprises a base layer, a back-end- of-line, BEOL, layer and a plurality of electrically conductive protrusions, each of the electrically conductive protrusions providing part of the top surface and being electrically connected to the BEOL layer; a further step 103 of producing a carrier wafer by bonding a cut face of each primary die to a substrate layer; a further step 105 of producing a plurality of secondary dies by dicing the carrier wafer, wherein each secondary die comprises one or more primary dies; and a further step 107 of producing the die assembly by bonding one or more of the secondary dies to a tertiary die, thereby producing an electrical connection from the BEOL layer of each primary die in each of the one or more secondary dies to a BEOL layer of the tertiary die via the plurality of electrically conductive protrusions of that primary die.
The method 100 for manufacturing the die assembly will be described in further detail with reference to figures 2 to 14 in the following.
Figure 2 provides a schematic cross-sectional view of an example of a wafer 200. The wafer 200 can be produced from a raw wafer (e.g. crystalline silicon) in one more processing steps. These processing steps, which are not the object of the present disclosure, may include operations such as ion implantation, layer deposition, etching, and so on.
The wafer 200 thus produced comprises a base layer 201 (e.g. a silicon layer) and a back-end-of-line (BEOL) layer 203 formed on top of the base layer 201 . A plurality of electrically conductive protrusions 205a, 205b, 205c are formed on top of the BEOL layer 203. Further electrically conductive protrusions (not shown) are formed in front of and behind each of the protrusions 205a, 205b, 205c in cross-sections parallel to the cross section shown in the figure. In other words, the protrusions 205a, 205b, 205c shown in the figure are representative of a larger, two-dimensional array of protrusions formed on the BEOL layer 203. The electrically conductive protrusions (including the ones shown in the figures, 205a-c) are electrically connected to the BEOL layer 203 of the wafer 200. “Electrically connected” means in direct material contact or connected via material having a high electrical conductivity. In an embodiment, the electrically conducting protrusions are made of copper. In an embodiment, the BEOL layer 203 is a metallization layer which interconnects devices (not shown) such as transistors, capacitors, or/and resistors that may be formed on the wafer 200.
Figure 3 shows a schematic cross-sectional view of the wafer 200 after a step of dicing. More specifically, the wafer 200 has been diced (i.e. cut into pieces) so as to produce a plurality of primary dies 301 a-c. Each primary die 301 a-c comprises a portion of the base layer 201 , a portion of the BEOL layer 203 and a subset of the plurality of electrically conductive protrusions 205a-c. Each of the electrically conductive protrusions 205a-c provides a part of the top surface of the respective primary die 301 a-c and, as already described above, is electrically connected to the BEOL layer 203.
Figure 4 shows a schematic diagram illustrating a step of bonding a respective cut edge of the plurality of primary dies 301 a-c to a substrate layer 401 by a temporary bonding material 403 for forming a carrier wafer 400 according to an embodiment.
Figure 5 shows a schematic diagram illustrating a step of depositing a filling material 501 on the substrate layer 401 and the plurality of primary dies 301 a-c bonded thereto, thereby embedding the plurality of primary dies 301 a-c in the filling material 501 according to an embodiment.
Figure 6 shows a schematic diagram illustrating a step of polishing a top surface of the filling material 501 according to an embodiment for revealing within the filling material 501 a respective contact surface of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400. Figure 7 shows a schematic diagram illustrating a step of depositing a dielectric material layer 701 on the top surface of the filling material 501 and the respective contact surface of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400.
As will be described in the following in the context of figures 8 to 10, the dielectric material layer 701 may define a respective through-hole above the contact surface of each of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400. Each through-hole in the dielectric material layer 701 above the contact surface of each of the plurality of electrically conductive protrusions 205a-c may be filled with a metallic material for forming a plurality of metal vias 901 a-c (illustrated in figure 9).
Figure 8 shows a schematic diagram illustrating a step of etching a respective through- hole 801 a-c in the dielectric material layer 701 above the contact surface of each of the plurality of electrically conductive protrusions 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the substrate layer 401 of the carrier wafer 400.
Figure 9 shows a schematic diagram illustrating a step of depositing metallic material in each of the plurality of through-holes 801 a-c in the dielectric material layer 701 above the contact surface of each of the plurality of electrically conductive protrusions 205a-c, thereby forming the plurality of metal vias 901 a-c. In an embodiment, the metallic material is copper.
Figure 10 shows a schematic diagram illustrating a step of providing a plurality of metal pads 1001 a-c on top of each of the plurality of metal vias 901 a-c according to an embodiment. The plurality of metal pads 1001 a-c are provided by depositing a metallic material on top of each of the plurality of metal vias 901 a-c. Each of the plurality of metal pads 1001 a-c is electrically connected to a respective electrically conductive protrusion 205a-c of each primary die of the plurality of primary dies 301 a-c bonded to the support layer 401 of the carrier wafer 400. In an embodiment, the metallic material is copper.
Figure 11 shows a schematic diagram illustrating a step of dicing the carrier wafer 400 into a plurality of secondary dies 110Oa-c according to an embodiment. In the embodiment illustrated in figure 11 each secondary die 1100a-c comprises one of the primary dies 301 a-c. Figure 12 shows a schematic diagram illustrating a step of dicing the carrier wafer 400 into a plurality of secondary dies 1200a, b according to a further embodiment. In the embodiment illustrated in figure 12, the secondary die 1200a comprises two primary dies, while the secondary die 1200b comprises only one primary die.
Figure 13 shows a schematic diagram illustrating a step of bonding the plurality of secondary dies 110Oa-c to a tertiary die 1301 according to an embodiment. The plurality of secondary dies 110Oa-c are bonded to the tertiary die 1301 in such a way that an electrical connection from the BEOL layer 203 of each primary die 301 a-c in each of the plurality secondary dies 110Oa-c to a BEOL layer 1303 of the tertiary die 1301 is produced via the plurality of electrically conductive protrusions 205a-c of that primary die 301 a-c. To this end, one or more electrical conductive protrusions 1305a-c arranged on a top surface of and electrically connected to the BEOL layer 1303 of the tertiary die 1301 may be bonded with the plurality of metal pads 901 a-c of the plurality of secondary dies 110Oa-c.
In an embodiment, the BEOL layer 203 of the plurality of primary dies 301 a-c may be electrically connected via the plurality of electrically conducting protrusions 205a-c with the BEOL layer 1303 of the tertiary die 1301.
In an embodiment, bonding the plurality of secondary dies 1100a-c, 1200a,b to the tertiary die 1301 for obtaining the die assembly comprises bonding using a thermal compression bonding.
Figure 14 shows a schematic diagram illustrating a step of depositing a respective solder bump 1401 a-c on top of each of the plurality of metal pads 1001 a-c of the secondary dies 1100a-c according to an embodiment. Thus, in an embodiment, bonding the plurality of secondary dies 1100a-c to the tertiary die 1301 may further comprise depositing the respective solder bump 1401 a-c on top of each of the plurality of metal pads 1001 a-c of the secondary dies 1100a-c and bonding the one or more electrical conductive protrusions 1305a-c arranged on the top surface of and electrically connected to the BEOL layer 1303 of the tertiary die 1301 with the plurality of solder bumps 1401a-c of the plurality of secondary dies 1100a-c.
While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations or embodiments, such feature or aspect may be combined with one or more other features or aspects of the other implementations or embodiments as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms "coupled" and "connected", along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.
Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.
Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

1 . A method (100) for manufacturing a die assembly, comprising: producing a plurality of primary dies (301 a-c) by dicing (101) a wafer (200), wherein each primary die (301 a-c) comprises a base layer (201), a back-end-of-line, BEOL, layer (203) and a plurality of electrically conductive protrusions (205a-c), wherein the electrically conductive protrusions provide part of a top surface of the respective primary die and are electrically connected to the back-end-of-line, BEOL, layer (203); producing a carrier wafer (400) by bonding (103) a cut face of each primary die (301 a-c) to a substrate layer (401); producing a plurality of secondary dies (110Oa-c) by dicing (105) the carrier wafer (400), wherein each secondary die comprises one or more primary dies; and producing the die assembly by bonding (107) one or more of the secondary dies (1100a- c) to a tertiary die (1301), thereby producing an electrical connection from the BEOL layer (203) of each primary die in each of the one or more secondary dies to a BEOL layer (1303) of the tertiary die (1301) via the plurality of electrically conductive protrusions (205a-c) of that primary die (301a-c).
2. The method (100) of claim 1 , wherein producing the carrier wafer (400) further comprises depositing a filling material (501) on the substrate layer (401) and the plurality of primary dies (301 a-c) bonded thereto, thereby embedding the plurality of primary dies (301 a-c) in the filling material (501).
3. The method (100) of claim 2, wherein producing the carrier wafer (400) further comprises polishing a top surface of the filling material (501), thereby revealing within the filling material (501) a respective contact surface of the plurality of electrically conductive protrusions (205a-c) of each primary die of the plurality of primary dies (301 a-c) bonded to the substrate layer (401) of the carrier wafer (400).
4. The method (100) of claim 3, wherein producing the carrier wafer (400) further comprises providing a dielectric material layer (701) on the top surface of the filling material (501), wherein the dielectric material layer (701) defines a through-hole (801 a-c) above the contact surface of each of the plurality of electrically conductive protrusions (205a-c) of each primary die of the plurality of primary dies (301 a-c) bonded to the substrate layer (401) of the carrier wafer (400), wherein each through-hole (801 a-c) in the dielectric material layer (701) above the contact surface of each of the plurality of electrically conductive protrusions (205a-c) is filled with a metallic material, thereby producing a plurality of metal vias (901 a-c).
5. The method (100) of claim 4, wherein providing the dielectric material layer (701) on the top surface of the filling material (501) comprises: depositing the dielectric material layer (701) on the top surface of the filling material (501) and the respective contact surface of the plurality of electrically conductive protrusions (205a-c) of each primary die of the plurality of primary dies (301 a-c) bonded to the substrate layer (401) of the carrier wafer (400); etching a respective through-hole (801a-c) in the dielectric material layer (701) above the contact surface of each of the plurality of electrically conductive protrusions (205a-c) of each primary die of the plurality of primary dies (301 a-c) bonded to the substrate layer (401) of the carrier wafer (400); and depositing the metallic material in each of the plurality of through-holes (801 a-c) in the dielectric material layer (701) above the contact surface of each of the plurality of electrically conductive protrusions (205a-c), thereby producing the plurality of metal vias (901 a-c).
6. The method (100) of claim 4 or 5, wherein producing the carrier wafer (400) further comprises providing a plurality of metal pads (1001 a-c) on top of each of the plurality of metal vias (901 a-c), wherein each of the plurality of metal pads (1001 a-c) is electrically connected to a respective electrically conductive protrusion (205a-c) of each primary die of the plurality of primary dies (301 a-c) bonded to the support layer (401) of the carrier wafer (400).
7. The method (100) of claim 6, wherein providing the plurality of metal pads (1001a- c) on top of each of the plurality of metal vias (901 a-c) comprises depositing a metallic material on top of each of the plurality of metal vias (901 a-c) to produce the plurality of metal pads (1001 a-c).
8. The method (100) of claim 6 or 7, wherein bonding the one or more of the plurality of secondary dies (1100a-c) to the tertiary die (1301) for producing the die assembly comprises bonding one or more electrical conductive protrusions (1305a-c) arranged on a top surface of and electrically connected to a BEOL layer (1303) of the tertiary die (1301) with the plurality of metal pads (1001 a-c) of the one or more of the plurality of secondary dies (1100a-c).
9. The method (100) of claim 8, wherein bonding the one or more of the plurality of secondary dies (1100a-c) to the tertiary die (1301) for producing the die assembly further comprises depositing a respective solder bump (1401 a-c) on top of each of the plurality of metal pads (1001 a-c) of the one or more of the plurality of secondary dies (110Oa-c) and bonding the one or more electrical conductive protrusions (1305a-c) arranged on the top surface of and electrically connected with the BEOL layer (1303) of the tertiary die (1301) with the plurality of solder bumps (1401 a-c) of the one or more of the plurality of secondary dies (1100a-c).
10. The method (100) of claim 8 or 9, wherein bonding the one or more of the plurality of secondary dies (1100a-c) to the tertiary die (1301) comprises bonding using a thermal compression bonding.
11. A die assembly manufactured by a method (100) according to any one of the preceding claims.
15
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