CN111128972A

CN111128972A - Wafer stacking method and wafer stacking structure

Info

Publication number: CN111128972A
Application number: CN201811294776.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-11-01
Filing date: 2018-11-01
Publication date: 2020-05-08

Abstract

The present disclosure provides a wafer stacking method and structure. The wafer stacking method comprises the following steps: providing a first wafer, an upper surface of the first wafer comprising first pads configured to be connected to a first signal; manufacturing a first redistribution layer on the first wafer, wherein the first redistribution layer comprises a first wiring electrically connected to the first bonding pad, and the first wiring comprises a first lead pad; bonding a second wafer on the first redistribution layer, the second wafer including a second pad arranged to connect the first signal and corresponding in position to the first pad; manufacturing a first through silicon via with the bottom connected to the first lead pad at the position, corresponding to the first lead pad, of the second wafer; and manufacturing a second redistribution layer on the second wafer to connect the second bonding pad and the first through silicon via and form a second lead pad. The wafer stacking method can improve the yield of chips with stacked structures.

Description

Wafer stacking method and wafer stacking structure

Technical Field

The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a wafer stacking method capable of improving an electrical connection effect between wafers, and a wafer stacking structure and a chip stacking structure manufactured by using the wafer stacking method.

Background

Stacking multiple chips and establishing mechanical and electrical connections is an important method of reducing the volume of an integrated circuit during its manufacture. As shown in fig. 1A and 1B, in the prior art, a TSV (Through Silicon Vias) is usually fabricated for each chip to be stacked, a Bump (Micro-Bump) is then formed for each TSV, and finally, positioning and bonding are performed in a wafer-to-wafer or wafer-to-wafer manner, so as to electrically connect an upper chip and a lower chip Through each Bump and the TSV.

First, in the wafer-to-wafer or wafer-to-wafer bonding process, the inefficiency results in high costs. In addition, TSV needs to be made for each chip in advance, and bumps are made, so that the risk of positioning error and connection error is high in the bonding process, which easily causes disconnection of the electrical connection path between the upper and lower chips, and causes reduction of yield.

Therefore, a wafer stacking method capable of overcoming the above problems is required.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a wafer stacking method and a wafer stacking structure, which are used to overcome at least some of the disadvantages of high chip stacking cost, high connection error probability, and low yield due to the limitations and defects of the related art.

According to a first aspect of the present disclosure, there is provided a wafer stacking method comprising:

providing a first wafer, an upper surface of the first wafer comprising first pads configured to be connected to a first signal;

manufacturing a first redistribution layer on the first wafer, wherein the first redistribution layer comprises a first wiring electrically connected to the first bonding pad, and the first wiring comprises a first lead pad;

bonding a second wafer on the first redistribution layer, the second wafer including a second pad arranged to connect the first signal and corresponding in position to the first pad;

manufacturing a first through silicon via with the bottom connected to the first lead pad at the position, corresponding to the first lead pad, of the second wafer;

and manufacturing a second redistribution layer on the second wafer to connect the second bonding pad and the first through silicon via and form a second lead pad.

In an exemplary embodiment of the present disclosure, the fabricating the first through silicon via having a bottom connected to the first lead pad includes:

manufacturing a through hole at a position of the second wafer corresponding to the first lead pad, wherein the bottom of the through hole exposes the first lead pad;

and filling a conductive material in the through hole, wherein the conductive material comprises metal.

In an exemplary embodiment of the present disclosure, in the process of fabricating the through hole, a groove for forming the second rewiring layer is simultaneously fabricated.

According to a second aspect of the present disclosure, there is provided a wafer stack structure, comprising:

a first wafer having an upper surface including first pads configured to connect to a first signal;

a first redistribution layer on the first wafer, the first redistribution layer including a first wire electrically connected to the first pad, the first wire including a first lead pad;

a second wafer, the bottom surface of which is bonded to the first redistribution layer, the upper surface of which includes a second pad configured to connect to the first signal and corresponding to the first pad, and a first through-silicon via electrically connected to the first lead pad at the bottom;

and a second rewiring layer located above the second wafer and including a second wire electrically connected to the first through-silicon-via and the second pad, the second wire including a second lead pad.

In an exemplary embodiment of the disclosure, the first through silicon via is fabricated after the first wafer is bonded with the first redistribution layer.

According to a third aspect of the present disclosure, there is provided a chip stacking method comprising:

providing a wafer stack structure as described in any of the above;

and scribing and cutting the wafer stacking structure to form a preset number of chips.

According to a fourth aspect of the present disclosure, there is provided a chip stacking structure comprising:

a first chip, an upper surface including a first pad configured to connect to a first signal;

a first redistribution layer on the first chip, the first redistribution layer including a first wiring electrically connected to the first pad, the first wiring including a first lead pad;

a second chip having a bottom surface bonded to the first redistribution layer and an upper surface including a second pad arranged to connect to the first signal and corresponding to the first pad and a first through-silicon-via electrically connected to the first lead pad at a bottom portion;

and a second redistribution layer on the second chip and including a second wiring electrically connected to the first through-silicon-via and the second pad, the second wiring including a second lead pad.

In an exemplary embodiment of the disclosure, the first through silicon via is fabricated after the first chip is bonded with the first redistribution layer.

According to a fifth aspect of the present disclosure, there is provided a wafer stacking method comprising:

providing a first wafer comprising a first pad configured to be connected to a first signal;

sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer comprises a first wiring electrically connected to the first pad, the first upper redistribution layer comprises a second wiring electrically connected to the first wiring, and the second wiring comprises a first lead pad;

bonding a second wafer on the first upper redistribution layer, the second wafer including a second pad arranged to connect the first signal and corresponding in position to the first pad;

two redistribution layers are fabricated on the second wafer to connect the second pad and the first through-silicon-via and form a second lead pad.

In an exemplary embodiment of the present disclosure, in the process of fabricating the through hole, a groove for forming a second lower heavy wiring layer is simultaneously fabricated.

In an exemplary embodiment of the present disclosure, the fabricating two redistribution layers on the second wafer to connect the second pad and the first through-silicon-via and form a second lead pad includes:

fabricating a second lower redistribution layer on the second wafer, the second lower redistribution layer including a third wire electrically connected to the first through-silicon-via and the second pad;

and manufacturing a second upper redistribution layer on the second lower redistribution layer, wherein the second upper redistribution layer comprises a fourth wiring electrically connected to the third wiring, and the fourth wiring comprises the second lead pad.

According to a sixth aspect of the present disclosure, there is provided a wafer stack structure comprising:

a first lower redistribution layer on the first wafer, including first wires electrically connected to the first pads;

a first upper redistribution layer on the first lower redistribution layer, including a second wiring electrically connecting the first wiring, the second wiring including a first lead pad;

a second wafer, the bottom surface of which is bonded to the first upper redistribution layer, the upper surface of which is provided with a second bonding pad connected with the first signal and corresponding to the first bonding pad, and a first through silicon via electrically connected to the first lead pad at the bottom;

a second lower rewiring layer located above the second wafer and including a third wire electrically connected to the second pad and the first through-silicon-via;

a second upper redistribution layer on the second lower redistribution layer, including a fourth wiring electrically connecting the third wiring, the fourth wiring including a second lead pad.

In an exemplary embodiment of the present disclosure, the first through silicon via is fabricated after the first wafer is bonded to the first upper redistribution layer.

According to a seventh aspect of the present disclosure, there is provided a chip stacking method comprising:

providing a wafer stack structure as described in any of the above;

According to an eighth aspect of the present disclosure, there is provided a chip stacking structure comprising:

a first lower redistribution layer on the first chip, including a first wiring electrically connected to the first pad;

the bottom surface of the second chip is bonded with the first upper heavy wiring layer, and the upper surface of the second chip is provided with a second bonding pad which is connected with the first signal and corresponds to the first bonding pad in position and a first silicon through hole of which the bottom is electrically connected with the first lead pad;

a second lower rewiring layer located above the second chip and including a third wire electrically connected to the second pad and the first through-silicon-via;

In an exemplary embodiment of the present disclosure, the first through silicon via is fabricated after the first chip is bonded to the first upper redistribution layer.

According to the wafer stacking method and the wafer stacking structure, through the mode of firstly bonding the wafer and then manufacturing the TSV, series connection between the same signal bonding pads at the same positions of the wafer is achieved through the one or two layers of the redistribution layers, the errors of mechanical alignment and electric connection of the TSV in the related technology can be avoided, series connection of signals of the bonding pads at the same positions of different wafer layers can be achieved only through mechanical connection between the wafers, salient points do not need to be manufactured, negative effects of the salient points on yield are reduced, manufacturing cost of chips of the stacking structure is reduced, and yield is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1A and 1B are schematic views of a chip stack structure in the related art.

Fig. 2 is a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure.

Fig. 3A to 3E schematically illustrate wafer stacking structures formed by stacking wafers in exemplary embodiments of the present disclosure.

FIG. 4 is a diagram of a wafer stack structure in accordance with one embodiment.

Fig. 5 is a flow chart of another wafer stacking method in an exemplary embodiment of the present disclosure.

FIGS. 6A-6F are schematic views illustrating a wafer stacking structure formed by the wafer stacking method shown in FIG. 5.

Fig. 7A and 7B are top views of the wafer stack structure shown in fig. 6F.

FIG. 8 is a diagram illustrating a wafer stack structure in accordance with one embodiment.

Fig. 9 is a flow chart of a chip stacking method in an exemplary embodiment of the disclosure.

Fig. 10 is a schematic diagram of the chip stacking method shown in fig. 9.

Fig. 11 is a schematic diagram of a chip stack structure in an exemplary embodiment of the disclosure.

Fig. 12 is a schematic diagram of yet another chip stack structure in an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, structures, steps, and so forth. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and/or processor structures and/or microcontroller structures.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Fig. 2 schematically illustrates a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure. Referring to fig. 2, a wafer stacking method 100 may include:

step S102, providing a first wafer, wherein the upper surface of the first wafer comprises a first bonding pad which is connected with a first signal;

step S104, manufacturing a first redistribution layer on the first wafer, wherein the first redistribution layer comprises a first wiring electrically connected to the first pad, and the first wiring comprises a first lead pad;

step S106, bonding a second wafer on the first redistribution layer, wherein the second wafer comprises a second bonding pad which is set to be connected with the first signal and corresponds to the first bonding pad in position;

step S108, manufacturing a first silicon through hole with the bottom connected to the first lead pad at the position, corresponding to the first lead pad, of the second wafer;

step S110, a second redistribution layer is fabricated on the second wafer to connect the second pad and the first tsv and form a second lead pad.

Fig. 3A to 3E are schematic process diagrams illustrating a wafer stacking structure manufactured by the wafer stacking method shown in fig. 2.

Fig. 3A shows the first wafer 10 provided in step S102, the first bonding pads P1-S1 connected to the first signal S1 are disposed on the top surface.

Fig. 3B illustrates step S104 of fabricating a first redistribution layer 11 on the first wafer 10, in which the first redistribution layer 11 is provided with first wirings C1-S1, and a first lead pad PV1 is provided on the upper surface of the first redistribution layer. The first wiring may be a metal structure, such as copper.

Although fig. 3A-3E illustrate embodiments in which the first wafer 10 does not include TSVs, it is understood that the first wafer 10 may include TSVs electrically connected to the first signals in other embodiments, and accordingly, the first wires are connected to the TSVs.

In the embodiment shown in fig. 3B, the distance between the first lead pad PV1 and the first pad P1-S1 in the horizontal direction is L1, and L1 ≠ 0, and those skilled in the art can set the direction of the relative position of the first lead pad PV1 and the first pad P1-S1 by themselves.

Fig. 3C is a schematic diagram illustrating that the second wafer 20 is bonded to the first upper redistribution layer 11 in step S106. The upper surface of the second wafer 20 includes second pads P2-S1 configured to be connected to the first signal S1.

It will be understood by those skilled in the art that the bonding process may include first performing Chemical Mechanical Polishing (CMP) on the upper surface of the first redistribution layer, then activating the surface of the first redistribution layer using plasma, and finally bonding the second wafer on the activated surface, which will not be described herein.

In the embodiment shown in fig. 3C, a structure for isolating the first wirings C1-S1 from the second wafer 20 needs to be included between the second wafer 20 and the first re-wiring layer 11. For example, the C1-S1 may be isolated from the second wafer 20 by growing an oxide layer or other insulating layer on the upper surface of the first redistribution layer. Alternatively, in some embodiments, the positions of C1-S1 may be controlled to be lower than the upper surface of the first redistribution layer 11 at the time of fabrication. This approach may be achieved, for example, by depositing the dielectric material of the first redistribution layer again for C1-S1 after C1-S1 is fabricated using a damascene process, such that the dielectric material covers C1-S1 and exposes only the PV 1. Alternatively, the bottom of the second wafer may be subjected to an insulating treatment in advance. The interlayer insulation mode can be various, and the interlayer insulation mode can be set by a person skilled in the art according to the actual situation.

Fig. 3D is a schematic diagram of step S108. A first through-silicon via TSV1 is fabricated and filled in the second wafer 20 at a location corresponding to PV 1.

In some embodiments, step S106 may include: manufacturing a through hole at the position of the second wafer corresponding to the first lead pad, wherein the bottom of the through hole exposes the first lead pad; and filling a conductive material in the through hole, wherein the conductive material comprises metal.

Fig. 3E is a schematic diagram of step S110. Depositing a first medium on the second wafer and manufacturing a second wire connecting the second bonding pad and the first through silicon via to form a second rewiring layer.

Therefore, the first bonding pad is connected with the first wiring and the second bonding pad in series through the first through silicon via (TSV1), the second wiring and the second bonding pad, electric connection between the bonding pads can be achieved without the aid of bumps, and the problems that material leakage, false soldering, misalignment and the like are prone to being caused in the chip stacking process in the related technology are solved.

Referring to the steps shown in fig. 1, repeated operations are performed, and stacking of multiple layers of wafers and series connection between pads with the same position and the same connection signal in different layers of wafers can be realized only through one redistribution layer, as shown in fig. 4, so that the problems of material leakage, insufficient soldering, inaccurate alignment and the like generated in the process of electrically connecting the wafer stacking structures in the related art are avoided, and the yield is improved.

Fig. 5 is a flow chart of another wafer stacking method provided by the present disclosure.

Referring to fig. 5, a wafer stacking method 500 may include:

step S502, providing a first wafer, wherein the first wafer comprises a first bonding pad which is arranged to be connected with a first signal;

step S504, sequentially fabricating a first lower redistribution layer and a first upper redistribution layer on the first wafer, where the first lower redistribution layer includes a first wire electrically connected to the first pad, the first upper redistribution layer includes a second wire electrically connected to the first wire, and the second wire includes a first lead pad;

step S506, bonding a second wafer on the first upper redistribution layer, where the second wafer includes a second pad configured to connect to the first signal and having a position corresponding to the first pad;

step S508, fabricating a first through silicon via having a bottom connected to the first lead pad at a position of the second wafer corresponding to the first lead pad;

step S510, two redistribution layers are fabricated on the second wafer to connect the second pad and the first tsv and form a second lead pad.

Fig. 6A to 6E are wafer stack structures manufactured by the wafer stacking method shown in fig. 5.

Fig. 6A is the first wafer 10 provided in step S502, the upper surface of the first wafer 10 includes first pads P1-S1 configured to connect to the first signal S1.

Fig. 6B is a schematic diagram of sequentially manufacturing the first lower redistribution layer 11 and the first upper redistribution layer 12 on the first wafer 10 in step S504. The first lower rewiring layer 11 includes first wirings C1 to S1 electrically connected to the first pads P1 to S1, the first upper rewiring layer 12 includes second wirings C2 to S1 electrically connected to the first wirings C1 to S1, and the second wirings C2 to S1 include first lead pads PV 1. The first wiring and the second wiring may be, for example, metal structures.

Although fig. 6A-6E illustrate embodiments in which first wafer 10 does not include TSVs, it is understood that in other embodiments, first wafer 10 may include TSVs electrically connected to the first signals, and accordingly, the first lower redistribution layer and the first upper redistribution layer may include wires connected to the first signals.

In the embodiment shown in fig. 6B, the distance between the first lead pad PV1 and the first pad P1-S1 in the horizontal direction is L1, and L1 ≠ 0, and those skilled in the art can set the direction of the relative position of the first lead pad PV1 and the first pad P1-S1 by themselves.

Fig. 6C is a schematic diagram illustrating the step S506 of bonding the second wafer 20 to the first upper redistribution layer 12. The upper surface of the second wafer 10 includes second pads P2-S1 configured to also connect to the first signal S1.

It will be understood by those skilled in the art that the bonding process may include first performing Chemical Mechanical Polishing (CMP) on the upper surface of the first upper redistribution layer, then activating the surface of the first upper redistribution layer using plasma, and finally bonding a second wafer on the activated surface, which will not be described in detail herein.

In the embodiment shown in fig. 6C, a structure for isolating the second wire C2-S1 from the second wafer 20 needs to be included between the second wafer 20 and the first upper redistribution layer 12. For example, the C2-S1 may be isolated from the second wafer 20 by growing an oxide or other insulating layer on the upper surface of the first upper redistribution layer 12. Alternatively, in some embodiments, the position of C2-S1 may be controlled to be below the upper surface of the first upper redistribution layer 12 at the time of fabrication. This approach may be achieved, for example, by depositing the dielectric material of the first upper redistribution layer 12 again on the C2-S1 after the C2-S1 is fabricated using a damascene process, such that the dielectric material covers the C2-S1 and exposes only the PV 1. Alternatively, the second wafer 20 or the bottom of the second wafer 20 may be subjected to an insulating process in advance. The interlayer insulation mode can be various, and the interlayer insulation mode can be set by a person skilled in the art according to the actual situation.

Fig. 6D is a schematic diagram of step S508. A first through-silicon via TSV1 is fabricated and filled in the second wafer 20 at a location corresponding to PV 1. In some embodiments, step S506 may include: manufacturing a through hole at the position of the second wafer corresponding to the first lead pad, wherein the bottom of the through hole is connected with the first lead pad; and filling a conductive material in the through hole, wherein the conductive material comprises metal.

Fig. 6E and 6F are schematic diagrams of step S110. A first dielectric is deposited on the second wafer 20 and a third wire C3-S1 connecting the second pad P2-S1 and the first through-silicon via PV1 is fabricated to form a second lower rewiring layer 21 (fig. 6D). Next, a second dielectric, which may be the same as or different from the first dielectric, for example, a different oxide, is deposited on the second lower heavy wiring layer 21 and fourth wiring C4-S1 and second lead pad PV2 electrically connecting the third wiring are fabricated to form a second upper heavy wiring layer 22. It is to be noted that a process of performing CMP on the deposition position (performing CMP on the second wafer 20 and the second lower redistribution layer 21) is further included before depositing the second lower redistribution layer 21 and the second upper redistribution layer.

Thus, in the embodiment, the connection between the first through silicon via and the pad is realized through the lower redistribution layer, that is, the signal of the first pad can be led out to the second wafer 20 without making a bump, so that the problems of material leakage, insufficient soldering, inaccurate alignment and the like easily caused in the wafer stacking process in the related art are avoided; the position of the lead pad is adjusted through the upper redistribution layer, so that more space can be provided for circuit design.

Fig. 7A and 7B are top views of a second lower rewiring layer and a second upper rewiring layer, respectively. Referring to fig. 7A, 7B, and 6F, on the same plane, a person skilled in the art can set the shape of the wiring by himself.

In other embodiments, the wafer stack structure may be fabricated by:

1. sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on a first wafer to lead out a signal of a first bonding pad to a first lead pad;

2. bonding a second wafer to the first upper redistribution layer;

3. depositing a first medium on the second wafer;

4. etching the through hole at the position of the second wafer and the first medium corresponding to the first lead pad;

5. etching a lead groove connected with the through hole and a lead groove connected with the second bonding pad in the first medium;

6. filling a conductive material in the through hole and the lead groove to form a first through silicon via and a third wiring and a second lower heavy wiring layer which are electrically connected with the first through silicon via and the second bonding pad;

7. performing CMP (chemical mechanical polishing) on the second lower heavy wiring layer;

8. depositing a second medium on the second lower heavy wiring layer;

9. and etching the lead groove on the second medium and filling the conductive material to form a fourth wiring, a second lead pad and a second upper heavy wiring layer which are electrically connected with the third wiring.

10. CMP is performed on the second upper redistribution layer.

It is understood that, although the embodiment of the present disclosure takes the pads connected to the same signal as an example, in other embodiments, the pads connected to other signals may be provided on the wafer of different layers, and the method and structure provided by the present disclosure may be applied as long as the pads connected to the same signal are corresponding in position in the vertical direction, as shown in fig. 8.

According to the embodiment of the disclosure, the wafers are bonded first, then the TSV is manufactured, and the bonding pads which are the same in relative position and are connected with the same signal in each layer of wafer are connected in series through one or two layers of redistribution layers (RDLs), so that mechanical alignment and electrical connection of the TSV to the signal of the lower layer can be realized at one time, and due to the fact that salient points do not need to be manufactured, the problem of reduction of yield caused by the related technology can be effectively avoided, and the manufacturing cost is reduced.

Fig. 9 is a schematic diagram of a chip stacking method provided by the present disclosure.

Referring to fig. 9, the chip stacking method may include:

step S91, providing the wafer stacking structure as described above;

step S92, dicing the wafer stack structure to form a predetermined number of chips.

Fig. 10 is a schematic diagram of the chip stacking method of fig. 9. Through the method shown in fig. 9, the chip with the structure shown in fig. 3E, fig. 4, fig. 6E, fig. 8 and the like can be manufactured, the chip does not have a bump structure, the interlayer is electrically connected through the redistribution layer and the TSV directly connected with the redistribution layer at the bottom, the reliability is high, and the problem that the chip in the related art is occasionally unstable in electrical connection can be avoided.

Fig. 11 and 12 are schematic diagrams of two chip stack structures.

Referring to fig. 11, the chip stack structure 110 may include:

a first chip 1 having an upper surface including first pads P1-S1 configured to connect a first signal S1;

a first re-wiring layer 2 on the first chip 1, including first wirings C1-S1 electrically connected to first pads P1-S1, the first wirings C1-S1 including first lead pads PV 1;

a second chip 3 having a bottom surface bonded to the first redistribution layer 2, an upper surface including second pads P2-S1 arranged to be connected to the first signal S1 and positioned to correspond to the first pads P1-S1, and a first through-silicon via TSV1 having a bottom electrically connected to the first lead pad PV 1;

the second rewiring layer 4, which is located over the second chip 3, includes second wirings C2-S1 electrically connected to the first through-silicon-via TSV1 and the second pads P2-S1, and the second wirings C2-S1 include second lead pads PV 2.

Referring to fig. 12, the chip stack structure 120 may include:

a first lower rewiring layer 2 located above the first chip 1 and including first wirings C1 to S1 electrically connected to first pads P1 to S1;

a first upper rewiring layer 3 located above the first lower rewiring layer 2 and including second wirings C2 to S1 electrically connecting the first wirings C1 to S1, the second wirings C2 to S1 including first lead pads PV 1;

a second chip 4 having a bottom surface bonded to the first upper redistribution layer 3, an upper surface provided with second pads P2-S1 connected to the first signal S1 and corresponding to the first pads P1-S1, and a first through-silicon via TSV1 having a bottom electrically connected to the first lead pad PV 1;

a second lower rewiring layer 5 on the second chip, including third wirings C3-S1 electrically connected to the second pads P2-S1 and the first through-silicon vias TSV 1;

the second upper rewiring layer 6, located above the second lower rewiring layer, includes fourth wirings C4 to S1 electrically connecting the third wirings C3 to S1, and the fourth wirings C4 to S1 include second lead pads PV 2.

Although the chip stack structure shown in fig. 11 and 12 includes only two layers of chips, it is understood that a person skilled in the art can set the number of layers of the chip stack according to practical requirements and the above embodiments, and the disclosure is not limited thereto.

It should be noted that the wafer stacking structure provided by the embodiments of the present disclosure is manufactured by the wafer stacking method provided by the embodiments of the present disclosure.

Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A wafer stacking method, comprising:

2. The wafer stacking method of claim 1, wherein the fabricating the first through-silicon-via having a bottom connected to the first lead pad comprises:

3. The wafer stacking method of claim 2, wherein a recess for forming a second redistribution layer is simultaneously formed during the through-hole formation.

4. A wafer stack structure, comprising:

5. A method of chip stacking, comprising:

providing the wafer stack structure of claim 4;

6. A chip stacking structure, comprising:

7. A wafer stacking method, comprising:

8. The wafer stacking method of claim 7, wherein the fabricating the first through-silicon-via having a bottom connected to the first lead pad comprises:

9. The wafer stacking method of claim 8, wherein a recess for forming a second lower heavy wiring layer is simultaneously formed in the process of forming the through hole.

10. The wafer stacking method of claim 7, wherein the fabricating two redistribution layers on the second wafer to connect the second pad and the first through-silicon-via and form a second lead pad comprises:

11. A wafer stack structure, comprising:

12. A method of chip stacking, comprising:

providing a wafer stack structure as recited in claim 11;

13. A chip stacking structure, comprising: