CN111261602A

CN111261602A - Interconnection method of semiconductor structure and semiconductor structure

Info

Publication number: CN111261602A
Application number: CN201811458490.4A
Authority: CN
Inventors: 吴秉桓
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-11-30
Filing date: 2018-11-30
Publication date: 2020-06-09

Abstract

The present disclosure provides an interconnection method for a semiconductor structure and a semiconductor structure. The interconnection method comprises the following steps: providing a stacked structure, wherein the stacked structure comprises a plurality of layers of bonded wafers or chips, each layer of the wafers or chips comprises a substrate and a wiring layer, and the wiring layer comprises a plurality of metal wires; forming through-silicon vias in the stacked structure, the through-silicon vias being connected to a first number of metal wires; performing insulation processing on a second number of metal wires connected with the through silicon vias, wherein the second number is smaller than the first number; and filling a conductive material in the through silicon via. The interconnection method disclosed by the invention can be used for manufacturing the semiconductor structure which enables each layer of wafer or chip in the stacked structure to be electrically connected through one mask etching process.

Description

Interconnection method of semiconductor structure and semiconductor structure

Technical Field

The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to an interconnection method of a semiconductor structure and a semiconductor structure.

Background

Stacking multiple chips and establishing mechanical and electrical connections is an important method of reducing the volume of an integrated circuit during its manufacture. In the current practice, a TSV (through silicon via) is usually fabricated for each chip to be stacked, a Bump (Micro-Bump) of each TSV is then formed, and finally, positioning bonding is performed in a wafer-to-wafer or wafer-to-wafer manner, so that electrical connection between an upper chip and a lower chip is achieved through each Bump and the TSV.

First, in the wafer-to-wafer or wafer-to-wafer bonding process, the inefficiency results in high costs. In addition, TSV needs to be made for each chip in advance, and bumps are made, so that the risk of positioning error and connection error is high in the bonding process, which easily causes disconnection of the electrical connection path between the upper and lower chips, and causes reduction of yield.

Therefore, there is a need for an inter-chip electrical connection solution that overcomes the above-mentioned problems.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide an interconnection method for a semiconductor structure and a semiconductor structure, which are used to overcome, at least to some extent, the problems of complicated manufacturing procedures, low yield, and the like of the semiconductor structure due to the limitations and disadvantages of the related art.

According to a first aspect of the present disclosure, there is provided an interconnection method of a semiconductor structure, comprising:

providing a stacked structure, wherein the stacked structure comprises a plurality of layers of bonded wafers or chips, each layer of the wafers or chips comprises a substrate and a wiring layer, and the wiring layer comprises a plurality of metal wires;

forming through-silicon vias in the stacked structure, the through-silicon vias being connected to a first number of the metal wires;

performing insulation processing on a second number of metal wires connected with the through silicon vias, wherein the second number is smaller than the first number;

and filling a conductive material in the through silicon via.

In an exemplary embodiment of the present disclosure, the forming of the through silicon via in the stacked structure includes:

vertically manufacturing m first blind holes H1n with a first diameter and a length L1n for the stacked structure, wherein the penetrating positions of each first blind hole in each layer of the wafer or chip are located between the metal wires, the first diameter is smaller than the spacing of the metal wires, L1n is smaller than the height L0 of the stacked structure, and n is a serial number;

etching a second blind hole H2n with a second diameter and a length L2n at the upper part of the first blind hole H1n, wherein the side wall of the second blind hole exposes the end faces of a first number of metal leads;

and filling a mask material in the second blind holes.

In an exemplary embodiment of the present disclosure, the insulating the second number of metal wires connected to the through silicon vias includes:

etching a third blind hole H3n with the second diameter and length L3n at the upper part of the second blind hole H2n, wherein the side wall of the third blind hole exposes the end face of the metal lead;

and carrying out insulation treatment on the end face of the metal wire in the third blind hole.

In an exemplary embodiment of the disclosure, the fabricating of the second blind hole H2n having the second diameter and the length L2n at the upper portion of the first blind hole H1n includes:

coating the interior of the m first blind vias and the upper surface of the stacked structure with a mask material;

dry etching the mask on the upper parts of the m first blind holes to remove the mask with the length of L2n from top to bottom in the first blind hole H1 n;

and manufacturing a second blind hole H2n with the second diameter and the length L2n at the position of the first blind hole H1n where the mask is removed, and enabling the side wall of the second blind hole to expose the end face of the metal wire.

In an exemplary embodiment of the present disclosure, the dry etching the mask on the upper portions of the m first blind vias to remove the mask having the length L2n from top to bottom in the first blind via H1n includes an operation of repeating the following steps:

removing a mask with the width of L3 on the upper surface of the stacked structure opposite to the first blind hole H1n through a photoetching process;

the mask having a length L2n is removed from above and below in the first blind hole H1n by a dry stripping process.

In an exemplary embodiment of the disclosure, the fabricating the second blind hole H2n having the second diameter and the length L2n at the portion where the mask is removed in the first blind hole H1n includes:

widening the part of the first blind hole H1n in x layers of the wafer or chip substrate to the second diameter through a first wet etching process, wherein the x layers of the wafer or chip substrate are within the length range of the first blind hole for removing the mask;

and widening the part of the first blind hole H1n in the wiring layer of the x layer of the wafer or chip to the second diameter by a second wet etching process to expose the end face of the metal wire, and forming a second blind hole H2 n.

In an exemplary embodiment of the present disclosure, the filling the conductive material in the through silicon via includes:

manufacturing dielectric isolation layers on the inner surfaces of the first blind hole and the second blind hole;

and etching the dielectric isolation layer at the position of the effective metal wire by a plasma dry etching process to expose the end face, part of the upper surface and the bottom of the first blind hole of the effective metal wire.

Sputtering seed metal to the inner walls and bottoms of the first blind hole and the second blind hole, wherein the seed metal comprises copper;

growing a metal within the first and second blind vias, the metal comprising copper.

In an exemplary embodiment of the present disclosure, further comprising:

grinding the bottom layer of the stacked structure to expose the conductive material filled at the bottom of the through silicon via;

and manufacturing a salient point on the surface of the conductive material.

In an exemplary embodiment of the present disclosure, a cross-sectional shape of the through silicon via includes a circle, a polygon, and an irregular pattern.

In an exemplary embodiment of the present disclosure, the insulation process includes processes of oxidizing, texturing, phase-changing, dry/wet etching, laser/high temperature destruction, coating an isolation layer, and the like, on the end surface of the metal wire.

According to a second aspect of the present disclosure, there is provided a semiconductor structure comprising:

a stacked structure comprising a plurality of layers of bonded wafers or chips, each layer of the wafers or chips comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires;

m through-silicon vias, fabricated in exemplary embodiments of the present disclosure, penetrating the stacked structure with a center of a penetration location on each layer of the wafer or chip located between the metal wires, the through-silicon vias comprising:

a first portion having a first diameter smaller than a pitch of the metal wires;

a second portion having a second diameter greater than the pitch of the metal wires, coupled to the upper surface of the first portion and aligned with the center of the first portion, sidewalls intersecting a first number of the metal wires;

and a third portion formed after and on the second portion by performing an invalidation process on a second number of the metal conductive lines on sidewalls of the second portion, the second number being less than the first number.

According to the interconnection method for the semiconductor structure, the blind hole penetrating through the stacking structure is manufactured on the bonded wafer or chip, the blind hole is enlarged through wet etching to expose the end face of the wire of the preset wafer or chip in the stacking structure, then insulation treatment is carried out on part of the end face of the wire, finally the blind hole is filled with the conductive material to form the TSV connected with the preset wire, the interconnection structure with the complexity of different wafers or chips can be manufactured through one-time etching process, and the problems that the manufacturing process is complex and the connection yield is low due to the fact that the bumps are used for achieving electric connection between the chips in the related art are solved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1A to 1D are a main flowchart and sub-flowcharts of step S2, step S3, and step S4, respectively, of an interconnection method in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic diagram of step S1.

Fig. 3 is a schematic diagram of step S21.

Fig. 4 is a flowchart of step S22.

Fig. 5 is a schematic diagram of step S221.

Fig. 6A to 6E are schematic diagrams of step S222.

Fig. 7A to 7D are schematic diagrams of step S223.

Fig. 8 is a schematic diagram of step S23.

Fig. 9 is a schematic diagram of step S31.

Fig. 10 is a schematic diagram of step S32.

Fig. 11 is a schematic diagram of step S41.

Fig. 12A to 12G are schematic diagrams of steps S42 to S45.

Fig. 13 is a schematic diagram of a conductive path in a completed interconnect structure.

Fig. 14A to 14B are schematic diagrams of step S5.

Fig. 15 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Fig. 1A schematically illustrates a flow chart of a semiconductor interconnect method in an exemplary embodiment of the present disclosure. Referring to fig. 1A, the interconnection method 100 may include:

step S1, providing a stacked structure, wherein the stacked structure comprises a plurality of layers of bonded wafers or chips, each layer of the wafers or chips comprises a substrate and a wiring layer, and the wiring layer comprises a plurality of metal wires;

step S2, forming through silicon vias in the stacked structure, wherein the through silicon vias are connected with a first number of metal wires;

step S3, performing insulation processing on a second number of metal wires connected to the through-silicon vias, where the second number is smaller than the first number;

step S4, filling a conductive material in the through silicon via.

The steps of the interconnection method 100 are described in detail below.

Fig. 2 is a schematic diagram of the stacked structure 200 provided in step S1. It is understood that a process of fabricating the stacked structure 200 (e.g., bonding wafers or chips) may be included before fig. 2, and the disclosure is not repeated herein.

Referring to fig. 2, the stack structure may include a wafer stack structure and a chip stack structure, preferably a wafer stack structure. Each layer of wafer or chip in the stacked structure 200 includes a substrate a and a wiring layer B, and the wiring layer B includes a plurality of metal wires 21. In fig. 2, the wafers or chips are directly bonded, thereby avoiding the complicated process of fabricating TSV and then fabricating bumps in the related art.

Fig. 3 to 8 are schematic diagrams illustrating the formation of the through silicon via on the stacked structure 200 in step S2.

Referring to fig. 1B, in some embodiments, forming the through silicon via for the stacked structure 200 may include:

step S21, vertically manufacturing m first blind holes with a first diameter and a length of L1n for the stacked structure, wherein the penetrating position of each first blind hole in each layer of the wafer or chip is located between the metal wires, the first diameter is smaller than the distance between the metal wires, L1n is smaller than the height L0 of the stacked structure, and n is a serial number;

step S22, etching a second blind hole H2n with a second diameter and a length L2n at the upper part of the first blind hole H1n, wherein the side wall of the second blind hole exposes the end faces of the first number of metal leads;

step S23, filling a mask material in the second blind via.

Fig. 3 is a schematic diagram of vertically fabricating m first blind vias H1n having a first diameter D1n and a length L1n for the stacked structure in step S21. Referring to fig. 3, each first blind via H1n is located between the metal wires 21 at the penetrating position in each layer of wafer or chip, the first diameter D1n is smaller than the pitch DLn of the metal wires, and the length L1n of the first blind via is smaller than the height L0 of the stacked structure. The first diameter D1n of each first blind hole may be determined according to the distance DLn between the corresponding metal wires, as long as the difference between D1n and DLn is greater than the predetermined safety distance to avoid etching the metal wires.

The first blind via can be formed by a photoresist coating, photolithography, development, etching, and other related processes, for example, and the disclosure is not limited thereto.

Fig. 4 is a flowchart of step S22 etching a second blind via having a second diameter and a length L2n in an upper portion of the first blind via H1 n.

Referring to fig. 4, step S22 may include:

step S221, coating a mask material on the inside of the m first blind vias and the upper surface of the stacked structure;

step S222, carrying out dry etching on the masks at the upper parts of the m first blind holes so as to remove the masks with the length of L2n from top to bottom in the first blind holes H1 n;

step S223 is to fabricate a second blind via with the second diameter and the length L2n at the position of the first blind via H1n where the mask is removed, so that the side wall of the second blind via exposes the end surface of the metal wire.

FIG. 5 is a drawing showing the inner sum of step S221 for m first blind holesA schematic illustration of a mask 22 is applied to the upper surface of the stacked structure. The mask material may be, for example, SiN or SiO₂The coating mask may deposit the above-described materials to the inside of each first blind via and the upper surface of the stack structure by, for example, a CVD (Chemical vapor deposition) process to form an inorganic thin film.

Fig. 6A to 6E are schematic views of sequentially dry-etching the mask above the m first blind vias to remove the mask having a length L2n from top to bottom in the first blind via H1 n.

Referring to fig. 6A, first, a mask with a width Lw is removed from the upper surface of the stacked structure opposite to the nth first blind via by a photolithography process, for example, by applying a photoresist 23 to position the position where the mask is removed.

Referring to FIG. 6B, after the process shown in FIG. 6A, the mask having a length L2n is removed from above and below in the first blind via H1n by a dry stripping process. In this step, the mask removal length corresponding to each first blind via may be determined according to the layer number x of the wafer or chip to be connected.

Referring to fig. 6C to 6E, the above process is repeated until the dry etching of the m first blind vias is completed. In fig. 6C, the paste is repeatedly applied for photolithography; in FIG. 6D, the next first blind via is dry etched; in FIG. 6E, the photoresist is removed after all first blind vias have been dry etched.

Fig. 7A to 7D are schematic diagrams illustrating that in step S223, a second blind via H2n having a second diameter D2n and a length L2n is formed at a position where the mask is removed in each first blind via, so that the side wall of the second blind via H2n is exposed at the end face of the metal wire. Wherein the second diameter D2n is greater than the pitch DLn of its corresponding metal wire.

Referring to fig. 7A, first, the portion of the first blind via H1n in the x-layer wafer or chip substrate a may be widened to a second diameter D2n by a first wet etching process. The first wet etching support is, for example, a substrate a having a width D2n-D1n etched by pouring a first etching solution of a first preset dose into the first blind holes H1n, and the kind and dose of the first etching solution may be set according to the type of the substrate.

Referring to FIG. 7B, in FIG. 7AOn the basis of the manufacturing process, the portion of the first blind via H1n in the wiring layer B of the x-layer wafer or chip is widened to the second diameter D2n by the second wet etching process to expose the end face of the metal wire 21, so as to form a second blind via H2 n. The second wet etching process is performed by filling the first blind via H1n with a second etching solution with a second preset dosage to etch the dielectric portion of the wiring layer B with the width D2n-D1n, the type and dosage of the second etching solution can be set according to the type of the dielectric, such as SiO₂Or Si₃N₄。

In fig. 7A and 7B, the second diameter D2n may be determined according to the pitch DLn of the metal wires as long as the difference between D2n and DLn is within a preset range so as to expose the end surfaces of the metal wires 21.

FIGS. 7C and 7D are schematic cross-sectional views of the second blind hole H2n in the manufacturing process shown in FIGS. 7A and 7B, respectively. Referring to FIG. 7C, in the process shown in FIG. 7A, the diameter of the blind via in substrate A is increased from small to large. Referring to fig. 7D, in the process shown in fig. 7B, after the diameter of the blind via is enlarged, a portion of the dielectric in the wiring layer B is etched away to expose the end surface of the metal wire 21. Although fig. 7C and 7D illustrate the cross-sectional shapes of the first and second blind holes as circles, in other embodiments of the present disclosure, the cross-sectional shapes of the first and second blind holes may further include polygons, irregular patterns, parallelogram (diamonds or squares), rounded quadrangles, and the like, which is not particularly limited by the present disclosure.

FIG. 8 is a schematic diagram of filling the second blind via with the mask material in step S23. The process of filling the mask material in step S23 is the same as that in step S221, and the disclosure is not repeated herein.

Fig. 9 and 10 are schematic diagrams illustrating the step S3 of performing an insulation process on the metal wire connected to the through silicon via.

Referring to fig. 1C, in some embodiments, step S3 may include:

step S31, manufacturing a third blind hole with the second diameter and the length L3n at the upper part of the second blind hole H2n, wherein the side wall of the third blind hole exposes the end face of the metal lead;

and step S32, carrying out insulation treatment on the end face of the metal wire in the third blind hole.

Fig. 9 is a schematic diagram of step S31 of fabricating a third blind hole having the second diameter and length L3n on the upper portion of the second blind hole H2 n. The length of the third blind holes made in different second blind holes is not exactly the same for different wire connection schemes. The mask filled in the second blind via can be etched by a dry etching process to form a third blind via.

Fig. 10 is a schematic view of the step S32 of performing insulation processing on the end face of the metal wire in the third blind via. If the sidewalls of the second blind holes expose the first number of metal wires, the second number of metal wires may be insulated in this step, where the second number is smaller than the first number, to form third blind holes having a length smaller than that of the second blind holes. In order to avoid the influence on the implementation of the wire connection scheme caused by the fact that the wire exposed at the upper part of the second blind hole participates in the conduction, in the step, the metal wire can be subjected to insulation treatment in insulation treatment modes such as oxidation, quality change, phase change, dry/wet etching, laser/high temperature damage, coating of an isolation layer and the like. For example, each third blind hole is filled with an ineffective solution to insulate the end face of the metal wire exposed from the side wall of the third blind hole. The ineffective solution can be various, the embodiment of the present disclosure is completed by using hydrogen peroxide solution, and the skilled person can set the insulation treatment method according to the actual situation.

Fig. 11 to 12G are schematic diagrams illustrating a process of filling the through silicon via with a conductive material in step S4.

Referring to fig. 1D, in some embodiments, step S4 may include:

step S41, removing the mask materials in the first blind hole and the second blind hole;

step S42, forming dielectric isolation layers on inner surfaces of the first blind via, the second blind via, and the third blind via;

step S43, etching the dielectric isolation layer at the effective metal wire position by a plasma dry etching process to expose the end face, part of the upper surface and the bottom of the first blind hole of the effective metal wire;

step S44, sputtering seed metal including copper on the inner walls and bottoms of the first, second, and third blind vias;

step S45, growing a metal in the first blind via, the second blind via, and the third blind via, the metal including copper.

Fig. 11 is a schematic diagram of removing the mask material in the first blind via, the second blind via, and the third blind via in step S41.

Referring to fig. 11, when the ineffective treatment of the metal wire is performed by the ineffective solution, the respective blind holes may be first water-washed and then heated to remove the ineffective solution. Then, the mask material of each blind hole is removed by using a wet etching process with different selection ratios of materials. Further, the removal of the entire mask and the ineffective solution may be performed by other methods, which are not particularly limited by the present disclosure.

Fig. 12A to 12G are schematic diagrams illustrating steps S42 to S45 of filling conductive material in the first, second and third blind vias.

In fig. 12A, to fill the first, second and third blind holes with conductive material, a dielectric isolation layer 24 is first formed on the inner surfaces of the first, second and third blind holes. The dielectric isolation layer 24 can be formed, for example, by depositing an isolation dielectric such as SiCN on the surface of the etched material by a chemical vapor deposition process, so that the dielectric isolation layer 24 covers the inner surfaces of the first blind via H1n, the second blind via H2n, and the third blind via H3n and the upper surface of the stacked structure.

In fig. 12B, the dielectric isolation layer is etched to expose the end surface of the metal wire 21 and the bottom of the first blind via.

FIG. 12C is an enlarged view of the process shown in FIG. 12B. Referring to fig. 12C, the dielectric isolation layer 24 at the metal wire position may be etched by a plasma dry etching process to expose the end surface, a portion of the upper surface and the bottom of the first blind via H1n of the effective metal wire 21. At this time, the dielectric isolation layer covering the lower surface of the metal wire and the side wall of the second blind hole cannot be seen from the section of the second blind hole at the metal wire position.

Fig. 12D is a schematic view of sputtering seed metal 25 to the inner walls and bottoms of the first blind via, the second blind via, and the third blind via, the seed metal 25 including, for example, copper. FIG. 12E is an enlarged view of the process shown in FIG. 12D. Referring to fig. 12E, the sputtering locations of the seed metal 25 may include the sidewalls of the first, second and third blind holes, the top and side surfaces of the end surface of the metal wire, and the bottom of the first blind hole, so that the tantalum or copper can be re-coated on the metal wire to enable the subsequently filled copper to be connected to the metal.

Fig. 12F is a schematic illustration of growing metal 26, such as copper or tungsten, in the first, second and third blind vias, such as electroplating.

FIG. 12G is a cross-sectional top view of the process shown in FIG. 12F.

Referring to fig. 14, by insulating the metal wires on the upper portion of the second blind via, the wires are prevented from participating in the conduction, and a complex interconnection structure in a multilayer wafer or chip can be realized.

Fig. 14A-14B are schematic diagrams of yet another step S5 of the interconnection method in one embodiment.

Step S5 may include grinding the bottom layer of the stacked structure to expose the conductive material filled in the bottom of each through-silicon via as shown in fig. 14A, and forming a bump 27 on the surface of the conductive material as shown in fig. 14B. The process enables the fabrication of structures that interconnect with other stacked structures.

Through the manufacturing process, the different TSV formed at the same time can enable the metal wires in the wafers or chips at different layers to be electrically connected, the defects that the manufacturing process is complex, the cost is high, the yield is low and the like when the stacking structure is electrically connected through manufacturing the salient points in the related technology are overcome, and the manufacturing efficiency of the 3D integrated circuit is improved.

Referring to fig. 15, a semiconductor structure 1500 may include:

a stacked structure 151 including a plurality of layers of bonded wafers or chips, each layer of wafers or chips including a substrate and a wiring layer including a plurality of metal wires 152;

the m through-silicon vias TSV, which are manufactured by the interconnection method and penetrate through the stacked structure, are located between the metal wires at the center of the penetrating position on each layer of the wafer or chip, and comprise:

a first portion H1n having a first diameter D1n less than the pitch DLn of the metal wires;

a second portion H2n having a second diameter D2n greater than the pitch DLn of the metal wires, coupled to the upper surface of the first portion H1n and aligned with the center of the first portion H1n, sidewalls intersecting a first number of the metal wires 21;

a third portion H3n formed after the second portion H2n and over the second portion H2n by performing a nullifying process on a second number of the metal conductive lines on sidewalls of the second portion H2n, the second number being less than the first number.

The TSV body includes metals such as copper and tungsten, and the outer layer insulating material 153 includes tantalum, tantalum nitride, and silicon carbonitride. The cross section of the through-silicon via TSV includes, but is not limited to, a circle, a quadrangle (square, rectangle, parallelogram, diamond), a polygon, and other irregular patterns.

The semiconductor structure provided by the embodiment of the disclosure does not have the salient points among the chips, and can complete a plurality of metal interconnection structures for connecting the chips on different layers through one TSV process, thereby avoiding the problems of inaccurate alignment, connection defects and the like easily caused by electrical connection among the chips through the salient points in the related art, and improving the efficiency and yield of manufacturing the 3D integrated circuit.

Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method of interconnecting semiconductor structures, comprising:

and filling a conductive material in the through silicon via.

2. The interconnect method of claim 1, wherein said forming a through silicon via in said stack structure comprises:

and filling a mask material in the second blind holes.

3. The interconnection method of claim 2, wherein said insulating a second number of said metal lines connected to said through-silicon-vias comprises:

etching a third blind hole H3n with the second diameter and length L3n at the upper part of the second blind hole H2n, wherein the side wall of the third blind hole exposes the end faces of a second number of the metal wires;

4. The interconnection method of claim 2, wherein said fabricating a second blind hole H2n having a second diameter and a length L2n in an upper portion of said first blind hole H1n comprises:

5. The interconnection method of claim 4, wherein the dry etching the mask above the m first blind vias to remove the mask with length L2n from top to bottom in the first blind via H1n comprises repeating the operations of:

6. The interconnection method of claim 4, wherein said fabricating a second blind via H2n having a second diameter and said length L2n in said first blind via H1n where said mask is removed comprises:

7. The interconnect method of claim 3, wherein said filling conductive material in said through silicon via comprises:

removing the mask material in the first blind hole and the second blind hole;

manufacturing dielectric isolation layers on the inner surfaces of the first blind hole, the second blind hole and the third blind hole;

etching the dielectric isolation layer at the position of the effective metal wire by a plasma dry etching process to expose the end face, part of the upper surface and the bottom of the first blind hole of the effective metal wire;

sputtering seed metal to the inner walls and bottoms of the first blind hole, the second blind hole and the third blind hole, wherein the seed metal comprises copper;

growing a metal in the first, second, and third blind vias, the metal comprising copper.

8. The interconnect method of claim 1, further comprising:

and manufacturing a salient point on the surface of the conductive material.

9. The interconnection method of claim 1, wherein the cross-sectional shape of the through-silicon-via includes a circle, a polygon, and an irregular pattern.

10. The method of claim 1, wherein the insulating process comprises oxidation, qualitative change, phase change, dry/wet etching, laser/high temperature damage, and isolation layer coating of the end surface of the metal wire.

11. A semiconductor structure, comprising:

m through-silicon vias penetrating the stacked structure, the through-silicon vias located between the metal wires, the through-silicon vias including:

12. The semiconductor structure of claim 11, wherein the cross-sectional shape of the through-silicon-via comprises a circle, a polygon, and an irregular pattern.