CN111128973A - Wafer stacking method and wafer stacking structure - Google Patents
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- 239000004020 conductor Substances 0.000 claims description 8
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- 238000004519 manufacturing process Methods 0.000 abstract description 16
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- 239000011229 interlayer Substances 0.000 description 2
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- 238000005498 polishing Methods 0.000 description 2
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- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
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Abstract
本公开提供一种晶圆堆叠方法与结构。晶圆堆叠方法包括：提供第一晶圆，所述第一晶圆的上表面包括设置为连接第一信号的第一焊盘；在所述第一晶圆上顺次制作第一下重布线层和第一上重布线层，所述第一下重布线层包括连接所述第一焊盘的第一布线，所述第一上重布线层包括连接所述第一布线的第二布线，所述第二布线具有第一引线垫；将第二晶圆键合于所述第一上重布线层上，所述第二晶圆的上表面包括设置为连接第二信号且位置对应于所述第一焊盘的第二焊盘；对所述第二晶圆对应于所述第一引线垫的位置制作底部连接于所述第一引线垫的第一硅通孔。本公开提供的晶圆堆叠方法可以提高具有堆叠结构的芯片的制造良品率。
The present disclosure provides a wafer stacking method and structure. The wafer stacking method includes: providing a first wafer, the upper surface of which includes a first pad configured to connect a first signal; and sequentially fabricating a first lower rewiring on the first wafer layer and a first upper redistribution layer, the first lower redistribution layer includes a first wiring connected to the first pad, the first upper redistribution layer includes a second wiring connected to the first wiring, The second wiring has a first lead pad; the second wafer is bonded on the first upper redistribution layer, and the upper surface of the second wafer includes a structure arranged to connect the second signal and the position corresponding to the forming a second pad of the first pad; and forming a first through-silicon via with a bottom connected to the first lead pad on the second wafer at a position corresponding to the first lead pad. The wafer stacking method provided by the present disclosure can improve the manufacturing yield of chips having a stacked structure.
Description
Technical Field
The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a wafer stacking method capable of improving an electrical connection effect between chips, and a wafer stacking structure and a chip stacking structure manufactured by using the wafer stacking method.
Background
Stacking multiple chips and establishing mechanical and electrical connections is an important method of reducing the volume of an integrated circuit during its manufacture. As shown in fig. 1A and 1B, in general, a TSV (Through Silicon Vias) is formed for each chip to be stacked, a Bump (Micro-Bump) is formed for each TSV, and finally, positioning and bonding are performed in a wafer-to-wafer or wafer-to-wafer manner, so that the upper chip and the lower chip are electrically connected by using each Bump and the TSV.
First, in the wafer-to-wafer or wafer-to-wafer bonding process, the inefficiency results in high costs. In addition, TSV needs to be made for each chip in advance, and bumps are made, so that the risk of positioning error and connection error is high in the bonding process, which easily causes disconnection of the electrical connection path between the upper and lower chips, and causes reduction of yield.
Therefore, a chip stacking method capable of overcoming the above problems is required.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a wafer stacking method and a wafer stacking structure, which are used to overcome at least some of the disadvantages of high chip stacking cost, high connection error probability, and low yield due to the limitations and defects of the related art.
According to a first aspect of the present disclosure, there is provided a wafer stacking method comprising:
providing a first wafer, an upper surface of the first wafer comprising first pads configured to connect to first signals;
sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer comprises a first wire connected with the first bonding pad, the first upper redistribution layer comprises a second wire connected with the first wire, and the second wire is provided with a first lead pad;
bonding a second wafer on the first upper redistribution layer, wherein the upper surface of the second wafer comprises a second bonding pad which is arranged to be connected with a second signal and corresponds to the first bonding pad in position;
and manufacturing a first through silicon via with the bottom connected to the first lead pad at the position of the second wafer corresponding to the first lead pad.
In an exemplary embodiment of the present disclosure, the fabricating the first through silicon via having a bottom connected to the first lead pad includes:
manufacturing a through hole at a position of the second wafer corresponding to the first lead pad, wherein the bottom of the through hole exposes the first lead pad;
and filling a conductive material in the through hole, wherein the conductive material comprises metal.
In an exemplary embodiment of the present disclosure, in the process of fabricating the through hole, a groove for forming a second lower heavy wiring layer is simultaneously fabricated.
In an exemplary embodiment of the present disclosure, further comprising:
and sequentially manufacturing a second lower heavy wiring layer and a second upper heavy wiring layer on the second wafer, wherein the second lower heavy wiring layer comprises a third wiring connected to the first through silicon via and a fourth wiring connected to the second bonding pad, the second upper heavy wiring layer comprises a fifth wiring connected to the third wiring and a sixth wiring connected to the fourth wiring, and the fifth wiring and the sixth wiring respectively comprise a second lead pad and a third lead pad.
In an exemplary embodiment of the present disclosure, a distance L1 between the first lead pad and the first pad in a horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1 ≠ L3 ≠ 0.
According to a second aspect of the present disclosure, there is provided a wafer stack structure, comprising:
a first wafer having an upper surface including first pads configured to connect to a first signal;
a first lower redistribution layer on the first wafer, including first wires electrically connected to the first pads;
a first upper redistribution layer on the first lower redistribution layer, including a second wiring electrically connected to the first wiring, the second wiring having a first lead pad;
a second wafer, the bottom surface of which is bonded to the first upper redistribution layer, including a second pad configured to connect to a second signal and a first through-silicon-via having a bottom directly connected to the first lead pad;
a second lower rewiring layer located above the second wafer and including a third wire electrically connected to the first through-silicon-via and a fourth wire electrically connected to the second pad;
and a second upper redistribution layer located above the second lower redistribution layer, including a fifth wire electrically connected to the third wire and a sixth wire electrically connected to the fourth wire, wherein the fifth wire and the sixth wire respectively include a second lead pad and a third lead pad.
In an exemplary embodiment of the present disclosure, a distance L1 between the first lead pad and the first pad in a horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1 ≠ L3 ≠ 0.
In an exemplary embodiment of the disclosure, the first through silicon via is fabricated after the second wafer is bonded with the first upper redistribution layer.
According to a third aspect of the present disclosure, there is provided a chip stacking method comprising:
providing a wafer stack structure according to any one of the above;
and scribing and cutting the wafer stacking structure to form a preset number of chips with the stacking structures.
According to a third aspect of the present disclosure, there is provided a chip stacking structure comprising:
a first chip, an upper surface including a first pad configured to connect to a first signal;
a first lower redistribution layer on the first chip, including a first wiring electrically connected to the first pad;
a first upper redistribution layer on the first lower redistribution layer, including a second wiring electrically connected to the first wiring, the second wiring having a first lead pad;
a second chip having a bottom surface bonded to the first upper redistribution layer, and including a second pad configured to connect to a second signal and a first through-silicon-via having a bottom portion directly connected to the first lead pad;
a second lower rewiring layer located above the second chip and including a third wire electrically connected to the first through-silicon-via and a fourth wire electrically connected to the second pad;
and a second upper redistribution layer located above the second lower redistribution layer, including a fifth wire electrically connected to the third wire and a sixth wire electrically connected to the fourth wire, wherein the fifth wire and the sixth wire respectively include a second lead pad and a third lead pad.
In an exemplary embodiment of the present disclosure, a distance L1 between the first lead pad and the first pad in a horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1 ≠ L3 ≠ 0.
In an exemplary embodiment of the present disclosure, the first through silicon via is fabricated after the second chip is bonded to the first upper redistribution layer.
According to the wafer stacking method provided by the embodiment of the disclosure, through the mode of firstly bonding the wafers and then manufacturing the TSV and the use of the two redistribution layers, the signal extraction between the wafers is realized, the errors of mechanical alignment and electric connection on the TSV in the related technology can be avoided, the signal extraction of the bonding pads located at the same positions of the wafers of different layers can be realized only by manufacturing the mechanical connection between the wafers, the negative influence on the yield of the TSV electric connection through the salient points is reduced, the manufacturing cost is reduced, and the yield is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1A and 1B are schematic views of a chip stack structure in the related art.
Fig. 2 is a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure.
Fig. 3A to 3D are schematic views illustrating a wafer stacking structure formed by applying the wafer stacking method according to an exemplary embodiment of the disclosure.
FIG. 4 is a flow chart of a wafer stacking method in yet another embodiment.
Fig. 5A and 5B are schematic views of a wafer stack structure formed by the wafer stacking method shown in fig. 4.
FIG. 6 is a schematic diagram of a wafer stack structure in yet another embodiment.
Fig. 7A and 7B are top views of the wafer stack structure shown in fig. 5B.
Fig. 8 is a flow chart of a chip stacking method in an exemplary embodiment of the disclosure.
Fig. 9 is a schematic diagram of the chip stacking method shown in fig. 8.
Fig. 10 is a schematic diagram of a chip stack structure in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, structures, steps, and so forth. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and/or processor structures and/or microcontroller structures.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 2 schematically illustrates a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure. Referring to fig. 2, the wafer stacking method may include:
step S102, providing a first wafer, wherein the upper surface of the first wafer comprises a first bonding pad which is set to be connected with a first signal;
step S104, sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer comprises a first wire connected with the first bonding pad, the first upper redistribution layer comprises a second wire connected with the first wire, and the second wire is provided with a first lead pad;
step S106, bonding a second wafer on the first upper redistribution layer, wherein the upper surface of the second wafer comprises a second bonding pad which is set to be connected with a second signal and corresponds to the first bonding pad in position;
step S108, a first through silicon via having a bottom connected to the first lead pad is formed at a position of the second wafer corresponding to the first lead pad.
Fig. 3A to 3D are chip stack structure diagrams manufactured by the chip stack method shown in fig. 2.
Fig. 3A shows the first wafer 1 provided in step S102, the upper surface of which includes first pads P1-S1 configured to be connected to the first signal S1.
Fig. 3B is a schematic diagram of step S104 of fabricating a first lower redistribution layer 11 and a first upper redistribution layer 12 on the first wafer 10, where the first lower redistribution layer 11 includes first wirings C1-S1 electrically connected to first pads P1-S1, the first upper redistribution layer 12 includes second wirings C2-S1 electrically connected to first wirings C1-S1, and the second wirings include first lead pads PV1 on an upper surface of the first upper redistribution layer 12. The first wiring and the second wiring may be, for example, metal structures.
Although fig. 3A-3D illustrate an embodiment in which first wafer 10 does not include TSVs, it is understood that in other embodiments, first wafer 10 may also include TSVs electrically connected to other signals, and accordingly, first lower redistribution layer and first upper redistribution layer may include wires and lead pads connected to the other signals.
In the embodiment shown in fig. 3B, the distance between the first lead pad PV1 and the first pad P1-S1 in the horizontal direction is L1, and L1 ≠ 0, and those skilled in the art can set the direction of the relative position of the first lead pad PV1 and the first pad P1-S1 by themselves.
Fig. 3C is a schematic diagram illustrating the step S106 of bonding the second wafer 20 to the first upper redistribution layer 12. The upper surface of the second wafer 20 includes second pads P2-S2 disposed to be connected to the second signal S2 and corresponding in position to the first pads.
It will be understood by those skilled in the art that the bonding process may include first performing Chemical Mechanical Polishing (CMP) on the upper surface of the first upper redistribution layer, then activating the surface of the first upper redistribution layer using plasma, and finally bonding a second wafer on the activated surface, which will not be described in detail herein.
In the embodiment shown in fig. 3C, a structure for isolating the second wires C2-S1 from the second wafer is required between the second wafer and the first upper redistribution layer. For example, the C2-S2 may be isolated from the second wafer by growing an oxide or other insulating layer on the upper surface of the first upper redistribution layer. Alternatively, in some embodiments, the position of C2-S2 may be controlled to be below the upper surface of the first upper redistribution layer at the time of fabrication. This approach may be achieved, for example, by depositing the dielectric material of the first upper redistribution layer again on C2-S2 after C2-S2 is fabricated using a damascene process, such that the dielectric material covers C2-S2 and exposes only the PV 1. Alternatively, the second wafer or the bottom of the second wafer may be subjected to an insulating treatment in advance. The interlayer insulation mode can be various, and the interlayer insulation mode can be set by a person skilled in the art according to the actual situation.
Fig. 3D is a schematic diagram illustrating that, in step S108, a first through silicon via connected to the first lead pad at the bottom is formed at a position of the second wafer corresponding to the first lead pad. In some embodiments, the process of making the first through-silicon-via may include, for example: a through hole is formed in the second wafer at a position corresponding to the first lead pad, the bottom of the through hole is exposed out of the first lead pad, and then a conductive material, such as a metal, is filled in the through hole.
Therefore, the first bonding pad is electrically connected with the first silicon through hole through the first wiring and the second wiring, the signal of the first bonding pad can be led out to the second wafer without manufacturing a bump, and the problems of material leakage, insufficient soldering, inaccurate alignment and the like easily caused in the chip stacking process in the related technology are avoided.
Further, the wafer stacking method may also provide for subsequent stacking. Fig. 4 is a flow chart of a chip stacking method in yet another embodiment of the present disclosure. Referring to fig. 4, the wafer stacking method may further include:
step S110 of fabricating a second lower redistribution layer on the second wafer, and fabricating a third wiring connected to the first through-silicon-via and a fourth wiring connected to the second pad in the second lower redistribution layer;
in step S112, a second upper redistribution layer is formed on the second lower redistribution layer, and a fifth wiring connected to the third wiring and a sixth wiring connected to the fourth wiring are formed in the second upper redistribution layer to form a second lead pad electrically connected to the first signal and a third lead pad electrically connected to the second signal, respectively.
Fig. 5A and 5B are schematic diagrams of the steps shown in fig. 4.
Referring to fig. 5A, the second lower redistribution layer 21 and the third and fourth wirings C3-S1, C4-S2 are formed on the second wafer 20 by first forming a first tsv on the second wafer, depositing a first dielectric on the second wafer and the first tsv to form a second lower redistribution layer, and simultaneously forming a third wiring electrically connecting the first tsv and a fourth wiring electrically connecting the second pad in the second lower redistribution layer; the first dielectric may be deposited on the second wafer to form a second lower redistribution layer, through holes may be formed in the second wafer and the second lower redistribution layer at positions corresponding to the first lead pads, and a conductive material may be filled in the through holes to form first through-silicon vias electrically connected to the first lead pads at bottoms thereof, and finally third wires electrically connected to the first through-silicon vias and fourth wires electrically connected to the second pads may be formed in the second lower redistribution layer. That is, for the multi-layer chip stack, the first through-silicon-via may be fabricated before the formation of the second lower redistribution layer or after the formation of the second lower redistribution layer, which is not particularly limited by the present disclosure. Wherein the first dielectric is, for example, an oxide.
Referring to fig. 5B, in order to prepare for the next wafer stacking, a second upper redistribution layer 21 may be further provided, and positions corresponding to lead pads for connecting respective signals are adjusted by fifth and sixth wirings, so as to provide conditions for signal extraction of pads with the same relative positions.
After the fifth and sixth wirings C5-S1 and C6-S2 are formed, a distance L1 between the first lead pad PV1 and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad PV3 and the first pad in the horizontal direction, and L1 ≠ L3 ≠ 0. Although the positions of the first lead pad and the third lead pad are aligned in the embodiments of the present disclosure to facilitate stacking and signal leading of wafers provided with the same circuit or the same kind of pad, in other embodiments, a person skilled in the art may also stack wafers with different circuits and adjust the positions of the lead pads to provide a larger design space, which is not limited by the present disclosure.
In this way, when the chip layers are stacked again with reference to steps S104 to S112, the structure shown in fig. 6 may be formed, that is, after the third wafer (the upper surface is provided with the third pads P3-S3 connected to the third signal S3) is bonded to the second upper redistribution layer 22, the second through-silicon vias TSV2 and the third through-silicon vias TSV3 are fabricated, and the third lower redistribution layer and the third upper redistribution layer are fabricated on the through-silicon vias to form the wirings capable of guiding the signals S1, S2, S3 connected to the pads to the uppermost layers (PV4, PV5, PV 6). In the embodiment of the present disclosure, S1, S2, S3 are chip select signals, for example.
Fig. 7A and 7B are top views of a second lower rewiring layer and a second upper rewiring layer, respectively. Referring to fig. 7A, 7B, and 5B, on the same plane, a person skilled in the art can set the shape of each wiring by himself.
In other embodiments, the chip stack structure may be fabricated by:
1. manufacturing two layers of redistribution layers on a first wafer to lead out signals of a first bonding pad to a first lead pad;
2. bonding a second wafer to the first upper redistribution layer;
3. depositing a first medium on the second wafer to form a second lower heavy wiring layer;
4. etching through holes at positions of the second wafer and the second lower heavy wiring layer corresponding to the first lead pads;
5. etching a lead slot connected with the through hole and a lead slot connected with the second bonding pad in the second lower heavy wiring layer;
6. filling a conductive material in the through hole and the lead groove to form a first through silicon via, a third wiring electrically connected to the first through silicon via, and a fourth wiring electrically connected to the second pad;
7. performing CMP (chemical mechanical polishing) on the second lower heavy wiring layer;
8. depositing a second dielectric on the second lower redistribution layer to form a second upper redistribution layer;
9. and etching the lead groove on the second upper redistribution layer and filling the conductive material to form a fifth wiring and a second lead pad which are electrically connected with the third wiring, and a sixth wiring and a third lead pad which are electrically connected with the fourth wiring.
10. CMP is performed on the second upper redistribution layer.
In the above process, the first dielectric and the second dielectric are both oxide, for example, and the materials of the two may be the same or different.
According to the embodiment of the disclosure, through bonding the wafer and then manufacturing the TSV, and guiding signals of the chip bonding pads of each layer with the same relative position to the uppermost layer through the two redistribution layers (RDLs), mechanical alignment and electrical connection of the TSV to signals of the lower layer can be realized at one time, and due to the fact that salient points do not need to be manufactured, the problem of reduction of yield caused by the related technology can be effectively avoided, and the manufacturing cost is reduced.
Fig. 8 is a flowchart of a chip stacking method according to an embodiment of the disclosure.
Referring to fig. 8, the chip stacking method may include:
step S81, providing a wafer stacking structure according to the above embodiment;
step S82, performing dicing and cutting on the wafer stack structure to form a preset number of chips with stack structures.
Fig. 9 is a schematic diagram of a chip manufactured using the chip stacking method shown in fig. 8, i.e., a wafer stack structure fabricated according to the above method embodiment is subjected to dicing and cutting to form unpackaged bare chips. It should be noted that the wafer stacking structure provided by the present disclosure includes the structure shown in fig. 3D or fig. 5B.
Fig. 10 is a schematic diagram of the chip structure fabricated in fig. 9.
Referring to fig. 10, the chip structure 100 may include:
a first chip 1 having an upper surface including first pads P1-S1 configured to connect a first signal S1;
a first lower rewiring layer 2 located above the first chip 1 and including first wirings C1 to S1 electrically connected to first pads P1 to S1;
a first upper rewiring layer 3 located above the first lower rewiring layer, including second wirings C2-S1 electrically connected to the first wirings C1-S1, the second wirings C2-S1 having first lead pads PV 1;
a second chip 4 bottom-bonded to the first upper redistribution layer 3, including second pads P2-S2 configured to connect to a second signal S2 and a first through-silicon via TSV1 with its bottom directly connected to the first lead pad PV 1;
a second lower rewiring layer 5 located over the second chip 4, including third wirings C3-S1 electrically connected to the first through-silicon vias TSV1 and fourth wirings C4-S2 electrically connected to the second pads P2-S2;
the second upper heavy wiring layer 6, which is located above the second lower heavy wiring layer 5, includes fifth wirings C5-S1 electrically connected to the third wirings C3-S1 and sixth wirings C6-S2 electrically connected to the fourth wirings C4-S2, and the fifth wirings C5-S1 and the sixth wirings C6-S2 include second and third lead pads PV2 and PV3, respectively.
Although fig. 10 shows a stacked structure including only two layers of chips, it is understood that a person skilled in the art can set the number of layers of stacked chips according to actual requirements and the structure shown in fig. 10, and the disclosure is not limited thereto.
The chip shown in fig. 10 does not have a bump structure, and the chips are electrically connected through the redistribution layer and the TSV with the bottom directly connected with the redistribution layer, so that the reliability is high, and the problem of unstable electrical connection of the chips in the related art can be avoided.
Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100090304A1 (en) * | 2008-09-08 | 2010-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding process for cmos image sensor |
| US20130260556A1 (en) * | 2012-03-27 | 2013-10-03 | International Business Machines Corporation | Bottom-up plating of through-substrate vias |
| CN209401620U (en) * | 2018-11-01 | 2019-09-17 | 长鑫存储技术有限公司 | Stacked wafer structure and chip stack structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100090304A1 (en) * | 2008-09-08 | 2010-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding process for cmos image sensor |
| US20130260556A1 (en) * | 2012-03-27 | 2013-10-03 | International Business Machines Corporation | Bottom-up plating of through-substrate vias |
| CN209401620U (en) * | 2018-11-01 | 2019-09-17 | 长鑫存储技术有限公司 | Stacked wafer structure and chip stack structure |
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