CN208954984U - Stacked wafer structure and chip stack structure - Google Patents
Stacked wafer structure and chip stack structure Download PDFInfo
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- CN208954984U CN208954984U CN201821792445.8U CN201821792445U CN208954984U CN 208954984 U CN208954984 U CN 208954984U CN 201821792445 U CN201821792445 U CN 201821792445U CN 208954984 U CN208954984 U CN 208954984U
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Abstract
The disclosure provides a kind of stacked wafer structure and chip stack structure.Stacked wafer structure includes: the first wafer, and upper surface includes the first pad for being set as the first signal of connection；First reroutes layer, is located on first wafer, and the first wiring including being electrically connected to first pad, first wiring includes first lead pad；Second wafer, bottom surface are bonded to described first and reroute layer, and upper surface includes being set as connecting first signal and position corresponds to the second pad of first pad and bottom is electrically connected to the first through silicon via of the first lead pad；Second reroutes layer, is located on second wafer, and the second wiring including being electrically connected to first through silicon via and second pad, second wiring includes the second leadframe pad.The yields of the chip of manufacture stacked structure can be improved in the stacked wafer structure that the disclosure provides.
Description
Technical field
This disclosure relates to which ic manufacturing technology field, is electrically connected between capable of improving wafer in particular to one kind
The stacked wafer structure of effect and the chip stack structure for using the stacked wafer structure fabrication.
Background technique
In ic manufacturing process, multiple chips are stacked and established with mechanical connection and electrical connection is to reduce collection
At the important method of circuit volume.Existing way is as shown in FIG. 1A and 1B, each chip manufacturing usually first stacked to needs
TSV (Through Silicon Vias, through silicon via), then forms the salient point (Micro-Bump) of each TSV, finally uses piece
Positioning bonding is carried out to the mode of wafer to piece or piece, realizes being electrically connected for upper layer chip and lower layer chip using each salient point and TSV
It connects.
Firstly, low efficiency causes at high cost in piece in bonding process to wafer of piece or piece.In addition, it is necessary to right in advance
Each chip manufacturing TSV, and salient point is made, positioning fault, the risk of connection fault are larger in bonding process, are easy to cause up and down
Electrical connection access between layer chip disconnects, and yields is caused to decline.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure is designed to provide a kind of stacked wafer structure and chip stack structure, at least to a certain degree
On overcome caused by the limitation and defect due to the relevant technologies chip to be stacked into this height, connection fault probability is big, yields is low
The disadvantages of.
According to the disclosure in a first aspect, providing a kind of stacked wafer structure, comprising:
First wafer, upper surface include the first pad for being set as the first signal of connection；
First reroutes layer, is located on first wafer, the first wiring including being electrically connected to first pad,
First wiring includes first lead pad；
Second wafer, bottom surface are bonded to described first and reroute layer, and upper surface includes being set as connecting first signal
And position is electrically connected to the first through silicon via of the first lead pad corresponding to the second pad of first pad and bottom；
Second reroutes layer, is located on second wafer, including is electrically connected to first through silicon via and described the
Second wiring of two pads, second wiring includes the second leadframe pad.
In an exemplary embodiment of the disclosure, first through silicon via is made in first wafer and first weight
After wiring layer bonding.
According to the second aspect of the disclosure, a kind of chip stack structure is provided, comprising:
First chip, upper surface include the first pad for being set as the first signal of connection；
First reroutes layer, is located on first chip, the first wiring including being electrically connected to first pad,
First wiring includes first lead pad；
Second chip, bottom surface are bonded to described first and reroute layer, and upper surface includes being set as connecting first signal
And position is electrically connected to the first through silicon via of the first lead pad corresponding to the second pad of first pad and bottom；
Second reroutes layer, is located on second chip, including is electrically connected to first through silicon via and described the
Second wiring of two pads, second wiring includes the second leadframe pad.
In an exemplary embodiment of the disclosure, first through silicon via is made in first chip and first weight
After wiring layer bonding.
According to the third aspect of the disclosure, a kind of stacked wafer structure is provided, comprising:
First wafer, upper surface include the first pad for being set as the first signal of connection；
First lower rewiring layer, is located on first wafer, the first cloth including being electrically connected to first pad
Line；
Layer is rerouted on first, be located at described first it is lower reroute on layer, the including being electrically connected first wiring
Two wirings, second wiring includes first lead pad；
Second wafer, bottom surface, which is bonded on described first, reroutes layer, upper surface be provided with connection first signal and
Position is electrically connected to the first through silicon via of the first lead pad corresponding to the second pad of first pad and bottom；
Second it is lower reroute layer, be located on second wafer, including be electrically connected to second pad and described the
The third of one through silicon via is routed；
Layer is rerouted on second, be located at described second it is lower reroute on layer, the including being electrically connected the third wiring
Four wirings, the 4th wiring includes the second leadframe pad.
In an exemplary embodiment of the disclosure, first through silicon via is made on first wafer and described first
After rewiring layer bonding.
According to the fourth aspect of the disclosure, a kind of chip stack structure is provided, comprising:
First chip, upper surface include the first pad for being set as the first signal of connection；
First lower rewiring layer, is located on first chip, the first cloth including being electrically connected to first pad
Line；
Layer is rerouted on first, be located at described first it is lower reroute on layer, the including being electrically connected first wiring
Two wirings, second wiring includes first lead pad；
Second chip, bottom surface, which is bonded on described first, reroutes layer, upper surface be provided with connection first signal and
Position is electrically connected to the first through silicon via of the first lead pad corresponding to the second pad of first pad and bottom；
Second it is lower reroute layer, be located on second chip, including be electrically connected to second pad and described the
The third of one through silicon via is routed；
Layer is rerouted on second, be located at described second it is lower reroute on layer, the including being electrically connected the third wiring
Four wirings, the 4th wiring includes the second leadframe pad.
In an exemplary embodiment of the disclosure, first through silicon via is made on first chip and described first
After rewiring layer bonding.
The stacked wafer structure and chip stack structure that the embodiment of the present disclosure provides, by first bonded wafer, make TSV again
Mode, reroute layer using one or two layers and realize series connection between the identical signal pad of wafer same position, can be to avoid
The fault of mechanical contraposition and electrical connection is carried out to TSV in the related technology, it is only necessary to make the connection of wafer room machine and can be realized and be located at
The series connection of the signal of the pad of different wafer layer same positions reduces salient point to the negative shadow of yields without making salient point
It rings, reduces the manufacturing cost of the chip of stacked structure, improve yields.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Figure 1A and Figure 1B is the schematic diagram of wafer iterative structure in the related technology.
Fig. 2 is the schematic diagram of stacked wafer structure in disclosure exemplary embodiment.
Fig. 3 A~Fig. 3 E schematically shows the schematic diagram of fabrication technology of stacked wafer structure in disclosure exemplary embodiment.
Fig. 4 is the schematic diagram of stacked wafer structure in one embodiment.
Fig. 5 is the schematic diagram of another stacked wafer structure in disclosure exemplary embodiment.
Fig. 6 A~Fig. 6 F is the schematic diagram of fabrication technology of stacked wafer structure shown in Fig. 5.
Fig. 7 A and Fig. 7 B are the top views of stacked wafer structure shown in Fig. 6 F.
Fig. 8 is the schematic diagram of stacked wafer structure in one embodiment.
Fig. 9 is a kind of schematic diagram of chip stack structure in disclosure exemplary embodiment.
Figure 10 is the schematic diagram of another chip stack structure in disclosure exemplary embodiment.
Figure 11 is the manufacturing process schematic diagram of chip stack structure shown in Fig. 9 and Figure 10.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used
Method, constituent element, structure, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and
So that all aspects of this disclosure thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, identical appended drawing reference indicates same or similar portion in figure
Point, thus repetition thereof will be omitted.Some block diagrams shown in the drawings are functional entitys, not necessarily necessary and object
The entity managed or be logically independent is corresponding.These functional entitys can be realized using software form, or in one or more
These functional entitys are realized in hardware module or integrated circuit, or in heterogeneous networks and/or processor structure and/or microcontroller
These functional entitys are realized in structure.
Disclosure example embodiment is described in detail with reference to the accompanying drawing.
Fig. 2 schematically shows the schematic diagram of stacked wafer structure in disclosure exemplary embodiment.
With reference to Fig. 2, stacked wafer structure 100 may include:
First wafer 10, upper surface include the first pad P1-S1 for being set as the first signal S1 of connection；
First reroutes layer 11, is located on the first wafer 10, the first wiring including being electrically connected to the first pad P1-S1
C1-S1, the first wiring C1-S1 include first lead pad PV1；
Second wafer 20, bottom surface are bonded to the first rewiring layer 11, upper surface include be set as the first signal S1 of connection and
Position is electrically connected to the first through silicon via of first lead pad PV1 corresponding to the second pad P2-S1 of the first pad P1-S1 and bottom
TSV1；
Second reroutes layer 21, is located on the second wafer 20, including is electrically connected to the weldering of the first through silicon via TSV1 and second
The second wiring C2-S1 of disk P2-S1, the second wiring C2-S1 includes the second leadframe pad PV2.
Fig. 3 A~Fig. 3 E is the manufacturing process schematic diagram using stacked wafer structure shown in Fig. 2.
Fig. 3 A is the first wafer 10, and upper surface is provided with the first pad P1-S1 of the first signal S1 of connection.
Fig. 3 B is that production first reroutes layer 11 on the first wafer 10, and the first rewiring layer 11 is provided with the first wiring
C1-S1, upper surface are provided with first lead pad PV1.Wherein, which can be metal structure, for example, copper.
Although Fig. 3 A~Fig. 3 E illustrates the embodiment that the first wafer 10 does not include TSV, it is to be understood that in other realities
Applying the first wafer 10 in example also may include the TSV for being electrically connected to first signal, correspondingly, the first wiring is connected with the TSV.
In the embodiment shown in figure 3b, first lead pad PV1 and the first pad P1-S1 is at a distance from the horizontal direction
L1, and L1 ≠ 0, those skilled in the art can pad the relative position of PV1 and the first pad P1-S1 with self-setting first lead
Direction.
Fig. 3 C is that the second wafer 20 is bonded to the schematic diagram that layer 11 is rerouted on first.The upper surface of second wafer 20
Including being set as being connected to the second pad P2-S1 of the first signal S1.
It will be appreciated by persons skilled in the art that bonding process may include the upper surface for rerouting layer to first first
(Chemical Mechanical Polishing, CMP) is chemically-mechanicapolish polished, then using plasma to the first weight
The surface of wiring layer is activated, and is finally bonded the second wafer in activating surface, the disclosure is repeated no more in this.
In Fig. 3 C illustrated embodiment, is rerouted between layer 11 in the second wafer 20 and first, need to include the first cloth of isolation
The structure of line C1-S1 and the second wafer 20.For example, can by first reroute layer upper surface grow oxide layer or other
Insulating layer is isolated C1-S1 and the second wafer 20.Alternatively, in some embodiments, the position of C1-S1 can be controlled in production
The upper surface of layer 11 is rerouted lower than first.This mode for example can by using Damascus technics make C1-S1 after,
The dielectric material for rerouting layer to C1-S1 deposition first again makes dielectric material covering C1-S1 and only exposes PV1.Alternatively,
Insulation processing can also be carried out in the bottom to the second wafer in advance.The mode of layer insulation can there are many, those skilled in the art
Member can self-setting according to the actual situation.
Fig. 3 D is the schematic diagram for making the first through silicon via TSV1 in the position corresponding to PV1 to the second wafer 20 and filling.
In some embodiments, through hole, through hole can be made in the position that the second wafer corresponds to first lead pad
Bottom expose first lead pad, next fill conductive material in the through hole, conductive material includes metal.
Fig. 3 E is to deposit first medium on the second wafer and make to connect the second of second pad and the first through silicon via
It is routed to form the schematic diagram of the second rewiring layer.
The first pad is connected by the first through silicon via (TSV1) and the first wiring, the second wiring with the second pad as a result, nothing
The electrical connection between pad need to can be realized by salient point, avoid the leakage that chip stacking process easily causes in the related technology
The problems such as material, rosin joint, inaccurate contraposition.
The step with reference to shown in Fig. 3 A~Fig. 3 E carries out repetitive operation, only can realize multilayer wafer by one layer of rewiring layer
Stacking and different layers wafer in position is identical, the series connection between the identical pad of connection signal, as shown in figure 4, thus keeping away
The problems such as having exempted from the material leakage generated during being electrically connected in the related technology to stacked wafer structure, rosin joint, inaccurate contraposition, mentions
Rate of good quality rate.
Fig. 5 is the schematic diagram for another stacked wafer structure that the disclosure provides.
With reference to Fig. 5, stacked wafer structure 500 may include:
First wafer 10, upper surface include the first pad P1-S1 for being set as the first signal S1 of connection；
First lower rewiring layer 11, is located on the first wafer 10, the first cloth including being electrically connected to the first pad P1-S1
Line C1-S1；
Layer 12 is rerouted on first, be located at first it is lower reroute on layer 11, the including the first wiring of electrical connection C1-S1
Two wiring C2-S1, the second wiring C2-S1 include first lead pad PV1；
Second wafer 20, bottom surface are bonded to rewiring layer 12 on first, and upper surface is provided with the first signal S1 of connection and position
Set the first through silicon via that first lead pad PV1 is electrically connected to corresponding to the second pad P2-S1 of the first pad P1-S1 and bottom
TSV1；
Second lower rewiring layer 21, is located on the second wafer 20, including be electrically connected to the second pad P2-S1 and the first silicon
The third of through-hole TSV1 is routed C3-S1；
Layer 22 is rerouted on second, be located at second it is lower reroute on layer 21, the including electrical connection third wiring C3-S1
Four wiring C4-S1, the 4th wiring C4-S1 includes the second leadframe pad PV2.
Fig. 6 A~Fig. 6 E is the manufacturing process schematic diagram of stacked wafer structure shown in fig. 5.
Fig. 6 A is the first wafer 10, and the upper surface of the first wafer 10 includes the first pad for being set as the first signal S1 of connection
P1-S1。
Fig. 6 B is that the signal that layer 12 is rerouted on layer 11, first is rerouted under sequentially making first on the first wafer 10
Figure.The first lower layer 11 that reroutes includes being electrically connected the first of the first pad P1-S1 to be routed C1-S1, reroutes layer 12 on first and wraps
The second the wiring C2-S1, the second wiring C2-S1 for including the first wiring of electrical connection C1-S1 includes first lead pad PV1.Wherein, first
Wiring and the second wiring for example can be metal structure.
Although Fig. 6 A~Fig. 6 E illustrates the embodiment that the first wafer 10 does not include TSV, it is to be understood that in other realities
Applying the first wafer 10 in example also may include the TSV for being electrically connected to the first signal, correspondingly, on the first lower rewiring layer and first
Rerouting layer may include the wiring being connected with the first signal.
In the embodiment shown in Fig. 6 B, first lead pad PV1 and the first pad P1-S1 is at a distance from the horizontal direction
L1, and L1 ≠ 0, those skilled in the art can pad the relative position of PV1 and the first pad P1-S1 with self-setting first lead
Direction.
Fig. 6 C is that the second wafer 20 is bonded to the schematic diagram that layer 12 is rerouted on first.The upper surface of second wafer 10
Including being set as being similarly coupled to the second pad P2-S1 of first signal S1.
It will be appreciated by persons skilled in the art that bonding process may include first to the upper table for rerouting layer on first
Face is chemically-mechanicapolish polished (Chemical Mechanical Polishing, CMP), then using plasma to first
The upper surface for rerouting layer is activated, and is finally bonded the second wafer in activating surface, the disclosure is repeated no more in this.
It in Fig. 6 C illustrated embodiment, is rerouted between layer 12 on the second wafer 20 and first, needs to include isolation second
It is routed the structure of C2-S1 and the second wafer 20.For example, can be by growing oxide layer to the upper surface for rerouting layer 12 on first
Or other insulating layers are isolated C2-S1 and the second wafer 20.Alternatively, in some embodiments, C2-S1 can be controlled in production
Position lower than the upper surface for rerouting layer 12 on first.This mode for example can be by making using Damascus technics
After C2-S1, again to the dielectric material for rerouting layer 12 in C2-S1 deposition first, makes dielectric material covering C2-S1 and only reveal
PV1 out.Alternatively, insulation processing can also be carried out the bottom to the second wafer 20 or the second wafer 20 in advance.The side of layer insulation
Formula can there are many, those skilled in the art can self-setting according to the actual situation.
Fig. 6 D is the schematic diagram for making the first through silicon via TSV1 in the position corresponding to PV1 to the second wafer 20 and filling.
In some embodiments, through hole can be made in the position that the second wafer corresponds to first lead pad, the bottom of through hole connects
Connect first lead pad；Conductive material is filled in through hole, conductive material includes metal.
Fig. 6 E and Fig. 6 F are to deposit first medium on the second wafer 20 and make to connect the second pad P2-S1 and first
The third wiring C3-S1 of through silicon via PV1 is to form the second lower schematic diagram for rerouting layer 21.Next, being rerouted under second
Second medium is deposited on layer 21 and makes the 4th wiring C4-S1 and the second leadframe pad PV2 for being electrically connected third wiring to be formed
Layer 22 is rerouted on second, which can be identical with first medium, can also be different, for example, different oxides.Value
It obtains it is noted that being rerouted on layer 21, second under deposition second further includes to deposition position progress CMP before rewiring layer
Process (carries out CMP to the second wafer 20 and the second lower layer 21 that reroutes).
In this way, the present embodiment realizes the connection of the first through silicon via and pad by rerouting layer under one, i.e., without system
It can be realized as salient point and the signal of the first pad be drawn out on the second wafer 20, avoid stacked wafer mistake in the related technology
The problems such as material leakage that journey easily causes, rosin joint, inaccurate contraposition；The tune to lead pad position is realized by a upper layer that reroutes
It is whole, more spaces can be provided for circuit design.
Fig. 7 A and Fig. 7 B are the second lower top view for rerouting rewiring layer on layer and second respectively.With reference to Fig. 7 A, Fig. 7 B
With Fig. 6 F, in the same plane, the shape that those skilled in the art can be routed with self-setting.
In further embodiments, stacked wafer structure can be made by following steps:
1. rerouting layer under sequentially making first on the first wafer, rerouting layer on first with by the signal of the first pad
It is drawn out to first lead pad；
2. the second wafer bonding is rerouted layer on first；
3. pair the second wafer deposits first medium；
4. the position that pair the second wafer and first medium correspond to first lead pad etches through hole；
5. etching connects the wire lead slot of the second pad of wire lead slot and connection of the through hole in first medium；
6. conductive material is filled in the through hole and the wire lead slot, to form the first through silicon via and be electrically connected to the first silicon
Through-hole, the third wiring of the second pad and the second lower rewiring layer；
7. pair second lower layer that reroutes carries out CMP (chemically mechanical polishing)；
8. pair second lower layer that reroutes deposits second medium；
9. pair second medium etch lead slot simultaneously fills conductive material, to form the 4th cloth for being electrically connected third wiring
Layer is rerouted on line, the second leadframe pad and second.
10. rerouting layer on pair second carries out CMP.
It is understood that although the embodiment of the present disclosure to be for connecting the pad of the same signal, in other embodiments
In, the wafer of different layers is also provided with the pad for connecting other signals, as long as connecting the pad of identical signal in Vertical Square
The method and structure that upward position correspondence can be provided using the disclosure, as shown in Figure 8.
The embodiment of the present disclosure passes through first bonded wafer and makes TSV again, and rerouting layer (RDL) by one or two layers will be each
Relative position is identical in layer crystal circle and the identical pad of connection signal is connected, and can once realize TSV to the machinery of lower layer signal
Contraposition and electrical connection, and due to being not necessarily to make salient point, it is possible to prevente effectively from the problem of yields caused by the relevant technologies declines, drop
Low manufacturing cost.
Fig. 9 and Figure 10 is the schematic diagram of two kinds of chip stack structures.
With reference to Fig. 9, chip stack structure 900 may include:
First chip 1, upper surface include the first pad P1-S1 for being set as the first signal S1 of connection；
First reroutes layer 2, is located on the first chip 1, the first wiring including being electrically connected to the first pad P1-S1
C1-S1, the first wiring C1-S1 include first lead pad PV1；
Second chip 3, bottom surface are bonded to the first rewiring layer 2, and upper surface includes being set as the first signal S1 of connection and position
Set the first through silicon via that first lead pad PV1 is electrically connected to corresponding to the second pad P2-S1 of the first pad P1-S1 and bottom
TSV1；
Second reroutes layer 4, is located on the second chip 3, including be electrically connected to the first through silicon via TSV1 and the second pad
The second wiring C2-S1 of P2-S1, the second wiring C2-S1 includes the second leadframe pad PV2.
With reference to Figure 10, chip stack structure 1000 may include:
First chip 1, upper surface include the first pad P1-S1 for being set as the first signal S1 of connection；
First lower rewiring layer 2, is located on the first chip 1, the first wiring including being electrically connected to the first pad P1-S1
C1-S1；
Layer 3 is rerouted on first, is located on the first lower rewiring layer 2, second including the first wiring of electrical connection C1-S1
It is routed C2-S1, the second wiring C2-S1 includes first lead pad PV1；
Second chip 4, bottom surface are bonded to rewiring layer 3 on first, and upper surface is provided with the first signal S1 of connection and position
The first through silicon via of first lead pad PV1 is electrically connected to corresponding to the second pad P2-S1 of the first pad P1-S1 and bottom
TSV1；
Second it is lower reroute layer 5, be located on the second chip, including be electrically connected to the second pad P2-S1 and the first silicon is logical
The third of hole TSV1 is routed C3-S1；
Layer 6 is rerouted on second, is located on the second lower rewiring layer, the 4th including electrical connection third wiring C3-S1
It is routed C4-S1, the 4th wiring C4-S1 includes the second leadframe pad PV2.
Although the chip stack structure shown in Fig. 9 and Figure 10 only includes layers of chips, it is to be understood that art technology
The number of plies that personnel can stack with above embodiments self-setting chip according to actual needs, the disclosure are not limited.
It is noted that the wafer that the stacked wafer structure that the embodiment of the present disclosure provides is provided by the embodiment of the present disclosure
Stacking method production.
Figure 11 is the schematic diagram of chip stack structure forming process in Fig. 9 and Figure 10.I.e. by proposing the embodiment of the present disclosure
The stacked wafer structure of confession carries out scribing and is cut to preset quantity chip.This chip does not have bump structure, interlayer
It is directly connected to reroute the TSV realization electrical connection of layer by rerouting layer and bottom, reliability with higher can be to avoid phase
In the technology of pass chip occasionally there are electrical connection instability problem.
In addition, above-mentioned attached drawing is only the schematic theory of processing included by method according to an exemplary embodiment of the present invention
It is bright, rather than limit purpose.It can be readily appreciated that the time that above-mentioned processing shown in the drawings did not indicated or limited these processing is suitable
Sequence.In addition, be also easy to understand, these processing, which can be, for example either synchronously or asynchronously to be executed in multiple modules.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope of the disclosure and design are wanted by right
It asks and points out.
Claims (8)
1. a kind of stacked wafer structure characterized by comprising
First wafer, upper surface include the first pad for being set as the first signal of connection；
First reroutes layer, is located on first wafer, the first wiring including being electrically connected to first pad, described
First wiring includes first lead pad；
Second wafer, bottom surface are bonded to described first and reroute layer, and upper surface includes being set as connecting first signal and position
Set the first through silicon via that the first lead pad is electrically connected to corresponding to the second pad of first pad and bottom；
Second reroutes layer, is located on second wafer, including is electrically connected to first through silicon via and second weldering
Second wiring of disk, second wiring includes the second leadframe pad.
2. stacked wafer structure as described in claim 1, which is characterized in that it is brilliant that first through silicon via is made in described second
After the round and described first rewiring layer bonding.
3. a kind of chip stack structure characterized by comprising
First chip, upper surface include the first pad for being set as the first signal of connection；
First reroutes layer, is located on first chip, the first wiring including being electrically connected to first pad, described
First wiring includes first lead pad；
Second chip, bottom surface are bonded to described first and reroute layer, and upper surface includes being set as connecting first signal and position
Set the first through silicon via that the first lead pad is electrically connected to corresponding to the second pad of first pad and bottom；
Second reroutes layer, is located on second chip, including is electrically connected to first through silicon via and second weldering
Second wiring of disk, second wiring includes the second leadframe pad.
4. chip stack structure as claimed in claim 3, which is characterized in that first through silicon via is made in second core
After piece and the first rewiring layer bonding.
5. a kind of stacked wafer structure characterized by comprising
First wafer, upper surface include the first pad for being set as the first signal of connection；
First lower rewiring layer, is located on first wafer, the first wiring including being electrically connected to first pad；
Layer is rerouted on first, is located at the described first lower the second cloth for rerouting on layer, being routed including electrical connection described first
Line, second wiring includes first lead pad；
Second wafer, bottom surface, which is bonded on described first, reroutes layer, and upper surface is provided with connection first signal and position
The first through silicon via of the first lead pad is electrically connected to corresponding to the second pad of first pad and bottom；
Second lower rewiring layer, is located on second wafer, including be electrically connected to second pad and first silicon
The third of through-hole is routed；
Layer is rerouted on second, is located at the described second lower the 4th cloth for rerouting on layer, being routed including being electrically connected the third
Line, the 4th wiring includes the second leadframe pad.
6. stacked wafer structure as claimed in claim 5, which is characterized in that it is brilliant that first through silicon via is made in described second
On circle and described first after the bonding of rewiring layer.
7. a kind of chip stack structure characterized by comprising
First chip, upper surface include the first pad for being set as the first signal of connection；
First lower rewiring layer, is located on first chip, the first wiring including being electrically connected to first pad；
Layer is rerouted on first, is located at the described first lower the second cloth for rerouting on layer, being routed including electrical connection described first
Line, second wiring includes first lead pad；
Second chip, bottom surface, which is bonded on described first, reroutes layer, and upper surface is provided with connection first signal and position
The first through silicon via of the first lead pad is electrically connected to corresponding to the second pad of first pad and bottom；
Second lower rewiring layer, is located on second chip, including be electrically connected to second pad and first silicon
The third of through-hole is routed；
Layer is rerouted on second, is located at the described second lower the 4th cloth for rerouting on layer, being routed including being electrically connected the third
Line, the 4th wiring includes the second leadframe pad.
8. chip stack structure as claimed in claim 7, which is characterized in that first through silicon via is made in second core
On piece and described first after the bonding of rewiring layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| US17/202,248 US11545468B2 (en) | 2018-11-01 | 2021-03-15 | Wafer stacking method and wafer stacking structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020088205A1 (en) * | 2018-11-01 | 2020-05-07 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
| WO2020088208A1 (en) * | 2018-11-01 | 2020-05-07 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
| CN114762103A (en) * | 2019-12-16 | 2022-07-15 | 华为技术有限公司 | Chip stacking structure and manufacturing method thereof |
| WO2024109053A1 (en) * | 2022-11-23 | 2024-05-30 | 华为技术有限公司 | Three-dimensional stacked structure and electronic device |
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2018
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020088205A1 (en) * | 2018-11-01 | 2020-05-07 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
| WO2020088208A1 (en) * | 2018-11-01 | 2020-05-07 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
| US11348873B2 (en) | 2018-11-01 | 2022-05-31 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
| US11545468B2 (en) | 2018-11-01 | 2023-01-03 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
| CN114762103A (en) * | 2019-12-16 | 2022-07-15 | 华为技术有限公司 | Chip stacking structure and manufacturing method thereof |
| WO2024109053A1 (en) * | 2022-11-23 | 2024-05-30 | 华为技术有限公司 | Three-dimensional stacked structure and electronic device |
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