CN211017065U

CN211017065U - Test structure

Info

Publication number: CN211017065U
Application number: CN201922197906.8U
Authority: CN
Inventors: 吴秉桓
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2020-07-14
Anticipated expiration: 2029-12-10

Abstract

The utility model relates to a test structure, test structure includes: the testing device comprises a substrate, wherein a plurality of silicon through hole structures are arranged in the substrate and connected into a plurality of mutually adjacent testing channels through connecting lines, and testing pads are arranged on the testing channels. Above-mentioned test structure can carry out the electrical property control to through-silicon via, can monitor short circuit, the electric leakage condition between the through-silicon via, can reflect whether complete and the quality of insulating layer of through-silicon via's lateral wall, can also monitor the bonding condition between the multilayer chip and whether have the side direction sculpture for the product yield promotes, has ensured the quality, practices thrift the cost.

Description

Test structure

Technical Field

The utility model relates to a semiconductor manufacturing field especially relates to a test structure.

Background

With the continuous improvement of the integration level, the number of device units on each chip is increased sharply, the area of the chip is increased, the increase of the inter-unit connection line affects the working speed of the circuit and occupies a large area, and the integrated circuit is seriously affected to further improve the integration level and the working speed, so that a three-dimensional integrated circuit is needed, the three-dimensional integrated circuit is an integrated circuit with a multi-layer device structure, Through Silicon Vias (TSVs) are needed to be connected between layers, the TSVs are an important development technology, short vertical electric connection or through holes of a silicon wafer is utilized to establish electric connection from the effective side to the back side of the chip, the TSVs provide the shortest interconnection path, and a path is created for the final 3D integration. However, at present, there is no electrical monitoring mechanism for the through silicon vias, and the short circuit and leakage conditions of the through silicon vias cannot be monitored, and the defects of poor bonding and large etching selectivity between multiple layers of chips can cause lateral etching when the through silicon vias are etched, and metal material connection or other abnormalities between adjacent through silicon vias can easily occur when the through silicon vias are filled with metal materials in the later period, and these problems cannot be detected, so that the product yield is low, the quality cannot be guaranteed, and the cost is increased.

SUMMERY OF THE UTILITY MODEL

Based on this, to above-mentioned problem, the utility model provides a test structure.

The utility model provides a test structure, include: the test structure comprises a substrate, wherein a plurality of through silicon via structures are arranged in the substrate and connected into a plurality of mutually adjacent test paths through connecting lines, and test pads are arranged on the test paths.

Above-mentioned test structure can carry out the electrical property control to through-silicon via, can monitor short circuit, the electric leakage condition between the through-silicon via, can reflect whether complete and the quality of insulating layer of through-silicon via's lateral wall, can also monitor the bonding condition between the multilayer chip and whether have the side direction sculpture for the product yield promotes, has ensured the quality, practices thrift the cost.

In one embodiment, the substrate comprises at least 2 substrate units stacked on each other, and the through silicon via structure connects the substrate units with each other. The test structure can monitor the bonding condition among the multiple layers of chips and whether lateral etching exists.

In one embodiment, at least one end of the test path has the test pad, and the test pad is formed on the upper surface of the substrate.

In one embodiment, the connecting line is located at an end of the through-silicon via structure.

In one embodiment, the test path includes a first test path and a second test path, the first test path includes a plurality of first test path units in a strip shape parallel to each other, and the second test path includes a plurality of second test path units in a strip shape parallel to each other.

In one embodiment, the first test path units and the second test path units are alternately arranged in parallel. The first testing access units and the second testing access units are alternately and parallelly arranged, so that wiring is simpler, cost is saved, and operation is easy.

In one embodiment, the connection lines in the first test path unit and the second test path unit are located on an upper surface of the substrate. The connecting wires in the first testing access unit and the second testing access unit are positioned on the upper surface of the substrate, so that the lower surface and the inner area of the substrate do not need to form the connecting wires, the connecting wires in the first testing access unit and the second testing access unit can be formed in one step, the process is reduced, the production efficiency is improved, the connecting wires in the first testing access unit are integrated, the connecting wires in the second testing access unit are also integrated, the connecting wires with smaller size can be formed, the integration level is improved, when the substrate comprises at least 2 substrate units, the connecting wires do not need to be formed between the substrate units and inside the substrate units, the wiring is simple, the process is simple, the operation is easy, and the cost is saved.

In one embodiment, the adjacent first test path units are connected with each other through connecting lines, so that the plurality of first test path units are connected into a whole, the adjacent second test path units are connected with each other through connecting lines, so that the plurality of second test path units are connected into a whole, the first test path and the second test path have an overlapping part, and the connecting lines in the first test path and the connecting lines in the second test path at the overlapping part are located on different planes. The number of the test pads is reduced, the test procedures are reduced, the time is saved, and the efficiency is improved.

In one embodiment, the first test via units and the second test via units are arranged perpendicular to each other, the first test via and the second test via have an overlap, and a connection line in the first test via and a connection line in the second test via at the overlap are located on different planes.

In one embodiment, the connection line in the first test via is located on a plane where one end of the through silicon via structure is located, and the connection line in the second test via is located on a plane where the other end of the through silicon via structure is located.

In one embodiment, the connecting lines in the first test path are alternately arranged up and down along the extending direction of the first test path, and the connecting lines in the second test path are alternately arranged up and down along the second test path, so that the connecting lines in the first test path and the connecting lines in the second test path at the overlapping position are located on different planes. The connecting lines in the first test passage are alternately arranged up and down along the extending direction of the first test passage, and the connecting lines in the second test passage are alternately arranged up and down along the second test passage, so that the test is more accurate.

Drawings

Fig. 1 to 5 are schematic structural diagrams of a test path in the test structure of the present invention.

Fig. 6 is a flowchart of a method for manufacturing a test structure according to the present invention.

Fig. 7 to 19 are schematic structural diagrams of steps in the method for manufacturing a test structure according to the present invention.

Fig. 10, 13, 17, and 19 are schematic structural views of the test structure of the present invention.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the methods or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

In one embodiment, a test structure is provided comprising: the test structure comprises a substrate 10, wherein a plurality of through silicon via structures 20 are arranged in the substrate 10, the plurality of through silicon via structures 20 are connected into a plurality of mutually adjacent test paths 40 through connecting lines 30, and test pads 50 are arranged on the test paths 40.

In this embodiment, above-mentioned test structure can carry out the electrical property control to through-silicon via, can monitor the short circuit between the through-silicon via, the electric leakage condition, can reflect whether complete and the quality of insulating layer of through-silicon via's lateral wall, can also monitor the bonding condition between the multilayer chip and whether have the side direction sculpture for the product yield promotes, has ensured the quality, practices thrift the cost.

In one embodiment, the substrate 10 includes at least 2 substrate units stacked on top of each other, with the through-silicon via structures 20 interconnecting the substrate units. The test structure can monitor the bonding condition among the multiple layers of chips and whether lateral etching exists. For example, the substrate 10 may be a single substrate 10, as shown in fig. 10 and 13, at this time, the test structure can electrically monitor the tsv structures 20, can monitor short circuits and leakage between the tsv structures 20, and mainly reflects whether sidewalls of the tsv structures 20 are complete and the quality of the insulating layer; the substrate 10 may also include 2 substrate units, as shown in fig. 17 and 19, in this case, the test structure can electrically monitor the tsv structures 20, can monitor short circuits and electrical leakage between the tsv structures 20, and mainly monitors the bonding condition between the substrate units and whether there is lateral etching.

In the present embodiment, the substrate 10 includes a chip or a base plate. The substrate is made of one or more of silicon, glass, silicon oxide, ceramic and metal.

In one embodiment, a dielectric layer 60 is formed on the upper surface of the substrate 10.

In one embodiment, the lower surface of substrate 10 is formed with a dielectric layer 60.

In one embodiment, a dielectric layer 60 is formed between the substrate units.

In one embodiment, at least one end of the test via 40 has a test pad 50, and the test pad 50 is formed on the upper surface of the substrate 10. In one embodiment, one end of the test via 40 has a test pad 50. In another embodiment, both ends of the test via 40 have test pads 50.

In one embodiment, the connecting lines 30 are located at the ends of the through-silicon via structures 20.

In one embodiment, test via 40 includes a first test via 401 and a second test via 402, where first test via 401 includes a plurality of first test via cells 4011 in a stripe shape parallel to each other, and second test via 402 includes a plurality of second test via cells 4021 in a stripe shape parallel to each other.

In one embodiment, as shown in fig. 1, a plurality of first test access units 4011 and a plurality of second test access units 4021 are alternately arranged in parallel. The first test access units 4011 and the second test access units 4021 are alternately arranged in parallel, so that wiring is simpler, cost is saved, and operation is easy. Current is passed through the first test access unit 4011 or the second test access unit 4021, and if current is detected in the other test access unit, it indicates that there is a short circuit or a leakage between the tsv structures 20, and if no current is detected in the other test access unit, it indicates that there is no short circuit or a leakage between the first test access unit 4011 and the second test access unit 4021. Whether the side wall of the silicon through hole structure 20 is complete and the quality of the insulating layer can be reflected through the test, if the silicon through hole structure is a multilayer substrate unit, the bonding condition among the multilayer substrate units can be monitored, whether lateral etching exists can be monitored, the yield of products is improved, the quality is guaranteed, and the cost is saved.

In one embodiment, as shown in fig. 1, the connection lines 30 in the first test access unit 4011 and the second test access unit 4021 are located at the upper end of the through silicon via structure 20, that is, the connection lines 30 in the first test access unit 4011 and the second test access unit 4021 are located on the upper surface of the substrate. The connecting lines 30 in the first test access unit 4011 and the second test access unit 4021 are located on the upper surface of the substrate, so that the connecting lines 30 do not need to be formed on the lower surface and the inner region of the substrate, and the connecting lines 30 in the first test access unit 4011 and the second test access unit 4021 can be formed in one step, thereby reducing the process flow and improving the production efficiency, and the connecting lines 30 in the first test access unit 4011 are integrated, and the connecting lines 30 in the second test access unit 4021 are also integrated, so that the connecting lines 30 with smaller size can be formed, the integration level is improved, when the substrate comprises at least 2 substrate units, the connecting lines 30 do not need to be formed between the substrate units and inside the substrate units, so that the wiring is simple, the process is simple, the operation is easy, and the cost is saved.

In one embodiment, as shown in fig. 1 and 17, the substrate 10 includes 2 substrate units stacked on each other, the through silicon via structure 20 connects the substrate units to each other, the test via 40 includes a first test via 401 and a second test via 402, the first test via 401 includes a plurality of first test via units 4011 in a strip shape parallel to each other, the second test via 402 includes a plurality of second test via units 4021 in a strip shape parallel to each other, the plurality of first test via units 4011 and the plurality of second test via units 4021 are alternately arranged in parallel to each other, and the connection lines 30 in the first test via units 4011 and the second test via units 4021 are located at the upper end of the through silicon via structure 20, that is, the connection lines 30 in the first test via units 4011 and the second test via units 4021 are located on the upper surface of the substrate 10. The substrate units are bonded with each other, poor bonding conditions may occur, or the substrate units have a large etching selection ratio, which may cause lateral etching during the formation of the through silicon via, resulting in leakage and short circuit between the through silicon via units 20. Current is passed through the first test access unit 4011 or the second test access unit 4021, and if current is detected in the other test access unit, it indicates that there is a short circuit or a leakage between the tsv structures 20, and if no current is detected in the other test access unit, it indicates that there is no short circuit or a leakage between the first test access unit 4011 and the second test access unit 4021. Whether the side wall of the silicon through hole structure 20 is complete and the quality of the insulating layer can be reflected through the test, if the silicon through hole structure is a multilayer substrate unit, the bonding condition among the multilayer substrate units can be monitored, whether lateral etching exists can be monitored, the yield of products is improved, the quality is guaranteed, and the cost is saved. In the embodiment, the connecting wires 30 do not need to be formed between and inside the substrate units, so that the wiring is simple, the process is simple, the operation is easy, and the cost is saved.

In one embodiment, as shown in fig. 2, adjacent first test access units 4011 are connected to each other through a connection line 30, so that several first test access units 4011 are connected into a whole, adjacent second test access units 4021 are connected to each other through a connection line 30, so that several second test access units 4021 are connected into a whole, first test access 401 and second test access 402 have an overlap, and connection line 30 in first test access 401 and connection line 30 in second test access 402 at the overlap are located on different planes. The number of the test pads 50 is reduced, the test procedures are reduced, the time is saved, and the efficiency is improved. Current is passed through the first test access unit 4011 or the second test access unit 4021, and if current is detected in the other test access unit, it indicates that there is a short circuit or a leakage between the tsv structures 20, and if no current is detected in the other test access unit, it indicates that there is no short circuit or a leakage between the first test access unit 4011 and the second test access unit 4021. Whether the side wall of the silicon through hole structure 20 is complete and the quality of the insulating layer can be reflected through the test, if the silicon through hole structure is a multilayer substrate unit, the bonding condition among the multilayer substrate units can be monitored, whether lateral etching exists can be monitored, the yield of products is improved, the quality is guaranteed, and the cost is saved.

In one embodiment, as shown in fig. 3, a plurality of first test access units 4011 and a plurality of second test access units 4021 are arranged perpendicular to each other, first test access 401 and second test access 402 have an overlap, and connection line 30 in first test access 401 and connection line 30 in second test access 402 at the overlap are located on different planes. Current is passed through the first test access unit 4011 or the second test access unit 4021, and if current is detected in the other test access unit, it indicates that there is a short circuit or a leakage between the tsv structures 20, and if no current is detected in the other test access unit, it indicates that there is no short circuit or a leakage between the first test access unit 4011 and the second test access unit 4021. Whether the side wall of the silicon through hole structure 20 is complete and the quality of the insulating layer can be reflected through the test, if the silicon through hole structure is a multilayer substrate unit, the bonding condition among the multilayer substrate units can be monitored, whether lateral etching exists can be monitored, the yield of products is improved, the quality is guaranteed, and the cost is saved.

In one embodiment, adjacent first test access units 4011 are connected to each other through a connection line 30, so that several first test access units 4011 are connected into a whole, adjacent second test access units 4021 are connected to each other through a connection line 30, so that several second test access units 4021 are connected into a whole, the first test access 401 and the second test access 402 have an overlapping portion, and the connection line 30 in the overlapping portion of the first test access 401 and the connection line 30 in the second test access 402 are located on different planes. The number of the test pads 50 is reduced, the test procedures are reduced, the time is saved, and the efficiency is improved.

In one embodiment, as shown in fig. 5, the connection line 30 in the first test via 401 is located on the plane of one end of the through-silicon via structure 20, and the connection line 30 in the second test via 402 is located on the plane of the other end of the through-silicon via structure 20. Current is passed through the first test access unit 4011 or the second test access unit 4021, and if current is detected in the other test access unit, it indicates that there is a short circuit or a leakage between the tsv structures 20, and if no current is detected in the other test access unit, it indicates that there is no short circuit or a leakage between the first test access unit 4011 and the second test access unit 4021. Whether the side wall of the silicon through hole structure 20 is complete and the quality of the insulating layer can be reflected through the test, if the silicon through hole structure is a multilayer substrate unit, the bonding condition among the multilayer substrate units can be monitored, whether lateral etching exists can be monitored, the yield of products is improved, the quality is guaranteed, and the cost is saved.

In one embodiment, as shown in fig. 4, the connection lines 30 in the first test vias 401 are alternately arranged up and down along the extending direction of the first test vias 401, and the connection lines 30 in the second test vias 402 are alternately arranged up and down along the second test vias 402, so that the connection lines 30 in the first test vias 401 and the connection lines 30 in the second test vias 402 at the overlapping positions are located on different planes. The connecting lines 30 in the first test path 401 are alternately arranged up and down along the extending direction of the first test path 401, and the connecting lines 30 in the second test path 402 are alternately arranged up and down along the second test path 402, so that the test is more accurate. Current is passed through the first test access unit 4011 or the second test access unit 4021, and if current is detected in the other test access unit, it indicates that there is a short circuit or a leakage between the tsv structures 20, and if no current is detected in the other test access unit, it indicates that there is no short circuit or a leakage between the first test access unit 4011 and the second test access unit 4021. Whether the side wall of the silicon through hole structure 20 is complete and the quality of the insulating layer can be reflected through the test, if the silicon through hole structure is a multilayer substrate unit, the bonding condition among the multilayer substrate units can be monitored, whether lateral etching exists can be monitored, the yield of products is improved, the quality is guaranteed, and the cost is saved.

In one embodiment, there is an isolation layer between the through silicon via structure 20 and the connection line 30. The isolation layer is made of one or more of titanium, tantalum, tungsten, titanium nitride, tantalum nitride and tungsten nitride.

In one embodiment, the material of the tsv structure 20 includes one or more of copper, aluminum, nickel, gold, silver, and titanium. The connecting wire 30 is made of one or more of copper, aluminum, nickel, gold, silver and titanium. The material of the dielectric layer 60 includes epoxy resin, silica gel, PI, PBO, PCB, silicon oxide, phosphosilicate glass, or fluorine-containing glass.

One embodiment, as shown in fig. 6, provides a method of fabricating a test structure, comprising:

s10: providing a substrate 10;

s11: forming a plurality of through-silicon via structures 20 in the substrate 10;

s12: forming connecting lines 30 among the plurality of through-silicon-via structures 20, wherein the plurality of through-silicon-via structures 20 are connected into a plurality of mutually adjacent test paths 40 through the connecting lines 30;

s13: a test pad 50 is formed on the test via 40.

In this embodiment, the preparation method of the test structure can electrically monitor the through silicon vias, can monitor the short circuit and electric leakage conditions between the through silicon vias, can reflect whether the side walls of the through silicon vias are complete and the quality of the insulating layer, and can also monitor the bonding conditions between the multilayer chips and whether lateral etching exists, so that the product yield is improved, the quality is guaranteed, and the cost is saved.

The method for manufacturing the test structure in this embodiment is used to manufacture the test structure in any one of the examples of fig. 1 to 5 in the above embodiments.

An embodiment of a method for fabricating a test structure is described in detail, and in particular, the method for fabricating a test structure includes:

in one embodiment, a method of making a test structure comprises:

s20: as shown in fig. 7, a substrate 10 is provided;

s21: as shown in fig. 8, a plurality of tsv structures 20 are formed in the substrate 10;

s22: as shown in fig. 9, a first connection line 301 is formed at the upper end of the tsv structure 20;

s23: as shown in fig. 10, a first dielectric layer 601 is formed on the upper surface of the substrate 10, and the test pad 50 is formed on the first dielectric layer 601.

In one embodiment, a method of making a test structure comprises:

s30: providing a substrate 10;

s31: forming a plurality of through-silicon via structures 20 in the substrate 10;

s32: forming a first connection line 301 on the upper end of the tsv structure 20;

s33: forming a first dielectric layer 601 on the upper surface of the substrate 10, and forming a test pad 50 on the first dielectric layer 601;

s34: as shown in fig. 11, a portion of the substrate 10 is removed to expose the lower end of the tsv structure 20;

s35: as shown in fig. 12, a second dielectric layer 602 is formed on the lower surface of the substrate 10, and an opening is formed in the second dielectric layer 602, exposing the substrate 10;

s36: as shown in fig. 13, a second connection line 302 is formed in the opening at the lower end of the tsv structure 20, and the opening is filled with a dielectric layer.

In one embodiment, a method of making a test structure comprises:

s40: as shown in fig. 14, a second substrate unit 102 is provided;

s41: as shown in fig. 15, a second dielectric layer 602 is formed on the upper surface of the second substrate unit 102;

s42: as shown in fig. 16, a first substrate unit 101 is formed on the upper surface of the second dielectric layer 602;

s43: forming a plurality of through silicon via structures 20 penetrating from the upper surface of the first substrate unit 101 to the inside of the second substrate unit 102 in the first substrate unit 101 and the second substrate unit 102;

s44: forming a first connection line 301 on the upper end of the tsv structure 20;

s45: a first dielectric layer 601 is formed on the upper surface of the first substrate unit 101, and a test pad 50 as shown in fig. 17 is formed on the first dielectric layer 601.

In one embodiment, a method of making a test structure comprises:

s50: providing a second substrate unit 102;

s51: as shown in fig. 18, a second connection line 302 is formed on the upper surface of the second substrate unit 102;

s52: forming a second dielectric layer 602 on the upper surface of the second substrate unit 102;

s53: forming a first substrate unit 101 on the upper surface of the second dielectric layer 602;

s54: forming a plurality of through silicon via structures 20 penetrating from the upper surface of the first substrate unit 101 to the second connection lines 302 in the first substrate unit 101 and the second substrate unit 102;

s55: forming a first connection line 301 on the upper end of the tsv structure 20;

s56: a first dielectric layer 601 is formed on the upper surface of the first substrate unit 101, and a test pad 50 as shown in fig. 19 is formed on the first dielectric layer 601.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only represent some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A test structure, comprising:

the test structure comprises a substrate, wherein a plurality of through silicon via structures are arranged in the substrate and connected into a plurality of mutually adjacent test paths through connecting lines, and test pads are arranged on the test paths.

2. The test structure of claim 1, wherein the substrate comprises at least 2 substrate units stacked on top of each other, and the through-silicon-via structure connects the substrate units to each other.

3. The test structure of claim 1, wherein at least one end of the test via has the test pad formed on an upper surface of the substrate.

4. The test structure of claim 1, wherein the connection line is located at an end of the through silicon via structure.

5. The test structure of claim 1, wherein the test vias comprise a first test via comprising a plurality of first test via cells in a strip parallel to each other and a second test via comprising a plurality of second test via cells in a strip parallel to each other.

6. The test structure of claim 5, wherein the first plurality of test via units and the second plurality of test via units are arranged in parallel and alternate with each other.

7. The test structure of claim 6, wherein the connecting lines in the first test via cell and the second test via cell are located on an upper surface of the substrate.

8. The test structure of claim 6, wherein adjacent first test via units are connected to each other by connecting lines, so that the plurality of first test via units are connected into a whole, and adjacent second test via units are connected to each other by connecting lines, so that the plurality of second test via units are connected into a whole, the first test via and the second test via have an overlap, and the connecting lines in the first test via and the connecting lines in the second test via at the overlap are located on different planes.

9. The test structure of claim 5, wherein the first test via units and the second test via units are arranged perpendicular to each other, the first test via and the second test via have an overlap, and a connection line in the first test via and a connection line in the second test via at the overlap are located on different planes.

10. The test structure of claim 9, wherein adjacent first test via units are connected to each other by connecting lines, so that the plurality of first test via units are connected into a whole, and adjacent second test via units are connected to each other by connecting lines, so that the plurality of second test via units are connected into a whole, the first test via and the second test via have an overlap, and the connecting lines in the first test via and the connecting lines in the second test via at the overlap are located on different planes.

11. The test structure of claim 10, wherein the connection line in the first test via is located on a plane of one end of the through silicon via structure, and the connection line in the second test via is located on a plane of the other end of the through silicon via structure.

12. The test structure of claim 10, wherein the connecting lines in the first test via alternate up and down along the extending direction of the first test via, and the connecting lines in the second test via alternate up and down along the extending direction of the second test via, such that the connecting lines in the first test via and the connecting lines in the second test via at the overlap are located on different planes.