CN210015848U

CN210015848U - Semiconductor interconnect structure

Info

Publication number: CN210015848U
Application number: CN201920441995.3U
Authority: CN
Inventors: 吴秉桓
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-04-02
Filing date: 2019-04-02
Publication date: 2020-02-04
Anticipated expiration: 2029-04-02

Abstract

The present disclosure provides a semiconductor interconnect structure. The semiconductor interconnect structure includes: the upper surface of the first semiconductor structure is provided with a first dielectric layer, and the first dielectric layer comprises a first conductive structure; the second semiconductor structure is bonded to the first dielectric layer, and the upper surface of the second semiconductor structure is a second dielectric layer; the second conductive structure is positioned on the second dielectric layer; the lower surface of the third conductive structure is connected with the first conductive structure, and the upper surface of the third conductive structure is connected with the second conductive structure; the second conductive structure and the third conductive structure are formed through the same conductive material filling process. The semiconductor interconnection structure provided by the present disclosure has lower resistance and higher strength.

Description

Semiconductor interconnect structure

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor interconnect structure fabricated by a one-step conductive material filling process.

Background

In the process of manufacturing a semiconductor structure, a conductive structure connected to a conductive structure (e.g., a pad, a wire, etc.) below a wafer is usually manufactured by first manufacturing a Through Silicon Via (TSV) for the wafer, then manufacturing a dielectric layer, and finally manufacturing a wire electrically connected to the TSV in the dielectric layer to form a wire connected to the conductive structure below the wafer.

In the mode, as the TSV and the conducting wire are manufactured in sequence, the manufacturing process is complex, and the requirement on process precision is high; when the conducting wire connected with the TSV is manufactured, a dielectric layer is easily remained on the interface of the conducting wire and the TSV, and the resistance value of the conducting structure is improved. Particularly, when a multilayer stack structure is manufactured, a plurality of TSVs and multilayer wires are often required to be manufactured to manufacture a conductive structure communicated with a lower conductive structure, and a residual dielectric layer exists at an interface between each TSV and each wire, so that the accumulation of increased resistance values and the increase of element parameter errors are caused, and the accuracy of a semiconductor element is affected.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The present disclosure is directed to a semiconductor interconnect structure manufactured by a single conductive material filling process, which is used to overcome, at least to some extent, the problems of complicated manufacturing process of the semiconductor interconnect structure and residual dielectric layer between a TSV and a conductive line due to the limitations and disadvantages of the related art.

According to an aspect of the present disclosure, there is provided a semiconductor interconnect structure comprising:

the upper surface of the first semiconductor structure is provided with a first dielectric layer, and the first dielectric layer comprises a first conductive structure;

the second semiconductor structure is bonded to the first dielectric layer, and the upper surface of the second semiconductor structure is a second dielectric layer;

the second conductive structure is positioned on the second dielectric layer;

the lower surface of the third conductive structure is connected with the first conductive structure, and the upper surface of the third conductive structure is connected with the second conductive structure;

the second conductive structure and the third conductive structure are formed through the same conductive material filling process.

In an exemplary embodiment of the present disclosure, a process of manufacturing the second conductive structure and the third conductive structure includes:

etching a wire groove on the second medium layer through a first photoetching process;

etching a vertical through hole on the lower surface of the wire groove through a second photoetching process, enabling the vertical through hole to pass through the second semiconductor structure and the first dielectric layer, and exposing the first conductive structure at the bottom;

and filling a conductive material to the wire groove and the vertical through hole at one time to form the second conductive structure and the third conductive structure at one time.

etching a vertical through hole in the second semiconductor structure and the first dielectric layer through a first photoetching process to expose the first conductive structure from the bottom of the vertical through hole;

etching a wire groove on the second medium layer through a second photoetching process;

In an exemplary embodiment of the present disclosure, a junction of the first vertical via and the wire trench includes a first chamfer and a second chamfer.

In an exemplary embodiment of the present disclosure, the first conductive structure is a pad, and the second conductive structure is a wire.

In an exemplary embodiment of the present disclosure, the first conductive structure and the second conductive structure are both conductive lines.

In an exemplary embodiment of the present disclosure, the first semiconductor structure includes a plurality of dielectric layers and a multi-layer wafer which are alternately stacked.

In an exemplary embodiment of the present disclosure, the second semiconductor structure includes a plurality of dielectric layers and a multi-layer wafer which are alternately stacked.

In an exemplary embodiment of the present disclosure, the etching of the wire trench on the second dielectric layer includes:

and etching the wire groove by a wet etching process, and controlling etching parameters to etch a first chamfer and a second chamfer at the joint of the vertical through hole and the wire groove.

In an exemplary embodiment of the present disclosure, the conductor materials of the first conductive structure, the second conductive structure, and the third conductive structure are the same.

The embodiment of the disclosure manufactures the groove and the vertical through hole of the conductive structure by using two photoetching processes, and forms the semiconductor interconnection structure by using the same conductive material filling process at one time, so that the manufacturing efficiency of the semiconductor interconnection structure can be improved, the manufacturing cost is reduced, the resistance of the semiconductor interconnection structure is reduced, and the problems of complex manufacturing process, interface residual dielectric layer and the like caused by manufacturing the TSV and the lead by related technologies in different times are avoided.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of a semiconductor interconnect structure provided in an exemplary embodiment of the present disclosure.

Fig. 2 is a flow chart of a process for fabricating a second conductive structure and a third conductive structure in an exemplary embodiment of the present disclosure.

Fig. 3A to 3F are schematic views of the manufacturing process shown in fig. 2.

FIG. 4 is a schematic illustration of the first chamfer T1 and the second chamfer T2.

Fig. 5 is a flow chart of a process for fabricating the second conductive structure and the third conductive structure in another embodiment.

Fig. 6A to 6C are schematic views of the manufacturing process shown in fig. 5.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Referring to fig. 1, a semiconductor interconnect structure 100 may include:

a first semiconductor structure 11, an upper surface of which is a first dielectric layer 111, the first dielectric layer 111 including a first conductive structure a;

a second semiconductor structure 12 bonded to the first dielectric layer 111, the upper surface of which is a second dielectric layer 121;

a second conductive structure B on the second dielectric layer 121;

the third conductive structure C passes through the first dielectric layer 111 and the second semiconductor structure 12, the lower surface of the third conductive structure C is connected with the first conductive structure A, and the upper surface of the third conductive structure C is connected with the second conductive structure B;

the second conductive structure B and the third conductive structure C are formed by the same conductive material filling process.

Referring to fig. 2, the process of fabricating the second and third conductive structures may include:

step S21, etching a wire groove on the second dielectric layer by a first photolithography process;

step S22, etching a vertical through hole on the lower surface of the wire groove by a second photoetching process, so that the vertical through hole passes through the second semiconductor structure and the first dielectric layer, and the first conductive structure is exposed at the bottom;

step S23 is to fill a conductive material to the wire trench and the vertical via at a time to form a second conductive structure and a third conductive structure at a time.

Fig. 3A to 3F are schematic views of the manufacturing process shown in fig. 2.

In fig. 3A, first a first semiconductor structure 11 with a first dielectric layer 111 on the top surface may be provided, where the first dielectric layer 111 includes a first conductive structure a.

In fig. 3B, the second semiconductor structure 12 is bonded to the first dielectric layer 111, and the upper surface of the second semiconductor structure 12 is the second dielectric layer 121.

In the embodiment of the present disclosure, the first semiconductor structure 11 and the second semiconductor structure 12 may include multiple layers of wafers and dielectric layers alternately connected by bonding, and each dielectric layer may also include conductive structures such as wires and pads, and the present disclosure does not limit the detailed structures of the first semiconductor structure 11 and the second semiconductor structure 12. Since the layers of semiconductor structures are connected by bonding rather than making bumps as is done in the related art, vias through the layers can be made by one etching process.

In fig. 3C, a first photolithography process is performed on the second dielectric layer 121, and after related processes such as photoresist coating, exposure, and development, the wire trench 122 is exposed.

In fig. 3D, the wire trench 122 is etched to form a wire trench 123.

In fig. 3E, a second photolithography process is performed on the conductive line trench 123, and after the related processes such as photoresist coating, exposure, and development, the vertical through hole 124 is exposed.

In fig. 3F, the vertical via site 124 is etched to form a vertical via 125 through the second semiconductor structure 12 and the first dielectric layer 111, exposing the first conductive structure a at the bottom.

Next, the conductive line trench 123 and the vertical via 125 are filled with a conductive material through a conductive material filling process, so as to form a second conductive structure B and a third conductive structure C connecting the first conductive structure a as shown in fig. 1. It is understood that the conductive material filling process includes, but is not limited to, an insulating wall deposition process, a seed metal deposition process, a metal growth process, a Chemical Mechanical Polishing (CMP) process, etc., the conductive material filling process includes, but is not limited to, copper, and the specific process of the conductive material filling process can be set by one skilled in the art.

Compared with the technical scheme that the TSV is manufactured firstly and then the conducting wire is manufactured in the dielectric layer in the related art, the second conducting structure B and the third conducting structure C which penetrate through multiple layers are manufactured simultaneously through the manufacturing process provided by the drawings in the figures 3A-3F only through one conducting material filling process, the problems of dielectric layer residue, resistance increase and the like caused by the scheme that the TSV and the conducting wires are manufactured in multiple layers in the related art are solved, the resistance of the whole conducting structure can be effectively reduced, and the strength of the longitudinal conducting structure is enhanced.

It is noted that in the process shown in fig. 3A-3F, since the vertical via 125 is formed after the conductive line trench 123, the process of etching the vertical via 125 forms two chamfers at the junction of the vertical via 125 and the conductive line trench 123.

The two chamfers are formed, so that the conductor mobility in the conductive material filling process is better, the gaps in the conductive structure are reduced, and the conductive material filling efficiency is improved.

Referring to fig. 5, in an exemplary embodiment of the present disclosure, a process of fabricating the second and third conductive structures includes:

step S51, etching a vertical through hole in the second semiconductor structure and the first dielectric layer by a first photolithography process to expose the first conductive structure at the bottom of the vertical through hole;

step S52, etching a wire trench on the second dielectric layer by a second photolithography process;

step S53, filling a conductive material into the wire trench and the vertical via at a time to form a second conductive structure and a third conductive structure at a time.

Fig. 6A to 6C are schematic views of the manufacturing process shown in fig. 5. Before the process shown in fig. 6A, the processes shown in fig. 3A and fig. 3B may be performed, which are not described herein again.

In fig. 6A, a first photolithography process is performed on the second dielectric layer 121, and after related processes such as photoresist coating, exposure, and development, the vertical through hole 126 is exposed.

In fig. 6B, the vertical via hole site 126 is etched to form a vertical via 127 through the second semiconductor structure 12 and the first dielectric layer 111, exposing the first conductive structure a at the bottom.

In fig. 6C, a second photolithography process is performed on the second dielectric layer 121, and after the related processes such as photoresist coating, exposure, and development, the wire trench 128 is exposed.

Next, the wire trench 128 is etched to form the wire trench 123 and the vertical via 125 as shown in fig. 3F, and the method for etching the wire trench 123 is, for example, wet etching. The first and second chamfers may also be fabricated by controlling process parameters in order to increase subsequent conductive material filling efficiency.

After the process shown in fig. 6C, the conductive material may be filled into the conductive line trench 123 and the vertical via 125 by a conductive material filling process, so as to form the second conductive structure B and the third conductive structure C connecting the first conductive structure a as shown in fig. 1. In an exemplary embodiment of the present disclosure, the conductor materials of the first conductive structure, the second conductive structure, and the third conductive structure are the same.

The manufacturing process provided in fig. 6A to 6C also simultaneously manufactures the second conductive structure B and the third conductive structure C penetrating through the multilayer wafer and the dielectric layer only by one conductive material filling process, thereby avoiding the problems of dielectric layer residue, resistance increase and the like caused by the scheme of manufacturing the multilayer TSV and the plurality of wires in the related art, effectively reducing the resistance of the whole conductive structure, and enhancing the strength of the longitudinal conductive structure.

In the embodiment of the present disclosure, the first conductive structure may be either a pad or a wire, and the second conductive structure is a wire.

In the semiconductor interconnect structure 100, since the third conductive structure C penetrates through the entire second semiconductor structure and is fabricated only by one conductive material filling process, no TSV-conductor interface exists in the middle, i.e., no dielectric layer remains, which can effectively reduce the resistance of the semiconductor interconnect structure 100 in the vertical direction and increase the strength of the semiconductor interconnect structure 100. In addition, since the second conductive structure B and the third conductive structure C are manufactured by one conductive material filling process, there is no clear interface between the two structures and no dielectric layer residue exists, so that the resistance of the semiconductor interconnect structure 100 can be further reduced. The advantage of the semiconductor interconnect structure 100 of reduced resistance is even more pronounced when the second semiconductor structure includes multiple layers of wafers and dielectric layers. Finally, the first chamfer and the second chamfer can enable the conductor in the conductive material filling process to have better fluidity and higher conductive material filling efficiency, and can also reduce gaps in the conductive structure when the third conductive structure C penetrates through the multilayer wafer and the dielectric layer, thereby overcoming the conditions of gap filling and the like possibly caused by increasing the length of the through hole.

In summary, in the semiconductor interconnect structure provided by the embodiment of the present disclosure, the second conductive structure and the third conductive structure are formed by using a conductive material filling process, so that the interface between the TSV and the conductive line caused by the conventional method can be eliminated, the residual dielectric layer can be eliminated, and the resistance of the semiconductor interconnect structure can be reduced. In addition, the through hole penetrating through the second semiconductor structure is manufactured through one photoetching process, so that the interfaces of a plurality of TSVs and wires caused by a traditional method in a stacked state of a multilayer wafer and a dielectric layer can be effectively reduced, the resistance of the semiconductor interconnection structure is further reduced, and the strength of the semiconductor interconnection structure is enhanced.

Furthermore, the above-described figures are merely schematic illustrations of processes included according to exemplary embodiments of the present invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A semiconductor interconnect structure, comprising:

the second conductive structure is positioned on the second dielectric layer;

2. The semiconductor interconnect structure of claim 1, wherein the second conductive structure and the third conductive structure are fabricated by a process comprising:

3. The semiconductor interconnect structure of claim 1, wherein the second conductive structure and the third conductive structure are fabricated by a process comprising:

4. The semiconductor interconnect structure of claim 2 or 3, wherein a junction of the vertical via and the wire trench comprises a first chamfer and a second chamfer.

5. The semiconductor interconnect structure of claim 1, wherein the first conductive structure is a pad and the second conductive structure is a wire.

6. The semiconductor interconnect structure of claim 1, wherein the first conductive structure and the second conductive structure are both conductive lines.

7. The semiconductor interconnect structure of claim 1, wherein the first semiconductor structure comprises a plurality of dielectric layers and a multi-layer wafer stacked alternately.

8. The semiconductor interconnect structure of claim 1 or 7, wherein the second semiconductor structure comprises a plurality of dielectric layers and a multi-layer wafer stacked alternately.

9. The semiconductor interconnect structure of claim 3, in which said etching a wire trench on said second dielectric layer comprises:

10. The semiconductor interconnect structure of claim 1, wherein the conductor material of the first conductive structure, the second conductive structure, and the third conductive structure are the same.