CN209119095U - Stacked wafer structure and chip stack structure - Google Patents
Stacked wafer structure and chip stack structure Download PDFInfo
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- CN209119095U CN209119095U CN201821796498.7U CN201821796498U CN209119095U CN 209119095 U CN209119095 U CN 209119095U CN 201821796498 U CN201821796498 U CN 201821796498U CN 209119095 U CN209119095 U CN 209119095U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The disclosure provides a kind of stacked wafer structure and chip stack structure.Stacked wafer structure includes: the first wafer, first lower reroute layer, layer is rerouted on first, the second wafer, second lower layer rerouted, reroutes layer on second.Wherein, the second wafer direct bonding reroutes layer on first, and the second wafer includes that bottom directly contacts the through silicon via that layer is rerouted on first, the through silicon via be made in the second wafer with after rewiring layer is bonded on first.It is respectively set in first wafer and the second wafer there are two the pad of the identical signal of connection, the location swap of the two pads in the first wafer and the second wafer.The yields of manufacture stacked chips can be improved in the stacked wafer structure that the disclosure provides.
Description
Technical field
This disclosure relates to which ic manufacturing technology field, is electrically connected between capable of improving wafer in particular to one kind
The stacked wafer structure of effect and the chip stack structure for using the stacked wafer structure fabrication.
Background technique
In ic manufacturing process, multiple chips are stacked and established with mechanical connection and electrical connection is to reduce collection
At the important feature of circuit volume.Existing way is as shown in FIG. 1A and 1B, each chip manufacturing usually first stacked to needs
TSV (Through Silicon Vias, through silicon via), then forms the salient point (Micro-Bump) of each TSV, finally uses piece
Positioning bonding is carried out to the mode of wafer to piece or piece, realizes being electrically connected for upper layer chip and lower layer chip using each salient point and TSV
It connects.
Firstly, low efficiency causes at high cost in piece in bonding process to wafer of piece or piece.In addition, it is necessary to right in advance
Each chip manufacturing TSV, and salient point is made, positioning fault, the risk of connection fault are larger in bonding process, are easy to cause up and down
Electrical connection access between layer chip disconnects, and yields is caused to decline.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure is designed to provide a kind of stacked wafer structure and chip stack structure, at least to a certain degree
On overcome caused by the limitation and defect due to the relevant technologies that stacked wafer is at high cost, connection fault probability is big, yields is low
The disadvantages of.
According to one aspect of the disclosure, a kind of stacked wafer structure is provided, comprising:
First wafer, upper surface include the first pad for being set as the first signal of connection and the second weldering of connection second signal
Disk；
First lower rewiring layer, is located on first wafer, the first cloth including being electrically connected to first pad
Line and the second wiring for being electrically connected to second pad；
Layer is rerouted on first, is located on the described first lower rewiring layer, including being electrically connected to first wiring
Third is routed and is electrically connected to the 4th wiring of second wiring, and the third wiring includes relatively close in the horizontal direction
The first lead pad of second pad, the 4th wiring includes the of first pad relatively close in the horizontal direction
Two leadframe pads；
Second wafer, bottom surface fit on described first and reroute layer, be provided with position corresponding to second pad and
It is set as the third pad for connecting first signal, position corresponds to first pad and is set as connecting second letter
Number the 4th pad, bottom is electrically connected to the first through silicon via of the first lead pad, bottom is electrically connected to second lead
Second through silicon via of pad.
In the illustrative embodiments of the disclosure, further includes:
Second it is lower reroute layer, be located on second wafer, including be electrically connected to first through silicon via and described
5th wiring of third pad, the 6th wiring for being electrically connected to second through silicon via and the 4th pad；
Layer is rerouted on second, is located on the described second lower rewiring layer, including being electrically connected to the 5th wiring
7th wiring and the 8th wiring for being electrically connected to the 6th wiring, the 7th wiring includes relatively close in the horizontal direction
The third leadframe pad of 4th pad, the 8th wiring includes the of the third pad relatively close in the horizontal direction
Four leadframe pads.
In the illustrative embodiments of the disclosure, further includes:
Third wafer, bottom surface fit on described second and reroute layer, be provided with position corresponding to first pad and
It is set as the 5th pad for connecting first signal, position corresponds to second pad and is set as connecting second letter
Number the 6th pad, bottom is electrically connected to the third through silicon via of the third leadframe pad, bottom is electrically connected to the 4th lead
4th through silicon via of pad；
Layer is rerouted under third, is located on the third wafer, including is electrically connected to the third through silicon via and described
9th wiring of the 5th pad, the tenth wiring for being electrically connected to the 4th through silicon via and the 6th pad；
Layer is rerouted in third, is located under the third and reroutes on layer, including being electrically connected to the 9th wiring
11st wiring and the 12nd wiring for being electrically connected to the tenth wiring, the 11st wiring include phase in the horizontal direction
To the 5th leadframe pad close to the 6th pad, the 12nd wiring includes the relatively close in the horizontal direction the described 5th
6th leadframe pad of pad.
In the illustrative embodiments of the disclosure, first through silicon via and second through silicon via are made in described
On two wafers and described first after the bonding of rewiring layer.
According to the second aspect of the disclosure, a kind of chip stack structure is provided, comprising:
First chip, upper surface include the first pad for being set as the first signal of connection and the second weldering of connection second signal
Disk；
First lower rewiring layer, is located on first chip, the first cloth including being electrically connected to first pad
Line and the second wiring for being electrically connected to second pad；
Layer is rerouted on first, is located on the described first lower rewiring layer, including being electrically connected to first wiring
Third is routed and is electrically connected to the 4th wiring of second wiring, and the third wiring includes relatively close in the horizontal direction
The first lead pad of second pad, the 4th wiring includes the of first pad relatively close in the horizontal direction
Two leadframe pads；
Second chip, bottom surface fit on described first and reroute layer, be provided with position corresponding to second pad and
It is set as the third pad for connecting first signal, position corresponds to first pad and is set as connecting second letter
Number the 4th pad, bottom is electrically connected to the first through silicon via of the first lead pad, bottom is electrically connected to second lead
Second through silicon via of pad.
In the illustrative embodiments of the disclosure, further includes:
Second it is lower reroute layer, be located on second chip, including be electrically connected to first through silicon via and described
5th wiring of third pad, the 6th wiring for being electrically connected to second through silicon via and the 4th pad；
Layer is rerouted on second, is located on the described second lower rewiring layer, including being electrically connected to the 5th wiring
7th wiring and the 8th wiring for being electrically connected to the 6th wiring, the 7th wiring includes relatively close in the horizontal direction
The third leadframe pad of 4th pad, the 8th wiring includes the of the third pad relatively close in the horizontal direction
Four leadframe pads.
In the illustrative embodiments of the disclosure, further includes:
Third chip, bottom surface fit on described second and reroute layer, be provided with position corresponding to first pad and
It is set as the 5th pad for connecting first signal, position corresponds to second pad and is set as connecting second letter
Number the 6th pad, bottom is electrically connected to the third through silicon via of the third leadframe pad, bottom is electrically connected to the 4th lead
4th through silicon via of pad；
Layer is rerouted under third, is located on the third chip, including is electrically connected to the third through silicon via and described
9th wiring of the 5th pad, the tenth wiring for being electrically connected to the 4th through silicon via and the 6th pad；
Layer is rerouted in third, is located under the third and reroutes on layer, including being electrically connected to the 9th wiring
11st wiring and the 12nd wiring for being electrically connected to the tenth wiring, the 11st wiring include phase in the horizontal direction
To the 5th leadframe pad close to the 6th pad, the 12nd wiring includes the relatively close in the horizontal direction the described 5th
6th leadframe pad of pad.
In the illustrative embodiments of the disclosure, first through silicon via and second through silicon via are made in described
On two chips and described first after the bonding of rewiring layer.
The stacked wafer structure and chip stack structure that the embodiment of the present disclosure provides, by first bonded wafer, make TSV again
Mode and using two layers reroute layer realize wafer between signal connect, can to avoid in the related technology to TSV carry out
The fault of machinery contraposition and electrical connection, it is only necessary to it makes wafer room machine and connects the electrical connection that can be realized between TSV, it is convex without making
Point reduces negative effect of the salient point to yields, reduces stacked wafer cost, improve yields.In addition, by letter
The chip that number corresponding pad locations are exchanged is stacked and is electrically connected, and can also be improved the flexibility ratio that chip uses, and improves core
Piece service efficiency.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Figure 1A and Figure 1B is the schematic diagram of chip stack structure in the related technology.
Fig. 2 is the schematic diagram of stacked wafer structure in disclosure exemplary embodiment.
Fig. 3 A~Fig. 3 D is to form showing for stacked wafer structure using stacked wafer structure in disclosure exemplary embodiment
It is intended to.
Fig. 4 is the schematic diagram of stacked wafer structure in another embodiment.
Fig. 5 A and Fig. 5 B are the manufacturing process schematic diagrames of stacked wafer structure shown in Fig. 4.
Fig. 6 A and Fig. 6 B are the top views of stacked wafer structure shown in Fig. 4.
Fig. 7 is the schematic diagram of stacked wafer structure in further embodiment.
Fig. 8 is the schematic diagram of chip stack structure in disclosure exemplary embodiment.
Fig. 9 is the manufacturing process schematic diagram of chip stack structure shown in Fig. 8.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
Omitted with technical solution of the disclosure it is one or more in the specific detail, or can be using other knots
Structure, constituent element, structure, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and
So that all aspects of this disclosure thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, identical appended drawing reference indicates same or similar portion in figure
Point, thus repetition thereof will be omitted.Some block diagrams shown in the drawings are functional entitys, not necessarily necessary and object
The entity managed or be logically independent is corresponding.These functional entitys can be realized using software form, or in one or more
These functional entitys are realized in hardware module or integrated circuit, or in heterogeneous networks and/or processor structure and/or microcontroller
These functional entitys are realized in structure.
Disclosure example embodiment is described in detail with reference to the accompanying drawing.
Fig. 2 is the schematic diagram for the stacked wafer structure that the embodiment of the present disclosure provides.
With reference to Fig. 2, stacked wafer structure 100 may include:
First wafer 10, upper surface include the second letter of the first pad P1-S1 and connection for being set as the first signal S1 of connection
The second pad P2-S2 of number S2；
First lower rewiring layer 11, is located on the first wafer 10, the first cloth including being electrically connected to the first pad P1-S1
Line C1-S1 and the second wiring C2-S2 for being electrically connected to the second pad P2-S2；
Layer 12 is rerouted on first, is located on the first lower rewiring layer 11, including being electrically connected to the first wiring C1-S1's
Third wiring C3-S1 and the 4th wiring C4-S2 for being electrically connected to the second wiring C2-S2, third wiring C3-S1 are included in level side
The first lead of upward relatively close second pad P2-S2 pads PV1, and the 4th wiring C4-S2 includes opposite in the horizontal direction leans on
The second leadframe pad PV2 of nearly first pad P1-S1；
Second wafer 20, bottom surface fit on first rewiring layer 12, be provided with position corresponding to the second pad P2-S2 and
It is set as the third pad P3-S1 of the first signal S1 of connection, position corresponds to the first pad P1-S1 and is set as the second letter of connection
The 4th pad P4-S2 of number S2, bottom are electrically connected to the first through silicon via TSV1 of first lead pad PV1, bottom is electrically connected to the
The second through silicon via TSV2 of two leadframe pad PV2.
Fig. 3 A~Fig. 3 D is the manufacturing process schematic diagram of stacked wafer structure shown in Fig. 2.
Fig. 3 A is the first wafer 10, the second letter of the first pad P1-S1 and connection including being set as the first signal S1 of connection
The second pad P2-S2 of number S2.
Fig. 3 B is that the signal that layer 12 is rerouted on layer 11, first is rerouted under sequentially making first on the first wafer 10
Figure.The first lower layer 11 that reroutes includes connecting the first wiring C1-S1 of the first pad P1-S1 and connecting the second pad P2-S2's
Second is routed C2-S2, and it includes being connected to the third wiring C3-S1 of the first wiring C1-S1 and being connected to that layer 12 is rerouted on first
The 4th wiring C4-S2 of second wiring C2-S2, third are routed C3-S1 and include relatively close second pad P2- in the horizontal direction
The first lead of S2 pads PV1, and the 4th wiring C4-S2 includes the second of relatively close first pad P1-S1 in the horizontal direction drawing
Line pads PV2.
Although Fig. 3 A~Fig. 3 D illustrates the embodiment that the first wafer 10 does not include TSV, it is to be understood that in other realities
Applying the first wafer 10 in example also may include the TSV for being electrically connected the second pad of TSV and electrical connection of the first pad.
Fig. 3 C is that the second wafer 20 is bonded to the schematic diagram that layer 12 is rerouted on first.Second wafer 20 includes setting
To connect the third pad P3-S1 of the first signal S1 and being set as the 4th pad P4-S2 of connection second signal, third pad
The position of P3-S1 corresponds to the first pad P2-S1 corresponding to the position of the second pad P2-S2, the 4th pad P4-S2.
It will be appreciated by persons skilled in the art that bonding process may include first to the upper table for rerouting layer on first
Face is chemically-mechanicapolish polished (Chemical Mechanical Polishing, CMP), then using plasma to first
The upper surface for rerouting layer is activated, and is finally bonded the second wafer in activating surface, the disclosure is repeated no more in this.
It in Fig. 3 C illustrated embodiment, is rerouted between layer 12 on the second wafer 20 and first, needs to include isolation third
It is routed the structure of the wiring of C3-S1 and the 4th C4-S2.For example, can be by the upper surface growth of oxygen for rerouting layer 12 on first
Change layer or other insulating layers C3-S1, C4-S2 and the second wafer 20 is isolated.Alternatively, in some embodiments, can make
When control C3-S1, C4-S2 position lower than the upper surface for rerouting layer on first.This mode for example can be by using
After Damascus technics makes third wiring, the 4th wiring, third wiring, the 4th is routed in deposition first reroutes layer again
Dielectric material, make the wiring of dielectric material covering third, the 4th wiring, and only expose PV1 and PV2.The mode of layer insulation
Can there are many, those skilled in the art can self-setting according to the actual situation.
Fig. 3 D is to make bottom corresponding to the position of first lead pad to the second wafer to be connected to the first of first lead pad
Through silicon via and corresponding to the second leadframe pad position production bottom be connected to the second leadframe pad the second through silicon via schematic diagram.
In some embodiments, the process for making through silicon via for example may include: to correspond to first lead pad and correspondence in the second wafer
Through hole is made respectively in the position of the second leadframe pad, so that the bottom of two through holes is exposed first lead pad and second respectively and is drawn
Line pad is subsequently filled conductive material in two through holes, and conductive material is, for example, metal.
The first pad passes through second by the first through silicon via of the first wiring and third wiring electrical connection, the second pad as a result,
Wiring and the 4th wiring are electrically connected the second through silicon via, and the tie point of the first signal and the second signal can exist without making salient point
Place-exchange is carried out on second wafer, avoids chip stacking process easily causes in the related technology material leakage, rosin joint, contraposition not
The problems such as quasi-.
Further, stacked wafer structure can also carry out the pad on the pad and the first wafer on the second wafer
Electrical connection.Fig. 4 is the schematic diagram of stacked wafer structure in the another embodiment of the disclosure.With reference to Fig. 4, stacked wafer structure can be with
Include:
Second lower rewiring layer 21, is located on the second chip 20, including be electrically connected to the first through silicon via TSV1 and third
The 5th wiring C5-S1 of pad P3-S1, the 6th wiring C6- for being electrically connected to the second through silicon via TSV2 and the 4th pad P4-S2
S2；
Layer 22 is rerouted on second, is located on the second lower rewiring layer 21, including being electrically connected to the 5th wiring C5-S1's
7th wiring C7-S1 and the 8th the wiring C8-S2, the 7th wiring C7-S1 for being electrically connected to the 6th wiring C6-S2 are included in level side
Third the leadframe pad PV3, the 8th wiring C8-S2 of upward relatively close 4th pad P4-S2 includes opposite in the horizontal direction lean on
The 4th leadframe pad PV4 of nearly third pad P3-S1.
Fig. 5 A and Fig. 5 B are the manufacturing process schematic diagrames of structure shown in Fig. 4.
With reference to Fig. 5 A, layer 21 and third wiring C3-S1, the 4th wiring are rerouted under making second on the second wafer 20
Then the process of C4-S2 both can deposit the on the second wafer and through silicon via to make through silicon via on the second wafer first
One medium, and make the 4th cloth for being electrically connected the second pad of third wiring and electrical connection of the through silicon via simultaneously in first medium
Line；Or deposit first medium first on the second wafer and reroute layer so as to form second lower, then to the second wafer with
The position production through hole of first lead pad and the second leadframe pad is corresponded on second lower rewiring layer and fills conductive material, with shape
The first through silicon via of first lead pad is electrically connected at bottom and bottom is electrically connected to the second through silicon via of the second leadframe pad, finally
The 4th wiring that production in layer is electrically connected the second pad of third wiring and electrical connection of the through silicon via is rerouted under second.I.e. pair
For multilayer stacked wafer, the production of through silicon via both can be before rerouting layer and being formed under second, can also be under second
After rerouting layer formation, the disclosure is not particularly limited this.Wherein, first medium is, for example, oxide.
With reference to Fig. 5 B, in order to prepare for the stacked wafer of next step, rewiring layer 22 on second can also be set, and lead to
It crosses the therein 7th and is routed the leadframe pad progress position friendship of C7-S1, the 8th wiring C8-S2 to the first signal of connection, second signal
It changes, to provide condition in the connection of the signal of the pad of different layers location swap.
Fig. 6 A and Fig. 6 B are that the second lower reroute reroutes on layer and second in Fig. 5 A and Fig. 5 B illustrated embodiment respectively
The top view of layer.7th wiring C7-S1 includes the third leadframe pad PV3 of relatively close 4th pad C4-S2 in the horizontal direction,
8th wiring C8-S2 includes the 4th leadframe pad PV4 of relatively close third pad C3-S1 in the horizontal direction.
In this way, structure as shown in Figure 7 can be formed when with reference to step S112 chip superposed layer again, i.e., by the
(upper surface includes being set as the 5th pad P5-S1 of the first signal S1 of connection and being set as connecting second signal S2 to three wafers
6th pad P6-S2) be bonded on second reroute layer 22 after make third under reroute layer, generation can be by different layers wafer
The stacked wafer structure that the signal tie point (pad) of middle location swap is together in series.
Wherein, 30 bottom surface of third wafer fits in rewiring layer 22 on second, is provided with position corresponding to the first pad P1-
S1 and it is set as connection the 5th pad P5-S1 of the first signal S1, position corresponds to the second pad P2-S2 and is set as connection the
The 6th pad P4-S2 of binary signal S2, bottom are electrically connected to the third through silicon via TSV3 of third leadframe pad PV3, bottom electrical connection
In the 4th through silicon via TSV4 of the 4th leadframe pad PV4；It reroutes layer 31 under third to be located on third wafer 30, including electrical connection
In third through silicon via TSV3 and the 5th pad P5-S1 the 9th wiring C9-S1, be electrically connected to the 4th through silicon via TSV4 and the 6th weldering
The tenth wiring C8-S2 of disk P4-S2；
It reroutes layer 32 in third to be located under third on rewiring layer 31, including being electrically connected to the 9th wiring C9-S1's
11st wiring C11-S1 and the 12nd wiring C12-S2 for being electrically connected to the tenth wiring C8-S2, the 11st wiring C11-S1 packet
The 5th leadframe pad PV5 of relatively close 6th pad P4-S2 in the horizontal direction is included, the 12nd wiring C12-S2 is included in level
The 6th leadframe pad PV6 of relatively close 5th pad P5-S1 on direction.
This structure is electrically connected more flexible, can be exchanged by interlayer pad locations, controls odd-level wafer and even number
The pad of the corresponding position of layer crystal circle works at the same time, and also can control the layer circuit work of half in stacked structure.
In further embodiments, stacked wafer structure can be made by following steps:
1. two layers of rewiring layer is made on the first wafer the signal of the first pad is drawn out to first lead pad, by
The signal of two pads is drawn out to the second leadframe pad, the position of first lead pad and the second leadframe pad respectively with the second pad and first
Pad is relatively close；
2. the second wafer bonding is rerouted layer on first；
3. pair the second wafer deposits first medium；
4. the first perforation of position etching that pair the second wafer and first medium correspond to first lead pad and the second leadframe pad
Hole and the second through hole；
5. rerouting etching in layer under second to connect first through hole and the wire lead slot of third pad and connect second
The wire lead slot of through hole and the 4th pad；
6. conductive material is filled in through hole and wire lead slot, to form the first through silicon via, the second through silicon via and electrical connection
In the first through silicon via and third pad the 5th wiring, be electrically connected to the 6th wiring of the second through silicon via and the 4th pad；
7. pair second lower layer that reroutes carries out CMP (chemically mechanical polishing)；
8. pair second lower layer that reroutes deposits second medium；
9. pair second medium etch lead slot simultaneously fills conductive material, to form the 7th wiring of the 5th wiring of electrical connection
With third leadframe pad, be electrically connected the 6th wiring the 8th wiring and the 4th leadframe pad.
10. rerouting layer on pair second carries out CMP.
In the above process, first medium, second medium are for example oxide, and the material of the two can be identical or not
Together.
The embodiment of the present disclosure passes through first bonded wafer and makes TSV again, and passes through two layers of rewiring layer (RDL) drawing signal
Out position exchange, the wafer stepped construction for connecting the pad of identical signal and being staggered can be realized without salient point, primary to realize
TSV is aligned and is electrically connected to the mechanical of lower layer signal, and due to being not necessarily to make salient point, it is possible to prevente effectively from caused by the relevant technologies
The problem of yields declines reduces manufacturing cost.
Fig. 8 is the schematic diagram for the chip stack structure that the embodiment of the present disclosure provides.
With reference to Fig. 8, chip stack structure 800 may include:
First chip 1, upper surface include the first pad P1-S1 and connection second signal for being set as the first signal S1 of connection
The second pad P2-S2 of S2；
First lower rewiring layer 2, is located on the first chip 1, the first wiring including being electrically connected to the first pad P1-S1
C1-S1 and the second wiring C2-S2 for being electrically connected to the second pad P2-S2；
Layer 3 is rerouted on first, be located at first it is lower reroute on layer 2, the including being electrically connected to the first wiring C1-S1
Three wiring C3-S1 and the 4th wiring C4-S2 for being electrically connected to the second wiring C2-S2, it includes in the horizontal direction that third, which is routed C3-S1,
The first lead of upper relatively close second pad P2-S2 pads PV1, and the 4th wiring C4-S2 includes relatively close in the horizontal direction
The second leadframe pad PV2 of first pad P1-S1；
Second chip 4, bottom surface fit in rewiring layer 3 on first, are provided with position corresponding to the second pad P2-S2 and set
It is set to the third pad P3-S1 of the first signal S1 of connection, position corresponds to the first pad P1-S1 and is set as connection second signal
The 4th pad P4-S2 of S2, bottom are electrically connected to the first through silicon via TSV1 of first lead pad PV1, bottom is electrically connected to second
The second through silicon via TSV2 of leadframe pad PV2；
Second lower rewiring layer 5, is located on the second chip 4, including be electrically connected to the first through silicon via TSV1 and third weldering
The 5th wiring C5-S1 of disk P3-S1, the 6th wiring C6-S2 for being electrically connected to the second through silicon via TSV2 and the 4th pad P4-S2；
Layer 6 is rerouted on second, be located at second it is lower reroute on layer 5, the including being electrically connected to the 5th wiring C5-S1
Seven wiring C7-S1 and the 8th wiring C8-S2 for being electrically connected to the 6th wiring C6-S2, the 7th wiring C7-S1 includes in the horizontal direction
The third leadframe pad PV3 of upper relatively close 4th pad P4-S2, the 8th wiring C8-S2 includes relatively close in the horizontal direction
The 4th leadframe pad PV4 of third pad P3-S1；
Third chip 7, bottom surface fit in rewiring layer 6 on second, are provided with position corresponding to the first pad P1-S1 and set
It is set to the 5th pad P5-S1 of the first signal S1 of connection, position corresponds to the second pad P2-S2 and is set as connection second signal
The 6th pad P4-S2 of S2, bottom are electrically connected to the third through silicon via TSV3 of third leadframe pad PV3, bottom is electrically connected to the 4th
The 4th through silicon via TSV4 of leadframe pad PV4；
Layer 8 is rerouted under third, is located on third chip 7, including is electrically connected to the weldering of third through silicon via TSV3 and the 5th
The 9th wiring C9-S1 of disk P5-S1, the tenth wiring C8-S2 for being electrically connected to the 4th through silicon via TSV4 and the 6th pad P4-S2；
Layer 9 is rerouted in third, is located under third and is rerouted on layer 8, the including being electrically connected to the 9th wiring C9-S1
11 wiring C11-S1 and the 12nd the wiring C12-S2, the 11st wiring C11-S1 for being electrically connected to the tenth wiring C8-S2 include
The 5th leadframe pad PV5 of relatively close 6th pad P4-S2 in the horizontal direction, the 12nd wiring C12-S2 are included in level side
The 6th leadframe pad PV6 of upward relatively close 5th pad P5-S1.
In chip stack structure shown in Fig. 8, the signal link position of odd-level and even level is exchanged, and can be realized to heap
The more flexible control of folded chip.
Fig. 9 is the manufacturing process schematic diagram of chip stack structure shown in Fig. 8, i.e., cuts the progress scribing of stacked wafer structure
It cuts to form un-encapsulated bare chip.The chip of structure manufacture as shown in Figure 9 does not have bump structure, leads between semiconductor layer
The TSV that overweight wiring layer and bottom are directly connected to reroute layer realizes electrical connection, and reliability with higher can be to avoid correlation
In technology chip occasionally there are electrical connection instability problem.
In addition, above-mentioned attached drawing is only the schematic theory of processing included by structure according to an exemplary embodiment of the present invention
It is bright, rather than limit purpose.It can be readily appreciated that the time that above-mentioned processing shown in the drawings did not indicated or limited these processing is suitable
Sequence.In addition, be also easy to understand, these processing, which can be, for example either synchronously or asynchronously to be executed in multiple modules.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope of the disclosure and design are wanted by right
It asks and points out.
Claims (8)
1. a kind of stacked wafer structure characterized by comprising
First wafer, upper surface include the first pad for being set as the first signal of connection and the second pad of connection second signal；
First it is lower reroute layer, be located on first wafer, including be electrically connected to first pad the first wiring and
It is electrically connected to the second wiring of second pad；
Layer is rerouted on first, is located on the described first lower rewiring layer, the third including being electrically connected to first wiring
It is routed and is electrically connected to the 4th wiring of second wiring, the third wiring includes relatively close in the horizontal direction described
The first lead pad of second pad, the 4th wiring includes second drawing for first pad relatively close in the horizontal direction
Line pad；
Second wafer, bottom surface fit on described first and reroute layer, are provided with position corresponding to second pad and setting
To connect the third pad of first signal, position corresponds to first pad and is set as connecting the second signal
4th pad, bottom are electrically connected to the first through silicon via of the first lead pad, bottom is electrically connected to second leadframe pad
Second through silicon via.
2. stacked wafer structure as described in claim 1, which is characterized in that further include:
Second lower rewiring layer, is located on second wafer, including be electrically connected to first through silicon via and the third
5th wiring of pad, the 6th wiring for being electrically connected to second through silicon via and the 4th pad；
Layer is rerouted on second, is located on the described second lower rewiring layer, the including being electrically connected to the 5th wiring the 7th
It is routed and is electrically connected to the 8th wiring of the 6th wiring, the 7th wiring includes relatively close in the horizontal direction described
The third leadframe pad of 4th pad, the 8th wiring includes the 4th drawing for the third pad relatively close in the horizontal direction
Line pad.
3. stacked wafer structure as claimed in claim 2, which is characterized in that further include:
Third wafer, bottom surface fit on described second and reroute layer, are provided with position corresponding to first pad and setting
To connect the 5th pad of first signal, position corresponds to second pad and is set as connecting the second signal
6th pad, bottom are electrically connected to the third through silicon via of the third leadframe pad, bottom is electrically connected to the 4th leadframe pad
4th through silicon via；
Layer is rerouted under third, is located on the third wafer, including be electrically connected to the third through silicon via and the described 5th
9th wiring of pad, the tenth wiring for being electrically connected to the 4th through silicon via and the 6th pad；
Layer is rerouted in third, is located under the third and is rerouted on layer, the including being electrically connected to the 9th wiring the tenth
One wiring and the 12nd wiring for being electrically connected to the tenth wiring, the 11st wiring include opposite in the horizontal direction lean on
5th leadframe pad of nearly 6th pad, the 12nd wiring includes the 5th pad relatively close in the horizontal direction
The 6th leadframe pad.
4. stacked wafer structure as claimed in any one of claims 1 to 3, first through silicon via and the second through silicon via system
Make on second wafer and described first after the bonding of rewiring layer.
5. a kind of chip stack structure characterized by comprising
First chip, upper surface include the first pad for being set as the first signal of connection and the second pad of connection second signal；
First it is lower reroute layer, be located on first chip, including be electrically connected to first pad the first wiring and
It is electrically connected to the second wiring of second pad；
Layer is rerouted on first, is located on the described first lower rewiring layer, the third including being electrically connected to first wiring
It is routed and is electrically connected to the 4th wiring of second wiring, the third wiring includes relatively close in the horizontal direction described
The first lead pad of second pad, the 4th wiring includes second drawing for first pad relatively close in the horizontal direction
Line pad；
Second chip, bottom surface fit on described first and reroute layer, are provided with position corresponding to second pad and setting
To connect the third pad of first signal, position corresponds to first pad and is set as connecting the second signal
4th pad, bottom are electrically connected to the first through silicon via of the first lead pad, bottom is electrically connected to second leadframe pad
Second through silicon via.
6. chip stack structure as claimed in claim 5, which is characterized in that further include:
Second lower rewiring layer, is located on second chip, including be electrically connected to first through silicon via and the third
5th wiring of pad, the 6th wiring for being electrically connected to second through silicon via and the 4th pad；
Layer is rerouted on second, is located on the described second lower rewiring layer, the including being electrically connected to the 5th wiring the 7th
It is routed and is electrically connected to the 8th wiring of the 6th wiring, the 7th wiring includes relatively close in the horizontal direction described
The third leadframe pad of 4th pad, the 8th wiring includes the 4th drawing for the third pad relatively close in the horizontal direction
Line pad.
7. chip stack structure as claimed in claim 6, which is characterized in that further include:
Third chip, bottom surface fit on described second and reroute layer, are provided with position corresponding to first pad and setting
To connect the 5th pad of first signal, position corresponds to second pad and is set as connecting the second signal
6th pad, bottom are electrically connected to the third through silicon via of the third leadframe pad, bottom is electrically connected to the 4th leadframe pad
4th through silicon via；
Layer is rerouted under third, is located on the third chip, including be electrically connected to the third through silicon via and the described 5th
9th wiring of pad, the tenth wiring for being electrically connected to the 4th through silicon via and the 6th pad；
Layer is rerouted in third, is located under the third and is rerouted on layer, the including being electrically connected to the 9th wiring the tenth
One wiring and the 12nd wiring for being electrically connected to the tenth wiring, the 11st wiring include opposite in the horizontal direction lean on
5th leadframe pad of nearly 6th pad, the 12nd wiring includes the 5th pad relatively close in the horizontal direction
The 6th leadframe pad.
8. such as the described in any item chip stack structures of claim 5~7, first through silicon via and the second through silicon via system
Make on second chip and described first after the bonding of rewiring layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821796498.7U CN209119095U (en) | 2018-11-01 | 2018-11-01 | Stacked wafer structure and chip stack structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128974A (en) * | 2018-11-01 | 2020-05-08 | 长鑫存储技术有限公司 | Wafer stacking method and wafer stacking structure |
| CN111819689A (en) * | 2020-01-20 | 2020-10-23 | 深圳市汇顶科技股份有限公司 | Stacked chip, manufacturing method, image sensor and electronic device |
| CN113097185A (en) * | 2021-03-31 | 2021-07-09 | 长江存储科技有限责任公司 | Wafer level die stack structure and method, die stack package structure and method |
-
2018
- 2018-11-01 CN CN201821796498.7U patent/CN209119095U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128974A (en) * | 2018-11-01 | 2020-05-08 | 长鑫存储技术有限公司 | Wafer stacking method and wafer stacking structure |
| CN111819689A (en) * | 2020-01-20 | 2020-10-23 | 深圳市汇顶科技股份有限公司 | Stacked chip, manufacturing method, image sensor and electronic device |
| CN113097185A (en) * | 2021-03-31 | 2021-07-09 | 长江存储科技有限责任公司 | Wafer level die stack structure and method, die stack package structure and method |
| CN113097185B (en) * | 2021-03-31 | 2022-01-25 | 长江存储科技有限责任公司 | Wafer level die stack structure and method, die stack package structure and method |
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