TWI675440B - Method for fabricating glass substrate package - Google Patents

Abstract

According to an embodiment of the present invention, a substrate is provided. The substrate includes a solid core glass substrate having a first surface and a second surface opposite to the first surface. The surface passes through to the second surface, wherein a metal conductor has a third surface and a fourth surface parallel to each other, wherein the third surface is coplanar with the first surface, and the fourth surface is coplanar with the second surface, and The glass substrate is directly connected to the metal conductors, and a first dielectric layer and a first metal layer are formed on the first surface, and the first metal layer is electrically connected to one of the metal conductors.

Description

Glass substrate package and manufacturing method thereof

The invention discloses a manufacturing method and a structure of a glass substrate, and discloses several embodiments related to setting up one or more wafers on a glass substrate to establish a packaging system.

The reduction in size, thickness, and function development of electronic devices are well-known trends, and placing a semiconductor package on a motherboard is also a trend of achieving high integration.

When the geometric size of the integrated circuit is reduced in proportion, the cost of each chip is reduced and the performance is improved. The metal connection between the integrated circuit and other circuits and system components becomes more important, but the reduction in the size of the electronic device makes This metal connection is becoming more and more unfavorable. Factors such as metal interconnections, parasitic capacitance, and increased resistance will reduce the performance of the chip. The most important ones are the voltage drop at the power and ground terminals, and the RC Delay of the critical signal path. Therefore, try to use a wider metal line to increase the capacitance to reduce the resistance.

In order to solve the above problems, a low-resistance metal (such as copper) layer is developed as a line between the low-dielectric layers in the integrated circuit.

The input and output terminals (IO) of high-performance integrated circuits have increased significantly, which has increased the demand for flip chip packages. The flip-chip package is formed by a metal bump on the aluminum metal pad on the wafer (usually Is a tin-lead bump), which is used for downward connection and is connected to a ceramic substrate or a plastic substrate through the shortest path. These packaging technologies can be used not only for single-chip packaging, but also for higher-level or higher-integration packaging. unit.

The flip-chip packaging technology uses an area array, which has the advantages of high-density metal interconnections and low inductance. However, it can be expected to include visual inspection of metal bump bonding in the later stage and avoid solder bump fatigue The matching of Temperature Coefficient of Expansion (TCE) is a big challenge.

The glass substrate can be used as an interposer between one or more wafers and a printed circuit board. When it is not required to have an active device interposer, the glass substrate can be a good substitute for an interposer made of silicon. Its advantages are: Lower material cost, and the thermal expansion coefficient of glass is close to that of the silicon substrate, so the reliability of metal interconnections is greatly improved, especially in the connection of metal bumps of small size, which can be expected to be good, but the glass window The substrate has some disadvantages compared to the silicon substrate, including the low thermal conductivity of the glass substrate and the difficulty of glass perforation, both of which will be discussed in this patent.

The invention discloses a structure of a glass substrate, comprising a glass substrate, a plurality of metal plugs, arranged in the glass substrate, an upper surface of the metal plug is coplanar with an upper surface of the glass substrate, and a lower surface of the metal plug and the glass The lower surface of the substrate is coplanar. The metal plug has a first side and a second side. The first side is parallel to the second side; a metal circuit layer is disposed on the glass substrate and is connected to one of the metal plugs; and a metal bump is disposed on the glass substrate and connected In the metal circuit layer, a minimum distance between a center line of the metal bump and a boundary of the glass substrate is between 20 micrometers and 40 micrometers.

The present invention discloses a packaging structure of a glass substrate, which includes a first glass substrate including a plurality of metal conductors, a metal circuit layer and a metal bump, wherein the metal conductive systems are disposed in the first glass substrate, and the metal A circuit layer is disposed on the first glass substrate and is connected to one of the metal conductors, and the metal bump is disposed on the first glass substrate and connected to the metal circuit layer; and a display panel substrate including a first Two glass substrates, a display area and a plurality of transparent electrode lines are provided on the surface of the second glass substrate, the first glass substrate is positioned above the display panel substrate, and the metal bumps of the first glass substrate are connected to the transparent One of the electrode lines, wherein the display area has four sides, and the distance between each side and the boundary of the display panel substrate is less than 100 microns.

The invention discloses a method for manufacturing a glass substrate, including providing a plurality of metal substrates, each of which has a plurality of metal wires, providing a plurality of substrates positioned between every two of the metal substrates, separating the metal substrates, and forming a glass layer on Between the metal substrates, the glass layer covers the metal wires; and cutting the glass layer and the metal substrates located on the glass layer to produce a first glass substrate.

These and other components, steps, features, benefits, and advantages of the present invention will now become apparent through a review of the following detailed description of illustrative embodiments, accompanying drawings, and patented scope.

2‧‧‧ network cable

4‧‧‧ network cable

2a‧‧‧Y axis

2b‧‧‧X axis

4a‧‧‧Y axis

4b‧‧‧X axis

3‧‧‧ clearance

5‧‧‧ clearance

6‧‧‧ metal wire

6a‧‧‧first cover

6b‧‧‧second cover

t1‧‧‧ clearance

t2‧‧‧ clearance

t3‧‧‧ clearance

8‧‧‧ Thermal Resistance Layer

10‧‧‧Mould

12‧‧‧ fixed layer

14‧‧‧ Receiving slot

16‧‧‧ glass layer

25‧‧‧ glass cylinder

20‧‧‧ the first substrate

22‧‧‧second substrate

21‧‧‧metal embolism

7‧‧‧ first metal sheet

71‧‧‧ Part I

73‧‧‧ Part Two

75‧‧‧ Part III

752‧‧‧metal wire

754‧‧‧Gap

71a‧‧‧perforation

73a‧‧‧perforation

9‧‧‧Second metal sheet

90a‧‧‧perforation

11‧‧‧ Third metal sheet

110a‧‧‧perforation

112a‧‧‧perforation

114a‧‧‧perforation

116a‧‧‧perforation

130‧‧‧ Bolt

132‧‧‧Bolt

150‧‧‧Metal fixed piece

150a‧‧‧perforated

13‧‧‧ Bolt

136‧‧‧Bolt

152‧‧‧Metal fixing piece

152a‧‧‧perforation

17‧‧‧nut

19‧‧‧ metal wire cube

23‧‧‧Mould

23a‧‧‧Air inlet

23b‧‧‧Liquid inlet

25‧‧‧ glass cylinder

21a‧‧‧First gap

21b‧‧‧Second Gap

24‧‧‧ first dielectric layer

24a‧‧‧ opening

26‧‧‧First metal layer

28‧‧‧Second metal layer

30‧‧‧Photoresist layer

30a‧‧‧Opening

32‧‧‧second dielectric layer

32a‧‧‧ opening

34‧‧‧ Third metal layer

36‧‧‧ Fourth metal layer

38‧‧‧Photoresistive layer

38a‧‧‧Opening

40‧‧‧ third dielectric layer

40a‧‧‧ opening

42‧‧‧ protective layer

44‧‧‧ Passive components

46‧‧‧Chip

56‧‧‧Chip

50‧‧‧ metal bump

48‧‧‧Metal pads

54‧‧‧solder layer

52‧‧‧ underfill

60‧‧‧Polymer Adhesive Layer

62‧‧‧metal wire

64‧‧‧ underfill

66‧‧‧Discrete passive components

68‧‧‧Metal pads

70‧‧‧solder layer

72‧‧‧ metal bump

61‧‧‧adhesive / barrier metal layer

63‧‧‧metal seed layer

65‧‧‧first electroplated metal layer

67‧‧‧solder layer

69‧‧‧Second plated metal layer

80‧‧‧ Dielectric layer

82‧‧‧ Dielectric layer

84‧‧‧Photoresistive layer

84a‧‧‧ opening

86‧‧‧Photoresistive layer

86a‧‧‧ opening

80a‧‧‧perforation

88‧‧‧ opening

90‧‧‧ Adhesive / Barrier Layer

92‧‧‧ seed layer

94‧‧‧ copper metal layer

96‧‧‧ Dielectric layer

98‧‧‧ polymer layer

98a‧‧‧ opening

100‧‧‧ Adhesive / Barrier Layer

102‧‧‧Photoresistive layer

102a‧‧‧ opening

104‧‧‧plated metal layer

106‧‧‧First glass substrate

108‧‧‧Second glass substrate

110‧‧‧organic light emitting diode layer

114‧‧‧Transparent electrode circuit

116‧‧‧Anisotropic conductive layer

117‧‧‧ conductive metal particles

109‧‧‧ MEMS display layer

111‧‧‧LCD display layer

128‧‧‧ Optical Layer

107‧‧‧ Third glass substrate

113‧‧‧metal embolism

119‧‧‧frameless display panel

119a‧‧‧display area

119b‧‧‧show border

125‧‧‧ display device

123‧‧‧shell

125b‧‧‧display device

129‧‧‧display device

127‧‧‧Connector

106a‧‧‧Minimum distance

58‧‧‧Metal pads

The drawings disclose illustrative embodiments of the invention. It does not explain all embodiments. Other embodiments may be used in addition or instead. To save space or to explain more effectively, obvious or unnecessary details may be omitted. Instead, some embodiments may be implemented without revealing all the details. When the same number appears in different drawings, it refers to the same or similar components or steps.

The aspects of the present invention can be more fully understood when the following description is read together with accompanying drawings, and the nature of the accompanying drawings should be regarded as illustrative rather than limiting. The drawings are not necessarily drawn to scale, but emphasize the principles of the invention.

FIG. 1 is a perspective view of the X-axis network cable and the Y-axis network cable of the present invention.

FIG. 2 is a schematic cross-sectional view of the X-axis network cable and the Y-axis network cable of the present invention.

FIG. 3 is a schematic cross-sectional view of the X-axis network cable, the Y-axis network cable, and the Z axis of the present invention.

FIG. 4 is a schematic perspective view of the X-axis network cable, the Y-axis network cable, and the Z axis of the present invention.

Figures 5a to 5i are schematic diagrams of the cross section of the Z axis of the present invention.

6a to 6j are schematic diagrams of the first process (method) for manufacturing a glass substrate according to the present invention.

Figures 6k to 6n are top views of a glass substrate produced by the first glass substrate manufacturing process of the present invention.

Figures 7a to 7o are schematic diagrams of the second manufacturing process (method) for manufacturing a glass substrate according to the present invention.

Figures 7p to 7r are top views of a glass substrate produced by the second glass substrate manufacturing process of the present invention.

8a to 8d are schematic cross-sectional views of metal pillars embedded in a glass substrate of the present invention.

FIG. 9a to FIG. 9s are schematic flowcharts of forming a plurality of metal lines on the upper and lower surfaces of a glass substrate according to the present invention.

9t to 9u are schematic cross-sectional views of a plurality of wafers provided on a glass substrate according to the present invention.

Figure 9v is a schematic cross-sectional view of a metal bump on a glass substrate according to the present invention.

FIG. 9w is a schematic cross-sectional view of a plurality of wafers provided on the upper and lower surfaces of a glass substrate according to the present invention.

FIG. 9x is a schematic cross-sectional view of the present invention in which a plurality of wafers and a 3D chip package are arranged on the upper and lower surfaces of a glass substrate.

Figure 9y is a top view of a plurality of wafers provided on a glass substrate according to the present invention.

FIG. 10a to FIG. 10j are schematic flowcharts of forming a metal circuit by a damascene process on a glass substrate according to the present invention.

11a to 11i are schematic diagrams of a process for forming a metal circuit by an embossing process on a glass substrate according to the present invention.

FIG. 12 is a schematic cross-sectional view of the first application of the glass substrate of the present invention.

FIG. 13 is a schematic cross-sectional view of a second application of the glass substrate of the present invention.

FIG. 14 is a schematic cross-sectional view of a third application of the glass substrate of the present invention.

FIG. 15 is a schematic cross-sectional view of a fourth application of the glass substrate of the present invention.

FIG. 16 is a schematic cross-sectional view of a fifth application of the glass substrate of the present invention.

Figure 17a is a schematic cross-sectional view of a third application of the glass substrate of the present invention.

FIG. 17b is a schematic cross-sectional view of an organic light emitting diode display panel according to a third application of the glass substrate of the present invention.

FIG. 18 is a schematic perspective view of a glass substrate combined with a display panel of the present invention.

FIG. 19 is a schematic diagram of a combination of a plurality of display panels according to the present invention.

Although certain embodiments have been depicted in the drawings, those skilled in the art should understand that the depicted embodiments are illustrative and that variations on the embodiments shown can be conceived and implemented within the scope of the present invention. And other embodiments described herein.

Figure 1 reveals a three-dimensional schematic view of a horizontal network cable 2 and a network cable 4. The network cable 4 is located below the network cable 2. The network cable 2 includes a plurality of Y-axis 2a and a plurality of X-axis 2b located on the Y-axis 2a. And the network cable 4 includes a plurality of Y-axis 4a and a plurality of X-axis 4b located on the Y-axis 4a, and a plurality of gaps 3 are formed in the network cable 2, and a plurality of gaps 5 are formed in the network cable 4, wherein the Y-axis 2a, X-axis 2b, Y-axis 4a, and X-axis 4b have the same diameter (or width), and their diameters are, for example, between 10 microns and 30 microns, between 20 microns and 100 microns, and between 40 microns Between 150 and 150 microns, between 50 and 200 microns, between 200 and 1000 microns, or between 500 and 10,000 microns. The material of the Y axis 2a, the X axis 2b, the Y axis 4a, and the X axis 4b is a metal wire or a polymer wire, such as a copper metal wire, a copper-gold alloy metal wire, a copper-gold-palladium alloy metal wire, Copper-gold-silver alloy metal wire, copper-platinum alloy metal wire, copper-iron alloy metal wire, copper-nickel alloy metal wire, copper-tungsten alloy metal wire, tungsten metal wire, brass metal wire, zinc-plated brass metal Wire, stainless steel wire, nickel-plated stainless steel wire, phosphor bronze wire, copper-plated aluminum wire, aluminum metal wire, phenolic resin wire, epoxy resin wire, melamine wire, formaldehyde resin wire, or polysiloxane resin wire. In addition, the cross sections of the Y axis 2a, the X axis 2b, the Y axis 4a, and the X axis 4b may include a circle, a square, an oval, a rectangle, or a long plate.

Fig. 2 is a schematic cross-sectional view of a network cable 2 and a network cable 4, in which a plurality of gaps 3 in the network cable 2 and a network cable 4 The plurality of gaps 5 are aligned with each other.

Please refer to FIG. 3, a plurality of Z-axis metal wires 6 pass through a plurality of gaps 3 in the network wire 2 and a plurality of gaps 5 in the network wire 4, wherein the diameter (or width) of the metal wire 6 is referred to Between 10 microns to 30 microns, between 20 microns to 100 microns, between 40 microns to 150 microns, between 50 microns to 200 microns, or between 500 microns and 10,000 microns. The material of the metal wire 6 includes copper metal wire, copper-gold alloy metal wire, copper-gold-palladium alloy metal wire, copper-gold-silver alloy metal wire, copper-platinum alloy metal wire, copper-iron alloy metal wire, copper- Nickel alloy metal wire, copper-tungsten alloy metal wire, tungsten metal wire, brass metal wire, zinc-plated brass metal wire, stainless steel metal wire, nickel-plated stainless steel metal wire, phosphor bronze metal wire, copper-plated aluminum metal wire, aluminum Metal wire, copper metal wire with titanium layer or copper metal wire with tantalum layer; in addition, the cross section of metal wire 6 may include circular, square, oval, rectangular (rectangular) or long plate shape, and metal wire The shape of 6 may be the same as or different from the Y axis 2a, the X axis 2b, the Y axis 4a, and the X axis 4b.

In addition, the applicant proposes that the material of the metal wire 6 can be a copper-tungsten alloy metal wire, wherein the alloy ratio of the copper-tungsten alloy metal wire includes 50% tungsten metal content and 50% copper metal content, 60% tungsten metal content and One of 40% copper metal content, 70% tungsten metal content and 30% copper metal content, 80% tungsten metal content and 20% copper metal content or 10% tungsten metal content.

FIG. 4 is a schematic perspective view of the metal wire 6 passing through the network cable 2 and the network cable 4.

Figures 5a to 5i show the shape and structure of the metal wire 6, for example, the shape of the metal wire 6 in Figure 5a is circular, the shape of the metal wire 6 in Figure 5d is square, and the metal wire in Figure 5g The shape of 6 is oval, the shape of metal wire 6 in Fig. 5g is rectangular, and the shape of metal wire 6 in Fig. 5b is circular, and a first cover layer 6a is formed on the metal wire 6, where The material of the first covering layer 6a may include a metal layer, such as a nickel-containing metal layer, a zinc-containing metal layer, a silver-containing metal layer, a titanium-containing metal layer, a tantalum-containing metal layer, and a chromium-containing metal layer. In addition, the first cover layer 6a may be an anti-oxidation layer, for example, an oxidation layer containing hexanox material; the shape of the metal wire 6 in FIG. 5e is square, and a first cover layer 6a is formed on the metal wire. Please refer to the above description for the material of the first cover layer 6a; the shape of the metal wire 6 in the figure 5h is rectangular, and a first cover layer 6a is formed on the metal wire 6, where this first For the material of the cover layer 6a, please refer to the description above; the shape of the metal wire 6 in the figure 5c is a circle Shape, which further includes a second cover layer 6b formed on the first cover layer 6a, wherein the second cover layer 6b may include an adhesive layer, and the material thereof includes, for example, a nickel-containing metal layer, a zinc-containing metal layer, A silver-containing metal layer, a titanium-containing metal layer, a tantalum-containing metal layer, and a chromium-containing metal layer, and the second cover layer 6b may be an anti-oxidation layer, for example, an anti-oxidation layer containing a hexaoxidized material; The shape of the metal wire 6 in the figure is a square, and a second cover layer 6b is formed on the first cover layer 6a. The material of the second cover layer 6b is shown in the above description. The metal line in the figure 5h The shape of 6 is rectangular, and a second cover layer 6b is formed on the first cover layer 6a. For the material of the second cover layer 6b, please refer to the description above.

Figures 6a to 6j disclose the first process for making a glass substrate according to the present invention. Please refer to Figure 6a to stretch the metal wire 6 to a suitable length, such as less than 5 meters and a length of 05. Between 1 meter and 1 meter, and between 1 meter and 3 meters in length, and at the same time, the network cable 4 is moved down to an appropriate position. At this time, the Y axis 2a, the X axis 2b, The length or width of the gap t1 between the Y axis 4a and the X axis 4b is larger than the diameter (width) of the metal wire 6.

Next, as shown in FIG. 6b, the Y-axis 2a, X-axis 2b, Y-axis 4a, and X-axis 4b are moved to change the gap t1 to t2, and then the gap between the plurality of metal wires 6 is reduced to a gap t3, where the gap is t3 is almost the same as the diameter (width) of the Y axis 2a, the X axis 2b, the Y axis 4a, and the X axis 4b. For example, the gap t3 is between 5 and 20 microns, between 20 and 50 microns, and Between 30 microns and 80 microns, between 20 microns and 100 microns, between Between 5 microns to 20 microns, between 40 microns to 150 microns, between 50 microns to 200 microns, between 200 microns to 1000 microns, and between 500 microns to 10,000 microns. At the same time, a tensile force can be applied to the metal wire 6 to stretch the metal wire 6 to maintain a certain strength, and fix the gap t3.

Next, as shown in FIG. 6c, a thermal resistance layer 8 is formed on the surface of the network cable 4, and the material of the thermal resistance layer 8 includes a polymer layer, such as a thermosetting resin, a phenol resin, an epoxy resin, and a melamine- Formaldehyde resin, polysiloxane resin or a cement (powder ash) layer, wherein the thermal deformation temperature of the thermal resistance layer 8 is between 400 ° C and 900 ° C. When the liquid thermal resistance layer 8 is formed on the wire mesh 4 The thermal resistance layer 8 passes through the gap 5 to cover the wire mesh 4 and covers the gap 5 between the Y-axis 4a, the X-axis 4b and the metal wire 6, and then heat-hardens the thermal resistance layer 8, wherein the hardened thermal resistance The thickness of layer 8 is between 0.05 m and 1 m, between 2 cm and 10 cm, or between 3 cm and 20 cm.

Next, as shown in FIG. 6d, a mold 10 is provided between the network cable 2 and the network cable 4. The mold 10 surrounds the metal wire 6 and the thermal resistance layer 8. The mold 10 is supported by a machine or a device. Or moving, the mold 10 may be a metal mold, a ceramic mold or a polymer mold, and if the mold 10 is a polymer mold, the mold 10 should have a heat distortion temperature between 400 ° C and 900 ° C or have Thermal deformation temperature between 800 ° C and 1300 ° C.

As shown in FIG. 6e, a fixed layer 12 is formed on the thermal resistance layer 8, wherein the fixed layer 12 can be a glass layer or a polymer layer. When the fixed layer 12 is a glass, the fixed layer 12 is formed on the thermal resistance layer 8 in a high-temperature liquid state. When the temperature of the fixed layer 12 drops to an appropriate temperature, it becomes a solid state, and the bottom of the fixed metal wire is fixed. The end portion, wherein the thickness of the fixing layer 12 is between 0.01 and 1 meter.

As shown in FIG. 6f, the metal wire 6 located under the network wire 4 is cut off, and the mold 10, the network wire 4, the fixing layer 12 and the network wire 2 are moved into an accommodation groove 14.

As shown in FIG. 6g, a high-temperature liquid glass layer 16 is placed in the receiving tank 14 and positioned on the fixed layer 12, and then the temperature of the liquid glass layer 16 is reduced to an appropriate temperature (glass transition temperature). It will become solid when it is below. The glass transition temperature of this glass layer 16 is between 300 ° C and 900 ° C, between 500 ° C and 800 ° C, between 900 ° C and 1200 ° C, and between 1000 ° C. The material of the glass layer 16 may be a low-melting glass material between 1800 and 1800 ° C. For example, the melting point is between 300 ° C and 900 ° C, between 800 ° C and 1300 ° C, and between 900 ° C and 1600. ℃, between 1000 ℃ to 1850 ℃, or between 1000 ℃ to 2000 ℃, or the melting point is less than 1500 ℃, and the thickness of this glass layer 16 is greater than 0.5 meters or greater than 0.1 meters. There are a few bubbles (or no bubbles) in the glass layer 16, such as 1 to 10 bubbles, 5 to 30 bubbles, or 20 to 60 bubbles in a cubic meter of glass layer 16, and each The diameter of the bubble is between 0.0001 cm and 0.01 cm, between 0.001 cm and 0.05 cm, between 0.05 cm and 0.1 cm, Between 0.05 cm and 0.5 cm, the glass layer 16 can be hot-pressed multiple times in advance to squeeze and remove the bubbles in the glass layer 16.

The glass layer 16 is an amorphous solid mixture, and its material includes a soda-lime glass, borosilicate glass, alumino-silica glass, phosphate glass, and sulfide glass. The material composition of the soda-lime glass includes silicon dioxide (SiO ₂ ) 74%, sodium oxide (Na ₂ O) 13%, calcium oxide (CaO) 10.5%, aluminum oxide (Al ₂ O ₃ ) 1.3%, potassium oxide (K ₂ O) 0.3%, sulfur oxide (SO ₃ ), Magnesium oxide (MgO) 0.2%, iron oxide (Fe2O3) 0.04%, titanium dioxide (TiO ₂ ), and the material composition of borosilicate glass includes 81% containing silicon dioxide (SiO ₂ ), boron trioxide (B ₂ O ₃₎ 12%, sodium oxide (Na ₂ O) 4.5%, alumina (Al ₂ O ₃ ) 2%, or the composition of phosphate glass includes 3% to 10% phosphorus pentoxide ( P ₂ O ₅ ) or contains phosphorus pentoxide (P ₂ O ₅ ) between 5% and 20%.

When the temperature of the glass is lower than the glass transition temperature, it will become a solid, and when the temperature of the glass is higher than the glass transition temperature, it will become a liquid. When the glass becomes a liquid, the shape of the glass can be changed by using, and then the temperature is lowered to the glass transition. Under temperature, make the glass solid, and remove thermal stress by an annealing process, and a surface treatment, such as coating or paint, can be used to improve the chemical durability and strength of the glass (such as strengthened glass, bulletproof glass or windshield) Glass), or have an optical characteristic (such as heat-insulating glass or anti-reflective glass).

In addition, the glass layer 16 may be replaced by a polymer layer, wherein when the polymer is hardened into a solid, its thermal expansion coefficient is between 3 ppm / ° C and 10 ppm / ° C.

As shown in FIG. 6h, the mold 10 and the receiving groove 14 are removed and the metal wire 6 is cut off from the network wire 2.

As shown in FIG. 6i, the network cable 4 and the thermal resistance layer 8 are cut away, and a glass pillar 25 is generated.

As shown in FIG. 6j, a part of the metal wires 6 exposed outside the glass pillar 25 is removed, and then the glass pillar 25 is cut to produce a plurality of first substrates 20 made of glass. The thickness of the first substrate 20 is between Between 20 microns and 100 microns, between 50 microns and 150 microns, between 50 microns and 150 microns, between 100 microns and 300 microns, between 150 microns and 2000 microns, or greater 1000 microns. The first substrate 20 can be subjected to a planarization process to planarize the surface, for example, a process such as chemical mechanical polishing (CMP), mechanical polishing, or laser cutting is used.

As shown in FIG. 6k, the first substrate 20 includes a plurality of second substrates 22, each of the second substrates 22 is arranged in an orderly manner in the first substrate 20, and each of the second substrates 22 has a plurality of metal plugs (metal plug) 21, in which the metal plugs 21 are formed by the original metal wires 6 with the same material and structure as the metal wires 6, and the metal plugs 21 in the second substrate 22 are solid pillars.

As shown in FIGS. 61 to 6n, the metal plugs 21 may be arranged in different shapes in the second substrate 22. As shown in FIG. 61, the metal plugs 21 are arranged on the four sides of the second substrate 22. As shown in FIG. 6m, the metal plugs 21 are arranged on the four sides of the second substrate 22 and at the center of the second substrate 22. As shown in FIG. 6n, in some specific aspects of the second substrate 22 These metal plugs 21 are not provided in the area.

Figures 7a to 7m disclose the second process of making a glass substrate according to the present invention. As shown in Figures 7a and 7b, a first metal sheet 7 is provided, and the thickness of the metal sheet 7 is between 20 microns and The first metal sheet is between 1000 microns, between 5 microns and 20 microns, between 10 microns and 50 microns, between 20 microns and 250 microns, or between 30 microns and 400 microns. 7 first portions 71, a second portion 73, and a third portion 75, wherein the third portion 75 is located between the first portion 71 and the second portion 75, and the third portion 75 includes a plurality of non-circular metal wires 752 connects the first portion 71 and the second portion 75. The cross-sectional shape of the metal wire 752 includes a square or a rectangle. In addition, the width of the metal wire 752 is greater than the thickness of the metal wire 752. The width of the metal wire 752 is, for example, between 20 microns and 1000 micrometers, 5 micrometers to 20 micrometers, 10 micrometers to 50 micrometers, 20 micrometers to 250 micrometers, 300 micrometers to 1500 micrometers, and 200 micrometers to 800 microns, between 100 microns and 500 microns, or between 150 microns and 3000 microns There is a gap 754 between every two metal wires 752, the gap 754 is between 20 microns to 1000 microns, between 5 microns to 20 microns, between 10 microns to 50 microns, Between 20 microns and 250 microns, between 300 microns and 1500 microns, between 200 microns and 800 microns, between 100 microns and 500 microns, or between 150 microns and 3000 microns, In addition, the material of the first metal sheet 7 includes a copper metal, a copper-gold alloy metal, a copper-gold-palladium alloy metal, a copper-gold-silver alloy metal, a copper-platinum alloy metal, a copper-iron alloy metal, and a copper-nickel alloy. Metal, copper-tungsten alloy metal, tungsten metal, brass metal, zinc-plated brass metal, stainless steel metal, nickel-plated stainless steel metal, phosphor bronze metal wire, copper-plated aluminum metal, aluminum metal. In addition, two perforations 71a are provided in the first portion 71 and two perforations 73a are provided in the second portion 73. The perforations 71a and 73a are provided with There is a diameter between 600 micrometers and 2000 micrometers, between 1000 micrometers and 3000 micrometers, or between 2000 micrometers and 5000 micrometers, wherein the distance between the two perforations 71a and the distance between the two perforations 73a is almost the same.

As shown in FIGS. 7c to 7d, a plurality of second metal pieces 9 are provided, and the thickness of each second metal piece 9 is between 25 micrometers and 600 micrometers, between 20 micrometers and 300 micrometers, and Between 30 microns and 250 microns, between 25 microns and 180 microns, and two perforations 90a are provided on the second metal sheet 9, the perforations 90a have a diameter between 600 microns and 2000 microns, between Between 1000 microns and 3000 microns or between 2000 microns and 5000 microns, and the distance between the perforations 90a and the distance between the two perforations 71a and the distance between the two perforations 73a are almost the same, the second metal sheet 9 The material includes a copper metal, copper-gold alloy metal, copper-gold-palladium alloy metal, copper-gold-silver alloy metal, copper-platinum alloy metal, copper-iron alloy metal, copper-nickel alloy metal, copper-tungsten alloy Metal, tungsten metal, brass metal, zinc-plated brass metal, stainless steel metal, nickel-plated stainless steel metal, phosphor bronze metal wire, copper-plated aluminum metal, aluminum metal.

As shown in FIG. 7e, a third metal sheet 11 is provided, the thickness of which is between 25 micrometers and 600 micrometers, between 20 micrometers and 300 micrometers, between 30 micrometers and 250 micrometers, and between 25 micrometers to 180 micrometers, and four perforations 110a, 112a, 114a, and 116a are provided on the third metal sheet 11, wherein the perforations 110a, 112a, 114a, and 116a have a diameter ranging from 600 micrometers to 2000 Between micrometers, between 1000 micrometers and 3000 micrometers, or between 2000 micrometers and 5000 micrometers, wherein the distance between the perforations 110a and 112a is almost the same as the distance between the perforations 114a and 116a, and is the same as above The distance between the two perforations 71a and the distance between the two perforations 73a are the same. The material of the third metal sheet 11 includes a copper metal, a copper-gold alloy metal, a copper-gold-palladium alloy metal, a copper-gold-silver alloy metal , Copper-platinum alloy metal, copper-iron alloy metal, copper-nickel alloy metal, copper-tungsten alloy metal, tungsten metal, brass metal, zinc-plated brass metal, stainless steel metal, nickel-plated stainless steel metal, phosphor bronze metal wire, Copper-plated aluminum metal, aluminum metal.

As shown in FIGS. 7f to 7i, a bolt 130 and a bolt 132 are provided, the bolt 130 and the bolt 132 are respectively passed through two perforations 150a on a metal fixing piece 150, and a bolt 134 and a bolt 136 are provided, Pass the bolts 134 and 136 through the two holes 152a on a metal fixing piece 152, and then bolts 130, 132, 134, and 136 through the holes 110a, 112a, 114a, and 116a in the third metal piece 11, respectively. The third metal piece 11 is set on the metal fixing piece 150, and then the bolt 130 and the bolt 132 pass through the two holes 90a on the second metal piece 9 and the bolt 134 and the bolt 136 pass through the two on the second metal piece 9 The perforation 90a enables the two second metal pieces 9 to be respectively disposed on the third metal piece 11, and then the bolts 130, 132, 134, and 136 pass through the perforations 71a and 73a in the first metal piece 7, respectively, so that the first A metal sheet 7 is disposed on the second metal sheet 9, and then the other second metal sheet 9 and the first metal sheet 7 are sequentially passed through the bolt 130, the bolt 132, the bolt 134, and the bolt 136 and overlap each other until The tops of the bolts 130, 132, 134, and 136 are left. Another third metal sheet 11 is provided on the top second metal sheet 9, and another two metal fixing sheets 152 are provided on the top third metal sheet 11. Finally, the bolt 130, the bolt 132, the bolt 134 and the bolt 136 are provided. The nuts 17 are respectively locked, so that these metal fixing pieces 150, the first metal piece 7, the second metal piece 9 and the third metal piece 11 are fixed into a metal wire block 19.

As shown in FIG. 7j, the wire block 19 is placed in a mold 23, and the mold 23 may include a metal mold, a ceramic mold, or a polymer mold. If the mold 23 is a polymer mold, then The heat distortion temperature is between 400 ° C and 900 ° C or between 800 ° C and 1300 ° C. In addition, the mold 23 includes an air inlet 23a and a liquid input port 23b. The air inlet 23a can be used for inputting nitrogen. And helium, and the liquid input port 23b can be used to input a high-temperature liquid glass layer.

As shown in FIG. 7k, a high-temperature liquid glass layer 16 is placed in the mold 23, and then the temperature of the liquid glass layer 16 decreases to a suitable temperature (glass transition temperature) and becomes a solid state. This glass layer Glass transition temperature of 16 Between 300 ° C and 900 ° C, between 500 ° C and 800 ° C, between 900 ° C and 1200 ° C, between 1000 ° C and 1800 ° C, the material of the glass layer 16 can be a low Glass materials with melting points, for example, the melting point is between 300 ° C and 900 ° C, between 800 ° C and 1300 ° C, between 900 ° C and 1600 ° C, between 1000 ° C and 1850 ° C or between Between 1000 ° C and 2000 ° C, or a melting point of less than 1500 ° C, and the thickness of the glass layer 16 is greater than 0.5 meters or greater than 0.1 meters, and there are a few bubbles (or no bubbles) in the glass layer 16, For example, there are 1 to 10 bubbles, 5 to 30 bubbles, or 20 to 60 bubbles in a cubic meter of glass layer 16, and the diameter of each bubble is between 0.0001 cm to 0.01 cm and between 0.001 The glass layer 16 can be removed by pressing and extruding the air bubbles in the glass layer 16 in advance by using multiple heat pressing methods in advance, from cm to 0.05 cm, between 0.05 cm to 0.1 cm, and between 0.05 cm to 0.5 cm.

As shown in FIG. 71, the mold 23 is removed, and the metal fixing piece 150, the metal fixing piece 152, the first portion 71, the second portion 73, and the second and third metal pieces of the first metal piece 7 are cut along the cutting line 16a. 11 is cut off, and a glass cylinder 25 is generated after completion, as shown in FIG. 7m.

As shown in FIG. 7n, a part of the metal wires 6 exposed outside the glass pillar 25 is removed, and then the glass pillar 25 is cut to produce a plurality of first substrates 20 made of glass. The thickness of the first substrate 20 is between Between 20 microns and 100 microns, between 50 microns and 150 microns, between 50 microns and 150 microns, between 100 microns and 300 microns, between 150 microns and 2000 microns, or greater 1000 microns. The first substrate 20 can be subjected to a planarization process to planarize the surface, for example, a process such as chemical mechanical polishing (CMP), mechanical polishing, or laser cutting is used.

As shown in FIG. 7o, the first substrate 20 includes a plurality of second substrates 22, each of the second substrates 22 is arranged in an orderly manner in the first substrate 20, and each of the second substrates 22 has a plurality of metal plugs (metal plug) 21, wherein these metal plugs 21 are formed by the original metal wire 752, and the material and structure are the same as the metal wire 752. In addition, the distance between the first gap 21a between the metal plugs 21 is controlled by the same distance as the original gap 754 between the metal wires 752, and the second gap 21b between the metal plugs 21 is formed by two pieces of phase. The distance between the metal lines 752 in the adjacent first metal sheet 7 is controlled or the same distance therefrom.

As shown in FIG. 7p to FIG. 7r, the metal plugs 21 can be arranged in different shapes in the second substrate 22. As shown in FIG. 7p, the metal plugs 21 are arranged on the four sides of the second substrate 22. As shown in FIG. 7q, the metal plugs 21 are arranged on the four sides of the second substrate 22 and at the center position of the second substrate 22, as shown in FIG. 7r, in some specific aspects of the second substrate 22 These metal plugs 21 are not provided in the area.

As shown in FIG. 8a, the cross-sectional view of the second substrate 22 shows the structure of the metal plug 21, and the second substrate 22 includes a fixed glass layer (or body) 16 and a plurality of metal plugs 21, wherein the glass layer 16 has On the upper surface and the opposite lower surface, the metal plug 21 passes from the upper surface to the lower surface and is disposed in the glass layer 16, wherein the area of the upper surface of the metal plug 21 is the same as that of the lower surface of the metal plug 21.

As shown in FIG. 8b, the upper surface of the metal plug 21 is (almost) coplanar with the upper surface of the glass layer 16, and the lower surface of the metal plug 21 is (almost) coplanar with the lower surface of the glass layer 16.

As shown in FIG. 8c, if the surface of the metal wire 6 or the metal wire 752 covers the first cover layer 6a, the upper surface of the first cover layer 6a is coplanar with the upper surface of the glass layer 16, and the first cover layer The lower surface of 6a is coplanar with the lower surface of the glass layer 16.

As shown in FIG. 8d, if the surface of the metal wire 6 or the metal wire 752 covers the first covering layer 6a and the second covering layer 6b, the upper surfaces of the first covering layer 6a and the second covering layer 6b and the glass layer 16 the upper surface is coplanar, while the first cover The lower surfaces of the layer 6a and the second cover layer 6b are coplanar with the lower surface of the glass layer 16.

As shown in FIG. 9a to FIG. 9r, this series of illustrations reveals that a plurality of lines are formed on the upper surface and the lower surface of the first substrate 20.

As shown in FIG. 9a of forming a silicon oxide layer (SiO _2), a silicon nitride layer is a first dielectric layer 24 on the surface of the first substrate 20, wherein the first dielectric layer 24 comprises (Si ₃ N ₄ ), a silicon oxynitride layer (SiON), a low dielectric constant dielectric layer (for example, a dielectric constant between 0.5 and 3), a polymer layer (for example, polyimide) , Benzocyclobutene (BCB), polybenzoxazole (PBO), poly-phenylene oxide (PPO), epoxy resin, epoxy, silosane ), The first dielectric layer 24 is formed by chemical deposition, and the thickness of the first dielectric layer 24 is between 0.3 micrometers and 5 micrometers, between 2 micrometers and 10 micrometers, and between Between 1 and 30 microns or greater.

As shown in FIG. 9B, a plurality of openings 24a are formed on the first dielectric layer 24 to expose the upper surface of the metal plug 21. The method of forming the openings 24a can be performed by an etching process, and the openings 24a have a width between Between 0.3 microns and 3 microns, between 0.5 microns and 8 microns, between 2 microns and 20 microns, or between 2 microns and 50 microns.

As shown in FIG. 9c, a first metal layer 26 is formed on the surface of the first dielectric layer 24, the metal plug 21, and the opening 24a. The first metal layer 26 includes a metal adhesion layer / barrier layer. For example, a titanium metal, a titanium-tungsten alloy, a titanium nitride, a chromium metal, a tantalum metal, a tantalum nitride, a nickel metal, or a nickel vanadium metal, and the first metal layer 26 is formed in an appropriate manner. For example, the first metal layer 26 is formed by a vacuum deposition method, a physical vapor deposition method (PVD), a plasma-assisted chemical vapor deposition (PECVD) method, a sputtering method, or an electroplating method. The thickness of the layer 26 is between 1 nanometer and 2 micrometers, between 0.3 micrometers and 3 micrometers, or between 0.5 micrometers and 10 micrometers.

As shown in FIG. 9d, a second metal layer 28 is formed on the first metal layer 26. The second metal layer 28 includes copper metal, gold metal or aluminum metal, and the second metal layer is formed in an appropriate manner. 28. For example, the second metal layer 28 is formed by a vacuum deposition method, a physical vapor deposition method (PVD), a plasma-assisted chemical vapor deposition (PECVD) method, a sputtering method, or a plating method. The thickness of the metal layer 28 is between 1 nanometer and 5 micrometers, between 1 micrometer and 5 micrometers, or between 5 micrometers and 30 micrometers.

As shown in FIG. 9e, a photoresist layer 30 is formed on the second metal layer 28. The forming method includes a spin coating method or a lamination method, and then passes through a 1x stepper and A chemical solution is used to perform an exposure process to form a plurality of openings 30a to expose the second metal layer 28. The photoresist layer 30 may include a positive type photoresist layer or a negative type photoresist layer. The photoresist layer 30 The thickness is between 3 microns and 50 microns.

As shown in FIG. 9f, an etching process is used to remove the first metal layer 26 and the second metal layer 28 in the opening 30a.

As shown in FIG. 9g, the photoresist layer 30 is removed using a cleaning process, such as washing with water.

As shown in FIG. 9h, a second dielectric layer 32 is formed on the first dielectric layer 24 and the second metal layer 28. The second dielectric layer 32 includes a silicon oxide layer (SiO ₂ ), a A silicon nitride layer (Si ₃ N ₄ ), a silicon oxynitride layer (SiON), a low dielectric constant dielectric layer (for example, a dielectric constant between 0.5 and 3), a polymer layer (for example, a Polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), poly-phenylene oxide (PPO), epoxy resin (epoxy) , Silosane), the second dielectric layer 32 is formed by chemical deposition, and the thickness of the second dielectric layer 32 is between 0.3 micrometers and 5 micrometers, and between 2 micrometers and 2 micrometers. Between 10 microns, between 1 and 30 microns, or greater than 30 microns.

As shown in FIG. 9i, a plurality of openings 32a are formed on the second dielectric layer 32 to expose the surface of the second metal layer 28. The method of forming the openings 32a can be performed by an etching process, and the openings 32a have a width between Between 0.3 microns and 3 microns, between 0.5 microns and 8 microns, between 2 microns and 20 microns, or between 2 microns and 50 microns.

As shown in FIG. 9j, a third metal layer 34 is formed on the surfaces of the second dielectric layer 32, the second metal layer 28, and the opening 32a. The third metal layer 34 includes a metal adhesion layer / barrier Layer, such as a titanium metal, a titanium-tungsten alloy, a titanium nitride, a chromium metal, a tantalum metal, a tantalum nitride, a nickel metal, or a nickel vanadium metal, and form a third metal in a suitable manner The third metal layer 34 is formed by, for example, a vacuum deposition method, a physical vapor deposition method (PVD), a plasma assisted chemical vapor deposition (PECVD) method, a sputtering method, or a plating method. The thickness of the tri-metal layer 34 is between 1 nanometer and 2 micrometers, between 0.3 micrometers and 3 micrometers, or between 0.5 micrometers and 10 micrometers.

As shown in FIG. 9k, a fourth metal layer 36 is formed on the third metal layer 34. The fourth metal layer 36 includes copper metal, gold metal, or aluminum metal, and the fourth metal layer is formed in an appropriate manner. 36. For example, the fourth metal layer 36 is formed by a vacuum deposition method, a physical vapor deposition method (PVD), a plasma assisted chemical vapor deposition (PECVD) method, a sputtering method, or a plating method. The thickness of the metal layer 36 is between 1 nanometer and 5 micrometers, between 1 micrometer and 5 micrometers, or between 5 micrometers and 30 micrometers.

As shown in FIG. 9l, a photoresist layer 38 is formed on the fourth metal layer 36, and the forming method includes a spin coating method or a lamination method, and then passes through a 1x stepper and A chemical solution is used to perform an exposure process to form a plurality of openings 38a to expose the fourth metal layer 36. The photoresist layer 38 may include a positive type photoresist layer or a negative type photoresist layer. The photoresist layer 38 The thickness is between 3 microns and 50 microns.

As shown in FIG. 9m, an etching process is used to remove the fourth metal layer 36 and the third metal layer 34 in the opening 38a.

As shown in FIG. 9n, the photoresist layer 38 is removed using a cleaning process, such as washing with water.

As shown in FIG. 9o, a third dielectric layer 40 is formed on the second dielectric layer 32 and the fourth metal layer 36. The third dielectric layer 40 includes a silicon oxide layer (SiO ₂ ), a A silicon nitride layer (Si ₃ N ₄ ), a silicon oxynitride layer (SiON), a low dielectric constant dielectric layer (for example, a dielectric constant between 0.5 and 3), a polymer layer (for example, a Polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), poly-phenylene oxide (PPO), epoxy resin (epoxy) , Silosane), the third dielectric layer 40 is formed by chemical deposition, and the thickness of the third dielectric layer 40 is between 0.3 micrometers and 5 micrometers, and between 2 micrometers and 2 micrometers. Between 10 microns, between 1 and 30 microns, or greater than 30 microns.

As shown in FIG. 9p, a plurality of openings 40a are formed on the third dielectric layer 40 to expose the surface of the fourth metal layer 36. The method of forming the openings 40a can be performed by an etching process, and the opening 24a has a width between Between 0.3 microns and 3 microns, between 0.5 microns and 8 microns, between 2 microns and 20 microns, or between 2 microns and 50 microns.

As shown in FIG. 9q, a protective layer 42 is formed in the opening 40a and is positioned on the fourth metal layer 36 and the third dielectric layer 40. This protective layer 42 can protect the fourth metal layer 36 and the third dielectric layer. 40 is not damaged and oxidized.

As shown in FIG. 9r, a process of repeating FIGS. 9a to 9p forms a first dielectric layer 24, a first metal layer 26, a second metal layer 28, and a second dielectric on the lower surface of the first substrate 20. The layer 32, the third metal layer 34, the fourth metal layer 36, and the third dielectric layer 40.

FIGS. 9a to 9r have clearly revealed that a plurality of metal lines are formed on the upper surface and the lower surface of the first substrate 20.

As shown in FIG. 9S, in addition, when the first metal layer 26 or the second metal layer 28 is formed, a passive element 44 may also be formed on the first dielectric layer 24 or the second dielectric layer 32 at the same time. An inductive element, a capacitive element, or a resistive element.

As shown in FIG. 9t, a plurality of wafers 46 and 56 are provided on the third dielectric layer 40 of the first substrate 20 through a flip chip or wire bonding packaging process. The wafer 46 is The chip packaging process is set, and the chip 56 is set through a wire packaging process. The chip 46 and the chip 56 may include a NAND flash memory chip, a flash memory chip, a dynamic random access memory chip (DRAM), a Static random access memory chip (SRAM), a central processing unit chip (CPU), a graphics processing unit chip (GPU), a digital signal processing chip (DSP chip), an integrated memory chip (containing dynamic random access memory) Fetch circuit unit, static random access memory circuit unit, flash memory circuit unit), a baseband chip, a wireless local area network (WLAN) chip, a logic chip, an analog chip, a global positioning System (GPS) chip, a Bluetooth chip, a micro-electro-mechanical system chip, a CMOS image sensor chip, a wireless local area network (WLAN) chip, or a plurality of circuit units integrated in a chip, the circuit unit Including a central processing unit, a graphics processing unit, a digital signal processing unit, a memory unit, and a flash memory unit.

The wafer 46 is disposed on the first substrate 20 by a flip-chip packaging process, wherein the wafer 46 includes a plurality of metal bumps 50 formed on a plurality of metal pads 48 respectively, wherein the metal pads 48 include an electroplated copper pad and a copper inlay Pad or an aluminum metal pad, and the metal bump 50 includes an adhesive layer / barrier metal layer formed on the metal pad 48, an electroplated metal layer or an electroless plated layer formed on the adhesive layer / barrier metal layer The adhesive layer / barrier metal layer includes a titanium-containing metal layer, a titanium-tungsten alloy layer, a titanium nitride layer, a chromium-containing metal layer, a tantalum-containing metal layer, a tantalum nitride layer, and a nickel metal. The electroplated metal layer includes a copper layer, a gold layer, a nickel layer, a tin-containing metal layer, a nickel layer, a solder layer, a solder layer on the nickel layer and the copper layer, and the electroless plating layer includes A copper layer, a gold layer, a nickel layer, and the thickness of the electroplated metal layer is between 2 microns and 5 microns, between 5 microns and 30 microns, or between 10 microns and 50 microns, and The metal bump 50 is connected to the fourth metal layer 36 exposed in the opening 40a via a solder layer 54. The fourth metal layer is a solder layer 54 in the opening 40a is formed based on the solder layer 36 or 54 this part of the metal bump 50.

An underfill layer 52 is formed between the wafer 46 and the third dielectric layer 40.

The wafer 56 is disposed on the third dielectric layer 40 of the first substrate 20 via a polymer adhesive layer 60. The wafer 56 includes a composite metal pad 58 including an electroplated copper pad and an inlay. A copper pad or an aluminum metal pad is connected to the metal pads 58 and the fourth metal layer 36 in the opening 40a by a plurality of metal wires 62, wherein the metal wires 62 include a gold wire, a copper wire, and an alloy. Wire, a silver-containing metal wire, an aluminum-containing metal wire, a gold-copper alloy wire, and an underfill layer 64 covering the chip 56, the metal wire 62, and the metal pad 58.

A plurality of discrete passive components 66 may be disposed on the third dielectric layer 40 of the first substrate 20, such as a discrete inductor element, a discrete capacitor element, and a discrete resistive element. The discrete passive component 66 includes a plurality of metal pads 68. The discrete passive component 66 may be connected to the fourth metal layer 36 through a solder layer 70 and disposed on the third dielectric layer 40.

As shown in FIG. 9u, a plurality of metal bumps 72 may be formed on the wiring layer on the lower surface of the first substrate 20.

The structure of the metal bump 72 is shown in FIG. 9v.

● The structure of the metal bump 72 on the left of Fig. 9v:

The structure of the first metal bump 72 includes an adhesion / barrier metal layer 61 formed on the metal pad 48 by sputtering or electroless plating, and a metal seed layer 63 formed by sputtering or electroless plating on the adhesion. / Barrier metal layer 61, a first An electroplated metal layer 65 is formed on the metal seed layer 63, and a solder layer 67 is formed on the electroplated metal layer 65, wherein the adhesion / barrier metal layer 61 includes, for example, a titanium metal, a titanium-tungsten alloy, a nitrogen Titanium, a chromium metal, a tantalum metal, a tantalum nitride, a nickel metal or a nickel vanadium metal, and the electroplated metal layer 65 includes a copper layer, a gold layer, or a nickel layer, and the solder layer 67 is formed. Formed by screen plating, ball mounting or a plating method, the material of the solder layer 67 includes a gold-tin alloy layer, a tin-silver alloy layer, a tin-silver-copper alloy layer, a An indium layer, a tin-bismuth alloy layer, a lead-free alloy layer, or a lead-containing alloy layer; the thickness of the metal seed layer 63 is between 0.05 μm and 2 μm, and the thickness of the first electroplated metal layer 65 is between 1 Micron to 5 micron, 2 micron to 8 micron, or 5 micron to 20 micron, and the thickness of the solder layer 67 is 30 micron to 80 micron, 50 micron to 100 micron Between micrometers, between 80 micrometers and 150 micrometers, or between 120 micrometers and 350 micrometers.

● The structure of the metal bump 72 on the right side of Figure 9v:

The structure of the second metal bump 72 includes an adhesion / barrier metal layer 61 formed on the metal pad 48 by sputtering or electroless plating, and a metal seed layer 63 formed by sputtering or electroless plating on the adhesion. On the / barrier metal layer 61, a first plated metal layer 65 is formed on the metal seed layer 63, and a second plated metal layer 69 is formed on the first plated metal layer 65, wherein the adhesion / barrier metal layer 61 includes, for example, a titanium metal, a titanium-tungsten alloy, a titanium nitride, a chromium metal, a tantalum metal, a tantalum nitride, a nickel metal, or a nickel vanadium metal, and the first electroplated metal layer 65 and the second The electroplated metal layer 69 includes a copper layer, a gold layer, or a nickel layer. The thickness of the adhesion / barrier metal layer 61 is between 0.05 μm and 2 μm, and the thickness of the metal seed layer 63 is between 0.05 μm and 2. The thickness of the first electroplated metal layer 65 is between 1 micrometer and 5 micrometers, between 2 micrometers and 8 micrometers, or between 5 micrometers and 20 micrometers. Thickness is between 1 μm and 5 μm, between 2 μm and 4 μm, and between 10 μm 30 microns or between 20 microns to 60 microns.

As shown in FIG. 9w, the wafer 46 may also be disposed on the lower surface of the first substrate 20, and the manner of arrangement is the same as that of the wafer 46 and the wafer 56. Please refer to the description above.

As shown in FIG. 9x, the chip 46 can be replaced with a 3D chip package, wherein the chip 46 has a plurality of metal pads 48 formed on the upper and lower surfaces, and the metal pads 48 on the upper surface are embedded in through-silicon vias (through- The metal layer in the silicon-via) is connected to the metal pads 48 on the lower surface, and another wafer 47 is disposed on the wafer 46 in a flip-chip manner, wherein the wafer 47 includes a plurality of metal pads 49 which pass through a The solder layer 51 is connected to metal pads 48 on the upper surface of the chip 46. The metal pads 49 include an electroplated copper pad, an inlaid copper pad, or an aluminum pad.

As shown in Figure 9y, this figure is a top view of the first substrate 20, and Figures 9u to 9w are cross-sectional views of the line L-L 'in Figure 9y. A plurality of wafers 46, 56 and discrete passives are shown. The element 66 may be disposed on the first substrate 20.

Then, the first substrate 20 is cut to generate a plurality of second substrates 22.

The first metal layer 26, the second metal layer 28, the third metal layer 34 and the fourth metal layer 36 disclosed in FIGS. 10a to 10j are formed on the upper surface of the first substrate 20 and On the lower surface.

As shown in FIG. 10a, the dielectric layer 24 in FIG. 9a includes a dielectric layer 80 and a dielectric layer 82. The dielectric layer 80 is formed by chemical vapor deposition (CVD) or a sputtering method. The dielectric layer 82 is formed on the dielectric layer 82. The dielectric layer 80 and the dielectric layer 82 may both include a low dielectric constant layer, and the thickness is between 0.3 micrometer and 5 micrometers or between 0.5 micrometer and 3 micrometers. Either a low dielectric constant silicon oxynitride layer is formed on a low dielectric constant silicon oxide layer, or a low dielectric constant polymer layer having a thickness between 0.3 microns and 5 microns Between 0.5 microns and 3 microns, or a silicon nitride layer formed on a low dielectric constant polymer layer, or between 0.3 microns and 5 microns, or between 0.5 microns and 3 microns Micron A low-k dielectric layer and a silicon nitride-containing layer are formed on the low-k dielectric layer. Next, as shown in FIG. 10b, a photoresist layer 84 is formed on the dielectric layer 82, and an opening 84a is formed to expose the dielectric layer 82 in the photoresist layer 84. Then, as shown in FIG. 10c, a dry layer is used. The dielectric layer 82 located in the opening 84a is removed by etching to form a trench to expose the dielectric layer 80. As shown in FIG. 10d, the photoresist layer 84 is removed. As shown in FIG. 10e, a light is formed. A resist layer 86 is formed on the dielectric layer 82 and the dielectric layer 80, and an opening 86a is formed to expose the dielectric layer 80 on the trench in the photoresist layer 84. As shown in FIG. 10f, use The dry etching method removes the dielectric layer 80 located in the opening 86a to form a perforation 80a to expose the metal plug 21, and then as shown in FIG. 10g, the photoresist layer 86 is removed to expose the opening 88. The opening 88 includes a trench. The grooves and perforations 80a, as shown in FIG. 10h, form an adhesion / barrier layer 90 on the surface of the metal plug 21 in the opening 88, on the sidewall of the opening 88 and the upper surface of the dielectric layer 82, where this adhesion / resistance The thickness of the barrier layer 90 is between 01 μm and 3 μm. The adhesion / barrier layer 90 can be formed by a sputtering method or a chemical vapor deposition (CVD) method. The barrier / barrier layer 90 includes a titanium metal, a titanium-tungsten alloy, a titanium nitride, a chromium metal, a tantalum metal, or a tantalum nitride. The adhesion / barrier layer 90 is, for example, sputtered with a tantalum metal layer on the metal. The surface of the plug 21, the sidewalls of the opening 88 and the upper surface of the dielectric layer 82, or, for example, chemical vapor deposition (CVD) or sputtering of a tantalum nitride layer on the surface of the metal plug 21, the sidewalls of the opening 88, and On the upper surface of the dielectric layer 82, as shown in FIG. 10i, a copper metal seed layer 92 is formed on the adhesion / barrier layer 90 by sputtering or chemical vapor deposition (CVD). The thickness is between 0.1 μm and 3 μm, and then a copper metal layer 94 is formed on the seed layer 92 by electroplating. The thickness of the copper metal layer 94 is between 0.5 μm and 5 μm, and the optimal thickness is between Between 1 μm and 2 μm, as shown in FIG. 10j, the copper metal layer 94, the seed layer 92, and the adhesion / barrier layer 90 located outside the opening 88 are removed by a chemical mechanical polishing (CMP) method. Until the upper surface of the dielectric layer 82 is exposed to the outside world.

The first metal layer 26, the second metal layer 28, the third metal layer 34, and the fourth metal layer 36 disclosed in FIGS. 11a to 11i are formed on the first substrate 20 by an embossing process. On the surface and the lower surface.

As shown in FIG. 11 a, an opening 96 a is located on the dielectric layer 96 on the surface of the first substrate 20, and the metal plug 21 is exposed. A polymer layer 98 is formed on the dielectric layer 96 and the metal plug 21.

As shown in FIG. 11b and FIG. 11c, an opening 98a is formed in the polymer layer 98 to expose only the central portion of the metal plug 21, or as shown in FIG. 11c, an opening 98a is formed in the polymer layer 98 to be exposed The metal plug 21 and the dielectric layer 96 are described below with the structure shown in FIG. 11b. In addition, when the polymer layer 98 forms an opening 98a, the polymer layer 98 is simultaneously patterned. The polymer layer 98 includes, for example, an Polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), poly-phenylene oxide (PPO), epoxy resin (epoxy ), Silosane, elastic polymer layer, porous dielectric material, the thickness of this polymer layer 98 is between 3 microns to 25 microns or between 5 microns to 50 microns. This polymerization The physical layer 98 is formed on the metal plug 21 and the dielectric layer 96 by a spin coating method, a screen plating method, or a lamination process method.

As shown in FIG. 11d, an adhesion / barrier layer 100 and a metal seed layer are formed on the polymer layer 98 and the metal plug 21, and the thickness of the adhesion / barrier layer 100 and the metal seed layer is between 0.1 μm and Between 3 microns or between 0.5 microns and 2 microns, the adhesion / barrier layer 100 includes, for example, a titanium metal, a titanium-tungsten alloy, a titanium nitride, a chromium metal, a tantalum metal, a nitride Tantalum, a nickel metal, or a nickel vanadium metal. The adhesion / barrier layer 100 is formed by a sputtering method, a vapor deposition method, or a chemical vapor deposition (CVD) method.

As shown in FIG. 11e, a photoresist layer 102 is formed on the adhesive / barrier layer 100 by a spin coating method or a lamination method. As shown in FIG. 11f, the photoresist layer 102 is patterned to form an opening 102a and a metal plug is formed. 21 on the adhesion / barrier layer 100.

As shown in FIG. 11g, a plated metal layer 104 is formed on the adhesion / barrier layer 100 in the opening 102a. The plated metal layer 104 includes a copper metal layer, a gold metal layer, or a nickel metal layer. The thickness of the layer 104 is between 2 microns and 10 microns, between 5 microns and 20 microns, or between 5 microns and 35 microns.

As shown in FIG. 11h, the photoresist layer 102 is removed.

As shown in FIG. 11i, the adhesion / barrier layer 100 and the metal seed layer that are not under the electroplated metal layer 104 are removed by dry etching or explicit etching. For example, the adhesion / barrier is removed by reactive ion etching. The layer 100 and the metal seed layer are removed, and the circuit layer is completed.

The first application of the present invention: as shown in FIG. 12, the second substrate 22 is bonded to an organic light-emitting diode (OLED) using a chip-on-glass (COG) method. On the display panel, the organic light emitting diode display panel includes a first glass substrate 106, a second glass substrate 108, an organic light emitting diode layer 110 (polymer light emitting diode layer, PLED) and a thin film transistor circuit layer. Between the first glass substrate 106 and the second glass substrate 108, and a plurality of transparent electrode lines 114 are located between the first glass substrate 106 and the second glass substrate 108, the metal bumps 72 of the second substrate 22 pass through a different The rectangular conductive layer 116 is connected to the transparent electrode line 114. The anisotropic conductive layer 116 includes a plurality of conductive metal particles 117, such as a nickel metal particle, a gold metal particle, a nickel-gold alloy particle, and a silver-tin alloy. Particles, a silver metal particle, a gold-plated particle, a silver-plated particle, and a nickel-plated particle. The organic light emitting diode display panel substrate includes a plurality of organic light emitting diode display panels, wherein the organic light emitting diode display panel may include a touch function, a distance between a center line of the metal bump 72 and a boundary of the glass substrate 106. A minimum distance 106a is between 3 microns and 10 microns, between 5 microns and 15 microns, between 10 microns and 25 microns, and between 20 microns and 40 microns.

Then, the second substrate 22 and the organic light emitting diode display panel substrate are cut to generate a plurality of packaging units.

The second application of the present invention: The organic light emitting diode display panel substrate of the first application can be replaced with a Micro Electro Mechanicah Systems (MEMS) substrate. As shown in FIG. 13, this micro electromechanical The system display panel includes a first glass substrate 106, a second glass substrate 108, a micro-electromechanical system display layer 109, and a thin film transistor circuit layer between the first glass substrate 106 and the second glass substrate 108, and a plurality of The transparent electrode circuit 114 is located between the first glass substrate 106 and the second glass substrate 108. The metal bump 72 of the second substrate 22 is connected to the transparent electrode circuit 114 through an anisotropic conductive layer 116, where the anisotropic conductive layer 116 includes a plurality of conductive metal particles 117, such as a nickel metal particle, a gold metal particle, a nickel-gold alloy particle, a silver-tin alloy particle, a silver metal particle, a gold-plated particle, a silver-plated particle, and a plating Nickel particles. The MEMS display panel substrate includes a plurality of MEMS display panels. The MEMS display panel may include a touch function. A minimum distance 106a between the center line of the metal bump 72 and the boundary of the glass substrate 106 is introduced. Between 3 microns to 10 microns, between 5 microns to 15 microns, between 10 microns to 25 microns, and between 20 microns to 40 microns.

Then, the second substrate 22 and the MEMS display panel substrate are cut to generate a plurality of packaging units.

A third application of the present invention: a plurality of light emitting diode elements 122 are provided on the lower surface of the second substrate 22, and the second substrate 22 is bonded to a liquid crystal display panel by using a chip-on-glass (COG) method The liquid crystal display panel includes a first glass substrate 106, a second glass substrate 108, a liquid crystal display layer 111, and a thin film transistor circuit layer between the first glass substrate 106 and the second glass substrate 108, and a plurality of The transparent electrode circuit 114 is located between the first glass substrate 106 and the second glass substrate 108. The metal bump 72 of the second substrate 22 is connected to the transparent electrode circuit 114 through an anisotropic conductive layer 116, where the anisotropic conductive layer 116 includes a plurality of conductive metal particles 117, such as a nickel metal particle Particles, a gold metal particle, a nickel-gold alloy particle, a silver-tin alloy particle, a silver metal particle, a gold-plated particle, a silver-plated particle, and a nickel-plated particle. The liquid crystal display panel substrate includes a plurality of liquid crystal display panels. The liquid crystal display panel may include a touch function. The liquid crystal display panel may include a touch function. The liquid crystal display panel includes an in-cell touch panel. TFT LCD) thin film transistor liquid crystal display. In addition, there is a plurality of optical layers 128 between the second substrate 22 and the liquid crystal display panel substrate, including a diffusion sheet layer, a prism sheet layer, a diffusion layer (or a diffusion plate), and a reflector layer. In addition, a minimum distance 106a between the center line of the metal bump 72 and the boundary of the glass substrate 106 is between 3 μm to 10 μm, between 5 μm to 15 μm, and between 10 μm to 25 μm. Between 20 and 40 microns.

Then, the second substrate 22 and the liquid crystal display panel substrate are cut to generate a plurality of packaging units.

The fourth application of the present invention: as shown in FIG. 15, the structure of this application is similar to the third application structure shown in FIG. 14. The second substrate 22 is bonded to a liquid crystal display panel by a flip-chip bonding method. The liquid crystal display panel includes a first glass substrate 106, a second glass substrate 108, an amorphous silicon thin film transistor liquid crystal display layer 111, and a thin film transistor circuit layer located on the first glass substrate 106 and the second glass substrate 108. Among them, a plurality of transparent electrode lines 114 are located on the lower surface of the first glass substrate 106 and a plurality of metal plugs 113 are in the first glass substrate 106. The metal plugs 113 are respectively connected to the transparent electrode lines 114. The structure of a glass substrate 106 can be referred to the second substrate 22 of the present invention. The metal bump 72 of the second substrate 22 is connected to the metal plug 113 through a solder layer 107. The material of the solder layer 107 includes a gold-tin alloy layer, a A tin-silver alloy layer, a tin-silver-copper alloy layer, an indium layer, a tin-bismuth alloy layer, a lead-free alloy layer, or a lead-containing alloy layer. In addition, the metal plug 113 and the transparent electrode line 114 are electrically connected to each other. The liquid crystal display panel substrate includes a plurality of liquid crystal display panels. The liquid crystal display panel may include a touch function. The liquid crystal display panel includes an in-cell TFT LCD thin film transistor liquid crystal display. There are a plurality of optical layers 128 between the two substrates 22 and the liquid crystal display panel substrate, including a diffusion sheet layer, a prism sheet layer, a diffusion layer (or a diffusion plate), and a reflector layer. A minimum distance 106a between the center line of the metal bump 72 and the boundary of the glass substrate 106 is between 30 microns and 100 microns, between 50 microns and 150 microns, between 100 microns and 250 microns, Between 5 microns and 300 microns.

Fifth application of the present invention: As shown in FIG. 16, this fifth application is similar to the fourth application described above, except that an organic light emitting diode layer 110 (polymer light emitting diode layer, PLED) is used instead of the fourth An amorphous silicon thin film liquid crystal display layer 111 in an application structure. The second substrate 22 is bonded to an organic light emitting diode display panel by a flip-chip bonding method. The organic light emitting diode display panel includes a first A glass substrate 106, a second glass substrate 108, an organic light emitting diode layer 110, and a thin film transistor circuit layer are located between the first glass substrate 106 and the second glass substrate 108, and further include a plurality of transparent electrode circuits 114 A plurality of metal plugs 113 are located on a surface below the first glass substrate 106 and a plurality of metal plugs 113 are in the first glass substrate 106. The metal plugs 113 are respectively connected to the transparent electrode lines 114. The structure of the first glass substrate 106 can be referred to the first The two substrates 22 and the metal bumps 72 of the second substrate 22 are connected to the metal plug 113 through a solder layer 107. The material of the solder layer 107 includes a gold-tin alloy layer, a tin-silver alloy layer, Sn - Ag - Cu alloy layer, a layer of indium, tin - bismuth alloy layer, an alloy layer or a lead-free lead alloy layer. In addition, the metal plug 113 and the transparent electrode line 114 are electrically connected to each other. The organic light emitting diode display panel substrate includes a plurality of organic light emitting diode display panels. The organic light emitting diode display panel may include a touch function. The organic light emitting diode display panel may include an in-cell touch panel. Control (in-cell TFT LCD) thin film transistor liquid crystal display. A minimum distance 106a between the center line of the metal bump 72 and the boundary of the glass substrate 106 is between 30 microns and 100 microns, between 50 microns and 150 microns, between 100 microns and 250 microns, Between 5 microns and 300 microns.

A sixth application of the present invention: as shown in FIG. 17a, the second substrate 22 may be an organic light emitting diode display surface A part of the board, the organic light emitting diode display panel substrate includes a second substrate 22 and a second glass substrate 108, and an organic light emitting diode layer 110 and a thin film transistor circuit layer are located on the second substrate 22 and the second substrate. Between the glass substrates 108, wherein the metal plug 21 in the second substrate 22 can be connected to the transparent electrode line 114 through the first metal layer 26, the organic light emitting diode display panel substrate includes a plurality of organic light emitting diode display panels, wherein The organic light emitting diode display panel may include a touch function. The organic light emitting diode display panel may include an in-cell TFT LCD thin film transistor liquid crystal display.

As shown in FIG. 17b, the organic light emitting diode display panel structure in the sixth application may include a plurality of thin film transistor circuit layers 700 and a plurality of organic light emitting elements 800 between the second substrate 22 and the second glass substrate 108. The thin film transistor circuit layer 700 includes a buffer layer 702 formed on the second substrate 22, a first gate electrode layer 704a and a first source electrode layer 704b are formed on the buffer layer 702, and a first insulating layer 706 Formed on the first gate electrode layer 704a, the first source electrode layer 704b, and the buffer layer 702, and a semiconductor oxide layer 710 is formed on the first insulating layer 706, the first gate electrode layer 704a, and the first source electrode layer On 704b, the oxide semiconductor layer 710 is connected to the first source electrode layer 704b through the opening of the first insulating layer 706. A second insulating layer 712 is formed on the oxide semiconductor layer 710 and the first insulating layer 706, and a second gate An electrode layer 714a and a second source electrode layer 714b are formed on the second insulating layer 712. The second source electrode layer 714b0 is connected to the oxide semiconductor layer 710 through the opening of the second insulating layer 712, and a protective layer 716 is formed on the first Two gate electrode layers 714a, second source On the electrode layer 714b and the second insulating layer 712, the organic light emitting element 800 is formed on the protective layer 716, and is connected to the second source electrode layer 714b through the opening of the protective layer 716.

The material of the oxide semiconductor layer 710 may include zinc oxide (ZnO). ZnO may be doped with at least one ion selected from the group consisting of: gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), magnesium (Mg ), Vanadium (V), and the material of the first gate electrode layer 704a, the first source electrode layer 704b, the second gate electrode layer 714a, and the second source electrode layer 714b may include tungsten (W), titanium ( Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), or an alloy thereof.

The organic light emitting device 800 includes an anode layer 802, a cathode layer 804, and an organic light emitting layer 806. The organic light emitting layer 806 is between the anode layer 802 and the cathode layer 804. The anode layer 802 is formed on the protective layer 716 and is connected to A second source electrode layer 714b, a third insulating layer 808 is formed on the protective layer 716 and the anode layer 802, and then an opening is formed in the third insulating layer 808 on the anode layer 802, and an organic light emitting layer 806 is formed on the third insulating layer. In the opening of the layer 808, a cathode layer 804 is formed on the third insulating layer 808 and the organic light-emitting layer 806. The buffer layer 702, the first insulating layer 70, the second insulating layer 712, and the protective layer 716 can be formed and formed. A conductive layer is used to connect the anode layer 802 to the metal plug 21 in the second substrate 22 through the conductive layer. In addition, the buffer layer 702, the first insulating layer 706, the second insulating layer 712, the protective layer 716, and the third insulating layer can be used. 808 forms an opening and forms a conductive layer. The cathode layer 804 is connected to the metal plug 21 in the second substrate 22 through the conductive layer. In addition, the buffer layer 702, the first insulating layer 706, the second insulating layer 712, the protective layer 716, and the first Three insulation layer 808 May include polyimide, polyamide, acryl resin, benzocyclobutene, phenol resin, silicon oxide layer (buffer layer 702 material) Silicon oxynitride layer (material of buffer layer 702).

The material of the anode layer 802 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), Indium gallium oxide (IGO), and aluminum zinc oxide (AZO), or at least one transparent material, or aluminum (Al), platinum (Pt), palladium (Pd) , Silver (Ag), magnesium (Mg), gold (Au), nickel (N), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo) , Titanium (Ti), tungsten (W), and copper (Cu) at least one metal group, and the material of the cathode layer 804 may include indium tin oxide (ITO), indium zinc oxide (indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO) At least one transparent material in the group.

The organic light emitting layer 806 may further include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The material of the organic light emitting layer 806 may include a host material of carbazole biphenyl (CBP) or 1,3-bis (carbazole-9-yl) benzene (mCP), and a material selected from two (1) -Phenylisoquinoline) (acetylacetonate) and iridium (III) (bis (1-phenylisoquinoline) (acetylacetonate) iridium, PIQIr (acac)), bis (1-phenylquinoline) (acetamidoacetone) Iridium (III) (bis (1-phenylquinoline) (acetylacetonate) iridium, PQIr (acac)), tris (1-phenylquinoline) iridium (III) (tris (1-phenylquinoline) iridium, PQIr), and eight Octaethylporphyrin platinum (PtOEP), a dopant material of at least one phosphorescent material, tris (dibenzoylmethane) (o-phenanthroline) 铕 (III)) (tris ( Dibenzoylmethane) (o-phenanthroline) europium (III), PED: Eu (DBM) 3 (Phen)) or perylene. The hole transport layer can be made from N, N'-bis (naphthalene-1-yl) -N, N'-diphenylbiphenyl (N, N'-Di (naphthalene-1-yl) -N, N'-diphenylbenzidine) , NPB) or poly (2,4-dioxyethylthiophene) (PEDOT). The hole injection layer can be made of copper phthalocyanine (CuPc) or 4,4 ', 4 "-tris (N- (3-methylphenyl) -N-phenylamino) triphenylamine (4,4', 4 "-tris (N- (3-methylphenyl) -N-phenylamino) triphenylamine, MTDATA).

As shown in FIG. 18 and FIG. 19, the display panel packaging structure generated by the first to sixth applications described above is a frameless display panel 119. The frameless display 119 includes a display area 119a. The region 119a has four display borders 119b. The distance between the display border 119b and the side border of the frameless display panel 119 is less than 15 microns, less than 20 microns, less than 30 microns, less than 50 microns, or less than 100 microns. The frame display panel 119 may be disposed in the housing 123 of a display device 125, and some elements may also be disposed in the display device 125 (or disposed on the second substrate 22), such as a speaker element, A battery element, a microphone element, a signal receiver element, a wireless signal receiving element or a wireless signal transmitting element.

As shown in FIG. 17, the display device 125 includes a plurality of connection terminals 127 on the housing 123. The connection terminals 127 include a signal connection terminal, a power connection terminal, and a ground connection terminal. The display device 125b is assembled and combined into another larger display device 129, wherein the connection end 127 of the display device 125 and the connection end 127 of the other display device 125b are connected to each other during assembly. The multiple display device 125 of the present invention can be assembled and combined into a large-scale display device. The display device, for example, assembled into an advertisement signboard, or the multiple display device 125 of the present invention can be used as a tile on the wall of a building, or can be used as a display element on the surface of a magic block.

The components, steps, features, benefits, and advantages that have been discussed are merely illustrative. None of them are discussed about them, nor are they intended to limit the scope of protection in any way. Many other specific embodiments are also intended to be included. It includes specific embodiments with fewer, additional, and / or different components, steps, features, benefits, and advantages. It also includes specific embodiments in which components and / or steps are arranged and / or sequenced in different ways.

When reading this disclosure, those skilled in the art will understand that the specific embodiments of this disclosure can be implemented or borrowed on computer hardware, software, firmware, or any combination thereof, and on one or more networks. help. Appropriate software may include computer-readable or machine-readable instructions on methods and techniques (and portions thereof) for designing and / or controlling the fabrication of wafer structures in accordance with the present disclosure. Any suitable software language can be used (machine-dependent or machine-independent). Furthermore, the specific embodiments of the present disclosure can be included in or performed by various signals, such as transmission over a wireless RF or IR communication link or downloading from the Internet.

Unless otherwise mentioned, all measurements, values, values, grades, positions, degrees, sizes, and other specifications described in this patent specification, including those in the claims below, are approximate or rated values and are not necessarily accurate ; It is intended to have a reasonable scope, it is related to its functions and consistent with those related to this technique.

Nothing that has been stated or stated is intended or should be construed as exclusive use that would cause any component, step, feature, purpose, benefit, advantage, or equivalent of disclosure, whether or not it is described in a claim.

The scope of protection is limited only by the request. After understanding this patent specification and the following implementation history to explain it, the scope is intended and should be interpreted as broad as consistent with the general meaning of the language used in the claim, and encompasses all structural and functional equivalents .

Claims (10)

A packaging structure includes: a first glass substrate having a first surface and a second surface, the second surface is opposite and parallel to the first surface, wherein the first glass substrate is provided with a plurality of metal plugs and penetrates the glass substrate , The upper surfaces of the metal plugs are coplanar with the first surface, the lower surfaces of the metal plugs are coplanar with the second surface; a metal circuit layer is disposed on the glass substrate and connected to the metal plugs One, the metal circuit layer has a first metal layer under the second surface and a bottom insulating dielectric layer under the first metal layer; a first metal bump is disposed under the glass substrate And connected to the metal circuit layer, wherein the first metal bump is located under the lowermost insulating dielectric layer and the first metal layer, the first metal bump passes through an opening of the lowermost insulating dielectric layer and the The first metal layer is connected to one of the metal plugs, the first metal bump has a second metal layer and a third metal layer in the opening of the bottom insulating dielectric layer and located in the bottom layer of insulation Under the surface of the dielectric layer; a first chip is located above the first surface and connected to the first metal bump through one of the metal plugs and the first metal layer; and an organic light emitting diode ( (OLED) display panel has a second glass substrate located under the first glass substrate and the first wafer, wherein the first metal bump is located between the first glass substrate and the second glass substrate and is electrically conductive The layers are connected to an electrical connection point of the organic light emitting diode (OLED) display panel, wherein the conductive layer is located between the first glass substrate and the second glass substrate and directly connects the electrical connection point and the The first metal bump. The packaging structure as described in item 1 of the application scope, wherein the metal plug includes a copper layer. The packaging structure as described in item 1 of the application scope, wherein the metal bump comprises a gold layer. According to the packaging structure described in item 1 of the application scope, a minimum distance between the center line of the first metal bump and a boundary of the second glass substrate is between 5 μm and 300 μm. The packaging structure as described in item 1 of the application scope, wherein the metal circuit layer includes a copper layer. The packaging structure as described in item 1 of the application scope, wherein the first chip includes a central processing unit (CPU) chip. The packaging structure as described in item 1 of the application scope, wherein the first chip includes a logic chip. The packaging structure as described in item 1 of the scope of application further includes a second chip and a plurality of passive components on the first surface, wherein a first connection point of the second chip is electrically connected to one of the ones A metal plug, a second connection point of the passive element is electrically connected to one of the metal plugs. As in the packaging structure described in item 1 of the application scope, the widths of the upper and lower surfaces of the metal plug are the same. As in the packaging structure described in item 1 of the scope of application, the upper and lower surfaces of the metal plug have the same area.