WO2019044857A1 - Wiring substrate, component mounting wiring substrate, semiconductor device, and method for manufacturing wiring substrate - Google Patents

Wiring substrate, component mounting wiring substrate, semiconductor device, and method for manufacturing wiring substrate Download PDF

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Publication number
WO2019044857A1
WO2019044857A1 PCT/JP2018/031835 JP2018031835W WO2019044857A1 WO 2019044857 A1 WO2019044857 A1 WO 2019044857A1 JP 2018031835 W JP2018031835 W JP 2018031835W WO 2019044857 A1 WO2019044857 A1 WO 2019044857A1
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WO
WIPO (PCT)
Prior art keywords
substrate
wiring
insulating layer
wiring board
conductive portion
Prior art date
Application number
PCT/JP2018/031835
Other languages
French (fr)
Japanese (ja)
Inventor
直大 高橋
真史 榊
啓吾 太田
宏 馬渡
俵屋　誠治
Original Assignee
大日本印刷株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大日本印刷株式会社 filed Critical 大日本印刷株式会社
Priority to JP2019539550A priority Critical patent/JP7184041B2/en
Publication of WO2019044857A1 publication Critical patent/WO2019044857A1/en
Priority to JP2022186816A priority patent/JP7400927B2/en
Priority to JP2023207045A priority patent/JP2024026314A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present disclosure relates to a wiring board, a semiconductor device, and a method of manufacturing the wiring board.
  • a technology (high density mounting technology) for mounting a high frequency element including a semiconductor element including an integrated circuit and a high frequency element including a passive element on a substrate at a high density is widely used.
  • As the high density mounting technology a wire bonding method of connecting using a small wire, a flip chip method of connecting using a connection terminal arranged in a grid shape without using a wire, or the like is adopted.
  • Patent Document 1 discloses a high density mounting technique using a flip chip method.
  • Patent Document 2 discloses the structure of a multilayer wiring board used for high density mounting technology.
  • connection terminals formed by the electrolytic plating method may have a large height variation (coplanarity). If the coplanarity is increased, there is a possibility that a connection failure may occur between the wiring substrate and the semiconductor element.
  • a multilayer wiring board it is necessary to arrange a large number of conductor patterns in the stacking direction or in the in-plane direction of each layer without short-circuiting each other. I can not but differ. Therefore, when the multilayer wiring board is viewed along the stacking direction, the region where the conductor pattern in one wiring layer is present does not partially overlap the region where the conductor pattern is present in another wiring layer. Become.
  • the insulating layers located on the regions where the conductor patterns exist in each wiring layer are formed. The height and the height of the insulating layer located above the area where the conductor pattern does not exist will be different. This causes the height positions of the electrodes provided on the surface layer of the multilayer wiring board to differ.
  • the height positions of a plurality of electrodes provided on the surface layer be approximately the same.
  • the height positions of the plurality of electrodes provided in the surface layer do not substantially coincide with each other, it becomes difficult to stably mount the electronic component.
  • the present disclosure aims to provide a wiring substrate with less variation in height of connection terminals. Another object of the present disclosure is to provide a high quality wiring board on which electronic components can be stably mounted, and a component mounting wiring board.
  • a substrate an insulating layer on the substrate, a height adjusting portion provided in the insulating layer, a first conductive portion provided on the insulating layer, and a first conductive portion And a second conductive portion provided on the insulating layer and the height adjusting portion, the height from the upper surface of the substrate to the upper surface of the first conductive portion, and the upper surface of the substrate to the upper surface of the second conductive portion
  • a wiring board is provided, the heights of which substantially match.
  • the wiring substrate includes a lower wiring provided between the substrate and the insulating layer, and a via portion provided in the insulating layer and disposed on the lower wiring, and the height adjusting portion is formed in the via portion.
  • the first conductive portion may be adjacent to the dummy via portion provided in the insulating layer, and the first conductive portion may be disposed on the insulating layer and the via portion and electrically connected to the lower wiring.
  • the height from the top surface of the substrate to the bottom of the via portion may be different from the height from the top surface of the substrate to the bottom of the dummy via portion.
  • the height from the top surface of the substrate to the bottom of the dummy via portion may be longer than the height from the top surface of the substrate to the bottom of the via portion.
  • a part of the lower wiring may overlap with and be separated from the second electrode.
  • the difference between the height from the top surface of the substrate to the top of the first electrode and the height from the top surface of the substrate to the top of the second electrode may be 1 ⁇ m or less.
  • the distance between the center line of the first electrode and the center line of the second electrode may be 10 ⁇ m to 100 ⁇ m in a cross sectional view.
  • the distance between the center of the first electrode and the center of the second electrode may be 20 ⁇ m to 50 ⁇ m.
  • the upper diameter of the via portion and the upper diameter of the dummy via may be 3 ⁇ m or more and 30 ⁇ m or less.
  • the distance between the center of the bottom of the via portion and the center of the bottom of the dummy via may be 5 ⁇ m to 10 ⁇ m.
  • the upper surfaces of the first electrode and the second electrode may be curved.
  • the wiring substrate may further include an upper wiring disposed on the insulating layer, and the upper wiring and the second electrode may be electrically connected.
  • the first conductive part, the second conductive part, the height adjusting part, and the insulating layer are formed by laminating first to Nth (N is an integer of 2 or more) wiring layers in this order.
  • An interlayer connection portion for electrically connecting at least two of the first to Nth wiring layers, which is a part of the multilayer wiring layer, is provided, and the insulating layer is formed of the first to Nth wiring layers.
  • the first conductive portion and the second conductive portion constitute an Nth wiring layer, and the height adjustment portion is disposed below the stacking direction of the second conductive portion. It may be provided in at least a part of the conductive portion constituting each of the first to (N-1) th wiring layers.
  • N is an integer of 3 or more, and a plurality of height adjusting portions may be provided below the stacking direction of at least a part of the conductor patterns constituting the Nth wiring layer.
  • the height adjusting portion may be electrically separated from the first to Nth wiring layers.
  • the wiring board may further include a plurality of electrodes electrically connected to the Nth wiring layer.
  • a component-mounted wiring substrate including the wiring substrate and at least one electronic component electrically connected to and mounted on any one of a plurality of electrodes.
  • a semiconductor device including the wiring substrate and a semiconductor element.
  • the semiconductor element may be a light emitting element.
  • a lower wiring is formed on a substrate, an insulating layer is formed on the substrate and the lower wiring, a via portion is formed in the insulating layer to overlap the lower wiring, and adjacent to the via portion
  • a method of manufacturing a wiring substrate is provided, in which a dummy via portion is formed in the insulating layer, a first electrode is formed on the via portion and the insulating layer, and a second electrode is formed on the dummy via portion and the insulating layer.
  • the height from the top surface of the substrate to the bottom of the via portion and the height from the top surface of the substrate to the bottom of the dummy via portion may be different in cross section.
  • the via portion and the dummy via portion may be formed using a photolithography method using a halftone mask or a laser irradiation method.
  • a wiring board with less variation in height of connection terminals it is possible to provide a high quality wiring board on which electronic components can be stably mounted, and a component mounting wiring board.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. It is a top view explaining the wiring board concerning one embodiment of this indication. It is a sectional view explaining a wiring board concerning one embodiment of this indication.
  • FIG. 28 is a process diagram illustrating a method of manufacturing a wiring board according to an embodiment of the present disclosure, which is a process diagram illustrating steps subsequent to the process diagram of FIG. 27.
  • 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.
  • 1 is a perspective view of an electrical device according to an embodiment of the present disclosure.
  • 1 is a perspective view of an electrical device according to an embodiment of the present disclosure. It is a sectional view explaining a wiring board concerning one embodiment of this indication.
  • a numerical range represented by using “to” means a range including the respective numerical values described before and after “to” as the lower limit value and the upper limit value.
  • terms such as “film”, “sheet”, “plate” and the like are not distinguished from each other based on difference in designation.
  • “plate” is a concept that also includes members that can be generally called “sheet” and "film”.
  • FIG. 1 shows a cross-sectional view of a light emitting device 1000 which is one of semiconductor devices.
  • the light emitting device 1000 includes the wiring substrate 100, the external terminal 105, the conductive portion 150, the light emitting element 300, the terminal 310, the reflective material 320, the sealing material 330, the lens 340 and the protective member 350.
  • the light emitting element 300 is one of semiconductor elements, and in this example, a GaN-based light emitting diode is used.
  • the reflector 320 has a function of reflecting light.
  • the reflector 320 includes a metal material. In this example, aluminum is used for the reflector 320.
  • the reflector 320 may be formed by depositing metal on the surface of a molded resin.
  • the sealing material 330 has a function of protecting the light-emitting element from external components such as moisture.
  • an organic resin such as an epoxy resin or a silicone resin is used.
  • an inert gas may be used for the sealing material 330.
  • the lens 340 has a function of diffusing or collecting light from the light emitting element.
  • a transparent material such as quartz is used.
  • the protective member 350 has a function of protecting the light emitting element from physical impact.
  • the protective member 350 has translucency.
  • an organic resin such as an epoxy resin or an acrylic resin is used.
  • the wiring substrate 100 is electrically connected to the light emitting element 300.
  • the conductive portion 150 (for example, the conductive portion 150-1 described later) of the wiring substrate 100 and the terminal 310 of the light emitting element 300 are connected by the flip chip method.
  • 24 or more conductive parts 150 (for example, conductive parts 150-1 described later) of the wiring substrate are arranged.
  • the external terminals 105 are provided on the wiring substrate 100.
  • the external terminal 105 is connected to an external wiring board or an electrode.
  • the details of the wiring substrate 100 and the conductive portion 150 will be described later. Note that the conductive portion, the terminal, the wiring, and the electrode can be used in the same meaning.
  • FIG. 2 is a top view of the wiring substrate 100 of FIG.
  • FIG. 3 is a cross-sectional view of the wiring substrate 100 between A1 and A2.
  • the wiring substrate 100 includes a substrate 110, a lower wire 120, an insulating layer 130, a via portion 141, a dummy via portion 143, and a conductive portion 150 (conductive portions 150-1 and 150-2).
  • a high resistance material is used for the substrate 110.
  • a silicon substrate is used as the substrate 110.
  • the thickness of the substrate 110 is not particularly limited, but may be appropriately set in the range of 100 ⁇ m to 700 ⁇ m. For example, 400 ⁇ m is used as the thickness of the substrate 110.
  • the substrate 110 may be an organic resin.
  • the thickness of the substrate 110 may be several ⁇ m to several tens ⁇ m.
  • the lower wiring 120 is provided on the substrate 110. Copper (Cu) is used for the lower interconnection 120. In addition to the copper (Cu), metal materials such as aluminum (Al), titanium (Ti), tungsten (W), gold (Au), silver (Ag), or nickel (Ni) are used for the lower wiring 120. It may be used.
  • the insulating layer 130 is provided on the substrate 110 and the lower wire 120.
  • a polyimide resin is used for the insulating layer 130.
  • the polyimide resin may also contain a photosensitive material.
  • the insulating layer 130 is not limited to the above.
  • an inorganic insulating material such as a silicon oxide film or a silicon nitride film may be used.
  • another organic insulating material such as an acrylic resin or an epoxy resin may be used.
  • the via portion 141 is a recess provided in the insulating layer 130.
  • the via portion 141 is disposed on the lower wire 120.
  • the dummy via portion 143 is a concave portion provided in the insulating layer 130 adjacent to the via portion 141.
  • the conductive portion 150 is disposed on the insulating layer 130.
  • a conductive portion 150-1 (or sometimes referred to as a first conductive portion).
  • the conductive portion 150-1 protrudes above the insulating layer 130.
  • a conductive portion 150-2 (or sometimes referred to as a second conductive portion).
  • the conductive portion 150-2 protrudes above the insulating layer 130.
  • the conductive portion 150-2 is disposed adjacent to the conductive portion 150-1. Note that the conductive portion 150-1 and the conductive portion 150-2 will be described as the conductive portion 150 when it is not necessary to separate them.
  • Conductive portion 150 includes a seed layer 147. Although copper (Cu) is used for the seed layer 147 and the conductive portion 150, gold (Au), silver (Ag), palladium (Pd), nickel (Ni), tin (Sn) are not limited thereto. It may be used.
  • the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 may not be flat.
  • the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 are curved.
  • the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have a convex shape.
  • a region 150-1F provided in the via portion 141 of the conductive portion 150-1 is electrically connected to the lower wire 120.
  • region 150-2 F provided in dummy via portion 143 of conductive portion 150-2 does not have electrical connection with lower interconnection 120. That is, it can be said that the region 150-1F constitutes a part of the electric circuit, whereas the region 150-2F is not a component of the electric circuit.
  • FIG. 4 is a cross-sectional view showing the positional configuration of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 in the wiring substrate 100.
  • the distance from the top surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141 is a distance DL1.
  • the distance from the top surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 is a distance DL2.
  • the distances DL1 and DL2 may be different. Specifically, it is desirable that the distance DL2 be longer than the distance DL1.
  • the upper diameter 141 W of the via portion 141 and the upper diameter 143 W of the dummy via portion are desirably 3 ⁇ m or more and 30 ⁇ m or less, more preferably 5 ⁇ m or more and 10 ⁇ m or less.
  • the distance between the center line 150-1C of the conductive portion 150-1 provided in the vertical direction with respect to the substrate 110 and the center line 150-2C of the conductive portion 150-2 Some 150P is preferably 10 ⁇ m to 100 ⁇ m, more preferably 20 ⁇ m to 50 ⁇ m.
  • the distance from the top surface 110A of the substrate 110 to the top 150-1A of the conductive portion 150-1 is a distance UL 150-1.
  • the distance from the top surface 110A of the substrate 110 to the top 150-2A of the conductive portion 150-2 is taken as a distance UL150-2.
  • FIG. 36 shows a cross-sectional view of the wiring board 90 of the conventional example.
  • wiring substrate 90 has the same configuration as wiring substrate 100 except that dummy via portion 143 is not provided. Since the wiring board 90 does not have the dummy via portion 143, the conductive portion 150-2 is provided only on the insulating layer 130.
  • the difference between the distance UL150-1 and the distance UL150-2 is about 1.5 to 3 ⁇ m, the height of the terminal is not stable, and a step is generated. Therefore, in the wiring substrate 90, when the distance 150P between the pitches becomes small, that is, the pitch becomes narrow (specifically, the distance 150P between the pitches is 100 ⁇ m or less, more specifically 50 ⁇ m or less). A connection failure is likely to occur between terminals of the semiconductor element. In particular, the connection failure is remarkable when the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have a convex shape.
  • the difference between the distance UL150-1 and the distance UL150-2 is provided by providing the dummy via portion 143 (also referred to as a height adjusting portion) in a portion not having the via portion 141. Can be made smaller.
  • the difference between the distance UL150-1 and the distance UL150-2 can be made 1 ⁇ m or less, more specifically, 0.5 ⁇ m or less. That is, by using this embodiment, it is possible to provide a wiring substrate with less variation in height of connection terminals. As a result, connection defects between the terminals of the wiring board and the terminals of the semiconductor element can be suppressed.
  • a substrate 110 is used.
  • a high resistance substrate such as a silicon substrate is used as the substrate 110.
  • the substrate 110 is not limited to the above, and may be a quartz glass substrate, a soda glass substrate, a borosilicate glass substrate, an alkali-free glass substrate, a sapphire substrate, an alumina carbide (Al 2 O 3 ) substrate, an aluminum nitride (AlN) substrate, A zirconia (ZrO 2 ) substrate, a resin substrate containing acrylic or polycarbonate, or the like, or a laminate of these substrates may be used.
  • a quartz glass substrate a soda glass substrate, a borosilicate glass substrate, an alkali-free glass substrate, a sapphire substrate, an alumina carbide (Al 2 O 3 ) substrate, an aluminum nitride (AlN) substrate, A zirconia (ZrO 2 ) substrate, a resin substrate containing acrylic or polycarbonate, or the like, or a laminate of these substrates may be used.
  • the substrate 110 may be a metal substrate on which an organic insulating layer or an inorganic insulating layer is formed.
  • the substrate 110 may be a through electrode substrate. In this case, a current can flow from the top surface 110A of the substrate 110 to the opposite side, which is preferable in separately providing the external terminal 105 shown in FIG.
  • the lower wiring 120 is formed on the substrate 110.
  • the lower wiring 120 is formed by plating, screen printing, sputtering or chemical vapor deposition (CVD).
  • Lower interconnection 120 is processed into a predetermined shape by photolithography and etching as appropriate.
  • the lower wiring 120 is provided on the substrate 110.
  • Copper (Cu) is used for the lower interconnection 120.
  • the lower interconnection 120 may be made of aluminum (Al), gold (Au), silver (Ag), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti), etc. in addition to copper (Cu). The following metal materials may be used.
  • the insulating layer 130 is formed on the substrate 110 and the lower wiring 120.
  • the insulating layer 130 is formed using a printing method, a coating method, or a dipping method.
  • an organic resin such as polyimide, acrylic, epoxy, or benzocyclobutene (BCB) may be used.
  • an organic-inorganic hybrid resin containing silica may be used for the insulating layer 130, or an inorganic film such as silicon oxide or silicon nitride formed by plasma CVD may be used.
  • a photosensitive material may be included.
  • a polyimide resin containing a photosensitive material such as diazonaphthoquinone formed by a coating method is used.
  • the via portion 141 and the dummy via portion 143 are formed in the insulating layer 130.
  • the via portion 141 is formed to overlap the lower wire 120.
  • the dummy via portion 143 is formed adjacent to the via portion 141 with a predetermined interval.
  • the via portion 141 and the dummy via portion 143 are formed using a photolithography method.
  • the portion corresponding to the via portion 141 is exposed as usual.
  • the portion corresponding to the dummy via portion 143 is exposed with the exposure amount reduced by the semi-transmissive film provided on the halftone mask as compared with the portion corresponding to the via portion 141. Therefore, the distance DL1 from the top surface 110A of the substrate 110 after development to the bottom portion 141D of the via portion 141 may be different from the distance DL2 from the top surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143.
  • the distance DL2 is longer than the distance DL1 (in other words, the depth of the dummy via portion 143 is shallower than the depth of the via portion 141).
  • the upper surface of the lower wire 120 is exposed in the via portion 141 by the above process.
  • the conductive portion 150 is formed.
  • the seed layer 147 is formed on the insulating layer 130, the via portion 141 and the dummy via portion 143.
  • the seed layer 147 is formed by an electroless plating method, a sputtering method, a printing method, or the like.
  • copper (Cu) gold (Au), silver (Ag), nickel (Ni), tin (Sn), palladium (Pd) or the like is used for the seed layer 147.
  • a copper (Cu) film formed by electroless plating is used for the seed layer 147.
  • a resist film 149 is formed on the seed layer 147.
  • the resist film 149 may be formed by a coating method, or a dry film resist may be used.
  • the resist film 149 is processed into a predetermined shape by photolithography.
  • the conductive portion 150 is formed in the portion where the seed layer 147 is exposed.
  • the conductive portion 150 is formed by electrolytic plating.
  • the conductive portion 150-1 is formed on the insulating layer 130 and the via portion 141 of the conductive portion 150
  • the conductive portion 150-2 is formed on the insulating layer 130 and the dummy via portion 143.
  • the portion of the seed layer 147 where the resist film 149 (see FIG. 11) and the conductive portion 150 are not formed is removed.
  • the above method is called semi-additive method.
  • the wiring substrate 100 is manufactured by the above method.
  • FIG. 13 shows a top view of the wiring substrate 100-1
  • FIG. 14 shows a cross-sectional view of the wiring substrate 100-1 along the line A1-A2.
  • the wiring substrate 100-1 includes the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2. It has upper wiring 160.
  • the upper wiring 160 is disposed on the insulating layer 130. Upper wire 160 and conductive portion 150-2 are electrically connected. In the wiring substrate 100-1, the conductive portion 150-2 can be used as a terminal.
  • the wiring board 100-1 can have the same effect as the wiring board 100 (the difference between the height of the conductive portion 150-1 and the height of the conductive portion 150-2 becomes smaller) by having the dummy via portion 143. .
  • FIG. 15 shows a top view of the wiring substrate 100-2
  • FIG. 16 shows a cross-sectional view of the wiring substrate 100-2 along line A1-A2.
  • the wiring substrate 100-2 includes the substrate 110, the lower wiring 120-2, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, the conductive portion 150-2, and It has upper wiring 160.
  • Lower interconnection 120-2 is extended so as to be electrically connected to conductive portion 150-1 (conductive portion 150-1L) on the left side and conductive portion 150-1 (conductive portion 150-1R) on the right side. ing. At this time, a portion 120-2P of the lower wire 120-2 overlaps with the conductive portion 150-2 and is separated. With this structure, the wiring board 100-2 can effectively utilize the space.
  • FIG. 17 shows a top view of the wiring board 100-3
  • FIG. 18 shows a cross-sectional view of the wiring board 100-3 along line A1-A2.
  • the wiring substrate 100-3 includes the substrate 110, the lower wire 120-3, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2.
  • the upper wiring 160-3 is provided.
  • a plurality of conductive portions 150-2 are arranged around the conductive portion 150-1. Specifically, eight conductive parts 150-2 are arranged around one conductive part 150-1.
  • the lower wire 120-3 and the upper wire 160-3R of the upper wire 160-3 are disposed in parallel with the insulating layer 130 interposed therebetween.
  • FIG. 19 shows a cross-sectional view of the wiring board 100-4.
  • the wiring substrate 100-4 includes an insulating layer 165 in addition to the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1 and the conductive portion 150-2. And a via portion 171, a dummy via portion 173, and a conductive portion 180 (conductive portions 180-1 and 180-2).
  • the via portion 171 is provided in the insulating layer 165 and disposed on the conductive portion 150-1.
  • the dummy via portion 173 is provided in the insulating layer 165, and is disposed so as to overlap with the conductive portion 150-2.
  • the conductive portion 180-1 is disposed on the insulating layer 165 and the via portion 171.
  • the conductive portion 180-2 is disposed on the insulating layer 165 and the dummy via portion 173.
  • the insulating layer 165 is formed by the same material and method as the insulating layer 130.
  • the insulating layer 165 is formed flat with respect to the top surface 110A of the substrate 110 by the conductive portion 150-2.
  • the via portion 171 is formed by the same method as the via portion 141.
  • the dummy via portion 173 is formed by the same method as the dummy via portion 143.
  • the conductive portion 180 is formed by the same material and method as the conductive portion 150.
  • the conductive portion 150 and the conductive portion 180 are stacked.
  • the distance from the upper surface 110A of the substrate 110 to the top 180-1A of the conductive portion 180-1 is taken as a distance UL 180-1.
  • the distance from the top surface 110A of the substrate 110 to the top 180-2A of the conductive portion 180-2 is a distance UL180-2.
  • the difference between the distance UL180-1 and the distance UL180-2 can be 1 ⁇ m or less. Therefore, the wiring board 100-5 can be mounted at high density as in the case of the wiring board 100.
  • the conductive portion 180-2 and the conductive portion 150-2 may be connected.
  • FIG. 20 shows a cross-sectional view of the wiring board 100-5.
  • the wiring substrate 100-5 includes an insulating layer 165 in addition to the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1 and the conductive portion 150-2.
  • the via portion 175 is formed by the same method as the via portion 171.
  • the conductive portion 183-1 is disposed on the insulating layer 165 and the conductive portion 150-1.
  • the conductive portion 183-1 is connected to the conductive portion 150-1.
  • the conductive portion 183-2 is disposed on the insulating layer 165 and the conductive portion 150-2. Conductive portion 183-2 is connected to conductive portion 150-2.
  • the conductive portion 183 is formed by electroless plating. In the conductive portion 183, nickel (Ni), palladium (Pd) and gold (Au) are sequentially stacked.
  • the conductive portion 183 may be referred to as UBM (Under Bump Metallization).
  • the conductive portion 185-1 is disposed on the conductive portion 183-1.
  • the conductive portion 185-2 is disposed on the conductive portion 183-2.
  • the conductive portion 185 contains tin (Sn).
  • the conductive portion 185 is soldered on the conductive portion 183.
  • the conductive portion 185 may be referred to as a solder bump.
  • the conductive portion 183 and the conductive portion 185 are sequentially stacked on the conductive portion 150.
  • the distance from the top surface 110A of the substrate 110 to the top portion 185-1A of the conductive portion 185-1 is a distance UL 185-1.
  • the distance from the top surface 110A of the substrate 110 to the top portion 185-2A of the conductive portion 185-2 is a distance UL 185-2.
  • the difference between the distance UL185-1 and the distance UL185-2 can be 1 ⁇ m or less. Therefore, also in the wiring substrate 100-5, connection failure can be suppressed and mounting can be performed with high density.
  • the conductive portion 183 and the conductive portion 185 are stacked in the wiring substrate 100-5 is illustrated, only one of the conductive portion 183 and the conductive portion 185 may be disposed.
  • FIG. 21 is a schematic cross-sectional view showing a multilayer wiring board in the third embodiment.
  • the schematic configuration of the multilayer wiring board 200 in the third embodiment will be described.
  • the multilayer wiring board 200 includes a multilayer wiring layer 200A in which the first wiring layer WL1 and the second wiring layer WL2 are stacked in this order on the upper surface 210H of the substrate 210.
  • the insulating layer 221 is located between the first wiring layer WL1 and the second wiring layer WL2, and the insulating layer 222 is located on the second wiring layer WL2.
  • An electrode 241 (also referred to as a first electrode) and an electrode 242 (also referred to as a second electrode) are provided on the insulating layer 222 which is to be a surface layer of the multilayer wiring layer 200A.
  • the electrode 242 is disposed adjacent to the electrode 241.
  • the first wiring layer WL1 is formed of a conductor pattern 211
  • the second wiring layer WL2 is formed of a conductor pattern 212 (also referred to as a first conductive portion) and a conductor pattern 213.
  • the conductor pattern 211 is located on the top surface 210H of the substrate 210 together with a height adjustment pattern 250 (also referred to as a height adjustment portion) described later, and the conductor pattern 211 and the height adjustment pattern 250 are the top surface of the substrate 210. In the in-plane direction of 210H, they are positioned at a predetermined distance from each other.
  • the conductor pattern 212 and the conductor pattern 213 are located at a predetermined distance from each other in the in-plane direction on the insulating layer 221.
  • Conductor patterns 211, 212, and 213 are also referred to as conductive portions.
  • the conductor pattern to be described later can be similarly made to be a conductive portion.
  • the conductive pattern 212 is also referred to as a first conductive portion
  • the conductive pattern 213 is also referred to as a second conductive portion.
  • the “substrate” in the third embodiment is not an abbreviation of an electronic circuit board, but means a board serving as a base for producing the multilayer wiring board 200. That is, as long as the wiring layer and the insulating layer can be sequentially stacked and formed as the wiring substrate, the substrate 210 in the multilayer wiring substrate 200 may not be an essential component.
  • the type of the substrate 210 is not particularly limited, and examples thereof include a glass epoxy substrate, a glass substrate, a silicon substrate, and the like.
  • the size, thickness and the like of the substrate 210 can be appropriately set in accordance with the desired size of the multilayer wiring substrate 200, the size and the number of electronic components mounted on the multilayer wiring substrate 200, and the like.
  • the electronic components that can be mounted on the multilayer wiring board 200 in the third embodiment include, for example, passive elements such as resistors, capacitors, and inductors, as well as active elements such as relays, transistors, and integrated circuits (ICs). Etc. Further, in the third embodiment, a multilayer wiring board on which any one or more of the electronic components exemplified above are mounted is referred to as a "component mounting wiring board".
  • the conductor pattern 211 and the conductor pattern 212 are made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like.
  • the conductor pattern 211 and the conductor pattern 212 are connected to each other through the via 231, and the electrode 241 is continuous with the upper surface of the conductor pattern 212. And the electrodes 241 can be electrically connected to each other (FIG. 21).
  • the conductive pattern 213 is also made of a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like.
  • the conductor pattern 212 and the electrode 242 can be electrically connected to each other by the fact that the electrode 242 is continuous with the upper surface of the conductor pattern 213 (FIG. 21).
  • the width and thickness of the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213 are appropriately set according to the size of the multilayer wiring board 200, the size and number of electronic components mounted on the multilayer wiring board 200, and the like. obtain.
  • the insulating layer 221 and the insulating layer 222 are made of, for example, an insulating material such as an epoxy resin, a polyimide resin, or an acrylic resin.
  • Insulating layer 221 is located on upper surface 210 H of substrate 210 so as to cover conductor pattern 211 and height adjustment portion 50, and insulating layer 222 is the upper surface of insulating layer 221 so as to cover conductor pattern 212 and conductor pattern 213. It is located in The thicknesses of the insulating layer 221 and the insulating layer 222 can be appropriately set in accordance with the desired size of the multilayer wiring board 200, the size and number of the conductor patterns, and the like.
  • the vias 231 are made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, as with the conductor patterns 211 to 213.
  • the dimensions and depth (height) of the via 231 are not particularly limited, but the size of the desired multilayer wiring board 200, the size and number of each of the conductor patterns 211 to 213, the thickness of each insulating layer, etc. It may be set appropriately according to
  • the electrode 241 and the electrode 242 are made of, for example, a metal material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), and a lead-tin alloy.
  • the electrodes 241 and 242 can be electrically connected to external terminals of an electronic component such as a semiconductor chip mounted on the multilayer wiring substrate 200.
  • the dimensions and thicknesses of the electrodes 241 and 242, and the shapes and heights of the electrodes 241 and 242 protruding from the upper surface of the insulating layer 222 are illustrated as long as electronic components can be stably mounted on the multilayer wiring substrate 200. It is not limited to the aspect represented by 21.
  • a portion of the electrode 241 protruding above the insulating layer 222 is referred to as a first protrusion, and a portion of the electrode 242 protruding above the insulating layer 222 is referred to as a second protrusion.
  • UBM Under Bump Metallization
  • the height adjustment pattern 250 is provided in the insulating layer 221 in the in-plane direction of the upper surface 210H of the substrate 210, and is located at a predetermined distance from the conductor pattern 211.
  • the “height adjustment pattern (also referred to as height adjustment portion)” is a conductor pattern (in the third embodiment, the conductor pattern 212 and the conductor in the third embodiment of the multilayer wiring board 200). This means a pattern for adjusting the height position in the stacking direction of the pattern 213).
  • the “adjustment” of the electrodes (the electrode 241 and the electrode 242 in the third embodiment) on which the electronic component is mounted
  • the meaning of adjusting the height of the conductor pattern located directly below the electrode is included so that the height positions substantially coincide.
  • the height adjustment pattern 250 is located immediately below the lamination direction of the conductor pattern 213 so as to correspond to the formation position of the conductor pattern 213 (electrode 242). Also, the height adjustment pattern 250 has a thickness substantially the same as the thickness of the conductor pattern 211.
  • the height adjustment pattern 250 is located directly below the conductor pattern 213 in the stacking direction and at the same height (hierarchical level) as the conductor pattern 211 (first wiring layer WL1) in the stacking direction.
  • the material for forming the height adjustment pattern 250 may be, for example, a nonconductive material such as a photosensitive resin material, or a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. It may be.
  • the height adjustment pattern 250 in the third embodiment is made of a conductive material, it is between the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213 from the viewpoint of preventing a short circuit with another conductor pattern. Preferably, they are electrically isolated.
  • the material of the height adjustment pattern 250 is not particularly limited unless otherwise specified in the present specification.
  • FIG. 37 is a reference diagram showing a multilayer wiring board 200 'in which a difference in height position in the stacking direction appears in the insulating layer 222' which is the surface layer by not providing the height adjustment pattern 250. .
  • FIG. 37 is drawn such that “difference D” is exaggerated for ease of understanding, it is not drawn as the actually occurring difference.
  • the effects and advantages of the height adjustment pattern 250 in the third embodiment will be described in detail based on comparison with a multilayer wiring board in which the height adjustment pattern 250 is not provided, with reference to FIG.
  • the conductor pattern 211 is provided on a portion of the upper surface 210H of the substrate 210 corresponding to the portion directly below the stacking direction of the electrodes 241.
  • the conductor pattern 211 is not provided on the Therefore, in the process of forming the multilayer wiring board 200 ′, when the insulating layer 221 ′ is provided to cover the conductor pattern 211, the height of the insulating layer 221 ′ covering the conductor pattern 211 immediately below the stacking direction of the electrodes 241.
  • the position is higher by the thickness of the conductor pattern 211 than the height position of the portion of the insulating layer 221 ′ immediately below the stacking direction of the electrodes 242.
  • the height adjustment pattern 250 is provided at the same height position as the conductor pattern 211 immediately below the stacking direction of the electrodes 242.
  • the upper surface of the insulating layer 221 provided in the upper layer of the upper layer can be made substantially flat, and the height positions of the two conductor patterns 212 and 213 formed on the insulating layer 221 can be made to substantially coincide (FIG. 21).
  • height positions of the electrode 241 and the electrode 242 (specifically, the height from the upper surface of the substrate 210 to the upper surface of the electrode 241 and the height from the upper surface of the substrate 210 to the upper surface of the electrode 242) Can substantially match, and a high quality multilayer wiring board 200 on which electronic components can be stably mounted can be realized.
  • the height adjustment pattern 250 is preferably provided such that the difference in height between the conductor patterns 212 and 213 is, for example, in the range of 0 ⁇ m to 3 ⁇ m, preferably 1.5 ⁇ m or less.
  • FIG. 22 is a schematic cross-sectional view showing a multilayer wiring board in the fourth embodiment.
  • the same reference numerals as in the third embodiment denote the same parts as in the third embodiment, and a detailed description thereof will be omitted.
  • a multilayer wiring board 200 in the fourth embodiment includes a multilayer wiring layer 200A in which three layers of first to third wiring layers WL1 to WL3 are stacked, and a conductor pattern 213 (electrode 242 that constitutes a third wiring layer WL3).
  • the third embodiment is different from the third embodiment in that the height adjustment pattern 251 is provided immediately below the stacking direction and the height adjustment pattern 250 is provided immediately below the height adjustment pattern 251.
  • the second wiring layer WL2 is provided between the first wiring layer WL1 and the third wiring layer WL3, and the second wiring layer WL2 has the conductor pattern 214. It consists of An insulating layer 223 is located between the second wiring layer WL2 and the third wiring layer WL3.
  • the conductor pattern 214 is positioned on the insulating layer 221 together with the height adjustment pattern 251, and the conductor pattern 214 and the height adjustment pattern 251 are spaced apart from each other by a predetermined distance in the in-plane direction on the insulation layer 221. There is. Vias 232 as interlayer connection parts are provided on the conductor patterns 214.
  • the height adjustment pattern 251 has a thickness substantially the same as the thickness of the conductor pattern 214, and has a configuration substantially the same as the height adjustment pattern 250.
  • the conductor pattern 214 is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, similarly to the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213.
  • the conductor pattern 211 and the conductor pattern 214 are connected via the via 231
  • the conductor pattern 214 and the conductor pattern 212 are connected via the via 232
  • the electrode 241 is continuous on the conductor pattern 212.
  • the conductor pattern 211, the conductor pattern 214, the conductor pattern 212, and the electrode 241 can be electrically connected to each other (FIG. 22).
  • the insulating layer 223 can be made of an insulating material such as an epoxy resin, a polyimide resin, or an acrylic resin. Note that the thickness of the insulating layer 223 is in a range that does not cause a short circuit between adjacent wiring layers (the first wiring layer WL1 and the second wiring layer WL2 and the second wiring layer WL2 and the third wiring layer WL3) in the stacking direction. It may be set appropriately.
  • the via 232 is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like.
  • the size (for example, width and depth) of the via 232 is not particularly limited, but it depends on the size of the desired multilayer wiring board 200, the size and pitch of each conductor pattern, the thickness of each insulating layer, etc. It may be set appropriately.
  • the height adjustment pattern 251 is located at a predetermined distance from the conductor pattern 214 in the in-plane direction on the insulating layer 221.
  • the conductor pattern 213 (electrode 242) is located above the height adjustment pattern 251, and the height adjustment pattern 250 is located below the height adjustment pattern 251.
  • the height adjustment pattern 251 has a thickness substantially the same as the thickness of the conductor pattern 214.
  • the height adjustment pattern 250 is positioned at the same height (level) as the conductor pattern 211 (first wiring layer WL1) immediately below the conductor pattern 213 (electrode 242) in the stacking direction, By positioning the height adjustment pattern 251 at the same height as the conductor pattern 214 (the second wiring layer WL2), the upper surface of the insulating layer 223 provided on the upper layer becomes substantially flat.
  • the height positions in the stacking direction of the conductive pattern 212 and the conductive pattern 213 (third wiring layer WL3) can be made approximately equal.
  • the multilayer wiring board 200 including the multilayer wiring layer 200A in which three wiring layers are stacked is described, but the present disclosure is not limited to this, and four or more wiring layers are provided. It may be a multilayer wiring board provided with a multilayer wiring layer in which
  • FIG. 23 is a schematic cross-sectional view showing a multilayer wiring board in the fifth embodiment.
  • the same reference numerals as in the third embodiment denote the same parts as in the third embodiment, and a detailed description thereof will be omitted.
  • the multilayer wiring board 200 in the fifth embodiment is different from the multilayer wiring board 200 in the third embodiment in that the height adjustment pattern 250 is electrically connected to the conductor pattern 213 through the via 233.
  • the height adjustment pattern 250 is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like.
  • the via 233 is also made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, similarly to the via 231.
  • the upper surface of the insulating layer 221 is substantially flat, so the stacking direction of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) provided on the insulating layer 221
  • the height positions of the patterns can be made to substantially coincide with each other, and the height adjustment pattern 250 can be used as part of a conductor pattern electrically connected to the conductor pattern 213 (electrode 242).
  • FIG. 24 is a schematic cross-sectional view showing a multilayer wiring board in the sixth embodiment.
  • the same reference numerals as in the third embodiment denote the same parts as in the third embodiment, and a detailed description thereof will be omitted.
  • the conductor pattern 211 is located not only directly below the lamination direction of the conductor pattern 212 (electrode 241) but also immediately below the lamination direction of the conductor pattern 213 (electrode 242). Is different from the multilayer wiring board 200 and the like of the third embodiment in that it is configured to have a laterally long width in the left-right direction on the illustration. That is, in the multilayer wiring board 200 in the sixth embodiment, the conductor pattern 211 also serves as the height adjustment pattern.
  • the conductor pattern 211 of the first wiring layer WL1 when the conductor pattern 211 of the first wiring layer WL1 is arranged according to the normal wiring rule, the conductor pattern 211 is arranged immediately below the lamination direction of the electrode 241. In some cases, the conductor pattern 211 may not be disposed. In such a case, in the third embodiment, the height adjustment pattern 250 is provided, so that the height positions of the conductor patterns 212 and 213 (electrodes 241 and 242) substantially coincide with each other. In the sixth embodiment, in place of the height adjustment pattern 250 of the third embodiment, the conductor pattern 211 not disposed according to the normal wiring rule is also drawn to the lower side in the stacking direction of the electrodes 242 in the third embodiment.
  • the height positions in the stacking direction of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) provided on the insulating layer 221 should be approximately the same. Can.
  • FIG. 25 is a schematic cross-sectional view showing a multilayer wiring board 200 in the seventh embodiment.
  • the same components as those of the multilayer wiring board 200 in each of the above-described embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted.
  • the conductor pattern 211 is provided in the region below the electrode 241 in the stacking direction, and in the region below the electrode 242 in the stacking direction, the height adjustment pattern 250 is provided.
  • neither the conductor pattern 211 nor the height adjustment pattern 250 is provided in the region below the stacking direction of the portion sandwiched between the electrode 241 and the electrode 242 (see FIG. 25).
  • the upper surface 210H of the substrate 210 is located in the region below the stacking direction of the portion sandwiched between the electrode 241 and the electrode 242.
  • the height position of the covering insulating layer 221 portion is lower than that of the insulating layer 221 covering each of the conductor pattern 211 and the height adjustment pattern 250.
  • the conductor pattern 217 is provided on the lower part of the insulating layer 221, and the height position of the insulating layer 223 covering the conductor pattern 217 covers the part on which the conductor pattern 214 and the conductor pattern 215 are provided. It is lower than the height position of 223.
  • the height positions of the conductor patterns 214 and 215 and the height position of the conductor pattern 217 are shifted.
  • the conductor pattern 218 is provided in the lower portion of the insulating layer 223 via the via 232C. Therefore, the height position of the portion of the insulating layer 222 covering the conductor pattern 218 is lower than the height position of the portion of the insulating layer 222 covering the conductor pattern 212 and the conductor pattern 213 respectively, and the top surface of the insulating layer 222 is formed. It appears as a recess 222C.
  • the recess 222C appears at the center in the in-plane direction of the surface layer of the multilayer wiring layer 200A, but the height positions of the electrodes 241 and 242 on which the electronic components are mounted are approximately one. I do. Therefore, the electronic component 270 can be stably mounted on the multilayer wiring substrate 200 via the electrode 241 and the electrode 242. That is, as in the multilayer wiring board 200 in the seventh embodiment, the wiring layer positioned in the uppermost layer (shown in FIG. 25) as long as there is no influence in stably mounting the electronic component 270 such as the recess 222C. In the embodiment, the height position of the portion (the conductor pattern 218 shown in FIG.
  • FIG. 26 is a schematic cross-sectional view showing a multilayer wiring board 200 in the eighth embodiment.
  • the multilayer wiring substrate 200 in the eighth embodiment is provided with the through hole vias 210TH penetrating in the thickness direction of the substrate 210, the multilayer wiring layer 200A is provided on the upper surface 210H of the substrate 210, and the multilayer wiring is provided on the lower surface 210L of the substrate 210. It has a structure in which the layer 200B is provided.
  • the through hole via 210TH is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like.
  • the through hole via 210TH functions as a conductor for electrically connecting the conductor pattern 211 of the multilayer wiring layer 200A and the conductor pattern 261 of the multilayer wiring layer 200B.
  • the multilayer wiring layer 200A the same configuration as that of the multilayer wiring layer in the multilayer wiring board 200 in the third embodiment is employed.
  • a multilayer structure in which the multilayer wiring layer 200A is inverted with the substrate 210 as a boundary is adopted as the multilayer wiring layer 200B in the eighth embodiment, but this is adopted for the sake of simplicity of the description,
  • the present invention is not limited to the structure, and various laminated structures may be appropriately set.
  • the first wiring layer WL200B formed of the conductor pattern 261 and the second wiring layer WL2B formed of the conductor patterns 262 and 263 are sequentially stacked from the lower surface 210L side of the substrate 210.
  • the insulating layer 271 is located between the layer WL200B and the second wiring layer WL2B, and the insulating layer 272 is located so as to cover the second wiring layer WL2B.
  • the electrode 281 and the electrode 282 are provided on the surface layer of the multilayer wiring layer 200B.
  • the first wiring layer WL200B is configured of the conductor pattern 261, and the conductor pattern 261 is located on the lower surface 210L of the substrate 210 together with the height adjustment pattern 252.
  • the conductor pattern 261 and the height adjustment pattern 252 are positioned at a predetermined distance in the in-plane direction on the lower surface 210L of the substrate 210.
  • the second wiring layer WL2B includes a conductor pattern 262 and a conductor pattern 263, and a via 34 is provided between the conductor pattern 261 and the conductor pattern 262 as an interlayer connection portion for electrically connecting them.
  • the electrode 281 is located on the top surface of the conductor pattern 262, and the electrode 282 is located continuously on the top surface of the conductor pattern 263.
  • the height adjustment pattern 252 has a thickness substantially the same as the thickness of the conductor pattern 261, and has a configuration substantially the same as the height adjustment pattern 250.
  • the height adjustment pattern 252 is located at substantially the same height (level) as the conductor pattern 261 (first wiring layer WL200B), and the stacking direction of the conductor pattern 263 (electrode 282) Since the lower surface of the insulating layer 271 is substantially flat by being positioned directly below, the height positions of the conductor pattern 262 (electrode 281) and the conductor pattern 263 (electrode 282) provided on the insulating layer 271 substantially coincide with each other. It will be done.
  • FIG. 27 is a process diagram illustrating a method of manufacturing a multilayer wiring board according to an embodiment of the present disclosure
  • FIG. 28 is a process diagram illustrating steps subsequent to the manufacturing process of FIG. Below, the manufacturing method of the multilayer wiring board 200 in 3rd Embodiment is demonstrated as an example.
  • a substrate mainly made of glass epoxy having a desired thickness and size is prepared as the substrate 210, and the conductor pattern 211 and the height adjustment pattern 250 are formed on the upper surface 210H of the substrate 210 (FIG. 27).
  • A) As a method of forming the conductive pattern 211, for example, a conductive layer is formed on the upper surface 210H of the substrate 210, a resist pattern is formed on the conductive layer, and then etching is performed using the resist pattern as a mask.
  • the resist pattern may be formed by exposure / development processing on a dry film resist or a liquid resist.
  • the height adjustment pattern 250 may be formed in a predetermined region (region where the height adjustment pattern 250 is to be formed) on the upper surface 210H of the substrate 210 after the conductor pattern 211 is formed, or the conductor pattern 211 is formed. It may be formed before.
  • the height adjustment pattern 250 may be formed simultaneously with the formation of the conductor pattern 211.
  • a method of forming the height adjustment pattern 250 made of a nonconductive material such as a photosensitive resin material
  • a photosensitive resin layer is formed by a spin coating method or the like, and the photosensitive resin layer is exposed to light. The method etc. which develop are mentioned.
  • the substrate 210 is not limited to the above-described substrate mainly composed of glass epoxy, and a substrate mainly composed of glass, silicon or the like may be suitably used.
  • the insulating layer 221 is formed so as to cover the conductor pattern 211 and the height adjustment pattern 250 (FIG. 27B).
  • the insulating layer 221 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating, or bar coating, dried and then heat cured.
  • the height position of the insulating layer 221 on the conductor pattern 211 and the height position of the insulating layer 221 on the height adjustment pattern 250 substantially coincide with each other.
  • a resin material which constitutes insulating layer 221 polyimide resin, acrylic resin, etc. other than epoxy resin are used.
  • the insulating layer 221 may have a single-layer structure or a stacked structure of two or more layers.
  • a through hole 231 ′ which penetrates the insulating layer 221 in the thickness direction is formed so that a part of the top surface of the conductor pattern 211 is exposed (FIG. 27C).
  • the through holes 231 ′ can be formed by, for example, forming a desired resist pattern on the insulating layer 221 and etching the same with a desired etching solution using the resist pattern as a mask.
  • the conductive pattern 212 and the conductive pattern 213 are formed on the insulating layer 221 while filling the through holes 31 ′ with a conductive material to form the vias 231 (FIG. 27D).
  • the via 231, the conductor pattern 212, and the conductor pattern 213 can be formed in the same manner as the above-described conductor pattern 211.
  • an alloy containing copper (Cu), nickel (Ni), gold (Au), or the like is suitably used.
  • the insulating layer 222 is formed to cover the conductor pattern 212 and the conductor pattern 213 (FIG. 28A).
  • the insulating layer 222 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating or bar coating, dried and then heat cured.
  • a resin material which comprises the insulating layer 222 the same thing as the resin material which comprises the insulating layer 221 may be used, and a different kind of resin material may be used.
  • a through hole 241 ′ penetrating the insulating layer 222 in the thickness direction is formed so that a part of the upper surface of the conductor pattern 212 is exposed, and a part of the upper surface of the conductor pattern 213 is exposed, A through hole 242 ′ penetrating in the thickness direction of the insulating layer 222 is formed (FIG. 28 (B)).
  • the through holes 241 ′ and the through holes 242 ′ may be formed by substantially the same method as the method of forming the through holes 231 ′ described above.
  • the through hole 241 ' is filled with a conductive material to form an electrode 241
  • the through hole 242' is filled with a conductive material to form an electrode 242 (FIG. 28C).
  • the electrodes 241 and 242 are made of a material (for example, copper (Cu), nickel (Ni), gold (Au), lead tin alloy, etc.) constituting the electrodes 241 and 42 in the same manner as the conductor patterns 211 to 213. It can be formed.
  • the multilayer wiring board 200 in which the height positions of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) substantially coincide with each other can be manufactured.
  • FIG. 29 is a cross-sectional view of the semiconductor device 500.
  • the semiconductor device 500 includes a chipped semiconductor element 600 including a transistor, a high frequency element 620, an interposer 700, and a package substrate 800.
  • the semiconductor element 600 has a function as a central processing unit (CPU: Central Processing Unit) or a function as a storage device.
  • the high frequency element is a passive element corresponding to high frequency, and includes an inductor, a capacitive element, a resistive element, and the like.
  • the interposer 700 has a function of relaying the package substrate 800, the semiconductor element 600 and the high frequency element 620.
  • the semiconductor element 600 and the high frequency element 620 and the interposer 700 are electrically connected to each other using a terminal 650.
  • the space between the semiconductor element 600 and the high frequency element 620 may be sealed with a mold resin.
  • the interposer 700 and the package substrate 800 are connected using the terminal 750. Further, the gap between the interposer 700 and the package substrate 800 may be sealed using an underfill resin.
  • the wiring substrate 100 can be used for the interposer 700 and the package substrate 800.
  • FIG. 30 and FIG. 31 are diagrams for explaining the electric device.
  • the semiconductor device including the wiring substrate 100 is, for example, a portable terminal (mobile phone, smart phone and notebook personal computer, game machine etc.), an information processing apparatus (desktop personal computer, server, car navigation etc.), home electric appliance It is used for various electric devices such as (microwave oven, air conditioner, washing machine, refrigerator), car and so on.
  • FIG. 30 shows a tiling LED 2000.
  • the light emitting devices 1000 are arranged in a grid shape, and the light emitting devices 1000 are mounted on the wiring substrate 100.
  • the wiring substrate 100 described in the first to eighth embodiments it is possible to suppress the variation in the direction of the light emitting surface of the LED element, and an apparatus with good display performance due to the effect of making it difficult to visually recognize joints of tiling. Can be provided.
  • FIG. 31A shows a smartphone 4000.
  • FIG. 31B shows a portable game machine 5000.
  • FIG. 31C illustrates a laptop personal computer 6000.
  • FIG. 32 is a cross-sectional view of the wiring substrate 100-6. As shown in FIG. 32, even if the distance DL2 is shorter than the distance DL1 in the wiring substrate 100-6, the same effect as the wiring substrate 100 can be obtained.
  • FIG. 25 is a cross-sectional view of the wiring board 100-7. As shown in FIG. 33, in the wiring substrate 100-7, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 may have a recess. Also in the wiring substrate 100-7, the same effect as the wiring substrate 100 can be obtained.
  • FIG. 34 shows a top view of the wiring board 100-8 and FIG. 27 shows a cross-sectional view of the wiring board 100-8 taken along line A1-A2.
  • the wiring substrate 100-8 includes the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, the conductive portion 150-2, the upper wiring
  • a conductive portion 122 is provided.
  • the conductive portion 122 is disposed on the substrate 110 in the same manner as the lower wiring 120. In addition, the conductive portion 122 is disposed to overlap with the dummy via portion 143 and the conductive portion 150-2. At this time, the distance DL1 from the top surface 110A of the substrate 110 to the bottom 141D of the via portion 141 may be equal to the distance DL2 from the top surface 110A of the substrate 110 to the bottom 143D of the dummy via portion 143. In the above, the conductive portion 122 and the conductive portion 150-2 are connected. Note that the conductive portion 122 may not have a function as an electrode.
  • region 150-2F and the conductive portion 122 provided in the dummy via portion 143 in the conductive portion 150-2 may not be components of the electric circuit.
  • region 150-2F on the upper side of region 150-2F in conductive portion 150-2 is connected to upper interconnection 160.
  • the region 150-2U and the upper wiring 160 may form part of an electric circuit.
  • the shapes of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 can be stabilized, and the variation in height of the terminals can be reduced as in the wiring substrate 100. .
  • an excimer laser When the laser irradiation is performed, an excimer laser, a neodymium: Yag laser (Nd: YAG) laser, a femtosecond laser, or the like is used as the laser.
  • an excimer laser When an excimer laser is used, light in the ultraviolet region is emitted.
  • light with a wavelength of 308 nm is emitted.
  • the hole diameter of the via portion 141 and the dummy via portion 143 is controlled by the irradiation diameter of the laser. At this time, the irradiation diameter by the laser may be 5 ⁇ m or more and less than 30 ⁇ m.
  • the output condition of the laser in the case of forming the dummy via portion 143 may be smaller than the output condition of the laser in the case of forming the via portion 141.
  • a reactive ion etching method or a wet etching method may be used, or a combination of a laser irradiation method and a wet etching method may be used.
  • a etching solution for the wet etching method any of hydrofluoric acid (HF), nitric acid (HNO 3 ) and an alkaline solution may be used.
  • the height adjustment pattern is a position deviated in the in-plane direction (left and right direction in the drawing) of the predetermined layer from the position directly below the lamination direction. May be located.

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Abstract

According to an embodiment of the present disclosure, provided is a wiring substrate that includes: a substrate; an insulating layer on the substrate; a height adjustment unit provided within the insulating layer; a first electrically conductive part provided on the insulating layer; and a second electrically conductive part adjacent to the electrically conductive part, provided on the insulating layer and the height adjustment unit, wherein the height from the substrate top surface to the top surface of the first electrically conductive part and the height from the top surface of the substrate to the top surface of the second electrically conductive part approximately match. In the wiring substrate, the height adjustment unit can also be a dummy via part that is adjacent to a via part placed on a lower part wiring, and is provided within the insulating layer. Also, in the wiring substrate, the first electrically conductive part and the second electrically conductive part configure an Nth wiring layer among multi-layer wiring layers made by laminating first to Nth (where N is an integer of 2 or more) wiring layers in this order, and the height adjustment unit, at the lower part in the lamination direction of the second electrically conductive part, may be provided at least on a portion of the electrically conductive parts configuring the respective first to N–1th wiring layers.

Description

配線基板、部品実装配線基板、半導体装置および配線基板の製造方法Wiring board, component mounting wiring board, semiconductor device, and method of manufacturing wiring board
　本開示は、配線基板、半導体装置および配線基板の製造方法に関する。 The present disclosure relates to a wiring board, a semiconductor device, and a method of manufacturing the wiring board.
　集積回路を含む半導体素子や受動素子など含む高周波素子を基板上に高密度に実装する技術（高密度実装技術）が広く用いられている。高密度実装技術には、小さなワイヤを用いて接続するワイヤボンディング法やワイヤを用いずに格子状に配置された接続端子を用いて接続するフリップチップ法などが採用されている。特許文献１には、フリップチップ法を用いた高密度実装技術が開示されている。特許文献２には、高密度実装技術に用いられる多層配線基板の構造が開示されている。 A technology (high density mounting technology) for mounting a high frequency element including a semiconductor element including an integrated circuit and a high frequency element including a passive element on a substrate at a high density is widely used. As the high density mounting technology, a wire bonding method of connecting using a small wire, a flip chip method of connecting using a connection terminal arranged in a grid shape without using a wire, or the like is adopted. Patent Document 1 discloses a high density mounting technique using a flip chip method. Patent Document 2 discloses the structure of a multilayer wiring board used for high density mounting technology.
特開２００４－０５５６６０号公報JP 2004-055660 特開２０１４－１７９５１８号公報JP, 2014-179518, A
　一方で、接続端子間の狭ピッチ化が進むと、接続端子間の高さのばらつきが生じる場合がある。とりわけ、電解めっき法により形成された接続端子は、高さのばらつき（コプラナリティ）が大きくなる場合がある。コプラナリティが大きくなると、配線基板と半導体素子との間で接続不良が生じる恐れがある。 On the other hand, as the narrowing of the pitch between the connection terminals proceeds, variations in height between the connection terminals may occur. In particular, the connection terminals formed by the electrolytic plating method may have a large height variation (coplanarity). If the coplanarity is increased, there is a possibility that a connection failure may occur between the wiring substrate and the semiconductor element.
　また、多層配線基板においては、多数の導体パターンを互いに短絡させることなく積層方向や各層の面内方向に高密度に配置する必要があるため、各配線層を構成する導体パターンの配置態様は各層で異ならざるを得ない。そのため、多層配線基板を積層方向に沿って見た場合に、一の配線層における導体パターンの存在する領域と、他の配線層における導体パターンの存在する領域とが部分的に重なり合わない状態となる。このような多層配線基板を作製するために、導体パターンの配置態様が互いに異なる配線層を、絶縁層を介して積層した場合、各配線層において導体パターンの存在する領域上に位置する絶縁層の高さと、導体パターンの存在しない領域上に位置する絶縁層の高さとが異なることになる。それが原因となり、多層配線基板の表層に設けられる各電極の高さ位置が異なってしまう。 Further, in a multilayer wiring board, it is necessary to arrange a large number of conductor patterns in the stacking direction or in the in-plane direction of each layer without short-circuiting each other. I can not but differ. Therefore, when the multilayer wiring board is viewed along the stacking direction, the region where the conductor pattern in one wiring layer is present does not partially overlap the region where the conductor pattern is present in another wiring layer. Become. In order to produce such a multilayer wiring board, when wiring layers having different arrangement patterns of conductor patterns are stacked via insulating layers, the insulating layers located on the regions where the conductor patterns exist in each wiring layer are formed. The height and the height of the insulating layer located above the area where the conductor pattern does not exist will be different. This causes the height positions of the electrodes provided on the surface layer of the multilayer wiring board to differ.
　一般的に、多層配線基板においては、半導体チップ等の電子部品を安定的に表面実装させるために、表層に設けられる複数の電極同士の高さ位置を略一致させることが望ましい。しかし、上記のように表層に設けられる複数の電極同士の高さ位置が略一致しなくなることで、電子部品を安定的に実装することが困難となってしまう。 In general, in a multilayer wiring board, in order to stably mount an electronic component such as a semiconductor chip on the surface, it is desirable that the height positions of a plurality of electrodes provided on the surface layer be approximately the same. However, as described above, when the height positions of the plurality of electrodes provided in the surface layer do not substantially coincide with each other, it becomes difficult to stably mount the electronic component.
　このような課題に鑑み、本開示は、接続端子の高さのばらつきが少ない配線基板を提供することを目的の一つとする。また、本開示は、電子部品を安定的に実装することができる高品質な配線基板、及び部品実装配線基板を提供することを目的の一つとする。 In view of such problems, the present disclosure aims to provide a wiring substrate with less variation in height of connection terminals. Another object of the present disclosure is to provide a high quality wiring board on which electronic components can be stably mounted, and a component mounting wiring board.
　本開示の一実施形態によると、基板と、基板上の絶縁層と、絶縁層内に設けられた高さ調整部と、絶縁層上に設けられた第１導電部と、第１導電部と隣接し、絶縁層および高さ調整部上に設けられた第２導電部と、を含み、基板上面から第１導電部の上面までの高さと、基板の上面から第２導電部の上面までの高さが略一致している、配線基板が提供される。 According to an embodiment of the present disclosure, a substrate, an insulating layer on the substrate, a height adjusting portion provided in the insulating layer, a first conductive portion provided on the insulating layer, and a first conductive portion And a second conductive portion provided on the insulating layer and the height adjusting portion, the height from the upper surface of the substrate to the upper surface of the first conductive portion, and the upper surface of the substrate to the upper surface of the second conductive portion A wiring board is provided, the heights of which substantially match.
　上記配線基板において、基板と絶縁層との間に設けられた下部配線と、絶縁層内に設けられ、下部配線上に配置されたビア部と、を含み、高さ調整部は、ビア部に隣接し、絶縁層内に設けられたダミービア部であり、第１導電部は、絶縁層およびビア部上に配置されるとともに、下部配線と電気的に接続されてもよい。 The wiring substrate includes a lower wiring provided between the substrate and the insulating layer, and a via portion provided in the insulating layer and disposed on the lower wiring, and the height adjusting portion is formed in the via portion. The first conductive portion may be adjacent to the dummy via portion provided in the insulating layer, and the first conductive portion may be disposed on the insulating layer and the via portion and electrically connected to the lower wiring.
　上記配線基板において、基板の上面からビア部の底部までの高さと、基板の上面からダミービア部の底部までの高さとは異なってもよい。 In the wiring substrate, the height from the top surface of the substrate to the bottom of the via portion may be different from the height from the top surface of the substrate to the bottom of the dummy via portion.
　上記配線基板において、基板の上面からビア部の底部までの高さよりも基板の上面からダミービア部の底部までの高さの方が長くてもよい。 In the wiring substrate, the height from the top surface of the substrate to the bottom of the dummy via portion may be longer than the height from the top surface of the substrate to the bottom of the via portion.
　上記配線基板において、断面視において、下部配線の一部は、第２電極と重畳し、かつ離間してもよい。 In the wiring substrate, in cross section, a part of the lower wiring may overlap with and be separated from the second electrode.
　上記配線基板において、断面視において、基板の上面から第１電極の最上部までの高さと、基板の上面から第２電極の最上部までの高さとの差が、１μｍ以下であってもよい。 In the wiring board, in a cross sectional view, the difference between the height from the top surface of the substrate to the top of the first electrode and the height from the top surface of the substrate to the top of the second electrode may be 1 μm or less.
　上記配線基板において、断面視において、第１電極の中心線と、第２電極の中心線との距離が１０μｍ以上１００μｍ以下であってもよい。 In the wiring board, the distance between the center line of the first electrode and the center line of the second electrode may be 10 μm to 100 μm in a cross sectional view.
　上記配線基板において、第１電極の中心と、第２電極の中心との距離が２０μｍ以上５０μｍ以下であってもよい。 In the wiring substrate, the distance between the center of the first electrode and the center of the second electrode may be 20 μm to 50 μm.
　上記配線基板において、ビア部の上部径およびダミービアの上部径は、３μｍ以上３０μｍ以下であってもよい。 In the wiring substrate, the upper diameter of the via portion and the upper diameter of the dummy via may be 3 μm or more and 30 μm or less.
　上記配線基板において、ビア部の底部の中心と、ダミービア部の底部の中心との距離が５μｍ以上１０μｍ以下であってもよい。 In the wiring substrate, the distance between the center of the bottom of the via portion and the center of the bottom of the dummy via may be 5 μm to 10 μm.
　上記配線基板において、第１電極および第２電極の上面は湾曲していてもよい。 In the wiring board, the upper surfaces of the first electrode and the second electrode may be curved.
　上記配線基板において、絶縁層上に配置された上部配線をさらに含み、上部配線と、第２電極とは、電気的に接続されてもよい。 The wiring substrate may further include an upper wiring disposed on the insulating layer, and the upper wiring and the second electrode may be electrically connected.
　上記配線基板において、第１導電部、第２導電部、高さ調整部、及び絶縁層は、第１～第Ｎ（Ｎは２以上の整数である。）配線層がこの順に積層されてなる多層配線層の一部であり、第１～第Ｎ配線層のうちの少なくとも２つの配線層を互いに電気的に接続するための層間接続部が設けられ、絶縁層は、第１～第Ｎ配線層のそれぞれの配線層の間を電気的に分離し、第１導電部および第２導電部は、第Ｎ配線層を構成し、高さ調整部は、第２導電部の積層方向下方において、第１～第Ｎ－１配線層のそれぞれを構成する導電部の少なくとも一部に設けられてもよい。 In the above wiring board, the first conductive part, the second conductive part, the height adjusting part, and the insulating layer are formed by laminating first to Nth (N is an integer of 2 or more) wiring layers in this order. An interlayer connection portion for electrically connecting at least two of the first to Nth wiring layers, which is a part of the multilayer wiring layer, is provided, and the insulating layer is formed of the first to Nth wiring layers. The first conductive portion and the second conductive portion constitute an Nth wiring layer, and the height adjustment portion is disposed below the stacking direction of the second conductive portion. It may be provided in at least a part of the conductive portion constituting each of the first to (N-1) th wiring layers.
　上記配線基板において、Ｎは３以上の整数であり、第Ｎ配線層を構成する導体パターンのうちの少なくとも一部の積層方向下方には、複数の高さ調整部が設けられていてもよい。 In the above wiring board, N is an integer of 3 or more, and a plurality of height adjusting portions may be provided below the stacking direction of at least a part of the conductor patterns constituting the Nth wiring layer.
　上記配線基板において、高さ調整部が、第１～第Ｎ配線層との間で電気的に分離されていてもよい。 In the wiring board, the height adjusting portion may be electrically separated from the first to Nth wiring layers.
　上記配線基板において、第Ｎ配線層に電気的に接続する複数の電極をさらに備えてもよい。 The wiring board may further include a plurality of electrodes electrically connected to the Nth wiring layer.
　本開示の一実施形態によると、上記配線基板と、複数の電極のいずれか一つに電気的に接続されて実装されてなる少なくとも１つの電子部品とを備える部品実装配線基板が提供される。 According to an embodiment of the present disclosure, provided is a component-mounted wiring substrate including the wiring substrate and at least one electronic component electrically connected to and mounted on any one of a plurality of electrodes.
　本開示の一実施形態によると、上記配線基板と、半導体素子と、を含む、半導体装置が提供される。 According to an embodiment of the present disclosure, there is provided a semiconductor device including the wiring substrate and a semiconductor element.
　上記半導体装置において、半導体素子は、発光素子であってもよい。 In the above semiconductor device, the semiconductor element may be a light emitting element.
　本開示の一実施形態によると、基板上に下部配線を形成し、基板および下部配線上に絶縁層を形成し、下部配線に重畳するように絶縁層にビア部を形成し、ビア部に隣接するように絶縁層にダミービア部を形成し、ビア部および絶縁層上に第１電極を形成し、ダミービア部および絶縁層上に第２電極を形成する、配線基板の製造方法が提供される。 According to an embodiment of the present disclosure, a lower wiring is formed on a substrate, an insulating layer is formed on the substrate and the lower wiring, a via portion is formed in the insulating layer to overlap the lower wiring, and adjacent to the via portion Thus, a method of manufacturing a wiring substrate is provided, in which a dummy via portion is formed in the insulating layer, a first electrode is formed on the via portion and the insulating layer, and a second electrode is formed on the dummy via portion and the insulating layer.
　上記配線基板の製造方法において、断面視において、基板の上面からビア部の底部までの高さと、基板の上面からダミービア部の底部までの高さとは異なってもよい。 In the method of manufacturing a wiring substrate, the height from the top surface of the substrate to the bottom of the via portion and the height from the top surface of the substrate to the bottom of the dummy via portion may be different in cross section.
　上記配線基板の製造方法において、ビア部およびダミービア部は、ハーフトーンマスクを用いたフォトリソグラフィ法またはレーザー照射法を用いて形成されてもよい。 In the method of manufacturing a wiring board, the via portion and the dummy via portion may be formed using a photolithography method using a halftone mask or a laser irradiation method.
　本開示の一実施形態によれば、接続端子の高さのばらつきが少ない配線基板を提供することができる。また、本開示の一実施形態によれば、電子部品を安定的に実装することができる高品質な配線基板、及び部品実装配線基板を提供することができる。 According to an embodiment of the present disclosure, it is possible to provide a wiring board with less variation in height of connection terminals. Further, according to an embodiment of the present disclosure, it is possible to provide a high quality wiring board on which electronic components can be stably mounted, and a component mounting wiring board.
本開示の一実施形態に係る発光装置を説明する断面図である。It is a sectional view explaining a light-emitting device concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する上面図である。It is a top view explaining the wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板の製造方法を説明する断面図である。FIG. 7 is a cross-sectional view illustrating the method of manufacturing the wiring board according to the embodiment of the present disclosure. 本開示の一実施形態に係る配線基板を説明する上面図である。It is a top view explaining the wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する上面図である。It is a top view explaining the wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する上面図である。It is a top view explaining the wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態における配線基板を表す概略断面図である。It is a schematic sectional drawing showing the wiring board in one embodiment of this indication. 本開示の一実施形態における配線基板を表す概略断面図である。It is a schematic sectional drawing showing the wiring board in one embodiment of this indication. 本開示の一実施形態における配線基板を表す概略断面図である。It is a schematic sectional drawing showing the wiring board in one embodiment of this indication. 本開示の一実施形態における配線基板を表す概略断面図である。It is a schematic sectional drawing showing the wiring board in one embodiment of this indication. 本開示の一実施形態における配線基板を表す概略断面図である。It is a schematic sectional drawing showing the wiring board in one embodiment of this indication. 本開示の一実施形態における配線基板を表す概略断面図である。It is a schematic sectional drawing showing the wiring board in one embodiment of this indication. 本開示の一実施形態の配線基板の製造方法を表す工程図である。It is process drawing showing the manufacturing method of the wiring board of one embodiment of this indication. 本開示の一実施形態の配線基板の製造方法を表す工程図であり、図２７の工程図に続く工程を表す工程図である。FIG. 28 is a process diagram illustrating a method of manufacturing a wiring board according to an embodiment of the present disclosure, which is a process diagram illustrating steps subsequent to the process diagram of FIG. 27. 本開示の一実施形態に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. 本開示の一実施形態に係る電気機器の斜視図である。1 is a perspective view of an electrical device according to an embodiment of the present disclosure. 本開示の一実施形態に係る電気機器の斜視図である。1 is a perspective view of an electrical device according to an embodiment of the present disclosure. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する上面図である。It is a top view explaining the wiring board concerning one embodiment of this indication. 本開示の一実施形態に係る配線基板を説明する断面図である。It is a sectional view explaining a wiring board concerning one embodiment of this indication. 従来例の配線基板を説明する断面図である。It is sectional drawing explaining the wiring board of a prior art example. 表層に位置する２つの導体パターンの積層方向における高さ位置の差となって現れている多層配線基板の構成例を表す参考図である。It is a reference drawing showing the example of composition of the multilayer wiring board which has appeared as a difference of the height position in the lamination direction of two conductor patterns located in the surface.
　以下、本開示の各実施形態に係る配線基板等について、図面を参照しながら詳細に説明する。なお、以下に示す各実施形態は本開示の実施形態の一例であって、本開示はこれらの実施形態に限定して解釈されるものではない。なお、本実施形態で参照する図面において、同一部分または同様な機能を有する部分には同一の符号または類似の符号（数字の後に－１、－２等を付しただけの符号）を付し、その繰り返しの説明は省略する場合がある。また、図面の寸法比率は説明の都合上実際の比率とは異なったり、構成の一部が図面から省略されたりする場合がある。 Hereinafter, the wiring board and the like according to each embodiment of the present disclosure will be described in detail with reference to the drawings. In addition, each embodiment shown below is an example of embodiment of this indication, Comprising: This indication is not limited and interpreted to these embodiment. In the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals or similar reference numerals (numbers simply attached with -1, -2, etc.) The repeated description may be omitted. Further, the dimensional ratio of the drawings may be different from the actual ratio for convenience of explanation, or part of the configuration may be omitted from the drawings.
　本明細書に添付した図面においては、理解を容易にするために、各部の形状、縮尺、縦横の寸法比等を、実物から変更したり、誇張したりしている場合がある。 In the drawings attached to the present specification, the shapes, scales, dimensional ratios of dimensions, etc. of the respective parts may be changed or exaggerated from the actual ones for easy understanding.
　本明細書等において「～」を用いて表される数値範囲は、「～」の前後に記載される数値のそれぞれを下限値及び上限値として含む範囲であることを意味する。本明細書等において、「フィルム」、「シート」、「板」等の用語は、呼称の相違に基づいて相互に区別されない。例えば、「板」は、「シート」、「フィルム」と一般に呼ばれ得るような部材をも含む概念である。 In the present specification and the like, a numerical range represented by using “to” means a range including the respective numerical values described before and after “to” as the lower limit value and the upper limit value. In the present specification and the like, terms such as "film", "sheet", "plate" and the like are not distinguished from each other based on difference in designation. For example, "plate" is a concept that also includes members that can be generally called "sheet" and "film".
　＜第１実施形態＞
　（１－１．発光装置の構成）
　図１に半導体装置の一つである発光装置１０００の断面図を示す。発光装置１０００は、配線基板１００、外部端子１０５、導電部１５０、発光素子３００、端子３１０、反射材３２０、封止材３３０、レンズ３４０および保護部材３５０を含む。 First Embodiment
(1-1. Configuration of light emitting device)
FIG. 1 shows a cross-sectional view of a light emitting device 1000 which is one of semiconductor devices. The light emitting device 1000 includes the wiring substrate 100, the external terminal 105, the conductive portion 150, the light emitting element 300, the terminal 310, the reflective material 320, the sealing material 330, the lens 340 and the protective member 350.
　発光素子３００は、半導体素子の一つであり、この例ではＧａＮ系の発光ダイオードが用いられる。 The light emitting element 300 is one of semiconductor elements, and in this example, a GaN-based light emitting diode is used.
　反射材３２０は、光を反射する機能を有する。反射材３２０には、金属材料が含まれる。この例では、反射材３２０にはアルミニウムが用いられる。なお、反射材３２０にはモールド成型した樹脂の表面に金属を蒸着させたものを用いてもよい。 The reflector 320 has a function of reflecting light. The reflector 320 includes a metal material. In this example, aluminum is used for the reflector 320. The reflector 320 may be formed by depositing metal on the surface of a molded resin.
　封止材３３０は、発光素子を水分などの外的成分から保護する機能を有する。封止材３３０には、エポキシ樹脂、シリコーン樹脂などの有機樹脂が用いられる。なお、封止材３３０には、有機樹脂のほか不活性ガスが用いられてもよい。 The sealing material 330 has a function of protecting the light-emitting element from external components such as moisture. For the sealing material 330, an organic resin such as an epoxy resin or a silicone resin is used. In addition to the organic resin, an inert gas may be used for the sealing material 330.
　レンズ３４０は、発光素子からの光を拡散させる、または集光させる機能を有する。レンズ３４０には、石英などの透明材料が用いられる。 The lens 340 has a function of diffusing or collecting light from the light emitting element. For the lens 340, a transparent material such as quartz is used.
　保護部材３５０は、発光素子を物理的衝撃から保護する機能を有する。保護部材３５０は、透光性を有する。保護部材３５０には、エポキシ樹脂、アクリル樹脂などの有機樹脂が用いられる。 The protective member 350 has a function of protecting the light emitting element from physical impact. The protective member 350 has translucency. For the protective member 350, an organic resin such as an epoxy resin or an acrylic resin is used.
　配線基板１００は、発光素子３００と電気的に接続されている。この例では、配線基板１００の導電部１５０（例えば、後述する導電部１５０－１）と、発光素子３００の端子３１０とがフリップチップ法により接続されている。このとき、配線基板の導電部１５０（例えば、後述する導電部１５０－１）は、２４個以上配置されている。また、配線基板１００には、外部端子１０５が設けられている。外部端子１０５は、外部の配線基板または電極と接続される。配線基板１００および導電部１５０の詳細については、以下に後述する。なお、導電部、端子、配線および電極は同様の意味として用いることができる。 The wiring substrate 100 is electrically connected to the light emitting element 300. In this example, the conductive portion 150 (for example, the conductive portion 150-1 described later) of the wiring substrate 100 and the terminal 310 of the light emitting element 300 are connected by the flip chip method. At this time, 24 or more conductive parts 150 (for example, conductive parts 150-1 described later) of the wiring substrate are arranged. In addition, the external terminals 105 are provided on the wiring substrate 100. The external terminal 105 is connected to an external wiring board or an electrode. The details of the wiring substrate 100 and the conductive portion 150 will be described later. Note that the conductive portion, the terminal, the wiring, and the electrode can be used in the same meaning.
　（１－２．配線基板の構成）
　図２は、図１の配線基板１００の上面図である。図３は、配線基板１００のうちＡ１－Ａ２間の断面図である。 (1-2. Configuration of wiring board)
FIG. 2 is a top view of the wiring substrate 100 of FIG. FIG. 3 is a cross-sectional view of the wiring substrate 100 between A1 and A2.
　配線基板１００は、基板１１０、下部配線１２０、絶縁層１３０、ビア部１４１、ダミービア部１４３、および導電部１５０（導電部１５０－１、導電部１５０－２）を有する。 The wiring substrate 100 includes a substrate 110, a lower wire 120, an insulating layer 130, a via portion 141, a dummy via portion 143, and a conductive portion 150 (conductive portions 150-1 and 150-2).
　基板１１０には、高抵抗な材料が用いられる。例えば、基板１１０には、シリコン基板が用いられる。基板１１０の板厚は、特に限定されないが、１００μｍ以上７００μｍ以下の範囲で適宜設定してもよい。例えば、基板１１０の板厚として４００μｍが用いられる。 For the substrate 110, a high resistance material is used. For example, a silicon substrate is used as the substrate 110. The thickness of the substrate 110 is not particularly limited, but may be appropriately set in the range of 100 μm to 700 μm. For example, 400 μm is used as the thickness of the substrate 110.
　また、基板１１０は、有機樹脂であってもよい。例えば、基板１１０がポリイミド樹脂などの有機樹脂の場合、基板１１０の厚さは数μｍ以上数十μｍ以下としてもよい。 The substrate 110 may be an organic resin. For example, in the case where the substrate 110 is an organic resin such as a polyimide resin, the thickness of the substrate 110 may be several μm to several tens μm.
　下部配線１２０は、基板１１０上に設けられる。下部配線１２０には、銅（Ｃｕ）が用いられる。なお、下部配線１２０には、銅（Ｃｕ）以外に、アルミニウム（Ａｌ）、チタン（Ｔｉ）、タングステン（Ｗ）、金（Ａｕ）、銀（Ａｇ）、またはニッケル（Ｎｉ）などの金属材料が用いられてもよい。 The lower wiring 120 is provided on the substrate 110. Copper (Cu) is used for the lower interconnection 120. In addition to the copper (Cu), metal materials such as aluminum (Al), titanium (Ti), tungsten (W), gold (Au), silver (Ag), or nickel (Ni) are used for the lower wiring 120. It may be used.
　絶縁層１３０は、基板１１０および下部配線１２０上に設けられる。例えば、絶縁層１３０には、ポリイミド樹脂が用いられる。また、上記ポリイミド樹脂は、感光材を含んでもよい。 The insulating layer 130 is provided on the substrate 110 and the lower wire 120. For example, a polyimide resin is used for the insulating layer 130. The polyimide resin may also contain a photosensitive material.
　なお、絶縁層１３０は、上記に限定されない。例えば、絶縁層１３０には、酸化シリコン膜、窒化シリコン膜などの無機絶縁材料が用いられてもよい。また、絶縁層１３０には、アクリル樹脂、エポキシ樹脂などの他の有機絶縁材料が用いられてもよい。 Note that the insulating layer 130 is not limited to the above. For example, as the insulating layer 130, an inorganic insulating material such as a silicon oxide film or a silicon nitride film may be used. Further, for the insulating layer 130, another organic insulating material such as an acrylic resin or an epoxy resin may be used.
　ビア部１４１は、絶縁層１３０に設けられた凹部である。ビア部１４１は、下部配線１２０上に配置される。 The via portion 141 is a recess provided in the insulating layer 130. The via portion 141 is disposed on the lower wire 120.
　ダミービア部１４３は、ビア部１４１に隣接して絶縁層１３０に設けられた凹部である。 The dummy via portion 143 is a concave portion provided in the insulating layer 130 adjacent to the via portion 141.
　導電部１５０は、絶縁層１３０上に配置される。導電部１５０のうち、絶縁層１３０およびビア部１４１上に配置されるものを導電部１５０－１という（あるいは第１導電部という場合がある）。上記において、導電部１５０－１は、絶縁層１３０の上部に突出する。また、導電部１５０のうち、絶縁層１３０およびダミービア部１４３上に配置されるものを導電部１５０－２という（あるいは第２導電部という場合がある）。上記において、導電部１５０－２は、絶縁層１３０の上部に突出する。導電部１５０－２は、導電部１５０－１に隣接して配置される。なお、導電部１５０－１および導電部１５０－２を分けて説明する必要がない場合には、導電部１５０として説明する。 The conductive portion 150 is disposed on the insulating layer 130. Among the conductive portions 150, one disposed on the insulating layer 130 and the via portion 141 is referred to as a conductive portion 150-1 (or sometimes referred to as a first conductive portion). In the above, the conductive portion 150-1 protrudes above the insulating layer 130. Further, among the conductive portions 150, one disposed on the insulating layer 130 and the dummy via portion 143 is referred to as a conductive portion 150-2 (or sometimes referred to as a second conductive portion). In the above, the conductive portion 150-2 protrudes above the insulating layer 130. The conductive portion 150-2 is disposed adjacent to the conductive portion 150-1. Note that the conductive portion 150-1 and the conductive portion 150-2 will be described as the conductive portion 150 when it is not necessary to separate them.
　導電部１５０は、シード層１４７を含んでいる。シード層１４７および導電部１５０には、銅（Ｃｕ）が用いられるが、これに限定されず、金（Ａｕ）、銀（Ａｇ）、パラジウム（Ｐｄ）、ニッケル（Ｎｉ）、錫（Ｓｎ）が用いられてもよい。 Conductive portion 150 includes a seed layer 147. Although copper (Cu) is used for the seed layer 147 and the conductive portion 150, gold (Au), silver (Ag), palladium (Pd), nickel (Ni), tin (Sn) are not limited thereto. It may be used.
　また、導電部１５０－１の上面および導電部１５０－２の上面は、平坦でなくてもよい。この例では、導電部１５０－１の上面および導電部１５０－２の上面は湾曲している。具体的には、導電部１５０－１の上面および導電部１５０－２の上面は凸形状を有している。 Further, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 may not be flat. In this example, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 are curved. Specifically, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have a convex shape.
　なお、図３において、導電部１５０－１のうちビア部１４１に設けられた領域１５０－１Ｆは、下部配線１２０と電気的に接続されている。一方で、導電部１５０－２のうちダミービア部１４３に設けられた領域１５０－２Ｆは、下部配線１２０と電気的な接続を有していない。つまり、領域１５０－１Ｆは、電気回路の一部を構成するのに対して、領域１５０－２Ｆは、電気回路の構成要素ではないということができる。 In FIG. 3, a region 150-1F provided in the via portion 141 of the conductive portion 150-1 is electrically connected to the lower wire 120. On the other hand, region 150-2 F provided in dummy via portion 143 of conductive portion 150-2 does not have electrical connection with lower interconnection 120. That is, it can be said that the region 150-1F constitutes a part of the electric circuit, whereas the region 150-2F is not a component of the electric circuit.
　次に、ビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の位置構成の詳細について、以下に説明する。 Next, details of the position configuration of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 will be described below.
　図４は、配線基板１００におけるビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の位置構成を示した断面図である。図４に示すように、基板１１０の上面１１０Ａからビア部１４１の底部１４１Ｄまでの距離を距離ＤＬ１とする。同様に、基板１１０の上面１１０Ａからダミービア部１４３の底部１４３Ｄまでの距離を距離ＤＬ２とする。このとき、距離ＤＬ１と距離ＤＬ２とは異なっていてもよい。具体的には、距離ＤＬ１よりも距離ＤＬ２の方が長いことが望ましい。 FIG. 4 is a cross-sectional view showing the positional configuration of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 in the wiring substrate 100. As shown in FIG. As shown in FIG. 4, the distance from the top surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141 is a distance DL1. Similarly, the distance from the top surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 is a distance DL2. At this time, the distances DL1 and DL2 may be different. Specifically, it is desirable that the distance DL2 be longer than the distance DL1.
　また、図４において、ビア部１４１の上部径１４１Ｗおよびダミービア部の上部径１４３Ｗは、３μｍ以上３０μｍ以下、より好ましくは５μｍ以上１０μｍ以下であることが望ましい。 Further, in FIG. 4, the upper diameter 141 W of the via portion 141 and the upper diameter 143 W of the dummy via portion are desirably 3 μm or more and 30 μm or less, more preferably 5 μm or more and 10 μm or less.
　また、図４において基板１１０に対して垂直方向に設けられた導電部１５０－１の中心線１５０－１Ｃと、導電部１５０－２の中心線１５０－２Ｃとの距離（ピッチ間距離という場合がある）１５０Ｐは、１０μｍ以上１００μｍ以下、より好ましくは２０μｍ以上５０μｍ以下であることが望ましい。 Further, in FIG. 4, the distance between the center line 150-1C of the conductive portion 150-1 provided in the vertical direction with respect to the substrate 110 and the center line 150-2C of the conductive portion 150-2 Some 150P is preferably 10 μm to 100 μm, more preferably 20 μm to 50 μm.
　（１－３．端子の高さばらつきについて）
　以下に、端子の高さのばらつきについて説明する。基板１１０の上面１１０Ａから導電部１５０－１の最上部１５０－１Ａまでの距離を距離ＵＬ１５０－１とする。同様に、基板１１０の上面１１０Ａから導電部１５０－２の最上部１５０－２Ａまでの距離を距離ＵＬ１５０－２とする。 (1-3. About the height variation of the terminal)
Below, the dispersion | variation in the height of a terminal is demonstrated. The distance from the top surface 110A of the substrate 110 to the top 150-1A of the conductive portion 150-1 is a distance UL 150-1. Similarly, the distance from the top surface 110A of the substrate 110 to the top 150-2A of the conductive portion 150-2 is taken as a distance UL150-2.
　ここで、従来例の配線基板９０の断面図を図３６に示す。図３６において、配線基板９０は、ダミービア部１４３を有していない以外は、配線基板１００と同様の構成を有する。配線基板９０は、ダミービア部１４３を有していないため、導電部１５０－２は、絶縁層１３０上にのみ設けられている。 Here, FIG. 36 shows a cross-sectional view of the wiring board 90 of the conventional example. In FIG. 36, wiring substrate 90 has the same configuration as wiring substrate 100 except that dummy via portion 143 is not provided. Since the wiring board 90 does not have the dummy via portion 143, the conductive portion 150-2 is provided only on the insulating layer 130.
　配線基板９０では、ビア部１４１に設けられた導電部１５０－１の形状とビア部１４１を有しない導電部１５０－２の形状とを同様にすることが難しい。そのため、距離ＵＬ１５０－１と距離ＵＬ１５０－２との差が１．５～３μｍ程度であり、端子の高さが安定せず、段差が生じていた。したがって、配線基板９０では、ピッチ間距離１５０Ｐが小さくなる、つまり狭ピッチになると（具体的には、ピッチ間距離１５０Ｐが１００μｍ以下、より具体的には５０μｍ以下）、配線基板９０の端子と、半導体素子の端子との間で接続不良が起こりやすい。とりわけ、上記接続不良は、導電部１５０－１の上面および導電部１５０－２の上面が凸形状を有する場合に顕著となっていた。 In the wiring substrate 90, it is difficult to make the shape of the conductive portion 150-1 provided in the via portion 141 similar to the shape of the conductive portion 150-2 not having the via portion 141. Therefore, the difference between the distance UL150-1 and the distance UL150-2 is about 1.5 to 3 μm, the height of the terminal is not stable, and a step is generated. Therefore, in the wiring substrate 90, when the distance 150P between the pitches becomes small, that is, the pitch becomes narrow (specifically, the distance 150P between the pitches is 100 μm or less, more specifically 50 μm or less). A connection failure is likely to occur between terminals of the semiconductor element. In particular, the connection failure is remarkable when the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have a convex shape.
　一方、上記図４に示す配線基板１００の場合、ビア部１４１を有しない部分にダミービア部１４３（高さ調整部ともいう）が設けられることにより、距離ＵＬ１５０－１と距離ＵＬ１５０－２との差を小さくすることができる。具体的には、配線基板１００の場合、距離ＵＬ１５０－１と距離ＵＬ１５０－２との差を１μｍ以下、より具体的には、０．５μｍ以下とすることができる。つまり、本実施形態を用いることより、接続端子の高さばらつきの少ない配線基板を提供することができる。これにより、配線基板の端子と、半導体素子の端子との接続不良が抑えられる。 On the other hand, in the case of the wiring substrate 100 shown in FIG. 4, the difference between the distance UL150-1 and the distance UL150-2 is provided by providing the dummy via portion 143 (also referred to as a height adjusting portion) in a portion not having the via portion 141. Can be made smaller. Specifically, in the case of the wiring substrate 100, the difference between the distance UL150-1 and the distance UL150-2 can be made 1 μm or less, more specifically, 0.5 μm or less. That is, by using this embodiment, it is possible to provide a wiring substrate with less variation in height of connection terminals. As a result, connection defects between the terminals of the wiring board and the terminals of the semiconductor element can be suppressed.
　（１－４．配線基板の製造方法）
　次に、図２乃至図４に示した配線基板１００の製造方法を図５乃至図１２を用いて説明する。 (1-4. Manufacturing method of wiring board)
Next, a method of manufacturing the wiring substrate 100 shown in FIGS. 2 to 4 will be described with reference to FIGS. 5 to 12.
　図５に示すように、基板１１０を用いる。例えば、基板１１０には、シリコン基板などの高抵抗基板が用いられる。 As shown in FIG. 5, a substrate 110 is used. For example, a high resistance substrate such as a silicon substrate is used as the substrate 110.
　なお、基板１１０は、上記に限定されず、石英ガラス基板、ソーダガラス基板、ホウ珪酸ガラス基板、無アルカリガラス基板、サファイア基板、炭化アルミナ（Ａｌ2Ｏ3）基板、窒化アルミニウム（ＡｌＮ）基板、ジルコニア（ＺｒＯ2）基板、アクリルまたはポリカーボネートなどを含む樹脂基板、またはこれらの基板が積層されたものが用いられてもよい。 The substrate 110 is not limited to the above, and may be a quartz glass substrate, a soda glass substrate, a borosilicate glass substrate, an alkali-free glass substrate, a sapphire substrate, an alumina carbide (Al 2 O 3 ) substrate, an aluminum nitride (AlN) substrate, A zirconia (ZrO 2 ) substrate, a resin substrate containing acrylic or polycarbonate, or the like, or a laminate of these substrates may be used.
　また、基板１１０は、金属基板上に有機絶縁層または無機絶縁層が形成されたものでもよい。また、基板１１０は、貫通電極基板でもよい。この場合、基板１１０の上面１１０Ａから反対側に電流を流すことができるため、図１に示した外部端子１０５を別途設ける上で好適である。 In addition, the substrate 110 may be a metal substrate on which an organic insulating layer or an inorganic insulating layer is formed. Also, the substrate 110 may be a through electrode substrate. In this case, a current can flow from the top surface 110A of the substrate 110 to the opposite side, which is preferable in separately providing the external terminal 105 shown in FIG.
　次に、図６に示すように、基板１１０上に下部配線１２０を形成する。下部配線１２０は、めっき法、スクリーン印刷法、スパッタリング法または化学気相成長（ＣＶＤ）法を用いて形成される。下部配線１２０は、適宜フォトリソグラフィ法およびエッチング法により所定の形状に加工される。下部配線１２０は、基板１１０上に設けられる。下部配線１２０には、銅（Ｃｕ）が用いられる。なお、下部配線１２０は、銅（Ｃｕ）以外に、アルミニウム（Ａｌ）、金（Ａｕ）、銀（Ａｇ）、ニッケル（Ｎｉ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、またはチタン（Ｔｉ）などの金属材料が用いられてもよい。 Next, as shown in FIG. 6, the lower wiring 120 is formed on the substrate 110. The lower wiring 120 is formed by plating, screen printing, sputtering or chemical vapor deposition (CVD). Lower interconnection 120 is processed into a predetermined shape by photolithography and etching as appropriate. The lower wiring 120 is provided on the substrate 110. Copper (Cu) is used for the lower interconnection 120. The lower interconnection 120 may be made of aluminum (Al), gold (Au), silver (Ag), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti), etc. in addition to copper (Cu). The following metal materials may be used.
　次に、図７に示すように、基板１１０および下部配線１２０上に絶縁層１３０を形成する。絶縁層１３０は、印刷法、塗布法、またはディッピング法を用いて形成される。絶縁層１３０には、ポリイミド、アクリル、エポキシ、ベンゾシクロブテン（ＢＣＢ）などの有機樹脂を用いてもよい。また、絶縁層１３０には、有機樹脂の他、シリカを含む有機無機ハイブリッド樹脂を用いてもよいし、プラズマＣＶＤ法により形成された酸化シリコン、窒化シリコン等の無機膜を用いてもよい。また、絶縁層１３０が有機樹脂の場合、感光材が含まれてもよい。例えば、絶縁層１３０には、塗布法により形成されたジアゾナフトキノンなどの感光材を含むポリイミド樹脂が用いられる。 Next, as shown in FIG. 7, the insulating layer 130 is formed on the substrate 110 and the lower wiring 120. The insulating layer 130 is formed using a printing method, a coating method, or a dipping method. For the insulating layer 130, an organic resin such as polyimide, acrylic, epoxy, or benzocyclobutene (BCB) may be used. In addition to the organic resin, an organic-inorganic hybrid resin containing silica may be used for the insulating layer 130, or an inorganic film such as silicon oxide or silicon nitride formed by plasma CVD may be used. When the insulating layer 130 is an organic resin, a photosensitive material may be included. For example, for the insulating layer 130, a polyimide resin containing a photosensitive material such as diazonaphthoquinone formed by a coating method is used.
　次に、図８に示すように絶縁層１３０にビア部１４１およびダミービア部１４３を形成する。ビア部１４１は、下部配線１２０に重畳するように形成される。ダミービア部１４３は、所定の間隔を有して、ビア部１４１に隣接して形成される。ビア部１４１およびダミービア部１４３は、フォトリソグラフィ法を用いて形成される。 Next, as shown in FIG. 8, the via portion 141 and the dummy via portion 143 are formed in the insulating layer 130. The via portion 141 is formed to overlap the lower wire 120. The dummy via portion 143 is formed adjacent to the via portion 141 with a predetermined interval. The via portion 141 and the dummy via portion 143 are formed using a photolithography method.
　フォトリソグラフィ法を用いる場合、ハーフトーンマスクを用いることが望ましい。具体的には、ポジ型の感光材（ジアゾナフトキノンなど）を有するポリイミド樹脂を露光するときに、ビア部１４１に相当する部分は通常と同じように露光される。一方、ダミービア部１４３に相当する部分は、ハーフトーンマスクに設けられた半透過膜によりビア部１４１に相当する部分に比べて露光量が低下されて露光される。このため、現像した後の基板１１０の上面１１０Ａからビア部１４１の底部１４１Ｄまでの距離ＤＬ１と、基板１１０の上面１１０Ａからダミービア部１４３の底部１４３Ｄまでの距離ＤＬ２とは異なってもよい。具体的には、距離ＤＬ１よりも距離ＤＬ２の方が長くなる（ビア部１４１の深さよりもダミービア部１４３の深さの方が浅いと言い換えることができる）。上記処理によって、ビア部１４１において、下部配線１２０の上面が露出する。 When using a photolithography method, it is desirable to use a halftone mask. Specifically, when a polyimide resin having a positive photosensitive material (such as diazonaphthoquinone) is exposed, the portion corresponding to the via portion 141 is exposed as usual. On the other hand, the portion corresponding to the dummy via portion 143 is exposed with the exposure amount reduced by the semi-transmissive film provided on the halftone mask as compared with the portion corresponding to the via portion 141. Therefore, the distance DL1 from the top surface 110A of the substrate 110 after development to the bottom portion 141D of the via portion 141 may be different from the distance DL2 from the top surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143. Specifically, the distance DL2 is longer than the distance DL1 (in other words, the depth of the dummy via portion 143 is shallower than the depth of the via portion 141). The upper surface of the lower wire 120 is exposed in the via portion 141 by the above process.
　次に、導電部１５０を形成する。まず、図９に示すように絶縁層１３０、ビア部１４１およびダミービア部１４３上に、シード層１４７を形成する。シード層１４７は、無電解めっき法、スパッタリング法、印刷法などにより形成される。シード層１４７には、銅（Ｃｕ）のほか、金（Ａｕ）、銀（Ａｇ）、ニッケル（Ｎｉ）、錫（Ｓｎ）、パラジウム（Ｐｄ）などが用いられる。例えば、シード層１４７には、無電解めっき法により形成された銅（Ｃｕ）膜が用いられる。 Next, the conductive portion 150 is formed. First, as shown in FIG. 9, the seed layer 147 is formed on the insulating layer 130, the via portion 141 and the dummy via portion 143. The seed layer 147 is formed by an electroless plating method, a sputtering method, a printing method, or the like. In addition to copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), palladium (Pd) or the like is used for the seed layer 147. For example, a copper (Cu) film formed by electroless plating is used for the seed layer 147.
　次に、図１０に示すように、シード層１４７上にレジスト膜１４９を形成する。レジスト膜１４９は、塗布法により形成されてもよいし、ドライフィルムレジストが用いられてもよい。レジスト膜１４９は、フォトリソグラフィ法により、所定の形状に加工される。 Next, as shown in FIG. 10, a resist film 149 is formed on the seed layer 147. The resist film 149 may be formed by a coating method, or a dry film resist may be used. The resist film 149 is processed into a predetermined shape by photolithography.
　次に、図１１に示すように、シード層１４７が露出している部分に導電部１５０を形成する。導電部１５０は、電解めっき法により形成される。このとき、導電部１５０のうち絶縁層１３０およびビア部１４１上に導電部１５０－１が形成され、絶縁層１３０およびダミービア部１４３上に導電部１５０－２が形成される。 Next, as shown in FIG. 11, the conductive portion 150 is formed in the portion where the seed layer 147 is exposed. The conductive portion 150 is formed by electrolytic plating. At this time, the conductive portion 150-1 is formed on the insulating layer 130 and the via portion 141 of the conductive portion 150, and the conductive portion 150-2 is formed on the insulating layer 130 and the dummy via portion 143.
　最後に、図１２に示すように、シード層１４７のうちレジスト膜１４９（図１１参照）および導電部１５０が形成されていない部分を除去する。上記方法は、セミアディティブ法と呼ばれる。以上の方法により、配線基板１００が製造される。 Finally, as shown in FIG. 12, the portion of the seed layer 147 where the resist film 149 (see FIG. 11) and the conductive portion 150 are not formed is removed. The above method is called semi-additive method. The wiring substrate 100 is manufactured by the above method.
　＜第２実施形態＞
　次に、配線基板１００と構造の異なる配線基板について説明する。なお、第１実施形態において示した配線基板１００と同様の構造、材料および方法については、その説明を援用する。また、各配線基板の構成は、適宜組み合わせて用いることができる。 Second Embodiment
Next, a wiring board different in structure from the wiring board 100 will be described. The description is incorporated for the same structure, material and method as the wiring substrate 100 shown in the first embodiment. Further, the configurations of the wiring boards can be used in appropriate combination.
（２－１．配線基板１００－１の構成）
　図１３に配線基板１００－１の上面図および図１４に配線基板１００－１のＡ１－Ａ２間の断面図を示す。図１３および図１４に示すように、配線基板１００－１は、基板１１０、下部配線１２０、絶縁層１３０、ビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の他に上部配線１６０を有する。 (2-1. Configuration of Wiring Board 100-1)
FIG. 13 shows a top view of the wiring substrate 100-1 and FIG. 14 shows a cross-sectional view of the wiring substrate 100-1 along the line A1-A2. As shown in FIGS. 13 and 14, the wiring substrate 100-1 includes the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2. It has upper wiring 160.
　上部配線１６０は、絶縁層１３０上に配置される。上部配線１６０と、導電部１５０－２とは、電気的に接続される。配線基板１００－１において、導電部１５０－２は端子として利用することができる。配線基板１００－１は、ダミービア部１４３を有することによって、配線基板１００と同様の効果（導電部１５０－１の高さと導電部１５０－２の高さとの差が小さくなる）を有することができる。 The upper wiring 160 is disposed on the insulating layer 130. Upper wire 160 and conductive portion 150-2 are electrically connected. In the wiring substrate 100-1, the conductive portion 150-2 can be used as a terminal. The wiring board 100-1 can have the same effect as the wiring board 100 (the difference between the height of the conductive portion 150-1 and the height of the conductive portion 150-2 becomes smaller) by having the dummy via portion 143. .
（２－２．配線基板１００－２の構成）
　図１５に配線基板１００－２の上面図および図１６に配線基板１００－２のＡ１－Ａ２間の断面図を示す。図１５および図１６に示すように、配線基板１００－２は、基板１１０、下部配線１２０－２、絶縁層１３０、ビア部１４１、ダミービア部１４３、導電部１５０－１、導電部１５０－２および上部配線１６０を有する。 (2-2. Configuration of Wiring Board 100-2)
FIG. 15 shows a top view of the wiring substrate 100-2 and FIG. 16 shows a cross-sectional view of the wiring substrate 100-2 along line A1-A2. As shown in FIGS. 15 and 16, the wiring substrate 100-2 includes the substrate 110, the lower wiring 120-2, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, the conductive portion 150-2, and It has upper wiring 160.
　下部配線１２０－２は、左側の導電部１５０－１（導電部１５０－１Ｌ）および右側の導電部１５０－１（導電部１５０－１Ｒ）と電気的に接続されるように延伸して配置されている。このとき、下部配線１２０－２の一部１２０－２Ｐは、導電部１５０－２と重畳し、かつ離隔している。この構造を有することにより配線基板１００－２は、空間を有効に利用することができる。 Lower interconnection 120-2 is extended so as to be electrically connected to conductive portion 150-1 (conductive portion 150-1L) on the left side and conductive portion 150-1 (conductive portion 150-1R) on the right side. ing. At this time, a portion 120-2P of the lower wire 120-2 overlaps with the conductive portion 150-2 and is separated. With this structure, the wiring board 100-2 can effectively utilize the space.
（２－３．配線基板１００－３の構成）
　図１７に配線基板１００－３の上面図および図１８に配線基板１００－３のＡ１－Ａ２間の断面図を示す。図１７および図１８に示すように、配線基板１００－３は、基板１１０、下部配線１２０－３、絶縁層１３０、ビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の他に上部配線１６０－３を有する。 (2-3. Configuration of Wiring Board 100-3)
FIG. 17 shows a top view of the wiring board 100-3 and FIG. 18 shows a cross-sectional view of the wiring board 100-3 along line A1-A2. As shown in FIGS. 17 and 18, the wiring substrate 100-3 includes the substrate 110, the lower wire 120-3, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2. In addition, the upper wiring 160-3 is provided.
　配線基板１００－３において、導電部１５０－１の周りに複数の導電部１５０－２が配置されている。具体的には、１個の導電部１５０－１を中心として、８個の導電部１５０－２が配置されている。 In the wiring substrate 100-3, a plurality of conductive portions 150-2 are arranged around the conductive portion 150-1. Specifically, eight conductive parts 150-2 are arranged around one conductive part 150-1.
　また、下部配線１２０－３と、上部配線１６０－３のうち上部配線１６０－３Ｒとは、絶縁層１３０を挟んで並行して配置される。 The lower wire 120-3 and the upper wire 160-3R of the upper wire 160-3 are disposed in parallel with the insulating layer 130 interposed therebetween.
（２－４．配線基板１００－４の構成）
　図１９に配線基板１００－４の断面図を示す。図１９に示すように、配線基板１００－４は、基板１１０、下部配線１２０、絶縁層１３０、ビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の他に絶縁層１６５、ビア部１７１、ダミービア部１７３および導電部１８０（導電部１８０－１および導電部１８０－２）を含む。 (2-4. Configuration of Wiring Board 100-4)
FIG. 19 shows a cross-sectional view of the wiring board 100-4. As shown in FIG. 19, the wiring substrate 100-4 includes an insulating layer 165 in addition to the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1 and the conductive portion 150-2. And a via portion 171, a dummy via portion 173, and a conductive portion 180 (conductive portions 180-1 and 180-2).
　配線基板１００－４において、ビア部１７１は、絶縁層１６５に設けられ、かつ導電部１５０－１上に配置される。ダミービア部１７３は、絶縁層１６５に設けられ、かつ導電部１５０－２と重畳して配置される。導電部１８０－１は、絶縁層１６５およびビア部１７１上に配置される。導電部１８０－２は、絶縁層１６５およびダミービア部１７３上に配置される。 In the wiring substrate 100-4, the via portion 171 is provided in the insulating layer 165 and disposed on the conductive portion 150-1. The dummy via portion 173 is provided in the insulating layer 165, and is disposed so as to overlap with the conductive portion 150-2. The conductive portion 180-1 is disposed on the insulating layer 165 and the via portion 171. The conductive portion 180-2 is disposed on the insulating layer 165 and the dummy via portion 173.
　絶縁層１６５は、絶縁層１３０と同様の材料および方法により形成される。絶縁層１６５は、導電部１５０－２が配置されていることで、基板１１０の上面１１０Ａに対して平坦に形成される。ビア部１７１は、ビア部１４１と同様の方法により形成される。ダミービア部１７３は、ダミービア部１４３と同様の方法により形成される。導電部１８０は、導電部１５０と同様の材料および方法により形成される。 The insulating layer 165 is formed by the same material and method as the insulating layer 130. The insulating layer 165 is formed flat with respect to the top surface 110A of the substrate 110 by the conductive portion 150-2. The via portion 171 is formed by the same method as the via portion 141. The dummy via portion 173 is formed by the same method as the dummy via portion 143. The conductive portion 180 is formed by the same material and method as the conductive portion 150.
　図１９に示すように、配線基板１００－５では、導電部１５０と導電部１８０が積層されている。ここで、基板１１０の上面１１０Ａから導電部１８０－１の最上部１８０－１Ａまでの距離を距離ＵＬ１８０－１とする。同様に、基板１１０の上面１１０Ａから導電部１８０－２の最上部１８０－２Ａまでの距離を距離ＵＬ１８０－２とする。このとき、距離ＵＬ１８０－１と距離ＵＬ１８０－２との差は１μｍ以下とすることができる。したがって、配線基板１００－５は、配線基板１００と同様に高密度に実装することが可能となる。 As shown in FIG. 19, in the wiring substrate 100-5, the conductive portion 150 and the conductive portion 180 are stacked. Here, the distance from the upper surface 110A of the substrate 110 to the top 180-1A of the conductive portion 180-1 is taken as a distance UL 180-1. Similarly, the distance from the top surface 110A of the substrate 110 to the top 180-2A of the conductive portion 180-2 is a distance UL180-2. At this time, the difference between the distance UL180-1 and the distance UL180-2 can be 1 μm or less. Therefore, the wiring board 100-5 can be mounted at high density as in the case of the wiring board 100.
　なお、配線基板１００－５において、導電部１８０－２と、導電部１５０－２とは、接続されてもよい。 Note that in the wiring substrate 100-5, the conductive portion 180-2 and the conductive portion 150-2 may be connected.
（２－５．配線基板１００－５の構成）
　図２０に配線基板１００－５の断面図を示す。図２０に示すように、配線基板１００－５は、基板１１０、下部配線１２０、絶縁層１３０、ビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の他に絶縁層１６５、ビア部１７１、ビア部１７５、導電部１８３（導電部１８３－１および導電部１８３－２）および導電部１８５（導電部１８５－１および導電部１８５－２）を含む。ビア部１７５は、ビア部１７１と同様の方法により形成される。 (2-5. Configuration of Wiring Board 100-5)
FIG. 20 shows a cross-sectional view of the wiring board 100-5. As shown in FIG. 20, the wiring substrate 100-5 includes an insulating layer 165 in addition to the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1 and the conductive portion 150-2. , A via portion 171, a via portion 175, a conductive portion 183 (conductive portions 183-1 and conductive portions 183-2), and a conductive portion 185 (conductive portions 185-1 and 1 conductive portions 185-2). The via portion 175 is formed by the same method as the via portion 171.
　導電部１８３のうち、導電部１８３－１は絶縁層１６５および導電部１５０－１上に配置される。導電部１８３－１は、導電部１５０－１と接続される。同様に、導電部１８３のうち、導電部１８３－２は絶縁層１６５および導電部１５０－２上に配置される。導電部１８３－２は、導電部１５０－２と接続される。 Of the conductive portion 183, the conductive portion 183-1 is disposed on the insulating layer 165 and the conductive portion 150-1. The conductive portion 183-1 is connected to the conductive portion 150-1. Similarly, in the conductive portion 183, the conductive portion 183-2 is disposed on the insulating layer 165 and the conductive portion 150-2. Conductive portion 183-2 is connected to conductive portion 150-2.
　導電部１８３は、無電解めっき法により形成される。導電部１８３は、ニッケル（Ｎｉ）、パラジウム（Ｐｄ）および金（Ａｕ）が順に積層されている。なお、導電部１８３は、ＵＢＭ（Ｕｎｄｅｒ　Ｂｕｍｐ　Ｍｅｔａｌｌｉｚａｔｉｏｎ）という場合がある。 The conductive portion 183 is formed by electroless plating. In the conductive portion 183, nickel (Ni), palladium (Pd) and gold (Au) are sequentially stacked. The conductive portion 183 may be referred to as UBM (Under Bump Metallization).
　導電部１８５のうち、導電部１８５－１は導電部１８３－１上に配置される。導電部１８５のうち、導電部１８５－２は導電部１８３－２上に配置される。 Of the conductive portion 185, the conductive portion 185-1 is disposed on the conductive portion 183-1. Of the conductive portion 185, the conductive portion 185-2 is disposed on the conductive portion 183-2.
　導電部１８５には錫（Ｓｎ）が含まれる。導電部１８５は、導電部１８３上にはんだ付けされる。導電部１８５は、はんだバンプという場合がある。 The conductive portion 185 contains tin (Sn). The conductive portion 185 is soldered on the conductive portion 183. The conductive portion 185 may be referred to as a solder bump.
　図２０に示す配線基板１００－５において、導電部１５０上に導電部１８３および導電部１８５が順に積層されている。ここで、基板１１０の上面１１０Ａから導電部１８５－１の最上部１８５－１Ａまでの距離を距離ＵＬ１８５－１とする。同様に、基板１１０の上面１１０Ａから導電部１８５－２の最上部１８５－２Ａまでの距離を距離ＵＬ１８５－２とする。このとき、距離ＵＬ１８５－１と距離ＵＬ１８５－２との差は１μｍ以下とすることができる。したがって、配線基板１００－５においても、接続不良が抑えられ、高密度に実装することが可能となる。 In the wiring substrate 100-5 shown in FIG. 20, the conductive portion 183 and the conductive portion 185 are sequentially stacked on the conductive portion 150. Here, the distance from the top surface 110A of the substrate 110 to the top portion 185-1A of the conductive portion 185-1 is a distance UL 185-1. Similarly, the distance from the top surface 110A of the substrate 110 to the top portion 185-2A of the conductive portion 185-2 is a distance UL 185-2. At this time, the difference between the distance UL185-1 and the distance UL185-2 can be 1 μm or less. Therefore, also in the wiring substrate 100-5, connection failure can be suppressed and mounting can be performed with high density.
　なお、配線基板１００－５において、導電部１８３および導電部１８５が積層されている例を示したが、導電部１８３および導電部１８５のいずれかのみが配置されてもよい。 Although the example in which the conductive portion 183 and the conductive portion 185 are stacked in the wiring substrate 100-5 is illustrated, only one of the conductive portion 183 and the conductive portion 185 may be disposed.
　＜第３実施形態＞
　第１実施形態及び第２実施形態と異なる構造を有する配線基板の一つである、多層配線基板について図面を参照して以下に説明する。図２１は、第３実施形態における多層配線基板を表す概略断面図である。第３実施形態における多層配線基板２００の概略構成について説明する。多層配線基板２００は、基板２１０の上面２１０Ｈに、第１配線層ＷＬ１及び第２配線層ＷＬ２がこの順で積層されてなる多層配線層２００Ａを備える。多層配線層２００Ａにおいて、第１配線層ＷＬ１と第２配線層ＷＬ２との間には絶縁層２２１が位置し、第２配線層ＷＬ２の上に絶縁層２２２が位置している。多層配線層２００Ａの表層となる絶縁層２２２に電極２４１（第１電極ともいう）及び電極２４２（第２電極ともいう）が設けられている。電極２４２は、電極２４１と隣接して配置される。 Third Embodiment
A multilayer wiring board which is one of the wiring boards having a structure different from the first embodiment and the second embodiment will be described below with reference to the drawings. FIG. 21 is a schematic cross-sectional view showing a multilayer wiring board in the third embodiment. The schematic configuration of the multilayer wiring board 200 in the third embodiment will be described. The multilayer wiring board 200 includes a multilayer wiring layer 200A in which the first wiring layer WL1 and the second wiring layer WL2 are stacked in this order on the upper surface 210H of the substrate 210. In the multilayer wiring layer 200A, the insulating layer 221 is located between the first wiring layer WL1 and the second wiring layer WL2, and the insulating layer 222 is located on the second wiring layer WL2. An electrode 241 (also referred to as a first electrode) and an electrode 242 (also referred to as a second electrode) are provided on the insulating layer 222 which is to be a surface layer of the multilayer wiring layer 200A. The electrode 242 is disposed adjacent to the electrode 241.
　第１配線層ＷＬ１は、導体パターン２１１で構成され、第２配線層ＷＬ２は、導体パターン２１２（第１導電部ともいう）及び導体パターン２１３で構成されている。導体パターン２１１は、後述する高さ調整用パターン２５０（高さ調整部ともいう）と共に、基板２１０の上面２１０Ｈに位置しており、導体パターン２１１と高さ調整用パターン２５０とが基板２１０の上面２１０Ｈの面内方向において互いに所定距離を隔てて位置している。導体パターン２１２及び導体パターン２１３は、絶縁層２２１上の面内方向において互いに所定距離を隔てて位置している。導体パターン２１１上に層間接続部としてのビア２３１が設けられている。また、電極２４１は導体パターン２１２の上面に連続して位置し、電極２４２は導体パターン２１３の上面に連続して位置している。以下、これらの各構成について以下に詳細に説明する。なお、導体パターン２１１，２１２，２１３は、導電部ともいう。後述する導体パターンも、同様に導電部とすることができる。さらに、導体パターン２１２は第１導電部、導体パターン２１３は第２導電部ともいう。 The first wiring layer WL1 is formed of a conductor pattern 211, and the second wiring layer WL2 is formed of a conductor pattern 212 (also referred to as a first conductive portion) and a conductor pattern 213. The conductor pattern 211 is located on the top surface 210H of the substrate 210 together with a height adjustment pattern 250 (also referred to as a height adjustment portion) described later, and the conductor pattern 211 and the height adjustment pattern 250 are the top surface of the substrate 210. In the in-plane direction of 210H, they are positioned at a predetermined distance from each other. The conductor pattern 212 and the conductor pattern 213 are located at a predetermined distance from each other in the in-plane direction on the insulating layer 221. Vias 231 as interlayer connection parts are provided on the conductor patterns 211. The electrode 241 is continuously positioned on the top surface of the conductor pattern 212, and the electrode 242 is continuously positioned on the top surface of the conductor pattern 213. Each of these configurations will be described in detail below. The conductor patterns 211, 212, and 213 are also referred to as conductive portions. The conductor pattern to be described later can be similarly made to be a conductive portion. Furthermore, the conductive pattern 212 is also referred to as a first conductive portion, and the conductive pattern 213 is also referred to as a second conductive portion.
　第３実施形態における「基板」は、電子回路基板の略称ではなく、多層配線基板２００を作製するための土台（ベース）となる板のことを意味する。すなわち、配線層と絶縁層とが順に積層されて配線基板として形成され得る限りにおいて、多層配線基板２００において基板２１０は必須の構成でなくてもよい。基板２１０の種類は特に限定されるものではなく、例えばガラスエポキシ基板、ガラス基板、シリコン基板等が挙げられる。なお、基板２１０の大きさ及び厚さ等は、所望の多層配線基板２００のサイズや、多層配線基板２００に搭載される電子部品のサイズや数等に応じて適宜設定され得る。なお、第３実施形態における多層配線基板２００に搭載され得る電子部品としては、例えばリレー、トランジスタ、集積回路（Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ（ＩＣ））等の能動素子の他、抵抗、コンデンサ、インダクタ等の受動素子等が挙げられる。また、第３実施形態において、上記に例示した電子部品のうちの何れか１以上の電子部品が実装されてなる多層配線基板を「部品実装配線基板」という。 The “substrate” in the third embodiment is not an abbreviation of an electronic circuit board, but means a board serving as a base for producing the multilayer wiring board 200. That is, as long as the wiring layer and the insulating layer can be sequentially stacked and formed as the wiring substrate, the substrate 210 in the multilayer wiring substrate 200 may not be an essential component. The type of the substrate 210 is not particularly limited, and examples thereof include a glass epoxy substrate, a glass substrate, a silicon substrate, and the like. The size, thickness and the like of the substrate 210 can be appropriately set in accordance with the desired size of the multilayer wiring substrate 200, the size and the number of electronic components mounted on the multilayer wiring substrate 200, and the like. The electronic components that can be mounted on the multilayer wiring board 200 in the third embodiment include, for example, passive elements such as resistors, capacitors, and inductors, as well as active elements such as relays, transistors, and integrated circuits (ICs). Etc. Further, in the third embodiment, a multilayer wiring board on which any one or more of the electronic components exemplified above are mounted is referred to as a "component mounting wiring board".
　導体パターン２１１及び導体パターン２１２は、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。第３実施形態においては、導体パターン２１１と導体パターン２１２とが、ビア２３１を介して互いに接続され、導体パターン２１２の上面に電極２４１が連続していることで、導体パターン２１１、導体パターン２１２、及び電極２４１が互いに電気的に接続され得る（図２１）。 The conductor pattern 211 and the conductor pattern 212 are made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. In the third embodiment, the conductor pattern 211 and the conductor pattern 212 are connected to each other through the via 231, and the electrode 241 is continuous with the upper surface of the conductor pattern 212. And the electrodes 241 can be electrically connected to each other (FIG. 21).
　導体パターン２１３も、導体パターン２１１及び導体パターン２１２と同様に、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。第３実施形態においては、導体パターン２１３の上面に電極２４２が連続していることで、導体パターン２１２と電極２４２とが互いに電気的に接続され得る（図２１）。なお、導体パターン２１１、導体パターン２１２、及び導体パターン２１３の幅や厚さ等は、多層配線基板２００のサイズ、多層配線基板２００に実装される電子部品のサイズや数等に応じて適宜設定され得る。 Similarly to the conductive pattern 211 and the conductive pattern 212, the conductive pattern 213 is also made of a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. In the third embodiment, the conductor pattern 212 and the electrode 242 can be electrically connected to each other by the fact that the electrode 242 is continuous with the upper surface of the conductor pattern 213 (FIG. 21). The width and thickness of the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213 are appropriately set according to the size of the multilayer wiring board 200, the size and number of electronic components mounted on the multilayer wiring board 200, and the like. obtain.
　絶縁層２２１及び絶縁層２２２は、例えばエポキシ樹脂、ポリイミド樹脂、アクリル樹脂等の絶縁材料で構成されてなる。絶縁層２２１は、導体パターン２１１及び高さ調整部５０を覆うように基板２１０の上面２１０Ｈに位置しており、絶縁層２２２は、導体パターン２１２及び導体パターン２１３を覆うように絶縁層２２１の上面に位置している。なお、絶縁層２２１及び絶縁層２２２の厚さは、所望の多層配線基板２００のサイズや各導体パターンのサイズや数等に応じて適宜設定され得る。 The insulating layer 221 and the insulating layer 222 are made of, for example, an insulating material such as an epoxy resin, a polyimide resin, or an acrylic resin. Insulating layer 221 is located on upper surface 210 H of substrate 210 so as to cover conductor pattern 211 and height adjustment portion 50, and insulating layer 222 is the upper surface of insulating layer 221 so as to cover conductor pattern 212 and conductor pattern 213. It is located in The thicknesses of the insulating layer 221 and the insulating layer 222 can be appropriately set in accordance with the desired size of the multilayer wiring board 200, the size and number of the conductor patterns, and the like.
　ビア２３１は、各導体パターン２１１～２１３と同様に、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。ビア２３１の寸法や深さ（高さ）は、特に限定されるものではないが、所望の多層配線基板２００のサイズ、各導体パターン２１１～２１３のサイズ及び数、並びに各絶縁層の厚さ等に応じて適宜設定され得る。 The vias 231 are made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, as with the conductor patterns 211 to 213. The dimensions and depth (height) of the via 231 are not particularly limited, but the size of the desired multilayer wiring board 200, the size and number of each of the conductor patterns 211 to 213, the thickness of each insulating layer, etc. It may be set appropriately according to
　電極２４１及び電極２４２は、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）、銀（Ａｇ）、鉛錫合金等の金属材料で構成されてなる。電極２４１及び電極２４２は、多層配線基板２００に実装される半導体チップ等の電子部品の外部端子と電気的に接続され得る。電極２４１及び電極２４２の寸法及び厚さや、絶縁層２２２の上面から突出する各電極２４１，２４２の形状や突出高さは、多層配線基板２００に電子部品が安定的に実装され得る限りにおいて、図２１に表される態様に限定されるものではない。電極２４１において、絶縁層２２２の上部に突出する部分を第１突出部といい、電極２４２において、絶縁層２２２の上部に突出する部分を第２突出部という。なお、図示は省略するが、各電極２４１，２４２と各導体パターン２１２，２１３との間に、ＵＢＭ（Ｕｎｄｅｒ　Ｂｕｍｐ　Ｍｅｔａｌｌｉｚａｔｉｏｎ）が設けられ得る。 The electrode 241 and the electrode 242 are made of, for example, a metal material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), and a lead-tin alloy. The electrodes 241 and 242 can be electrically connected to external terminals of an electronic component such as a semiconductor chip mounted on the multilayer wiring substrate 200. The dimensions and thicknesses of the electrodes 241 and 242, and the shapes and heights of the electrodes 241 and 242 protruding from the upper surface of the insulating layer 222 are illustrated as long as electronic components can be stably mounted on the multilayer wiring substrate 200. It is not limited to the aspect represented by 21. A portion of the electrode 241 protruding above the insulating layer 222 is referred to as a first protrusion, and a portion of the electrode 242 protruding above the insulating layer 222 is referred to as a second protrusion. Although not shown, UBM (Under Bump Metallization) may be provided between the electrodes 241 and 242 and the conductor patterns 212 and 213.
　高さ調整用パターン２５０は、基板２１０の上面２１０Ｈの面内方向において、絶縁層２２１内に設けられ、導体パターン２１１から所定距離を隔てて位置している。「高さ調整用パターン（高さ調整部ともいう）」とは、多層配線基板２００における電子部品が実装される電極の直下に位置する導体パターン（第３実施形態においては、導体パターン２１２及び導体パターン２１３）の積層方向における高さ位置を調整するパターンを意味する。また、ここでの「調整」には、電子部品が多層配線基板２００に安定的に実装され得る限りにおいて、電子部品が実装される電極（第３実施形態においては、電極２４１及び電極２４２）の高さ位置が略一致するように、電極直下に位置する導体パターンの高さを調整する意味が含まれる。第３実施形態においては、高さ調整用パターン２５０は、導体パターン２１３（電極２４２）の形成位置に対応するように、当該導体パターン２１３の積層方向直下に位置している。また、高さ調整用パターン２５０は、導体パターン２１１の厚さと略同一の厚さを有する。第３実施形態においては、高さ調整用パターン２５０が、導体パターン２１３の積層方向直下で、積層方向における導体パターン２１１（第１配線層ＷＬ１）と同じ高さ（階層）に位置していることにより、上面が略平坦となっている絶縁層２２１上に設けられる導体パターン２１２及び導体パターン２１３の積層方向における高さ位置が略一致することになる。高さ調整用パターン２５０を構成する材料としては、例えば、感光性樹脂材料等の非導電材料であってもよいし、銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料であってもよい。第３実施形態における高さ調整用パターン２５０は、導電材料により構成される場合において、他の導体パターンとの短絡を防止する観点から、導体パターン２１１、導体パターン２１２、及び導体パターン２１３との間で電気的に分離されているのが好ましい。なお、本明細書において断りのない限り、高さ調整用パターン２５０の材質は特に限定されるものではない。 The height adjustment pattern 250 is provided in the insulating layer 221 in the in-plane direction of the upper surface 210H of the substrate 210, and is located at a predetermined distance from the conductor pattern 211. The “height adjustment pattern (also referred to as height adjustment portion)” is a conductor pattern (in the third embodiment, the conductor pattern 212 and the conductor in the third embodiment of the multilayer wiring board 200). This means a pattern for adjusting the height position in the stacking direction of the pattern 213). Moreover, in the “adjustment” in this case, as long as the electronic component can be stably mounted on the multilayer wiring substrate 200, the “adjustment” of the electrodes (the electrode 241 and the electrode 242 in the third embodiment) on which the electronic component is mounted The meaning of adjusting the height of the conductor pattern located directly below the electrode is included so that the height positions substantially coincide. In the third embodiment, the height adjustment pattern 250 is located immediately below the lamination direction of the conductor pattern 213 so as to correspond to the formation position of the conductor pattern 213 (electrode 242). Also, the height adjustment pattern 250 has a thickness substantially the same as the thickness of the conductor pattern 211. In the third embodiment, the height adjustment pattern 250 is located directly below the conductor pattern 213 in the stacking direction and at the same height (hierarchical level) as the conductor pattern 211 (first wiring layer WL1) in the stacking direction. As a result, the height positions in the stacking direction of the conductor pattern 212 and the conductor pattern 213 provided on the insulating layer 221 having the substantially flat upper surface substantially coincide with each other. The material for forming the height adjustment pattern 250 may be, for example, a nonconductive material such as a photosensitive resin material, or a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. It may be. When the height adjustment pattern 250 in the third embodiment is made of a conductive material, it is between the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213 from the viewpoint of preventing a short circuit with another conductor pattern. Preferably, they are electrically isolated. The material of the height adjustment pattern 250 is not particularly limited unless otherwise specified in the present specification.
　図３７は、高さ調整用パターン２５０が設けられていないことにより、表層である絶縁層２２２’において、積層方向における高さ位置の差が現れている多層配線基板２００’を表す参考図である。なお、図３７においては理解を容易にするために「差Ｄ」が誇張されるように描かれているが、実際に生じる差として描かれたものではない。図３７を参照して、高さ調整用パターン２５０が設けられていない多層配線基板との比較に基づき、第３実施形態における高さ調整用パターン２５０の作用効果について詳細に説明する。 FIG. 37 is a reference diagram showing a multilayer wiring board 200 'in which a difference in height position in the stacking direction appears in the insulating layer 222' which is the surface layer by not providing the height adjustment pattern 250. . Although FIG. 37 is drawn such that “difference D” is exaggerated for ease of understanding, it is not drawn as the actually occurring difference. The effects and advantages of the height adjustment pattern 250 in the third embodiment will be described in detail based on comparison with a multilayer wiring board in which the height adjustment pattern 250 is not provided, with reference to FIG.
　図３７に示される多層配線基板２００’において、基板２１０の上面２１０Ｈにおける、電極２４１の積層方向直下に相当する部分に導体パターン２１１が設けられているが、電極２４２の積層方向直下に相当する部分には導体パターン２１１が設けられていない。そのため、多層配線基板２００’の形成過程において、導体パターン２１１を覆うように絶縁層２２１’を設けた場合、電極２４１の積層方向直下の導体パターン２１１を覆っている絶縁層２２１’部分の高さ位置が、電極２４２の積層方向直下の絶縁層２２１’部分の高さ位置に比べて導体パターン２１１の厚さだけ高くなることになる。 In the multilayer wiring board 200 ′ shown in FIG. 37, the conductor pattern 211 is provided on a portion of the upper surface 210H of the substrate 210 corresponding to the portion directly below the stacking direction of the electrodes 241. The conductor pattern 211 is not provided on the Therefore, in the process of forming the multilayer wiring board 200 ′, when the insulating layer 221 ′ is provided to cover the conductor pattern 211, the height of the insulating layer 221 ′ covering the conductor pattern 211 immediately below the stacking direction of the electrodes 241. The position is higher by the thickness of the conductor pattern 211 than the height position of the portion of the insulating layer 221 ′ immediately below the stacking direction of the electrodes 242.
　この状態の絶縁層２２１’上に、ビア２３１を介して導体パターン２１１に接続される導体パターン２１２を設け、電極２４２の積層方向直下の絶縁層２２１’上に導体パターン２１３を設けた場合、導体パターン２１２と導体パターン２１３との間に積層方向における高さ位置の差Ｄが現れてしまう（図３７）。よって、導体パターン２１２の上面に設けられる電極２４１と、導体パターン２１３の上面に設けられる電極２４２との間にも高さ位置の差が現れてしまう。そうなると、高さ位置の差が現れた両電極を介して、電子部品を安定的に実装することが困難になってしまう。 When the conductor pattern 212 connected to the conductor pattern 211 through the via 231 is provided on the insulating layer 221 ′ in this state, and the conductor pattern 213 is provided on the insulating layer 221 ′ directly below the stacking direction of the electrodes 242, the conductor A difference D in height position in the stacking direction appears between the pattern 212 and the conductor pattern 213 (FIG. 37). Therefore, the difference in height position also appears between the electrode 241 provided on the upper surface of the conductive pattern 212 and the electrode 242 provided on the upper surface of the conductive pattern 213. In such a case, it becomes difficult to stably mount the electronic component through both electrodes in which the difference in height position appears.
　一方、第３実施形態の多層配線基板２００によれば、上述の通り、電極２４２の積層方向直下において導体パターン２１１と同じ高さ位置に高さ調整用パターン２５０が設けられていることで、これらの上層に設けられる絶縁層２２１の上面を略平坦にすることができ、絶縁層２２１上に形成される２つの導体パターン２１２，２１３の高さ位置を略一致させることができる（図２１）。このため、電子部品が実装され得る電極２４１及び電極２４２の高さ位置（具体的には、基板２１０の上面から電極２４１の上面までの高さと、基板２１０の上面から電極２４２の上面までの高さ）も略一致することになり、電子部品が安定的に実装され得る高品質な多層配線基板２００を実現することができる。なお、導体パターン２１２，２１３間の高さ位置の差が、例えば０μｍ～３μｍの範囲内、好ましくは１．５μｍ以下となるように、高さ調整用パターン２５０が設けられていることが好ましい。上記の範囲内に当該高さ位置の差が調整されることにより、多層配線基板２００の表層に対して略平行に電子部品が実装され得る。当該高さ位置の差が３μｍを超えると、電子部品を多層配線基板２００に実装する際に、電子部品と多層配線基板２００との接続不良が生じやすくなるおそれがある。 On the other hand, according to the multilayer wiring board 200 of the third embodiment, as described above, the height adjustment pattern 250 is provided at the same height position as the conductor pattern 211 immediately below the stacking direction of the electrodes 242. The upper surface of the insulating layer 221 provided in the upper layer of the upper layer can be made substantially flat, and the height positions of the two conductor patterns 212 and 213 formed on the insulating layer 221 can be made to substantially coincide (FIG. 21). Therefore, height positions of the electrode 241 and the electrode 242 (specifically, the height from the upper surface of the substrate 210 to the upper surface of the electrode 241 and the height from the upper surface of the substrate 210 to the upper surface of the electrode 242) Can substantially match, and a high quality multilayer wiring board 200 on which electronic components can be stably mounted can be realized. The height adjustment pattern 250 is preferably provided such that the difference in height between the conductor patterns 212 and 213 is, for example, in the range of 0 μm to 3 μm, preferably 1.5 μm or less. By adjusting the difference between the height positions within the above range, the electronic component can be mounted substantially parallel to the surface layer of the multilayer wiring board 200. When the difference in height position exceeds 3 μm, a connection failure between the electronic component and the multilayer wiring substrate 200 may easily occur when the electronic component is mounted on the multilayer wiring substrate 200.
　＜第４実施形態＞
　図２２は、第４実施形態における多層配線基板を表す概略断面図である。なお、第３実施形態と略同一の構成については同一の符号を付し、その詳細な説明を省略する。第４実施形態における多層配線基板２００は、第１～第３配線層ＷＬ１～ＷＬ３の３層が積層されてなる多層配線層２００Ａを備え、第３配線層ＷＬ３を構成する導体パターン２１３（電極２４２）の積層方向直下に高さ調整用パターン２５１が設けられ、高さ調整用パターン２５１の積層方向直下に高さ調整用パターン２５０が設けられている点が第３実施形態と異なっている。すなわち、第４実施形態における多層配線基板２００においては、第１配線層ＷＬ１と第３配線層ＷＬ３との間に第２配線層ＷＬ２が設けられており、第２配線層ＷＬ２は、導体パターン２１４で構成されている。第２配線層ＷＬ２と第３配線層ＷＬ３との間には、絶縁層２２３が位置している。 Fourth Embodiment
FIG. 22 is a schematic cross-sectional view showing a multilayer wiring board in the fourth embodiment. The same reference numerals as in the third embodiment denote the same parts as in the third embodiment, and a detailed description thereof will be omitted. A multilayer wiring board 200 in the fourth embodiment includes a multilayer wiring layer 200A in which three layers of first to third wiring layers WL1 to WL3 are stacked, and a conductor pattern 213 (electrode 242 that constitutes a third wiring layer WL3). The third embodiment is different from the third embodiment in that the height adjustment pattern 251 is provided immediately below the stacking direction and the height adjustment pattern 250 is provided immediately below the height adjustment pattern 251. That is, in the multilayer wiring board 200 in the fourth embodiment, the second wiring layer WL2 is provided between the first wiring layer WL1 and the third wiring layer WL3, and the second wiring layer WL2 has the conductor pattern 214. It consists of An insulating layer 223 is located between the second wiring layer WL2 and the third wiring layer WL3.
　導体パターン２１４は、高さ調整用パターン２５１と共に絶縁層２２１上に位置し、導体パターン２１４及び高さ調整用パターン２５１は、絶縁層２２１上の面内方向において互いに所定距離を隔てて位置している。導体パターン２１４上には層間接続部としてのビア２３２が設けられている。高さ調整用パターン２５１は、導体パターン２１４の厚さと略同一の厚さを有し、高さ調整用パターン２５０と略同一の構成を有する。 The conductor pattern 214 is positioned on the insulating layer 221 together with the height adjustment pattern 251, and the conductor pattern 214 and the height adjustment pattern 251 are spaced apart from each other by a predetermined distance in the in-plane direction on the insulation layer 221. There is. Vias 232 as interlayer connection parts are provided on the conductor patterns 214. The height adjustment pattern 251 has a thickness substantially the same as the thickness of the conductor pattern 214, and has a configuration substantially the same as the height adjustment pattern 250.
　導体パターン２１４は、導体パターン２１１、導体パターン２１２及び導体パターン２１３と同様に、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。第４実施形態においては、導体パターン２１１と導体パターン２１４とがビア２３１を介して接続され、導体パターン２１４と導体パターン２１２とがビア２３２を介して接続され、導体パターン２１２上に電極２４１が連続していることで、導体パターン２１１、導体パターン２１４、導体パターン２１２、及び電極２４１が互いに電気的に接続され得る（図２２）。 The conductor pattern 214 is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, similarly to the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213. In the fourth embodiment, the conductor pattern 211 and the conductor pattern 214 are connected via the via 231, the conductor pattern 214 and the conductor pattern 212 are connected via the via 232, and the electrode 241 is continuous on the conductor pattern 212. As a result, the conductor pattern 211, the conductor pattern 214, the conductor pattern 212, and the electrode 241 can be electrically connected to each other (FIG. 22).
　絶縁層２２３は、絶縁層２２１及び絶縁層２２２と同様に、例えばエポキシ樹脂、ポリイミド樹脂、アクリル樹脂等の絶縁材料で構成され得る。なお、絶縁層２２３の厚さは、積層方向における隣接する配線層（第１配線層ＷＬ１と第２配線層ＷＬ２、第２配線層ＷＬ２と第３配線層ＷＬ３）間で短絡しない程度の範囲で適宜設定され得る。 Similarly to the insulating layer 221 and the insulating layer 222, the insulating layer 223 can be made of an insulating material such as an epoxy resin, a polyimide resin, or an acrylic resin. Note that the thickness of the insulating layer 223 is in a range that does not cause a short circuit between adjacent wiring layers (the first wiring layer WL1 and the second wiring layer WL2 and the second wiring layer WL2 and the third wiring layer WL3) in the stacking direction. It may be set appropriately.
　ビア２３２は、ビア２３１と同様に、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。ビア２３２のサイズ（例えば幅や深さ）は、特に限定されるものではないが、所望の多層配線基板２００のサイズ、各導体パターンのサイズやピッチ、並びに各絶縁層の厚さ等に応じて適宜設定され得る。 Similarly to the via 231, the via 232 is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. The size (for example, width and depth) of the via 232 is not particularly limited, but it depends on the size of the desired multilayer wiring board 200, the size and pitch of each conductor pattern, the thickness of each insulating layer, etc. It may be set appropriately.
　高さ調整用パターン２５１は、絶縁層２２１上の面内方向において、導体パターン２１４から所定距離を隔てて位置している。第４実施形態においては、高さ調整用パターン２５１の上方に導体パターン２１３（電極２４２）が位置し、高さ調整用パターン２５１の下方に高さ調整用パターン２５０が位置している。また、高さ調整用パターン２５１は、導体パターン２１４の厚さと略同一の厚さを有する。第４実施形態においては、導体パターン２１３（電極２４２）の積層方向直下において、高さ調整用パターン２５０を導体パターン２１１（第１配線層ＷＬ１）と同じ高さ（階層）に位置させるとともに、高さ調整用パターン２５１を導体パターン２１４（第２配線層ＷＬ２）と同じ高さに位置させることにより、これらの上層に設けられる絶縁層２２３の上面が略平坦になるため、絶縁層２２３上に設けられる導体パターン２１２及び導体パターン２１３（第３配線層ＷＬ３）の積層方向における高さ位置を略一致させることができる。 The height adjustment pattern 251 is located at a predetermined distance from the conductor pattern 214 in the in-plane direction on the insulating layer 221. In the fourth embodiment, the conductor pattern 213 (electrode 242) is located above the height adjustment pattern 251, and the height adjustment pattern 250 is located below the height adjustment pattern 251. The height adjustment pattern 251 has a thickness substantially the same as the thickness of the conductor pattern 214. In the fourth embodiment, the height adjustment pattern 250 is positioned at the same height (level) as the conductor pattern 211 (first wiring layer WL1) immediately below the conductor pattern 213 (electrode 242) in the stacking direction, By positioning the height adjustment pattern 251 at the same height as the conductor pattern 214 (the second wiring layer WL2), the upper surface of the insulating layer 223 provided on the upper layer becomes substantially flat. The height positions in the stacking direction of the conductive pattern 212 and the conductive pattern 213 (third wiring layer WL3) can be made approximately equal.
　第４実施形態においては、３層の配線層が積層されてなる多層配線層２００Ａを備える多層配線基板２００を説明したが、本開示はこれに限定されるものではなく、４層以上の配線層が積層されてなる多層配線層を備える多層配線基板であってもよい。 In the fourth embodiment, the multilayer wiring board 200 including the multilayer wiring layer 200A in which three wiring layers are stacked is described, but the present disclosure is not limited to this, and four or more wiring layers are provided. It may be a multilayer wiring board provided with a multilayer wiring layer in which
　＜第５実施形態＞
　図２３は、第５実施形態における多層配線基板を表す概略断面図である。なお、第３実施形態と略同一の構成については同一の符号を付し、その詳細な説明を省略する。第５実施形態における多層配線基板２００は、高さ調整用パターン２５０がビア２３３を介して導体パターン２１３に電気的に接続されている点が、第３実施形態における多層配線基板２００と異なっている。すなわち、第５実施形態においては、高さ調整用パターン２５０は、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。ビア２３３についても、ビア２３１と同様に、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなることは言うまでもない。 Fifth Embodiment
FIG. 23 is a schematic cross-sectional view showing a multilayer wiring board in the fifth embodiment. The same reference numerals as in the third embodiment denote the same parts as in the third embodiment, and a detailed description thereof will be omitted. The multilayer wiring board 200 in the fifth embodiment is different from the multilayer wiring board 200 in the third embodiment in that the height adjustment pattern 250 is electrically connected to the conductor pattern 213 through the via 233. . That is, in the fifth embodiment, the height adjustment pattern 250 is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. It goes without saying that the via 233 is also made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, similarly to the via 231.
　上記構成によれば、第３実施形態と同様に絶縁層２２１の上面が略平坦になるため、絶縁層２２１上に設けられる導体パターン２１２（電極２４１）及び導体パターン２１３（電極２４２）の積層方向における高さ位置を略一致させることができるとともに、高さ調整用パターン２５０を導体パターン２１３（電極２４２）と導通する導体パターンの一部に利用することができる。 According to the above configuration, as in the third embodiment, the upper surface of the insulating layer 221 is substantially flat, so the stacking direction of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) provided on the insulating layer 221 The height positions of the patterns can be made to substantially coincide with each other, and the height adjustment pattern 250 can be used as part of a conductor pattern electrically connected to the conductor pattern 213 (electrode 242).
　＜第６実施形態＞
　図２４は、第６実施形態における多層配線基板を表す概略断面図である。なお、第３実施形態と略同一の構成については同一の符号を付し、その詳細な説明を省略する。第４実施形態においては、導体パターン２１１が、導体パターン２１２（電極２４１）の積層方向直下のみならず、導体パターン２１３（電極２４２）の積層方向直下にも位置しており、基板２１０の上面２１０Ｈの図示上における左右方向に横長な幅で構成されている点が第３実施形態の多層配線基板２００等と異なる。すなわち、第６実施形態における多層配線基板２００は、導体パターン２１１が高さ調整用パターンを兼ねている。第６実施形態においては、第１配線層ＷＬ１の導体パターン２１１を通常の配線ルールに従って配置しようとすると、電極２４１の積層方向直下には導体パターン２１１が配置されるが、電極２４２の積層方向直下には導体パターン２１１が配置されないことがある。このような場合に、第３実施形態においては高さ調整用パターン２５０が設けられることで、導体パターン２１２，２１３（電極２４１，２４２）の高さ位置を略一致させている。第６実施形態においては、第３実施形態の高さ調整用パターン２５０に代えて、通常の配線ルールに従えば配置されない導体パターン２１１を電極２４２の積層方向下方にも引き回すことで、第３実施形態と同様に絶縁層２２１の上面が略平坦になるため、絶縁層２２１上に設けられる導体パターン２１２（電極２４１）及び導体パターン２１３（電極２４２）の積層方向における高さ位置を略一致させることができる。 Sixth Embodiment
FIG. 24 is a schematic cross-sectional view showing a multilayer wiring board in the sixth embodiment. The same reference numerals as in the third embodiment denote the same parts as in the third embodiment, and a detailed description thereof will be omitted. In the fourth embodiment, the conductor pattern 211 is located not only directly below the lamination direction of the conductor pattern 212 (electrode 241) but also immediately below the lamination direction of the conductor pattern 213 (electrode 242). Is different from the multilayer wiring board 200 and the like of the third embodiment in that it is configured to have a laterally long width in the left-right direction on the illustration. That is, in the multilayer wiring board 200 in the sixth embodiment, the conductor pattern 211 also serves as the height adjustment pattern. In the sixth embodiment, when the conductor pattern 211 of the first wiring layer WL1 is arranged according to the normal wiring rule, the conductor pattern 211 is arranged immediately below the lamination direction of the electrode 241. In some cases, the conductor pattern 211 may not be disposed. In such a case, in the third embodiment, the height adjustment pattern 250 is provided, so that the height positions of the conductor patterns 212 and 213 (electrodes 241 and 242) substantially coincide with each other. In the sixth embodiment, in place of the height adjustment pattern 250 of the third embodiment, the conductor pattern 211 not disposed according to the normal wiring rule is also drawn to the lower side in the stacking direction of the electrodes 242 in the third embodiment. Since the upper surface of the insulating layer 221 is substantially flat as in the embodiment, the height positions in the stacking direction of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) provided on the insulating layer 221 should be approximately the same. Can.
　＜第７実施形態＞
　図２５は、第７実施形態における多層配線基板２００を表す概略断面図である。なお、上述した各実施形態における多層配線基板２００と同様の構成については同一の符号を付し、その詳細な説明を省略する。第７実施形態では、基板２１０の上面２１０Ｈにおいて、電極２４１の積層方向下方の領域には導体パターン２１１が設けられ、電極２４２の積層方向下方の領域には高さ調整用パターン２５０が設けられているが、電極２４１と電極２４２との間に挟まれる部分の積層方向下方の領域には、導体パターン２１１も高さ調整用パターン２５０も設けられていない（図２５参照）。このため、導体パターン２１１及び高さ調整用パターン２５０を被覆する絶縁層２２１を設けた場合、電極２４１と電極２４２との間に挟まれる部分の積層方向下方の領域において基板２１０の上面２１０Ｈ部分を覆う絶縁層２２１部分の高さ位置が、導体パターン２１１及び高さ調整用パターン２５０のそれぞれを覆う絶縁層２２１部分より低くなっている。その低くなっている絶縁層２２１部分に導体パターン２１７が設けられ、導体パターン２１７を覆う絶縁層２２３部分の高さ位置が、導体パターン２１４及び導体パターン２１５が設けられている部分をそれぞれ覆う絶縁層２２３の高さ位置より低くなっている。すなわち、第２配線層ＷＬ２において、導体パターン２１４，２１５の高さ位置と導体パターン２１７の高さ位置とがずれている。そして、低くなっている絶縁層２２３部分にビア２３２Ｃを介して導体パターン２１８が設けられている。このため、導体パターン２１８を覆っている絶縁層２２２部分の高さ位置が、導体パターン２１２及び導体パターン２１３をそれぞれ覆っている絶縁層２２２部分の高さ位置より低くなり、絶縁層２２２の上面に凹部２２２Ｃとなって現れている。 Seventh Embodiment
FIG. 25 is a schematic cross-sectional view showing a multilayer wiring board 200 in the seventh embodiment. The same components as those of the multilayer wiring board 200 in each of the above-described embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted. In the seventh embodiment, on the upper surface 210H of the substrate 210, the conductor pattern 211 is provided in the region below the electrode 241 in the stacking direction, and in the region below the electrode 242 in the stacking direction, the height adjustment pattern 250 is provided. However, neither the conductor pattern 211 nor the height adjustment pattern 250 is provided in the region below the stacking direction of the portion sandwiched between the electrode 241 and the electrode 242 (see FIG. 25). Therefore, when the insulating layer 221 covering the conductor pattern 211 and the height adjustment pattern 250 is provided, the upper surface 210H of the substrate 210 is located in the region below the stacking direction of the portion sandwiched between the electrode 241 and the electrode 242. The height position of the covering insulating layer 221 portion is lower than that of the insulating layer 221 covering each of the conductor pattern 211 and the height adjustment pattern 250. The conductor pattern 217 is provided on the lower part of the insulating layer 221, and the height position of the insulating layer 223 covering the conductor pattern 217 covers the part on which the conductor pattern 214 and the conductor pattern 215 are provided. It is lower than the height position of 223. That is, in the second wiring layer WL2, the height positions of the conductor patterns 214 and 215 and the height position of the conductor pattern 217 are shifted. Then, the conductor pattern 218 is provided in the lower portion of the insulating layer 223 via the via 232C. Therefore, the height position of the portion of the insulating layer 222 covering the conductor pattern 218 is lower than the height position of the portion of the insulating layer 222 covering the conductor pattern 212 and the conductor pattern 213 respectively, and the top surface of the insulating layer 222 is formed. It appears as a recess 222C.
　第７実施形態における多層配線基板２００においては、多層配線層２００Ａの表層の面内方向中央に凹部２２２Ｃが現れているが、電子部品が実装される電極２４１及び電極２４２の高さ位置が略一致している。このため、電極２４１及び電極２４２を介して多層配線基板２００へ電子部品２７０が安定的に実装され得る。すなわち、第７実施形態における多層配線基板２００のように、凹部２２２Ｃのような電子部品２７０を安定的に実装させ得る上で影響のない限りにおいて、最上層に位置する配線層（図２５に示す態様においては第３配線層ＷＬ３）を構成する各導体パターンのうち電極に接続されない部分（図２５に示される導体パターン２１８）の高さ位置が、電極に接続される部分（図２５に示される導体パターン２１２，２１３）の高さ位置よりも低くてもよく、電子部品２７０が実装され得る電極同士の高さ位置が略一致するものであればよい。 In the multilayer wiring board 200 in the seventh embodiment, the recess 222C appears at the center in the in-plane direction of the surface layer of the multilayer wiring layer 200A, but the height positions of the electrodes 241 and 242 on which the electronic components are mounted are approximately one. I do. Therefore, the electronic component 270 can be stably mounted on the multilayer wiring substrate 200 via the electrode 241 and the electrode 242. That is, as in the multilayer wiring board 200 in the seventh embodiment, the wiring layer positioned in the uppermost layer (shown in FIG. 25) as long as there is no influence in stably mounting the electronic component 270 such as the recess 222C. In the embodiment, the height position of the portion (the conductor pattern 218 shown in FIG. 25) not connected to the electrode among the conductor patterns constituting the third wiring layer WL3) is shown in the portion (FIG. 25) connected to the electrode. It may be lower than the height position of the conductor patterns 212 and 213), as long as the height positions of the electrodes on which the electronic component 270 can be mounted substantially coincide with each other.
　＜第８実施形態＞
　図２６は、第８実施形態における多層配線基板２００を表す概略断面図である。なお、上述した各実施形態と同様の構成については同一の符号を付し、その詳細な説明を省略する。第８実施形態における多層配線基板２００は、基板２１０の厚さ方向に貫通するスルーホールビア２１０ＴＨが設けられ、基板２１０の上面２１０Ｈに多層配線層２００Ａが設けられ、基板２１０の下面２１０Ｌに多層配線層２００Ｂが設けられた構造を有する。スルーホールビア２１０ＴＨは、例えば銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等の導電材料で構成されてなる。スルーホールビア２１０ＴＨは、多層配線層２００Ａの導体パターン２１１と多層配線層２００Ｂの導体パターン２６１とを電気的に接続する導電体として機能する。なお、多層配線層２００Ａとしては第３実施形態における多層配線基板２００における多層配線層と同様の構成を採用している。第８実施形態における多層配線層２００Ｂとして、基板２１０を境界として多層配線層２００Ａを反転させた積層構造を採用しているが、説明の簡略化のために便宜的に採用したものであり、当該構造に限定されるものではなく、種々の積層構造が適宜設定され得る。 Eighth Embodiment
FIG. 26 is a schematic cross-sectional view showing a multilayer wiring board 200 in the eighth embodiment. In addition, about the structure similar to each embodiment mentioned above, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. The multilayer wiring substrate 200 in the eighth embodiment is provided with the through hole vias 210TH penetrating in the thickness direction of the substrate 210, the multilayer wiring layer 200A is provided on the upper surface 210H of the substrate 210, and the multilayer wiring is provided on the lower surface 210L of the substrate 210. It has a structure in which the layer 200B is provided. The through hole via 210TH is made of, for example, a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like. The through hole via 210TH functions as a conductor for electrically connecting the conductor pattern 211 of the multilayer wiring layer 200A and the conductor pattern 261 of the multilayer wiring layer 200B. As the multilayer wiring layer 200A, the same configuration as that of the multilayer wiring layer in the multilayer wiring board 200 in the third embodiment is employed. A multilayer structure in which the multilayer wiring layer 200A is inverted with the substrate 210 as a boundary is adopted as the multilayer wiring layer 200B in the eighth embodiment, but this is adopted for the sake of simplicity of the description, The present invention is not limited to the structure, and various laminated structures may be appropriately set.
　多層配線層２００Ｂは、導体パターン２６１により構成される第１配線層ＷＬ２００Ｂ及び導体パターン２６２，２６３により構成される第２配線層ＷＬ２Ｂが基板２１０の下面２１０Ｌ側から順に積層されてなり、第１配線層ＷＬ２００Ｂと第２配線層ＷＬ２Ｂとの間に絶縁層２７１が位置し、第２配線層ＷＬ２Ｂを覆うように絶縁層２７２が位置している。多層配線層２００Ｂの表層に電極２８１及び電極２８２が設けられている。第１配線層ＷＬ２００Ｂは、導体パターン２６１で構成されており、導体パターン２６１は、高さ調整用パターン２５２と共に、基板２１０の下面２１０Ｌ上に位置している。導体パターン２６１と高さ調整用パターン２５２とは、基板２１０の下面２１０Ｌ上の面内方向において所定距離を隔てて位置している。第２配線層ＷＬ２Ｂは、導体パターン２６２及び導体パターン２６３で構成され、導体パターン２６１と導体パターン２６２との間にそれらを電気的に接続する層間接続部としてのビア３４が設けられている。導体パターン２６２の上面に電極２８１が位置しており、導体パターン２６３の上面に連続して電極２８２が位置している。高さ調整用パターン２５２は、導体パターン２６１の厚さと略同一の厚さを有し、高さ調整用パターン２５０と略同一の構成を有する。第８実施形態においても、高さ調整用パターン２５２が、導体パターン２６１（第１配線層ＷＬ２００Ｂ）と略同一の高さ（階層）に位置し、かつ、導体パターン２６３（電極２８２）の積層方向直下に位置していることで、絶縁層２７１の下面が略平坦になるため、絶縁層２７１上に設けられる導体パターン２６２（電極２８１）及び導体パターン２６３（電極２８２）の高さ位置が略一致することになる。 In the multilayer wiring layer 200B, the first wiring layer WL200B formed of the conductor pattern 261 and the second wiring layer WL2B formed of the conductor patterns 262 and 263 are sequentially stacked from the lower surface 210L side of the substrate 210. The insulating layer 271 is located between the layer WL200B and the second wiring layer WL2B, and the insulating layer 272 is located so as to cover the second wiring layer WL2B. The electrode 281 and the electrode 282 are provided on the surface layer of the multilayer wiring layer 200B. The first wiring layer WL200B is configured of the conductor pattern 261, and the conductor pattern 261 is located on the lower surface 210L of the substrate 210 together with the height adjustment pattern 252. The conductor pattern 261 and the height adjustment pattern 252 are positioned at a predetermined distance in the in-plane direction on the lower surface 210L of the substrate 210. The second wiring layer WL2B includes a conductor pattern 262 and a conductor pattern 263, and a via 34 is provided between the conductor pattern 261 and the conductor pattern 262 as an interlayer connection portion for electrically connecting them. The electrode 281 is located on the top surface of the conductor pattern 262, and the electrode 282 is located continuously on the top surface of the conductor pattern 263. The height adjustment pattern 252 has a thickness substantially the same as the thickness of the conductor pattern 261, and has a configuration substantially the same as the height adjustment pattern 250. Also in the eighth embodiment, the height adjustment pattern 252 is located at substantially the same height (level) as the conductor pattern 261 (first wiring layer WL200B), and the stacking direction of the conductor pattern 263 (electrode 282) Since the lower surface of the insulating layer 271 is substantially flat by being positioned directly below, the height positions of the conductor pattern 262 (electrode 281) and the conductor pattern 263 (electrode 282) provided on the insulating layer 271 substantially coincide with each other. It will be done.
　［多層配線基板の製造方法］
　図２７は、本開示の一実施形態の多層配線基板の製造方法を表す工程図であり、図２８は、図２７の製造工程に続く工程を表す工程図である。以下では、第３実施形態における多層配線基板２００の製造方法を例として説明する。 [Method of manufacturing multilayer wiring board]
FIG. 27 is a process diagram illustrating a method of manufacturing a multilayer wiring board according to an embodiment of the present disclosure, and FIG. 28 is a process diagram illustrating steps subsequent to the manufacturing process of FIG. Below, the manufacturing method of the multilayer wiring board 200 in 3rd Embodiment is demonstrated as an example.
　まず、基板２１０として、所望の厚さと大きさとを有するガラスエポキシを主材とする基板を準備し、基板２１０の上面２１０Ｈに、導体パターン２１１、及び高さ調整用パターン２５０を形成する（図２７（Ａ））。導体パターン２１１を形成する方法としては、例えば基板２１０の上面２１０Ｈに導電層を形成し、この導電層上にレジストパターンを形成し、その後、このレジストパターンをマスクとしてエッチングする方法等が挙げられる。基板２１０の上面２１０Ｈに導電層を形成する方法としては、例えば、スパッタリング法等の真空成膜法や、めっき法（無電解めっき法、基板２１０の上面２１０Ｈに形成されたシード層を介した電解めっき法等）等が挙げられる。レジストパターンは、ドライフィルムレジストや液レジストに対する露光・現像処理により形成され得る。高さ調整用パターン２５０は、導体パターン２１１を形成した後に基板２１０の上面２１０Ｈにおける所定の領域（高さ調整用パターン２５０を形成すべき領域）に形成されてもよいし、導体パターン２１１を形成する前に形成されてもよい。なお、高さ調整用パターン２５０が導電材料により構成される場合、上記導体パターン２１１を形成するのと同時に高さ調整用パターン２５０を形成してもよい。感光性樹脂材料等の非導電材料により構成される高さ調整用パターン２５０を形成する方法としては、例えばスピンコート法等により感光性樹脂層を形成し、この感光性樹脂層に対して露光・現像を行う方法等が挙げられる。なお、基板２１０としては、上述したガラスエポキシを主材とする基板に限定されるものではなく、ガラス、シリコン等を主材とする基板が好適に用いられ得る。 First, a substrate mainly made of glass epoxy having a desired thickness and size is prepared as the substrate 210, and the conductor pattern 211 and the height adjustment pattern 250 are formed on the upper surface 210H of the substrate 210 (FIG. 27). (A)). As a method of forming the conductive pattern 211, for example, a conductive layer is formed on the upper surface 210H of the substrate 210, a resist pattern is formed on the conductive layer, and then etching is performed using the resist pattern as a mask. As a method of forming a conductive layer on the upper surface 210H of the substrate 210, for example, vacuum deposition such as sputtering, plating (electroless plating, electrolysis through a seed layer formed on the upper surface 210H of the substrate 210) Plating etc.). The resist pattern may be formed by exposure / development processing on a dry film resist or a liquid resist. The height adjustment pattern 250 may be formed in a predetermined region (region where the height adjustment pattern 250 is to be formed) on the upper surface 210H of the substrate 210 after the conductor pattern 211 is formed, or the conductor pattern 211 is formed. It may be formed before. When the height adjustment pattern 250 is made of a conductive material, the height adjustment pattern 250 may be formed simultaneously with the formation of the conductor pattern 211. As a method of forming the height adjustment pattern 250 made of a nonconductive material such as a photosensitive resin material, for example, a photosensitive resin layer is formed by a spin coating method or the like, and the photosensitive resin layer is exposed to light. The method etc. which develop are mentioned. The substrate 210 is not limited to the above-described substrate mainly composed of glass epoxy, and a substrate mainly composed of glass, silicon or the like may be suitably used.
　次に、導体パターン２１１、及び高さ調整用パターン２５０を覆うように絶縁層２２１を形成する（図２７（Ｂ））。この絶縁層２２１は、エポキシ樹脂溶液等を、スピンコート、ディップコート、スプレーコート、バーコート等の方法で塗布し、乾燥後、加熱硬化させる、いわゆる塗布法により形成され得る。本実施形態においては、導体パターン２１１上の絶縁層２２１の高さ位置と高さ調整用パターン２５０上の絶縁層２２１の高さ位置とが略一致する。絶縁層２２１を構成する樹脂材料としては、エポキシ樹脂の他、ポリイミド樹脂、アクリル樹脂等が使用される。また、絶縁層２２１は、単層構造であっても、２層以上の積層構造であってもよい。 Next, the insulating layer 221 is formed so as to cover the conductor pattern 211 and the height adjustment pattern 250 (FIG. 27B). The insulating layer 221 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating, or bar coating, dried and then heat cured. In the present embodiment, the height position of the insulating layer 221 on the conductor pattern 211 and the height position of the insulating layer 221 on the height adjustment pattern 250 substantially coincide with each other. As a resin material which constitutes insulating layer 221, polyimide resin, acrylic resin, etc. other than epoxy resin are used. The insulating layer 221 may have a single-layer structure or a stacked structure of two or more layers.
　次に、導体パターン２１１の上面の一部が露出するように、絶縁層２２１を厚さ方向に貫通する貫通孔２３１’を形成する（図２７（Ｃ））。貫通孔２３１’は、例えば、絶縁層２２１上に所望のレジストパターンを形成し、このレジストパターンをマスクとして所望のエッチング液でエッチングする等の方法により形成され得る。 Next, a through hole 231 ′ which penetrates the insulating layer 221 in the thickness direction is formed so that a part of the top surface of the conductor pattern 211 is exposed (FIG. 27C). The through holes 231 ′ can be formed by, for example, forming a desired resist pattern on the insulating layer 221 and etching the same with a desired etching solution using the resist pattern as a mask.
　次に、貫通孔３１’に導電材料を充填してビア２３１を形成しつつ、絶縁層２２１上に導体パターン２１２及び導体パターン２１３を形成する（図２７（Ｄ））。ビア２３１、導体パターン２１２及び導体パターン２１３は、上述した導体パターン２１１と同様にして形成され得る。ビア２３１、導体パターン２１２及び導体パターン２１３の形成には、銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）等、これらを含む合金が好適に用いられる。 Next, the conductive pattern 212 and the conductive pattern 213 are formed on the insulating layer 221 while filling the through holes 31 ′ with a conductive material to form the vias 231 (FIG. 27D). The via 231, the conductor pattern 212, and the conductor pattern 213 can be formed in the same manner as the above-described conductor pattern 211. For forming the vias 231, the conductor pattern 212, and the conductor pattern 213, an alloy containing copper (Cu), nickel (Ni), gold (Au), or the like is suitably used.
　その後、導体パターン２１２及び導体パターン２１３を覆うように絶縁層２２２を形成する（図２８（Ａ））。絶縁層２２２は、エポキシ樹脂溶液等を、スピンコート、ディップコート、スプレーコート、バーコート等の方法で塗布し、乾燥後、加熱硬化させる、いわゆる塗布法により形成され得る。絶縁層２２２を構成する樹脂材料としては、絶縁層２２１を構成する樹脂材料と同一のものを用いてもよいし、異なる種類の樹脂材料を用いてもよい。 After that, the insulating layer 222 is formed to cover the conductor pattern 212 and the conductor pattern 213 (FIG. 28A). The insulating layer 222 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating or bar coating, dried and then heat cured. As a resin material which comprises the insulating layer 222, the same thing as the resin material which comprises the insulating layer 221 may be used, and a different kind of resin material may be used.
　次に、導体パターン２１２の上面の一部が露出するように、絶縁層２２２を厚さ方向に貫通する貫通孔２４１’を形成するとともに、導体パターン２１３の上面の一部が露出するように、絶縁層２２２の厚さ方向に貫通する貫通孔２４２’を形成する（図２８（Ｂ））。貫通孔２４１’及び貫通孔２４２’は、上述した貫通孔２３１’の形成方法と略同一の方法により形成され得る。 Next, a through hole 241 ′ penetrating the insulating layer 222 in the thickness direction is formed so that a part of the upper surface of the conductor pattern 212 is exposed, and a part of the upper surface of the conductor pattern 213 is exposed, A through hole 242 ′ penetrating in the thickness direction of the insulating layer 222 is formed (FIG. 28 (B)). The through holes 241 ′ and the through holes 242 ′ may be formed by substantially the same method as the method of forming the through holes 231 ′ described above.
　次に、貫通孔２４１’に導電材料を充填して電極２４１を形成し、貫通孔２４２’に導電材料を充填して電極２４２を形成する（図２８（Ｃ））。電極２４１及び電極２４２は、電極２４１，４２を構成する材料（例えば、銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）、鉛錫合金等）を用い、導体パターン２１１～２１３と同様にして形成され得る。以上の工程により、導体パターン２１２（電極２４１）及び導体パターン２１３（電極２４２）の高さ位置が略一致した多層配線基板２００が作製され得る。 Next, the through hole 241 'is filled with a conductive material to form an electrode 241, and the through hole 242' is filled with a conductive material to form an electrode 242 (FIG. 28C). The electrodes 241 and 242 are made of a material (for example, copper (Cu), nickel (Ni), gold (Au), lead tin alloy, etc.) constituting the electrodes 241 and 42 in the same manner as the conductor patterns 211 to 213. It can be formed. Through the above-described steps, the multilayer wiring board 200 in which the height positions of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) substantially coincide with each other can be manufactured.
　＜第９実施形態＞
　本実施形態では、第１実施形態で説明した発光素子以外の素子を含んだ半導体装置について説明する。 The Ninth Embodiment
In the present embodiment, a semiconductor device including an element other than the light emitting element described in the first embodiment will be described.
　図２９は、半導体装置５００の断面図である。図２９に示すように、半導体装置５００は、トランジスタを含むチップ化された半導体素子６００、高周波素子６２０、インターポーザ７００、およびパッケージ基板８００を有する。半導体素子６００は、中央演算処理装置（ＣＰＵ：Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）としての機能、または記憶装置としての機能を有する。高周波素子は、高周波に対応した受動素子であり、インダクタ、容量素子、抵抗素子などを含む。インターポーザ７００は、パッケージ基板８００と、半導体素子６００および高周波素子６２０とを中継する機能を有する。半導体素子６００および高周波素子６２０と、インターポーザ７００とは、端子６５０を用いて電気的に接続される。また、半導体素子６００と、高周波素子６２０との間はモールド樹脂によって封止されていてもよい。また、インターポーザ７００と、パッケージ基板８００とは、端子７５０を用いて接続される。また、インターポーザ７００と、パッケージ基板８００との間隙は、アンダーフィル樹脂を用いて封止されてもよい。インターポーザ７００およびパッケージ基板８００には、配線基板１００を用いることができる。 FIG. 29 is a cross-sectional view of the semiconductor device 500. As shown in FIG. 29, the semiconductor device 500 includes a chipped semiconductor element 600 including a transistor, a high frequency element 620, an interposer 700, and a package substrate 800. The semiconductor element 600 has a function as a central processing unit (CPU: Central Processing Unit) or a function as a storage device. The high frequency element is a passive element corresponding to high frequency, and includes an inductor, a capacitive element, a resistive element, and the like. The interposer 700 has a function of relaying the package substrate 800, the semiconductor element 600 and the high frequency element 620. The semiconductor element 600 and the high frequency element 620 and the interposer 700 are electrically connected to each other using a terminal 650. The space between the semiconductor element 600 and the high frequency element 620 may be sealed with a mold resin. In addition, the interposer 700 and the package substrate 800 are connected using the terminal 750. Further, the gap between the interposer 700 and the package substrate 800 may be sealed using an underfill resin. The wiring substrate 100 can be used for the interposer 700 and the package substrate 800.
　＜第１０実施形態＞
　本実施形態では、第１～第８実施形態において説明した配線基板１００を電気機器に適用した例について説明する。 Tenth Embodiment
In this embodiment, an example in which the wiring substrate 100 described in the first to eighth embodiments is applied to an electric device will be described.
　図３０および図３１は、電気機器を説明する図である。配線基板１００を含んだ半導体装置は、例えば、携帯端末（携帯電話、スマートフォンおよびノート型パーソナルコンピュータ、ゲーム機器等）、情報処理装置（デスクトップ型パーソナルコンピュータ、サーバ、カーナビゲーション等）、家庭用電気機器（電子レンジ、エアコン、洗濯機、冷蔵庫）、自動車等、様々な電気機器に用いられている。 FIG. 30 and FIG. 31 are diagrams for explaining the electric device. The semiconductor device including the wiring substrate 100 is, for example, a portable terminal (mobile phone, smart phone and notebook personal computer, game machine etc.), an information processing apparatus (desktop personal computer, server, car navigation etc.), home electric appliance It is used for various electric devices such as (microwave oven, air conditioner, washing machine, refrigerator), car and so on.
　図３０は、タイリングＬＥＤ２０００である。タイリングＬＥＤ２０００には、発光装置１０００が格子状に配置され、発光装置１０００は配線基板１００に実装されている。第１～第８実施形態で説明した配線基板１００を用いることによりＬＥＤ素子の発光面の方向バラツキを抑制することが可能となり、タイリングのつなぎ目が視認され難くなる効果により、表示性能の良い装置を提供することができる。 FIG. 30 shows a tiling LED 2000. In the tiling LED 2000, the light emitting devices 1000 are arranged in a grid shape, and the light emitting devices 1000 are mounted on the wiring substrate 100. By using the wiring substrate 100 described in the first to eighth embodiments, it is possible to suppress the variation in the direction of the light emitting surface of the LED element, and an apparatus with good display performance due to the effect of making it difficult to visually recognize joints of tiling. Can be provided.
　図３１（Ａ）はスマートフォン４０００である。図３１（Ｂ）は携帯用ゲーム機５０００である。図３１（Ｃ）は、ノート型パーソナルコンピュータ６０００である。 31A shows a smartphone 4000. FIG. FIG. 31B shows a portable game machine 5000. FIG. 31C illustrates a laptop personal computer 6000.
　これらの電気機器において、配線基板１００が用いられることにより、高密度の実装が可能となる。したがって、電気機器の小型化、高性能化が可能となる。 In these electric devices, by using the wiring substrate 100, high-density mounting can be achieved. Therefore, downsizing and higher performance of the electric device can be achieved.
　以上説明した実施形態は、本開示の理解を容易にするために記載されたものであって、本開示を限定するために記載されたものではない。したがって、上記実施形態に開示された各要素は、本開示の技術的範囲に属するすべての設計変更や均等物をも含む趣旨である。 The embodiments described above are described to facilitate understanding of the present disclosure, and are not described to limit the present disclosure. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents that fall within the technical scope of the present disclosure.
　（変形例１）
　本開示の第１実施形態では、基板１１０の上面１１０Ａからビア部１４１の底部１４１Ｄまでの距離ＤＬ１よりも基板１１０の上面１１０Ａからダミービア部１４３の底部１４３Ｄまでの距離ＤＬ２の方が長い例を示したが、これに限定されない。図３２は、配線基板１００－６の断面図である。図３２に示すように、配線基板１００－６において距離ＤＬ１よりも距離ＤＬ２の方が短くても配線基板１００と同様の効果を有することができる。 (Modification 1)
In the first embodiment of the present disclosure, an example is shown in which the distance DL2 from the top surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 is longer than the distance DL1 from the top surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141. However, it is not limited to this. FIG. 32 is a cross-sectional view of the wiring substrate 100-6. As shown in FIG. 32, even if the distance DL2 is shorter than the distance DL1 in the wiring substrate 100-6, the same effect as the wiring substrate 100 can be obtained.
　（変形例２）
　本開示の第１実施形態では、導電部１５０－１の上面および導電部１５０－２の上面は、凸形状を有する例を示したが、これに限定されない。図２５は、配線基板１００－７の断面図である。図３３に示すように、配線基板１００－７は、導電部１５０－１の上面および導電部１５０－２の上面が凹部を有してもよい。配線基板１００－７においても、配線基板１００と同様の効果を有することができる。 (Modification 2)
In the first embodiment of the present disclosure, although the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have an example having a convex shape, the present invention is not limited thereto. FIG. 25 is a cross-sectional view of the wiring board 100-7. As shown in FIG. 33, in the wiring substrate 100-7, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 may have a recess. Also in the wiring substrate 100-7, the same effect as the wiring substrate 100 can be obtained.
　（変形例３）
　本開示の第１実施形態では、導電部１５０－２が下部配線１２０と接続されない例を示したが、導電部１５０－２は下部配線１２０と異なる導電部と接続されてもよい。図３４に配線基板１００－８の上面図および図２７に配線基板１００－８のＡ１－Ａ２間の断面図を示す。図３４および図３５に示すように、配線基板１００－８は、基板１１０、下部配線１２０、絶縁層１３０、ビア部１４１、ダミービア部１４３、導電部１５０－１、導電部１５０－２、上部配線１６０の他に導電部１２２を有する。 (Modification 3)
In the first embodiment of the present disclosure, the example in which the conductive portion 150-2 is not connected to the lower wiring 120 is shown, but the conductive portion 150-2 may be connected to a conductive portion different from the lower wiring 120. FIG. 34 shows a top view of the wiring board 100-8 and FIG. 27 shows a cross-sectional view of the wiring board 100-8 taken along line A1-A2. As shown in FIGS. 34 and 35, the wiring substrate 100-8 includes the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, the conductive portion 150-2, the upper wiring In addition to 160, a conductive portion 122 is provided.
　導電部１２２は、下部配線１２０と同様に基板１１０上に配置されている。また、導電部１２２は、ダミービア部１４３および導電部１５０－２と重畳して配置されている。このとき、基板１１０の上面１１０Ａからビア部１４１の底部１４１Ｄまでの距離ＤＬ１と基板１１０の上面１１０Ａからダミービア部１４３の底部１４３Ｄまでの距離ＤＬ２とが等しくてもよい。上記において、導電部１２２と導電部１５０－２とが接続されている。なお、導電部１２２は、電極としての機能を有さなくてもよい。このとき、導電部１５０－２のうちダミービア部１４３に設けられた領域１５０－２Ｆおよび導電部１２２は、電気回路の構成要素でなくてもよい。一方で、導電部１５０－２のうち領域１５０－２Ｆの上側の領域１５０－２Ｆは、上部配線１６０と接続されている。このとき、領域１５０－２Ｕおよび上部配線１６０は、電気回路の一部を構成してもよい。 The conductive portion 122 is disposed on the substrate 110 in the same manner as the lower wiring 120. In addition, the conductive portion 122 is disposed to overlap with the dummy via portion 143 and the conductive portion 150-2. At this time, the distance DL1 from the top surface 110A of the substrate 110 to the bottom 141D of the via portion 141 may be equal to the distance DL2 from the top surface 110A of the substrate 110 to the bottom 143D of the dummy via portion 143. In the above, the conductive portion 122 and the conductive portion 150-2 are connected. Note that the conductive portion 122 may not have a function as an electrode. At this time, the region 150-2F and the conductive portion 122 provided in the dummy via portion 143 in the conductive portion 150-2 may not be components of the electric circuit. On the other hand, region 150-2F on the upper side of region 150-2F in conductive portion 150-2 is connected to upper interconnection 160. At this time, the region 150-2U and the upper wiring 160 may form part of an electric circuit.
　上記構造を有することにより、ビア部１４１、ダミービア部１４３、導電部１５０－１および導電部１５０－２の形状が安定し、配線基板１００と同様に端子の高さのばらつきを低減させることができる。 With the above structure, the shapes of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 can be stabilized, and the variation in height of the terminals can be reduced as in the wiring substrate 100. .
　（変形例４）
　本開示の第１実施形態では、フォトリソグラフィ法により、ビア部１４１およびダミービア部１４３を形成する例を説明したが、これに限定されない。ビア部１４１およびダミービア部１４３は、レーザー照射法により形成されてもよい。 (Modification 4)
In the first embodiment of the present disclosure, although the example in which the via portion 141 and the dummy via portion 143 are formed by the photolithography method has been described, the present invention is not limited thereto. The via portion 141 and the dummy via portion 143 may be formed by a laser irradiation method.
　レーザー照射を行う場合、レーザーには、エキシマレーザー、ネオジウム：ヤグレーザー（Ｎｄ：ＹＡＧ）レーザー、フェムト秒レーザー等が用いられる。エキシマレーザーを用いる場合、紫外領域の光が照射される。例えば、エキシマレーザーにおいて塩化キセノンを用いる場合、波長が３０８ｎｍの光が照射される。なお、ビア部１４１およびダミービア部１４３の穴径は、レーザーの照射径により制御される。このとき、レーザーによる照射径は、５μｍ以上３０μｍ未満としてもよい。 When the laser irradiation is performed, an excimer laser, a neodymium: Yag laser (Nd: YAG) laser, a femtosecond laser, or the like is used as the laser. When an excimer laser is used, light in the ultraviolet region is emitted. For example, when using xenon chloride in an excimer laser, light with a wavelength of 308 nm is emitted. The hole diameter of the via portion 141 and the dummy via portion 143 is controlled by the irradiation diameter of the laser. At this time, the irradiation diameter by the laser may be 5 μm or more and less than 30 μm.
　上記において、ダミービア部１４３を形成する場合のレーザーの出力条件は、ビア部１４１を形成する場合のレーザーの出力条件よりも小さくてもよい。 In the above, the output condition of the laser in the case of forming the dummy via portion 143 may be smaller than the output condition of the laser in the case of forming the via portion 141.
　なお、絶縁層１３０が、無機絶縁層の場合、反応性イオンエッチング法、ウェットエッチング法を用いてもよいし、レーザー照射法とウェットエッチング法を組み合わせて用いてもよい。ウェットエッチング法のためのエッチング液としては、フッ酸（ＨＦ）、硝酸（ＨＮＯ3）、アルカリ溶液のいずれかを用いてもよい。 In the case where the insulating layer 130 is an inorganic insulating layer, a reactive ion etching method or a wet etching method may be used, or a combination of a laser irradiation method and a wet etching method may be used. As an etching solution for the wet etching method, any of hydrofluoric acid (HF), nitric acid (HNO 3 ) and an alkaline solution may be used.
　（変形例５）
　上記各実施形態における多層配線基板２００においては、図２１～図２６に示される通り、表層に位置する導体パターンの積層方向の略直下に高さ調整用パターンが設けられている態様が描かれているが、この態様に限定されるものではない。例えば、表層に位置する導体パターンの高さ位置を略一致させ得る限り、表層に位置する導体パターンの少なくとも一部の積層方向下方に高さ調整用パターンが位置するものであればよい。すなわち、表層に位置する導体パターンの積層方向の直下でなくても、当該積層方向の直下の位置から所定の層の面内方向（図示においては左右方向）にずれた位置に高さ調整用パターンが位置するものであってもよい。 (Modification 5)
In the multilayer wiring board 200 in each of the above embodiments, as shown in FIGS. 21 to 26, the aspect in which the height adjustment pattern is provided substantially directly below the lamination direction of the conductor patterns located in the surface layer is drawn. However, the present invention is not limited to this aspect. For example, as long as the height positions of the conductor patterns located in the surface layer can be made to substantially coincide with each other, the height adjustment pattern may be located below the stacking direction of at least a part of the conductor patterns located in the surface layer. That is, even if it is not directly under the lamination direction of the conductor pattern positioned on the surface layer, the height adjustment pattern is a position deviated in the in-plane direction (left and right direction in the drawing) of the predetermined layer from the position directly below the lamination direction. May be located.
　（変形例６）
　上記実施形態においては、２つ又は３つの配線層を有する多層配線基板を例に挙げて説明したが、この態様に限定されるものではなく、４つ以上の配線層を有するものであってもよい。 (Modification 6)
Although the multilayer wiring board having two or three wiring layers has been described as an example in the above embodiment, the present invention is not limited to this embodiment, and even if four or more wiring layers are provided. Good.
　９０・・・配線基板、１００・・・配線基板、１０５・・・外部端子、１１０・・・基板、１２０・・・下部配線、１２２・・・導電部、１３０・・・絶縁層、１４１・・・ビア部、１４３・・・ダミービア部、１４７・・・シード層、１４９・・・レジスト膜、１５０・・・導電部、１６０・・・上部配線、１６５・・・絶縁層、１７１・・・ビア部、１７３・・・ダミービア部、１８０・・・導電部、１８３・・・導電部、１８５・・・導電部、２００・・・多層配線基板、２１０・・・基板、２１１，２１２，２１３，２１４，２１５，２１６，２１７，２１８，２６１，２６２，２６３・・・導体パターン、２２１，２２２，２２３・・・絶縁層、２３１，２３２，２３３・・・ビア（層間接続部）、２４１，２４２，２８１，２８２・・・電極、２５０，２５１，２５２・・・高さ調整用パターン、３００・・・発光素子、３１０・・・端子、３２０・・・反射材、３３０・・・封止材、３４０・・・レンズ、３５０・・・保護部材、５００・・・半導体装置、６００・・・半導体素子、６２０・・・高周波素子、６５０・・・端子、６７０・・・半導体素子、７００・・・インターポーザ、７５０・・・端子、８００・・・パッケージ基板、１０００・・・発光装置、２０００・・・タイリングＬＥＤ、４０００・・・スマートフォン、５０００・・・携帯用ゲーム機、６０００・・・ノート型パーソナルコンピュータ 90 ... wiring board, 100 ... wiring board, 105 ... external terminal, 110 ... board, 120 ... lower wiring, 122 ... conductive part, 130 ... insulating layer, 141 · · · · · · Via portion, 143 · · · dummy via portion, 147 · · · seed layer, 149 · · · resist film, 150 · · · conductive portion, 160 · · · upper wiring, 165 · · · · · · · · · · · · · · -Via part 173: dummy via part 180: conductive part 183: conductive part 185: conductive part 200: multilayer wiring board 210: board 211, 212 213, 214, 215, 216, 217, 218, 261, 262, 263 · · · conductor pattern, 221, 222, 223 · · · insulating layer, 231, 232, 233 · · · via (interlayer connection portion), 241 , 242, 281, 2 2: Electrode, 250, 251, 252: Height adjustment pattern, 300: Light emitting element, 310: Terminal, 320: Reflective material, 330: Sealing material, 340 · · · Lens, 350 · · · protection member, 500 · · · semiconductor device, 600 · · · semiconductor element, 620 · · · high frequency element, 650 · · · · · · · · · · · · semiconductor element, 700 · · · · 750: terminal 800: package substrate 1000: light-emitting device 2000: tiling LED 4000: smart phone 5000: portable game machine 6000: notebook type Personal computer

Claims (22)

  1. 　基板と、
    　前記基板上の絶縁層と、
    　前記絶縁層内に設けられた高さ調整部と、
    　前記絶縁層上に設けられた第１導電部と、
    　前記第１導電部と隣接し、前記絶縁層および前記高さ調整部上に設けられた第２導電部と、を含み、
    　前記基板上面から前記第１導電部の上面までの高さと、前記基板の上面から前記第２導電部の上面までの高さが略一致している、
    　配線基板。     A substrate,
    An insulating layer on the substrate;
    A height adjustment unit provided in the insulating layer;
    A first conductive portion provided on the insulating layer;
    And a second conductive portion provided adjacent to the first conductive portion and provided on the insulating layer and the height adjustment portion,
    The height from the upper surface of the substrate to the upper surface of the first conductive portion substantially matches the height from the upper surface of the substrate to the upper surface of the second conductive portion.
    Wiring board.
  2. 　前記基板と前記絶縁層との間に設けられた下部配線と、
    　前記絶縁層内に設けられ、前記下部配線上に配置されたビア部と、を含み、
    　前記高さ調整部は、前記ビア部に隣接し、前記絶縁層内に設けられたダミービア部であり、
    　前記第１導電部は、前記絶縁層および前記ビア部上に配置されるとともに、前記下部配線と電気的に接続される、
    　請求項１に記載の配線基板。     Lower wiring provided between the substrate and the insulating layer;
    A via portion provided in the insulating layer and disposed on the lower wiring,
    The height adjustment portion is a dummy via portion adjacent to the via portion and provided in the insulating layer,
    The first conductive portion is disposed on the insulating layer and the via portion, and is electrically connected to the lower wiring.
    The wiring board according to claim 1.
  3. 　前記基板の上面から前記ビア部の底部までの高さと、前記基板の上面から前記ダミービア部の底部までの高さとは異なる、
    　請求項２に記載の配線基板。     The height from the top surface of the substrate to the bottom of the via portion is different from the height from the top surface of the substrate to the bottom of the dummy via portion,
    The wiring board according to claim 2.
  4. 　前記基板の上面から前記ビア部の底部までの高さよりも前記基板の上面から前記ダミービア部の底部までの高さの方が長い、
    　請求項３に記載の配線基板。     The height from the top surface of the substrate to the bottom of the dummy via portion is longer than the height from the top surface of the substrate to the bottom of the via portion,
    The wiring board according to claim 3.
  5. 　断面視において、前記下部配線の一部は、前記第２導電部と重畳し、かつ離間する、
    　請求項４に記載の配線基板。     In a cross sectional view, a part of the lower wiring overlaps and is separated from the second conductive portion.
    The wiring board according to claim 4.
  6. 　断面視において、前記基板の上面から前記第１導電部の最上部までの高さと、前記基板の上面から前記第２導電部の最上部までの高さとの差が、１μｍ以下である、
    　請求項２に記載の配線基板。     In a cross sectional view, the difference between the height from the top surface of the substrate to the top of the first conductive portion and the height from the top surface of the substrate to the top of the second conductive portion is 1 μm or less
    The wiring board according to claim 2.
  7. 　断面視において、前記第１導電部の中心線と、前記第２導電部の中心線との距離は、１０μｍ以上１００μｍ以下である、
    　請求項２に記載の配線基板。     In a cross sectional view, a distance between a center line of the first conductive portion and a center line of the second conductive portion is 10 μm to 100 μm.
    The wiring board according to claim 2.
  8. 　断面視において、前記第１導電部の中心線と、前記第２導電部の中心線との距離は、２０μｍ以上５０μｍ以下である、
    　請求項２に記載の配線基板。     In a cross sectional view, the distance between the center line of the first conductive portion and the center line of the second conductive portion is not less than 20 μm and not more than 50 μm.
    The wiring board according to claim 2.
  9. 　前記ビア部の上部径および前記ダミービア部の上部径は、３μｍ以上３０μｍ以下である、
    　請求項２に記載の配線基板。     The upper diameter of the via portion and the upper diameter of the dummy via portion are 3 μm or more and 30 μm or less.
    The wiring board according to claim 2.
  10. 　前記ビア部の上部径および前記ダミービア部の上部径は、５μｍ以上１０μｍ以下である、
    　請求項２に記載の配線基板。     The upper diameter of the via portion and the upper diameter of the dummy via portion are 5 μm or more and 10 μm or less.
    The wiring board according to claim 2.
  11. 　前記第１導電部の上面および前記第２導電部の上面は湾曲している、
    　請求項２に記載の配線基板。     The upper surface of the first conductive portion and the upper surface of the second conductive portion are curved,
    The wiring board according to claim 2.
  12. 　前記絶縁層上に配置された上部配線をさらに含み、
    　前記上部配線と、第２導電部とは、電気的に接続される、
    　請求項２に記載の配線基板。     Further comprising an upper wire disposed on the insulating layer,
    The upper wiring and the second conductive portion are electrically connected,
    The wiring board according to claim 2.
  13. 　前記第１導電部、前記第２導電部、前記高さ調整部、及び前記絶縁層は、第１～第Ｎ（Ｎは２以上の整数である。）配線層がこの順に積層されてなる多層配線層の一部であり、
    　前記第１～第Ｎ配線層のうちの少なくとも２つの配線層を互いに電気的に接続するための層間接続部が設けられ、
    　前記絶縁層は、前記第１～第Ｎ配線層のそれぞれの配線層の間を電気的に分離し、
    　前記第１導電部および前記第２導電部は、前記第Ｎ配線層を構成し、
    　前記高さ調整部は、前記第２導電部の積層方向下方において、前記第１～第Ｎ－１配線層のそれぞれを構成する導電部の少なくとも一部に設けられる、
    　請求項１に記載の配線基板。     The first conductive portion, the second conductive portion, the height adjusting portion, and the insulating layer are multi-layered in which first to Nth (N is an integer of 2 or more) wiring layers are stacked in this order. Part of the wiring layer,
    An interlayer connection portion is provided to electrically connect at least two of the first to Nth wiring layers to each other,
    The insulating layer electrically isolates each of the first to Nth wiring layers,
    The first conductive portion and the second conductive portion constitute the Nth wiring layer,
    The height adjustment portion is provided on at least a part of the conductive portions constituting each of the first to (N-1) th wiring layers below the stacking direction of the second conductive portion.
    The wiring board according to claim 1.
  14. 　Ｎは３以上の整数であり、前記第２導電部のうちの少なくとも一部の積層方向下方には、複数の高さ調整部が設けられている請求項１３に記載の配線基板。 14. The wiring board according to claim 13, wherein N is an integer of 3 or more, and a plurality of height adjusting portions are provided below at least a part of the second conductive portions in the stacking direction.
  15. 　前記高さ調整部が、前記第１～第Ｎ配線層との間で電気的に分離されている請求項１３に記載の配線基板。 The wiring board according to claim 13, wherein the height adjustment portion is electrically separated from the first to Nth wiring layers.
  16. 　前記第Ｎ配線層に電気的に接続する複数の電極をさらに備える請求項１３乃至１５のいずれか一に記載の配線基板。 The wiring board according to any one of claims 13 to 15, further comprising a plurality of electrodes electrically connected to the Nth wiring layer.
  17. 　請求項１６に記載の配線基板と、前記複数の電極のいずれか一つに電気的に接続されて実装されてなる少なくとも１つの電子部品とを備える部品実装配線基板。 A component mounting wiring substrate comprising: the wiring substrate according to claim 16; and at least one electronic component electrically connected to and mounted on any one of the plurality of electrodes.
  18. 　請求項１乃至１２のいずれか一に記載の配線基板と、
    　半導体素子と、を含む、半導体装置。     A wiring board according to any one of claims 1 to 12.
    And a semiconductor device.
  19. 　前記半導体素子は、発光素子である、
    　請求項１８に記載の半導体装置。     The semiconductor device is a light emitting device.
    The semiconductor device according to claim 18.
  20. 　基板上に下部配線を形成し、
    　前記基板および前記下部配線上に絶縁層を形成し、
    　前記下部配線に重畳するように前記絶縁層にビア部を形成し、
    　前記ビア部に隣接するように前記絶縁層にダミービア部を形成し、
    　前記ビア部および前記絶縁層上に第１導電部を形成し、
    　前記ダミービア部および前記絶縁層上に第２導電部を形成する、
    　配線基板の製造方法。     Form the lower wiring on the substrate,
    Forming an insulating layer on the substrate and the lower wiring;
    Forming a via portion in the insulating layer so as to overlap the lower wiring;
    Forming a dummy via portion in the insulating layer adjacent to the via portion;
    Forming a first conductive portion on the via portion and the insulating layer;
    Forming a second conductive portion on the dummy via portion and the insulating layer;
    Method of manufacturing a wiring board.
  21. 　断面視において、
    　前記基板の上面から前記ビア部の底部までの高さと、前記基板の上面から前記ダミービア部の底部までの高さとは異なる、
    　請求項２０に記載の配線基板の製造方法。     In cross section,
    The height from the top surface of the substrate to the bottom of the via portion is different from the height from the top surface of the substrate to the bottom of the dummy via portion,
    A method of manufacturing a wiring board according to claim 20.
  22. 　前記ビア部および前記ダミービア部は、ハーフトーンマスクを用いたフォトリソグラフィ法またはレーザー照射法を用いて形成される、
    　請求項２１に記載の配線基板の製造方法。     The via portion and the dummy via portion are formed using a photolithography method or a laser irradiation method using a halftone mask.
    A method of manufacturing a wiring board according to claim 21.
PCT/JP2018/031835 2017-08-29 2018-08-28 Wiring substrate, component mounting wiring substrate, semiconductor device, and method for manufacturing wiring substrate WO2019044857A1 (en)

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JP2001093935A (en) * 1999-09-20 2001-04-06 Rohm Co Ltd Semiconductor device and semiconductor chip used therefor
JP2002368383A (en) * 2001-06-05 2002-12-20 Toshiba Corp Method for manufacturing complex member, mask substrate for manufacturing complex member, complex member and wiring board
JP2008160042A (en) * 2006-12-26 2008-07-10 Denso Corp Multilayer board
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