JP7184041B2 - Wiring board and semiconductor device - Google Patents

Description

The present disclosure relates to a wiring board, a semiconductor device, and a method of manufacturing a wiring board.

2. Description of the Related Art A technology (high-density mounting technology) for mounting semiconductor devices including integrated circuits and high-frequency devices including passive devices on a substrate at high density is widely used. High-density mounting techniques include a wire bonding method that uses small wires for connection, and a flip chip method that uses connection terminals arranged in a grid pattern without using wires for connection. Japanese Patent Application Laid-Open No. 2002-200003 discloses a high-density mounting technique using a flip-chip method. Patent Document 2 discloses the structure of a multilayer wiring board used in high-density mounting technology.

JP 2004-055660 A JP 2014-179518 A

On the other hand, as the pitch between the connection terminals becomes narrower, variations in height between the connection terminals may occur. In particular, connection terminals formed by electroplating may have a large variation in height (coplanarity). If the coplanarity increases, there is a risk that connection failure will occur between the wiring board and the semiconductor element.

In addition, in a multilayer wiring board, since it is necessary to arrange a large number of conductor patterns at high density in the lamination direction and the in-plane direction of each layer without short-circuiting each other, the arrangement of the conductor patterns constituting each wiring layer is different for each layer. must be different. Therefore, when the multilayer wiring board is viewed along the stacking direction, the area where the conductor pattern exists in one wiring layer and the area where the conductor pattern exists in the other wiring layer do not partially overlap. Become. In order to manufacture such a multilayer wiring board, when wiring layers having different conductor pattern arrangement patterns are laminated via an insulating layer, the insulating layer located on the region where the conductor pattern exists in each wiring layer is The height differs from the height of the insulating layer located on the area where the conductor pattern does not exist. Due to this, the height position of each electrode provided on the surface layer of the multilayer wiring board is different.

Generally, in a multilayer wiring board, in order to stably surface-mount an electronic component such as a semiconductor chip, it is desirable that the height positions of a plurality of electrodes provided on the surface layer are approximately the same. However, since the height positions of the plurality of electrodes provided on the surface layer do not substantially match each other as described above, it becomes difficult to stably mount the electronic component.

In view of such problems, one object of the present disclosure is to provide a wiring board in which the height variation of connection terminals is small. Another object of the present disclosure is to provide a high-quality wiring board and a component-mounted wiring board on which electronic components can be stably mounted.

According to one embodiment of the present disclosure, a substrate, an insulating layer on the substrate, a height adjustment part provided in the insulating layer, a first conductive part provided on the insulating layer, and a first conductive part a second conductive portion adjacent to and provided on the insulating layer and the height adjustment portion; A wiring board is provided that has substantially the same height.

The wiring board includes a lower wiring provided between the substrate and the insulating layer, and a via section provided in the insulating layer and arranged on the lower wiring, wherein the height adjusting section is provided in the via section. A dummy via portion is adjacent and provided in the insulating layer, and the first conductive portion may be arranged on the insulating layer and the via portion, and may be electrically connected to the lower wiring.

In the above wiring board, the height from the top surface of the substrate to the bottom of the via portion may be different from the height from the top surface of the substrate to the bottom of the dummy via portion.

In the above wiring board, the height from the upper surface of the substrate to the bottom of the dummy via may be longer than the height from the upper surface of the substrate to the bottom of the via.

In the above wiring board, a part of the lower wiring may overlap and be separated from the second electrode in a cross-sectional view.

In the above wiring board, a difference between a height from the upper surface of the substrate to the top of the first electrode and a height from the upper surface of the substrate to the top of the second electrode may be 1 μm or less in a cross-sectional view.

In the above wiring board, the distance between the center line of the first electrode and the center line of the second electrode may be 10 μm or more and 100 μm or less in a cross-sectional view.

In the above wiring board, the distance between the center of the first electrode and the center of the second electrode may be 20 μm or more and 50 μm or less.

In the above wiring board, the top diameter of the via portion and the top diameter of the dummy via may be 3 μm or more and 30 μm or less.

In the above wiring board, the distance between the center of the bottom of the via portion and the center of the bottom of the dummy via may be 5 μm or more and 10 μm or less.

In the above wiring board, the upper surfaces of the first electrode and the second electrode may be curved.

The wiring substrate may further include an upper wiring disposed on the insulating layer, and the upper wiring and the second electrode may be electrically connected.

In the wiring board, the first conductive portion, the second conductive portion, the height adjustment portion, and the insulating layer are formed by laminating first to N-th (N is an integer of 2 or more) wiring layers in this order. An interlayer connection part is provided for electrically connecting at least two wiring layers among the first to Nth wiring layers, and is a part of the multilayer wiring layer. The wiring layers of the layers are electrically separated, the first conductive section and the second conductive section constitute the Nth wiring layer, the height adjusting section is located below the second conductive section in the stacking direction, It may be provided in at least a part of the conductive portion forming each of the 1st to (N-1)th wiring layers.

In the above wiring board, N is an integer of 3 or more, and a plurality of height adjustment portions may be provided below at least a portion of the conductor patterns forming the Nth wiring layer in the stacking direction.

In the wiring board, the height adjusting portion may be electrically separated from the first to Nth wiring layers.

The wiring board may further include a plurality of electrodes electrically connected to the Nth wiring layer.

According to one embodiment of the present disclosure, there is provided a component-mounted wiring board that includes the wiring board described above and at least one electronic component that is electrically connected to and mounted on any one of the plurality of electrodes.

According to one embodiment of the present disclosure, a semiconductor device is provided that includes the wiring board and a semiconductor element.

In the above semiconductor device, the semiconductor element may be a light emitting element.

According to one embodiment of the present disclosure, a lower wire is formed on a substrate, an insulating layer is formed on the substrate and the lower wire, a via portion is formed in the insulating layer so as to overlap the lower wire, and adjacent to the via portion. A method for manufacturing a wiring board is provided, comprising: forming a dummy via portion in an insulating layer so as to form a first electrode on the via portion and the insulating layer; and forming a second electrode on the dummy via portion and the insulating layer.

In the method for manufacturing the wiring board described above, in a cross-sectional view, the height from the top surface of the substrate to the bottom of the via portion may be different from the height from the top surface of the substrate to the bottom of the dummy via portion.

In the wiring board manufacturing method described above, the via portion and the dummy via portion may be formed using a photolithography method using a halftone mask or a laser irradiation method.

According to an embodiment of the present disclosure, it is possible to provide a wiring board with little variation in the height of connection terminals. Further, according to an embodiment of the present disclosure, it is possible to provide a high-quality wiring board and a component-mounted wiring board on which electronic components can be stably mounted.

1 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present disclosure; FIG. 1 is a top view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 4A is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present disclosure; 1 is a top view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a top view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a top view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 1A to 1D are process diagrams showing a method for manufacturing a wiring board according to an embodiment of the present disclosure; FIG. 28 is a process diagram showing a method for manufacturing a wiring board according to an embodiment of the present disclosure, and is a process diagram showing a process following the process diagram of FIG. 27 ; 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure; FIG. 1 is a perspective view of an electrical device according to an embodiment of the present disclosure; FIG. 1 is a perspective view of an electrical device according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a top view illustrating a wiring board according to an embodiment of the present disclosure; FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment of the present disclosure; FIG. and FIG. 11 is a cross-sectional view for explaining a conventional wiring board. FIG. 10 is a reference diagram showing a configuration example of a multilayer wiring board that appears as a difference in height position in the stacking direction of two conductor patterns located on the surface layer;

Hereinafter, wiring boards and the like according to respective embodiments of the present disclosure will be described in detail with reference to the drawings. Each embodiment shown below is an example of the embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same reference numerals or similar reference numerals (-1, -2, etc. after the numerals), The repeated description may be omitted. Also, the dimensional ratios in the drawings may differ from the actual ratios for the convenience of explanation, and a part of the configuration may be omitted from the drawings.

In the drawings attached to this specification, in order to facilitate understanding, the shape, scale, ratio of vertical and horizontal dimensions, etc. of each part may be changed from the real thing or exaggerated.

In this specification and the like, a numerical range represented by "to" means a range including the numerical values described before and after "to" as lower and upper limits, respectively. In this specification and the like, terms such as "film", "sheet", and "plate" are not distinguished from each other based on the difference in designation. For example, "plate" is a concept that includes members that can be generally called "sheets" and "films."

<First embodiment>
(1-1. Configuration of Light Emitting Device)
FIG. 1 shows a cross-sectional view of a light-emitting device 1000 which is one of semiconductor devices. Light emitting device 1000 includes wiring board 100 , external terminal 105 , conductive portion 150 , light emitting element 300 , terminal 310 , reflector 320 , sealing material 330 , lens 340 and protective member 350 .

The light-emitting element 300 is one of semiconductor elements, and in this example, a GaN-based light-emitting diode is used.

The reflector 320 has a function of reflecting light. Reflective material 320 includes a metal material. In this example, aluminum is used for the reflector 320 . It should be noted that the reflecting material 320 may be formed by vapor-depositing a metal on the surface of molded resin.

The encapsulant 330 has a function of protecting the light emitting element from external components such as moisture. An organic resin such as epoxy resin or silicone resin is used for the sealing material 330 . In addition to the organic resin, inert gas may be used for the sealing material 330 .

Lens 340 has the function of diffusing or concentrating light from the light emitting element. A transparent material such as quartz is used for the lens 340 .

The protective member 350 has a function of protecting the light emitting element from physical impact. The protective member 350 has translucency. An organic resin such as an epoxy resin or an acrylic resin is used for the protective member 350 .

The wiring board 100 is electrically connected to the light emitting element 300 . In this example, the conductive portion 150 (for example, a conductive portion 150-1 described later) of the wiring board 100 and the terminal 310 of the light emitting element 300 are connected by a flip chip method. At this time, 24 or more conductive portions 150 (for example, a conductive portion 150-1 to be described later) of the wiring board are arranged. Also, the wiring substrate 100 is provided with an external terminal 105 . The external terminals 105 are connected to external wiring boards or electrodes. Details of the wiring substrate 100 and the conductive portion 150 will be described later. Incidentally, the conductive part, the terminal, the wiring and the electrode can be used with the same meaning.

(1-2. Configuration of Wiring Board)
FIG. 2 is a top view of the wiring board 100 of FIG. FIG. 3 is a cross-sectional view of the wiring board 100 along A1-A2.

The wiring substrate 100 has a substrate 110, a lower wiring 120, an insulating layer 130, a via portion 141, a dummy via portion 143, and conductive portions 150 (conductive portions 150-1 and 150-2).

A high resistance material is used for the substrate 110 . For example, a silicon substrate is used for the substrate 110 . The thickness of the substrate 110 is not particularly limited, but may be appropriately set within a range of 100 μm or more and 700 μm or less. For example, the thickness of the substrate 110 is 400 μm.

Also, the substrate 110 may be an organic resin. For example, when the substrate 110 is made of organic resin such as polyimide resin, the thickness of the substrate 110 may be several μm or more and several tens of μm or less.

A lower wiring 120 is provided on the substrate 110 . Copper (Cu) is used for the lower wiring 120 . In addition to copper (Cu), the lower wiring 120 is made of a metal material such as aluminum (Al), titanium (Ti), tungsten (W), gold (Au), silver (Ag), or nickel (Ni). may be used.

An insulating layer 130 is provided on the substrate 110 and the lower wiring 120 . For example, polyimide resin is used for the insulating layer 130 . Further, the polyimide resin may contain a photosensitive material.

Note that the insulating layer 130 is not limited to the above. For example, an inorganic insulating material such as a silicon oxide film or a silicon nitride film may be used for the insulating layer 130 . Also, the insulating layer 130 may be made of other organic insulating materials such as acrylic resin and epoxy resin.

The via portion 141 is a recess provided in the insulating layer 130 . The via part 141 is arranged on the lower wiring 120 .

Dummy via portion 143 is a recess provided in insulating layer 130 adjacent to via portion 141 .

A conductive portion 150 is disposed on the insulating layer 130 . Among the conductive portions 150, the portion disposed on the insulating layer 130 and the via portion 141 is called a conductive portion 150-1 (or sometimes called a first conductive portion). In the above, the conductive portion 150-1 protrudes above the insulating layer . Among the conductive portions 150, those arranged on the insulating layer 130 and the dummy via portion 143 are referred to as conductive portions 150-2 (or sometimes referred to as second conductive portions). In the above, the conductive portion 150-2 protrudes above the insulating layer . Conductive portion 150-2 is arranged adjacent to conductive portion 150-1. It should be noted that the conductive portion 150-1 and the conductive portion 150-2 will be described as the conductive portion 150 when it is not necessary to separately describe them.

Conductive portion 150 includes seed layer 147 . Copper (Cu) is used for the seed layer 147 and the conductive portion 150, but is not limited thereto, and gold (Au), silver (Ag), palladium (Pd), nickel (Ni), and tin (Sn) are used. may be used.

Also, the upper surface of conductive portion 150-1 and the upper surface of conductive portion 150-2 may not be flat. In this example, the upper surface of conductive portion 150-1 and the upper surface of conductive portion 150-2 are curved. Specifically, the upper surface of conductive portion 150-1 and the upper surface of conductive portion 150-2 have a convex shape.

3, the region 150-1F provided in the via portion 141 of the conductive portion 150-1 is electrically connected to the lower wiring 120. As shown in FIG. On the other hand, the region 150-2F provided in the dummy via portion 143 of the conductive portion 150-2 is not electrically connected to the lower wiring 120. FIG. In other words, it can be said that the region 150-1F constitutes a part of the electric circuit, whereas the region 150-2F is not a component of the electric circuit.

Next, the details of the positional configuration of via portion 141, dummy via portion 143, conductive portion 150-1 and conductive portion 150-2 will be described below.

FIG. 4 is a sectional view showing the positional configuration of via portion 141, dummy via portion 143, conductive portion 150-1 and conductive portion 150-2 in wiring board 100. As shown in FIG. As shown in FIG. 4, the distance from the top surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141 is defined as a distance DL1. Similarly, the distance from the upper surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 is defined as a distance DL2. At this time, the distance DL1 and the distance DL2 may be different. Specifically, it is desirable that the distance DL2 is longer than the distance DL1.

In FIG. 4, the top diameter 141W of the via portion 141 and the top diameter 143W of the dummy via portion are preferably 3 μm or more and 30 μm or less, more preferably 5 μm or more and 10 μm or less.

Also, in FIG. 4, the distance between the center line 150-1C of the conductive portion 150-1 and the center line 150-2C of the conductive portion 150-2 provided in the direction perpendicular to the substrate 110 (sometimes referred to as the distance between pitches). A) 150P is preferably 10 μm or more and 100 μm or less, more preferably 20 μm or more and 50 μm or less.

(1-3. Variation in terminal height)
Variation in terminal height will be described below. The distance from the upper surface 110A of the substrate 110 to the uppermost portion 150-1A of the conductive portion 150-1 is defined as a distance UL150-1. Similarly, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 150-2A of the conductive portion 150-2 is defined as the distance UL150-2.

Here, FIG. 36 shows a sectional view of a conventional wiring board 90. As shown in FIG. In FIG. 36, wiring board 90 has the same configuration as wiring board 100 except that it does not have dummy via portion 143 . Since the wiring substrate 90 does not have the dummy via portion 143, the conductive portion 150-2 is provided only on the insulating layer .

In the wiring board 90, it is difficult to make the shape of the conductive portion 150-1 provided in the via portion 141 and the shape of the conductive portion 150-2 without the via portion 141 the same. Therefore, the difference between the distance UL150-1 and the distance UL150-2 was about 1.5 to 3 μm, and the height of the terminal was not stable, resulting in a step. Therefore, in the wiring substrate 90, when the inter-pitch distance 150P becomes small, that is, the pitch becomes narrow (specifically, the inter-pitch distance 150P is 100 μm or less, more specifically 50 μm or less), the terminals of the wiring substrate 90, Poor connection with the terminals of the semiconductor element is likely to occur. In particular, the above-described connection failure is conspicuous when the upper surface of conductive portion 150-1 and the upper surface of conductive portion 150-2 have a convex shape.

On the other hand, in the case of the wiring substrate 100 shown in FIG. 4, the dummy via portion 143 (also referred to as a height adjustment portion) is provided in the portion without the via portion 141, thereby reducing the difference between the distance UL150-1 and the distance UL150-2. can be made smaller. Specifically, in the case of the wiring board 100, the difference between the distance UL150-1 and the distance UL150-2 can be 1 μm or less, more specifically 0.5 μm or less. In other words, by using this embodiment, it is possible to provide a wiring board with less variation in the height of the connection terminals. As a result, poor connection between the terminals of the wiring board and the terminals of the semiconductor element can be suppressed.

(1-4. Manufacturing method of wiring board)
Next, a method for manufacturing the wiring substrate 100 shown in FIGS. 2 to 4 will be described with reference to FIGS. 5 to 12. FIG.

As shown in FIG. 5, a substrate 110 is used. For example, the substrate 110 is a high resistance substrate such as a silicon substrate.

The substrate 110 is not limited to the above, and may be a quartz glass substrate, a soda glass substrate, a borosilicate glass substrate, an alkali-free glass substrate, a sapphire substrate, an alumina carbide (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, A zirconia (ZrO ₂ ) substrate, a resin substrate containing acrylic or polycarbonate, or a laminate of these substrates may be used.

Also, the substrate 110 may be a metal substrate on which an organic insulating layer or an inorganic insulating layer is formed. Also, the substrate 110 may be a through electrode substrate. In this case, a current can flow from the upper surface 110A of the substrate 110 to the opposite side, which is suitable for separately providing the external terminals 105 shown in FIG.

Next, as shown in FIG. 6, the lower wiring 120 is formed on the substrate 110 . The lower wiring 120 is formed using a plating method, a screen printing method, a sputtering method, or a chemical vapor deposition (CVD) method. The lower wiring 120 is appropriately processed into a predetermined shape by photolithography and etching. A lower wiring 120 is provided on the substrate 110 . Copper (Cu) is used for the lower wiring 120 . In addition to copper (Cu), the lower wiring 120 is made of aluminum (Al), gold (Au), silver (Ag), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti), or the like. of metal materials may be used.

Next, as shown in FIG. 7, an insulating layer 130 is formed on the substrate 110 and the lower wiring 120 . The insulating layer 130 is formed using a printing method, a coating method, or a dipping method. Organic resins such as polyimide, acrylic, epoxy, and benzocyclobutene (BCB) may be used for the insulating layer 130 . In addition to the organic resin, the insulating layer 130 may be made of an organic-inorganic hybrid resin containing silica, or may be made of an inorganic film such as silicon oxide or silicon nitride formed by plasma CVD. Also, if the insulating layer 130 is an organic resin, it may contain a photosensitive material. For example, the insulating layer 130 is made of polyimide resin containing a photosensitive material such as diazonaphthoquinone formed by a coating method.

Next, via portions 141 and dummy via portions 143 are formed in the insulating layer 130 as shown in FIG. The via part 141 is formed to overlap the lower wiring 120 . Dummy via portion 143 is formed adjacent to via portion 141 at a predetermined interval. Via portion 141 and dummy via portion 143 are formed using a photolithographic method.

When using photolithography, it is desirable to use a halftone mask. Specifically, when exposing a polyimide resin having a positive photosensitive material (such as diazonaphthoquinone), the portion corresponding to the via portion 141 is exposed in the same manner as usual. On the other hand, the portion corresponding to the dummy via portion 143 is exposed with a lower amount of exposure than the portion corresponding to the via portion 141 due to the semi-transmissive film provided on the halftone mask. Therefore, the distance DL1 from the upper surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141 after development and the distance DL2 from the upper surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 may be different. Specifically, the distance DL2 is longer than the distance DL1 (it can be rephrased that the depth of the dummy via portion 143 is shallower than the depth of the via portion 141). Through the above process, the upper surface of the lower wiring 120 is exposed at the via portion 141 .

Next, the conductive portion 150 is formed. First, a seed layer 147 is formed on the insulating layer 130, the via section 141 and the dummy via section 143, as shown in FIG. The seed layer 147 is formed by an electroless plating method, a sputtering method, a printing method, or the like. The seed layer 147 is made of copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), palladium (Pd), or the like. For example, the seed layer 147 is a copper (Cu) film formed by electroless plating.

Next, as shown in FIG. 10, a resist film 149 is formed on the seed layer 147. Then, as shown in FIG. The resist film 149 may be formed by a coating method, or dry film resist may be used. The resist film 149 is processed into a predetermined shape by photolithography.

Next, as shown in FIG. 11, a conductive portion 150 is formed in the portion where the seed layer 147 is exposed. The conductive portion 150 is formed by electroplating. At this time, the conductive portion 150 - 1 is formed on the insulating layer 130 and the via portion 141 of the conductive portion 150 , and the conductive portion 150 - 2 is formed on the insulating layer 130 and the dummy via portion 143 .

Finally, as shown in FIG. 12, portions of the seed layer 147 where the resist film 149 (see FIG. 11) and the conductive portion 150 are not formed are removed. The above method is called a semi-additive method. The wiring board 100 is manufactured by the above method.

<Second embodiment>
Next, a wiring board having a structure different from that of the wiring board 100 will be described. The descriptions of the structures, materials, and methods that are the same as those of the wiring board 100 shown in the first embodiment are incorporated herein. Moreover, the configurations of the respective wiring substrates can be used in combination as appropriate.

(2-1. Configuration of Wiring Board 100-1)
FIG. 13 shows a top view of wiring board 100-1, and FIG. 14 shows a cross-sectional view of wiring board 100-1 along A1-A2. As shown in FIGS. 13 and 14, wiring board 100-1 includes substrate 110, lower wiring 120, insulating layer 130, via portion 141, dummy via portion 143, conductive portion 150-1 and conductive portion 150-2. It has an upper wiring 160 .

The upper wiring 160 is arranged on the insulating layer 130 . The upper wiring 160 and the conductive portion 150-2 are electrically connected. In the wiring board 100-1, the conductive portion 150-2 can be used as a terminal. Wiring board 100-1 having dummy via portion 143 can have the same effect as wiring board 100 (the difference between the height of conductive portion 150-1 and the height of conductive portion 150-2 is reduced). .

(2-2. Configuration of Wiring Board 100-2)
FIG. 15 shows a top view of wiring board 100-2, and FIG. 16 shows a cross-sectional view of wiring board 100-2 along A1-A2. As shown in FIGS. 15 and 16, wiring substrate 100-2 includes substrate 110, lower wiring 120-2, insulating layer 130, via portion 141, dummy via portion 143, conductive portion 150-1, conductive portion 150-2 and It has an upper wiring 160 .

Lower wiring 120-2 is arranged to extend so as to be electrically connected to left conductive portion 150-1 (conductive portion 150-1L) and right conductive portion 150-1 (conductive portion 150-1R). ing. At this time, the portion 120-2P of the lower wiring 120-2 overlaps and is separated from the conductive portion 150-2. With this structure, the wiring board 100-2 can effectively use the space.

(2-3. Configuration of Wiring Board 100-3)
FIG. 17 shows a top view of the wiring board 100-3, and FIG. 18 shows a cross-sectional view of the wiring board 100-3 along A1-A2. As shown in FIGS. 17 and 18, wiring board 100-3 includes substrate 110, lower wiring 120-3, insulating layer 130, via portion 141, dummy via portion 143, conductive portion 150-1 and conductive portion 150-2. It also has an upper wiring 160-3.

In wiring board 100-3, a plurality of conductive portions 150-2 are arranged around conductive portion 150-1. Specifically, eight conductive portions 150-2 are arranged around one conductive portion 150-1.

Further, the lower wiring 120-3 and the upper wiring 160-3R of the upper wirings 160-3 are arranged in parallel with the insulating layer 130 interposed therebetween.

(2-4. Configuration of Wiring Board 100-4)
FIG. 19 shows a cross-sectional view of the wiring board 100-4. As shown in FIG. 19, wiring substrate 100-4 includes substrate 110, lower wiring 120, insulating layer 130, via portion 141, dummy via portion 143, conductive portion 150-1, conductive portion 150-2, and insulating layer 165. , via portion 171, dummy via portion 173 and conductive portion 180 (conductive portion 180-1 and conductive portion 180-2).

In the wiring substrate 100-4, the via portion 171 is provided in the insulating layer 165 and arranged on the conductive portion 150-1. The dummy via portion 173 is provided in the insulating layer 165 and arranged so as to overlap with the conductive portion 150-2. Conductive portion 180 - 1 is disposed on insulating layer 165 and via portion 171 . Conductive portion 180 - 2 is arranged on insulating layer 165 and dummy via portion 173 .

Insulating layer 165 is formed using the same material and method as insulating layer 130 . The insulating layer 165 is formed flat with respect to the upper surface 110A of the substrate 110 by arranging the conductive portion 150-2. The via portion 171 is formed by a method similar to that of the via portion 141 . The dummy via portion 173 is formed by a method similar to that of the dummy via portion 143 . Conductive portion 180 is formed using the same material and method as conductive portion 150 .

As shown in FIG. 19, in the wiring board 100-5, the conductive portion 150 and the conductive portion 180 are laminated. Here, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 180-1A of the conductive portion 180-1 is defined as the distance UL180-1. Similarly, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 180-2A of the conductive portion 180-2 is defined as a distance UL180-2. At this time, the difference between the distance UL180-1 and the distance UL180-2 can be 1 μm or less. Therefore, the wiring board 100-5 can be mounted with high density like the wiring board 100. FIG.

In wiring board 100-5, conductive portion 180-2 and conductive portion 150-2 may be connected.

(2-5. Configuration of Wiring Board 100-5)
FIG. 20 shows a cross-sectional view of the wiring substrate 100-5. As shown in FIG. 20, wiring substrate 100-5 includes substrate 110, lower wiring 120, insulating layer 130, via portion 141, dummy via portion 143, conductive portion 150-1, conductive portion 150-2, and insulating layer 165. , via portion 171, via portion 175, conductive portion 183 (conductive portion 183-1 and conductive portion 183-2) and conductive portion 185 (conductive portion 185-1 and conductive portion 185-2). The via portion 175 is formed by a method similar to that of the via portion 171 .

Among the conductive portions 183, the conductive portion 183-1 is arranged on the insulating layer 165 and the conductive portion 150-1. Conductive portion 183-1 is connected to conductive portion 150-1. Similarly, of the conductive portions 183, the conductive portion 183-2 is arranged on the insulating layer 165 and the conductive portion 150-2. Conductive portion 183-2 is connected to conductive portion 150-2.

The conductive portion 183 is formed by an electroless plating method. The conductive portion 183 is formed by laminating nickel (Ni), palladium (Pd) and gold (Au) in this order. The conductive portion 183 may be called UBM (Under Bump Metallization).

Among the conductive portions 185, the conductive portion 185-1 is arranged on the conductive portion 183-1. Among the conductive portions 185, the conductive portion 185-2 is arranged on the conductive portion 183-2.

The conductive portion 185 contains tin (Sn). Conductive portion 185 is soldered onto conductive portion 183 . Conductive portions 185 are sometimes referred to as solder bumps.

In the wiring substrate 100-5 shown in FIG. 20, the conductive portion 183 and the conductive portion 185 are laminated in order on the conductive portion 150. As shown in FIG. Here, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 185-1A of the conductive portion 185-1 is defined as the distance UL185-1. Similarly, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 185-2A of the conductive portion 185-2 is defined as the distance UL185-2. At this time, the difference between the distance UL185-1 and the distance UL185-2 can be 1 μm or less. Therefore, even in the wiring substrate 100-5, poor connection can be suppressed, and high-density mounting can be achieved.

Although an example in which the conductive portions 183 and 185 are laminated in the wiring substrate 100-5 is shown, only one of the conductive portions 183 and 185 may be arranged.

<Third Embodiment>
A multilayer wiring board, which is one of wiring boards having a structure different from those of the first and second embodiments, will be described below with reference to the drawings. FIG. 21 is a schematic cross-sectional view showing a multilayer wiring board according to the third embodiment. A schematic configuration of a multilayer wiring board 200 according to the third embodiment will be described. The multilayer wiring board 200 includes a multilayer wiring layer 200A formed by laminating a first wiring layer WL1 and a second wiring layer WL2 in this order on an upper surface 210H of a substrate 210. FIG. In the multilayer wiring layer 200A, an insulating layer 221 is positioned between the first wiring layer WL1 and the second wiring layer WL2, and an insulating layer 222 is positioned on the second wiring layer WL2. An electrode 241 (also referred to as a first electrode) and an electrode 242 (also referred to as a second electrode) are provided on an insulating layer 222 serving as a surface layer of the multilayer wiring layer 200A. Electrode 242 is positioned adjacent to electrode 241 .

The first wiring layer WL1 is composed of a conductor pattern 211, and the second wiring layer WL2 is composed of a conductor pattern 212 (also referred to as a first conductive portion) and a conductor pattern 213. FIG. The conductor pattern 211 is positioned on the top surface 210H of the substrate 210 together with a height adjustment pattern 250 (also referred to as a height adjustment portion), which will be described later. They are positioned at a predetermined distance from each other in the in-plane direction of 210H. The conductor pattern 212 and the conductor pattern 213 are positioned at a predetermined distance from each other in the in-plane direction on the insulating layer 221 . A via 231 is provided as an interlayer connection on the conductor pattern 211 . Also, the electrode 241 is continuously positioned on the upper surface of the conductor pattern 212 , and the electrode 242 is continuously positioned on the upper surface of the conductor pattern 213 . Each of these configurations will be described in detail below. The conductor patterns 211, 212, and 213 are also referred to as conductive portions. A conductor pattern, which will be described later, can also be a conductive portion. Furthermore, the conductor pattern 212 is also called a first conductive portion, and the conductive pattern 213 is also called a second conductive portion.

The “substrate” in the third embodiment is not an abbreviation for electronic circuit board, but means a board that serves as a base for manufacturing the multilayer wiring board 200 . That is, the substrate 210 may not be an essential component in the multilayer wiring board 200 as long as the wiring layer and the insulating layer can be laminated in order to form the wiring board. The type of the substrate 210 is not particularly limited, and examples thereof include glass epoxy substrates, glass substrates, silicon substrates, and the like. The size, thickness, and the like of the substrate 210 can be appropriately set according to the desired size of the multilayer wiring board 200, the size and number of electronic components mounted on the multilayer wiring board 200, and the like. Electronic components that can be mounted on the multilayer wiring board 200 in the third embodiment include, for example, active elements such as relays, transistors, and integrated circuits (ICs), as well as passive elements such as resistors, capacitors, and inductors. etc. Further, in the third embodiment, a multilayer wiring board on which one or more of the electronic components exemplified above are mounted is referred to as a "component-mounted wiring board".

The conductor pattern 211 and the conductor pattern 212 are made of a conductive material such as copper (Cu), nickel (Ni), gold (Au), or the like. In the third embodiment, the conductor pattern 211 and the conductor pattern 212 are connected to each other through the via 231, and the electrode 241 is continuous on the upper surface of the conductor pattern 212, so that the conductor pattern 211, the conductor pattern 212, and electrodes 241 can be electrically connected to each other (FIG. 21).

Like the conductor patterns 211 and 212, the conductor pattern 213 is also made of a conductive material such as copper (Cu), nickel (Ni), or gold (Au). In the third embodiment, the conductive pattern 212 and the electrode 242 can be electrically connected to each other because the electrode 242 is continuous on the upper surface of the conductive pattern 213 (FIG. 21). The width, thickness, etc. of the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213 are appropriately set according to the size of the multilayer wiring board 200, the size and number of electronic components mounted on the multilayer wiring board 200, and the like. obtain.

The insulating layer 221 and the insulating layer 222 are made of an insulating material such as epoxy resin, polyimide resin, acrylic resin, or the like. The insulating layer 221 is positioned on the upper surface 210H of the substrate 210 so as to cover the conductor pattern 211 and the height adjustment portion 50, and the insulating layer 222 is positioned on the upper surface of the insulating layer 221 so as to cover the conductor pattern 212 and the conductor pattern 213. located in The thickness of the insulating layer 221 and the insulating layer 222 can be appropriately set according to the desired size of the multilayer wiring board 200, the size and number of each conductor pattern, and the like.

The vias 231 are made of a conductive material such as copper (Cu), nickel (Ni), gold (Au), like the conductor patterns 211-213. Although the dimensions and depth (height) of the via 231 are not particularly limited, the size of the desired multilayer wiring board 200, the size and number of each conductor pattern 211 to 213, the thickness of each insulating layer, etc. can be set appropriately according to

The electrodes 241 and 242 are made of metal materials such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), and lead-tin alloys. The electrodes 241 and 242 can be electrically connected to external terminals of electronic components such as semiconductor chips mounted on the multilayer wiring board 200 . The dimensions and thicknesses of the electrodes 241 and 242, and the shapes and heights of the electrodes 241 and 242 protruding from the upper surface of the insulating layer 222 may be changed as long as the electronic components can be stably mounted on the multilayer wiring board 200. 21 is not intended to be limiting. A portion of the electrode 241 that protrudes above the insulating layer 222 is called a first protrusion, and a portion of the electrode 242 that protrudes above the insulating layer 222 is called a second protrusion. Although not shown, UBM (Under Bump Metallization) may be provided between the electrodes 241 and 242 and the conductor patterns 212 and 213 .

The height adjustment pattern 250 is provided within the insulating layer 221 in the in-plane direction of the upper surface 210H of the substrate 210 and is positioned at a predetermined distance from the conductor pattern 211 . A “height adjustment pattern (also referred to as a height adjustment portion)” means a conductor pattern (in the third embodiment, a conductor pattern 212 and a conductor It means a pattern for adjusting the height position in the stacking direction of the pattern 213). Further, the “adjustment” here includes the adjustment of the electrodes (the electrodes 241 and 242 in the third embodiment) on which the electronic components are mounted, as long as the electronic components can be stably mounted on the multilayer wiring board 200. It includes the meaning of adjusting the height of the conductor pattern located directly under the electrode so that the height positions are substantially the same. In the third embodiment, the height adjusting pattern 250 is positioned directly below the conductor pattern 213 (electrode 242) in the stacking direction so as to correspond to the formation position of the conductor pattern 213 (electrode 242). Also, the height adjustment pattern 250 has a thickness substantially the same as the thickness of the conductor pattern 211 . In the third embodiment, the height adjustment pattern 250 is positioned immediately below the conductor pattern 213 in the lamination direction and at the same height (layer) as the conductor pattern 211 (first wiring layer WL1) in the lamination direction. As a result, the height positions in the stacking direction of the conductor pattern 212 and the conductor pattern 213 provided on the insulating layer 221 having a substantially flat upper surface are substantially the same. The material forming the height adjustment pattern 250 may be, for example, a non-conductive material such as a photosensitive resin material, or a conductive material such as copper (Cu), nickel (Ni), or gold (Au). There may be. When the height adjustment pattern 250 in the third embodiment is made of a conductive material, from the viewpoint of preventing short circuits with other conductor patterns, the height adjustment pattern 250 between the conductor patterns 211, 212, and 213 are preferably electrically isolated by The material of the height adjustment pattern 250 is not particularly limited unless otherwise specified in this specification.

FIG. 37 is a reference diagram showing a multilayer wiring board 200′ in which height differences in the stacking direction appear in the insulating layer 222′, which is the surface layer, due to the absence of the height adjustment pattern 250. FIG. . In FIG. 37, the "difference D" is exaggerated for easy understanding, but it is not drawn as an actual difference. With reference to FIG. 37, based on a comparison with a multilayer wiring board in which the height adjusting pattern 250 is not provided, the effect of the height adjusting pattern 250 in the third embodiment will be described in detail.

In the multilayer wiring board 200' shown in FIG. 37, the conductor pattern 211 is provided on the upper surface 210H of the substrate 210 at the portion directly below the electrode 241 in the stacking direction. is not provided with the conductor pattern 211 . Therefore, in the process of forming the multilayer wiring board 200 ′, when the insulating layer 221 ′ is provided so as to cover the conductor pattern 211 , the height of the insulating layer 221 ′ covering the conductor pattern 211 immediately below the electrode 241 in the stacking direction is The position is higher by the thickness of the conductor pattern 211 than the height position of the insulating layer 221 ′ portion directly under the electrode 242 in the stacking direction.

When the conductor pattern 212 connected to the conductor pattern 211 through the via 231 is provided on the insulating layer 221′ in this state, and the conductor pattern 213 is provided on the insulating layer 221′ immediately below the electrode 242 in the stacking direction, the conductor A height position difference D in the stacking direction appears between the pattern 212 and the conductor pattern 213 (FIG. 37). Therefore, a height position difference also appears between the electrode 241 provided on the upper surface of the conductive pattern 212 and the electrode 242 provided on the upper surface of the conductive pattern 213 . In that case, it becomes difficult to stably mount an electronic component through both electrodes having a difference in height position.

On the other hand, according to the multilayer wiring board 200 of the third embodiment, as described above, the height adjustment pattern 250 is provided at the same height position as the conductor pattern 211 immediately below the electrodes 242 in the stacking direction. The upper surface of the insulating layer 221 provided on the upper layer can be made substantially flat, and the height positions of the two conductor patterns 212 and 213 formed on the insulating layer 221 can be substantially matched (FIG. 21). Therefore, the height positions of the electrodes 241 and 242 on which electronic components can be mounted (specifically, the height from the top surface of the substrate 210 to the top surface of the electrode 241 and the height from the top surface of the substrate 210 to the top surface of the electrode 242) ) also substantially match, and it is possible to realize a high-quality multilayer wiring board 200 on which electronic components can be stably mounted. It is preferable that the height adjusting pattern 250 is provided so that the height position difference between the conductor patterns 212 and 213 is, for example, within the range of 0 μm to 3 μm, preferably 1.5 μm or less. By adjusting the height position difference within the above range, the electronic component can be mounted substantially parallel to the surface layer of the multilayer wiring board 200 . If the height position difference exceeds 3 μm, there is a risk that a connection failure between the electronic component and the multilayer wiring board 200 is likely to occur when the electronic component is mounted on the multilayer wiring board 200 .

<Fourth Embodiment>
FIG. 22 is a schematic cross-sectional view showing a multilayer wiring board according to the fourth embodiment. In addition, the same code|symbol is attached|subjected about the substantially same structure as 3rd Embodiment, and the detailed description is abbreviate|omitted. A multilayer wiring board 200 in the fourth embodiment includes a multilayer wiring layer 200A in which three layers of first to third wiring layers WL1 to WL3 are laminated, and conductor patterns 213 (electrodes 242 ) in the stacking direction, and a height adjusting pattern 250 is provided directly under the height adjusting pattern 251 in the stacking direction. That is, in the multilayer wiring board 200 according to the fourth embodiment, the second wiring layer WL2 is provided between the first wiring layer WL1 and the third wiring layer WL3. consists of An insulating layer 223 is located between the second wiring layer WL2 and the third wiring layer WL3.

The conductor pattern 214 is positioned on the insulating layer 221 together with the height adjusting pattern 251, and the conductor pattern 214 and the height adjusting pattern 251 are positioned on the insulating layer 221 with a predetermined distance therebetween in the in-plane direction. there is A via 232 is provided as an interlayer connection on the conductor pattern 214 . The height adjusting pattern 251 has substantially the same thickness as the conductor pattern 214 and has substantially the same configuration as the height adjusting pattern 250 .

The conductor pattern 214, like the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213, is made of a conductive material such as copper (Cu), nickel (Ni), and gold (Au). In the fourth embodiment, the conductor pattern 211 and the conductor pattern 214 are connected through the via 231, the conductor pattern 214 and the conductor pattern 212 are connected through the via 232, and the electrode 241 is continuously formed on the conductor pattern 212. By doing so, the conductor pattern 211, the conductor pattern 214, the conductor pattern 212, and the electrode 241 can be electrically connected to each other (FIG. 22).

The insulating layer 223 can be made of an insulating material such as epoxy resin, polyimide resin, or acrylic resin, like the insulating layers 221 and 222 . The thickness of the insulating layer 223 is within a range that does not cause a short circuit between adjacent wiring layers (the first wiring layer WL1 and the second wiring layer WL2, the second wiring layer WL2 and the third wiring layer WL3) in the stacking direction. It can be set as appropriate.

The vias 232, like the vias 231, are made of a conductive material such as copper (Cu), nickel (Ni), gold (Au), or the like. The size (e.g., width and depth) of the via 232 is not particularly limited, but depends on the desired size of the multilayer wiring board 200, the size and pitch of each conductor pattern, the thickness of each insulating layer, and the like. It can be set as appropriate.

The height adjusting pattern 251 is positioned at a predetermined distance from the conductor pattern 214 in the in-plane direction on the insulating layer 221 . In the fourth embodiment, the conductor pattern 213 (electrode 242 ) is positioned above the height adjusting pattern 251 and the height adjusting pattern 250 is positioned below the height adjusting pattern 251 . Also, the height adjustment pattern 251 has substantially the same thickness as the conductor pattern 214 . In the fourth embodiment, the height adjustment pattern 250 is positioned at the same height (hierarchy) as the conductor pattern 211 (first wiring layer WL1) immediately below the conductor pattern 213 (electrode 242) in the stacking direction. By locating the height adjustment pattern 251 at the same height as the conductor pattern 214 (second wiring layer WL2), the upper surface of the insulating layer 223 provided thereabove becomes substantially flat. The height positions in the stacking direction of the conductor pattern 212 and the conductor pattern 213 (the third wiring layer WL3) can be substantially matched.

In the fourth embodiment, the multilayer wiring board 200 including the multilayer wiring layer 200A in which three wiring layers are laminated has been described, but the present disclosure is not limited to this, and four or more wiring layers are provided. It may be a multilayer wiring board provided with a multilayer wiring layer formed by laminating.

<Fifth Embodiment>
FIG. 23 is a schematic cross-sectional view showing a multilayer wiring board according to the fifth embodiment. In addition, the same code|symbol is attached|subjected about the substantially same structure as 3rd Embodiment, and the detailed description is abbreviate|omitted. The multilayer wiring board 200 according to the fifth embodiment differs from the multilayer wiring board 200 according to the third embodiment in that the height adjustment pattern 250 is electrically connected to the conductor pattern 213 through the via 233. . That is, in the fifth embodiment, the height adjustment pattern 250 is made of a conductive material such as copper (Cu), nickel (Ni), gold (Au), or the like. It goes without saying that the vias 233 are made of a conductive material such as copper (Cu), nickel (Ni), gold (Au), etc., like the vias 231 .

According to the above configuration, the upper surface of the insulating layer 221 is substantially flat as in the third embodiment. In addition, the height adjustment pattern 250 can be used as part of the conductor pattern that is electrically connected to the conductor pattern 213 (electrode 242).

<Sixth embodiment>
FIG. 24 is a schematic cross-sectional view showing a multilayer wiring board according to the sixth embodiment. In addition, the same code|symbol is attached|subjected about the substantially same structure as 3rd Embodiment, and the detailed description is abbreviate|omitted. In the fourth embodiment, the conductor pattern 211 is positioned not only directly under the conductor pattern 212 (electrode 241) in the stacking direction, but also directly under the conductor pattern 213 (electrode 242) in the stacking direction. 3 differs from the multilayer wiring board 200 and the like of the third embodiment in that it is configured with a width that is horizontally long in the left-right direction on the drawing. That is, in the multilayer wiring board 200 according to the sixth embodiment, the conductor pattern 211 also serves as a height adjusting pattern. In the sixth embodiment, when the conductor pattern 211 of the first wiring layer WL1 is arranged according to the normal wiring rule, the conductor pattern 211 is arranged immediately below the electrode 241 in the stacking direction, but the conductor pattern 211 is arranged directly below the electrode 242 in the stacking direction. , the conductor pattern 211 may not be arranged. In such a case, the height adjustment pattern 250 is provided in the third embodiment, so that the height positions of the conductor patterns 212 and 213 (electrodes 241 and 242) are substantially matched. In the sixth embodiment, instead of the height adjustment pattern 250 of the third embodiment, the conductor pattern 211, which is not arranged according to the normal wiring rule, is routed below the electrodes 242 in the stacking direction. Since the upper surface of the insulating layer 221 is substantially flat as in the form, the height positions in the stacking direction of the conductive pattern 212 (electrode 241) and the conductive pattern 213 (electrode 242) provided on the insulating layer 221 should be substantially matched. can be done.

<Seventh embodiment>
FIG. 25 is a schematic cross-sectional view showing a multilayer wiring board 200 according to the seventh embodiment. Note that the same reference numerals are given to the same configurations as those of the multilayer wiring board 200 in each of the above-described embodiments, and detailed description thereof will be omitted. In the seventh embodiment, on the upper surface 210H of the substrate 210, the conductor pattern 211 is provided in the area below the electrode 241 in the stacking direction, and the height adjustment pattern 250 is provided in the area below the electrode 242 in the stacking direction. However, neither the conductor pattern 211 nor the height adjustment pattern 250 is provided in the area below the portion sandwiched between the electrodes 241 and 242 in the stacking direction (see FIG. 25). Therefore, when the insulating layer 221 covering the conductor pattern 211 and the height adjusting pattern 250 is provided, the upper surface 210H portion of the substrate 210 is covered in the region below the portion sandwiched between the electrodes 241 and 242 in the stacking direction. The height position of the covering insulating layer 221 portion is lower than the insulating layer 221 portion covering each of the conductor pattern 211 and the height adjusting pattern 250 . Conductive pattern 217 is provided in the lower portion of insulating layer 221, and the height position of insulating layer 223 covering conductive pattern 217 is the insulating layer covering the portions provided with conductive patterns 214 and 215, respectively. It is lower than the height position of 223. That is, the height positions of the conductor patterns 214 and 215 and the height position of the conductor pattern 217 are shifted in the second wiring layer WL2. A conductive pattern 218 is provided through a via 232C in the portion of the insulating layer 223 that is lowered. Therefore, the height position of the insulating layer 222 portion covering the conductor pattern 218 is lower than the height position of the insulating layer 222 portion covering the conductor pattern 212 and the conductor pattern 213, respectively. It appears as a concave portion 222C.

In the multilayer wiring board 200 according to the seventh embodiment, the concave portion 222C appears in the center of the surface of the multilayer wiring layer 200A in the in-plane direction, but the height positions of the electrodes 241 and 242 on which the electronic components are mounted are substantially the same. I am doing it. Therefore, the electronic component 270 can be stably mounted on the multilayer wiring board 200 via the electrodes 241 and 242 . That is, as in the multilayer wiring board 200 in the seventh embodiment, the uppermost wiring layer (shown in FIG. 25) is used as long as it does not affect the stable mounting of the electronic component 270 such as the recess 222C. In the embodiment, the height position of the portion not connected to the electrode (conductor pattern 218 shown in FIG. 25) among the conductor patterns constituting the third wiring layer WL3) corresponds to the height position of the portion connected to the electrode (shown in FIG. 25). It may be lower than the height position of the conductor patterns 212, 213), and the height positions of the electrodes on which the electronic component 270 can be mounted should be approximately the same.

<Eighth embodiment>
FIG. 26 is a schematic cross-sectional view showing a multilayer wiring board 200 according to the eighth embodiment. In addition, the same code|symbol is attached|subjected about the structure similar to each embodiment mentioned above, and the detailed description is abbreviate|omitted. A multilayer wiring board 200 according to the eighth embodiment is provided with through-hole vias 210TH penetrating in the thickness direction of the substrate 210, a multilayer wiring layer 200A is provided on an upper surface 210H of the substrate 210, and a multilayer wiring layer is provided on a lower surface 210L of the substrate 210. It has a structure provided with a layer 200B. The through-hole via 210TH is made of a conductive material such as copper (Cu), nickel (Ni), gold (Au), or the like. The through-hole via 210TH functions as a conductor that electrically connects the conductor pattern 211 of the multilayer wiring layer 200A and the conductor pattern 261 of the multilayer wiring layer 200B. The multilayer wiring layer 200A has the same configuration as the multilayer wiring layer in the multilayer wiring board 200 in the third embodiment. As the multilayer wiring layer 200B in the eighth embodiment, a laminated structure in which the multilayer wiring layer 200A is inverted with respect to the substrate 210 is adopted. The structure is not limited, and various laminated structures can be set as appropriate.

The multilayer wiring layer 200B is formed by stacking a first wiring layer WL200B composed of a conductor pattern 261 and a second wiring layer WL2B composed of conductor patterns 262 and 263 in this order from the lower surface 210L side of the substrate 210. An insulating layer 271 is positioned between the layer WL200B and the second wiring layer WL2B, and an insulating layer 272 is positioned to cover the second wiring layer WL2B. Electrodes 281 and 282 are provided on the surface layer of the multilayer wiring layer 200B. The first wiring layer WL200B is composed of a conductor pattern 261, and the conductor pattern 261 is positioned on the lower surface 210L of the substrate 210 together with the height adjustment pattern 252. As shown in FIG. The conductor pattern 261 and the height adjustment pattern 252 are positioned with a predetermined distance therebetween in the in-plane direction on the lower surface 210L of the substrate 210 . The second wiring layer WL2B is composed of a conductor pattern 262 and a conductor pattern 263, and a via 34 is provided between the conductor pattern 261 and the conductor pattern 262 as an interlayer connecting portion for electrically connecting them. Electrode 281 is positioned on the upper surface of conductive pattern 262 , and electrode 282 is positioned continuously on the upper surface of conductive pattern 263 . The height adjusting pattern 252 has substantially the same thickness as the conductor pattern 261 and has substantially the same configuration as the height adjusting pattern 250 . Also in the eighth embodiment, the height adjustment pattern 252 is positioned at substantially the same height (layer) as the conductor pattern 261 (first wiring layer WL200B), and the conductor pattern 263 (electrode 282) is laminated in the direction of lamination. Since the lower surface of the insulating layer 271 is substantially flat by being positioned directly below, the height positions of the conductive pattern 262 (electrode 281) and the conductive pattern 263 (electrode 282) provided on the insulating layer 271 are substantially matched. will do.

[Manufacturing method of multilayer wiring board]
FIG. 27 is a process diagram showing a method for manufacturing a multilayer wiring board according to an embodiment of the present disclosure, and FIG. 28 is a process diagram showing a process following the manufacturing process of FIG. A method for manufacturing the multilayer wiring board 200 according to the third embodiment will be described below as an example.

First, a substrate mainly made of glass epoxy having a desired thickness and size is prepared as the substrate 210, and the conductor pattern 211 and the height adjustment pattern 250 are formed on the upper surface 210H of the substrate 210 (FIG. 27). (A)). Examples of the method of forming the conductor pattern 211 include a method of forming a conductive layer on the upper surface 210H of the substrate 210, forming a resist pattern on this conductive layer, and then etching using this resist pattern as a mask. Methods for forming a conductive layer on the upper surface 210H of the substrate 210 include, for example, a vacuum film formation method such as a sputtering method, a plating method (electroless plating method), and electrolysis via a seed layer formed on the upper surface 210H of the substrate 210. plating method, etc.). A resist pattern can be formed by exposing and developing a dry film resist or a liquid resist. The height adjusting pattern 250 may be formed in a predetermined region (the region where the height adjusting pattern 250 is to be formed) on the upper surface 210H of the substrate 210 after the conductive pattern 211 is formed. may be formed prior to If the height adjusting pattern 250 is made of a conductive material, the height adjusting pattern 250 may be formed at the same time as the conductive pattern 211 is formed. As a method for forming the height adjustment pattern 250 made of a non-conductive material such as a photosensitive resin material, for example, a photosensitive resin layer is formed by a spin coating method or the like, and the photosensitive resin layer is exposed to light. A method of performing development and the like can be mentioned. The substrate 210 is not limited to the above-described substrate mainly made of glass epoxy, and substrates mainly made of glass, silicon, or the like can be suitably used.

Next, an insulating layer 221 is formed so as to cover the conductor pattern 211 and the height adjusting pattern 250 (FIG. 27(B)). This insulating layer 221 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by spin coating, dip coating, spray coating, bar coating, or the like, dried, and cured by heating. In this embodiment, the height position of the insulating layer 221 on the conductor pattern 211 and the height position of the insulating layer 221 on the height adjusting pattern 250 substantially match. As the resin material forming the insulating layer 221, in addition to epoxy resin, polyimide resin, acrylic resin, or the like is used. Further, the insulating layer 221 may have a single-layer structure or a laminated structure of two or more layers.

Next, a through hole 231' is formed through the insulating layer 221 in the thickness direction so that a portion of the upper surface of the conductive pattern 211 is exposed (FIG. 27(C)). The through holes 231 ′ can be formed by, for example, forming a desired resist pattern on the insulating layer 221 and etching with a desired etchant using this resist pattern as a mask.

Next, conductive patterns 212 and 213 are formed on the insulating layer 221 while filling the through holes 31' with a conductive material to form vias 231 (FIG. 27(D)). The via 231, the conductor pattern 212 and the conductor pattern 213 can be formed in the same manner as the conductor pattern 211 described above. Copper (Cu), nickel (Ni), gold (Au), and other alloys containing these are preferably used to form the vias 231 , the conductor patterns 212 , and the conductor patterns 213 .

After that, an insulating layer 222 is formed so as to cover the conductor pattern 212 and the conductor pattern 213 (FIG. 28(A)). The insulating layer 222 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating, or bar coating, dried, and cured by heating. As the resin material forming the insulating layer 222, the same resin material as that forming the insulating layer 221 may be used, or a different kind of resin material may be used.

Next, a through hole 241′ is formed through the insulating layer 222 in the thickness direction so that a portion of the upper surface of the conductor pattern 212 is exposed, and a portion of the upper surface of the conductor pattern 213 is exposed. A through-hole 242' is formed through the insulating layer 222 in the thickness direction (FIG. 28(B)). The through hole 241' and the through hole 242' can be formed by substantially the same method as the above-described forming method of the through hole 231'.

Next, the through holes 241' are filled with a conductive material to form electrodes 241, and the through holes 242' are filled with a conductive material to form electrodes 242 (FIG. 28C). The electrode 241 and the electrode 242 use the material (for example, copper (Cu), nickel (Ni), gold (Au), lead-tin alloy, etc.) constituting the electrodes 241 and 42, and are formed in the same manner as the conductor patterns 211 to 213. can be formed. Through the above steps, the multilayer wiring board 200 in which the height positions of the conductor pattern 212 (electrode 241) and the height position of the conductor pattern 213 (electrode 242) are substantially the same can be manufactured.

<Ninth Embodiment>
In this embodiment, a semiconductor device including elements other than the light emitting element described in the first embodiment will be described.

29 is a cross-sectional view of the semiconductor device 500. FIG. As shown in FIG. 29, a semiconductor device 500 has a chipped semiconductor element 600 including a transistor, a high frequency element 620 , an interposer 700 and a package substrate 800 . The semiconductor element 600 has a function as a central processing unit (CPU) or a memory device. A high-frequency element is a passive element corresponding to high frequencies, and includes an inductor, a capacitive element, a resistive element, and the like. The interposer 700 has a function of relaying between the package substrate 800 and the semiconductor element 600 and the high frequency element 620 . Semiconductor element 600 and high-frequency element 620 are electrically connected to interposer 700 using terminals 650 . Also, the space between the semiconductor element 600 and the high frequency element 620 may be sealed with a mold resin. Also, the interposer 700 and the package substrate 800 are connected using terminals 750 . Also, the gap between the interposer 700 and the package substrate 800 may be sealed using an underfill resin. The wiring board 100 can be used for the interposer 700 and the package board 800 .

<Tenth Embodiment>
In this embodiment, an example in which the wiring board 100 described in the first to eighth embodiments is applied to an electric device will be described.

30 and 31 are diagrams for explaining electrical equipment. Semiconductor devices including the wiring board 100 are, for example, mobile terminals (mobile phones, smart phones, notebook personal computers, game machines, etc.), information processing devices (desktop personal computers, servers, car navigation systems, etc.), and household electric appliances. (microwave ovens, air conditioners, washing machines, refrigerators), automobiles, and various other electric appliances.

FIG. 30 is a tiling LED 2000. FIG. The light-emitting devices 1000 are arranged in a grid pattern on the tiling LEDs 2000 , and the light-emitting devices 1000 are mounted on the wiring board 100 . By using the wiring substrate 100 described in the first to eighth embodiments, it is possible to suppress the directional variation of the light emitting surface of the LED element, and the effect of making the joints of the tiling less visible, resulting in a device with good display performance. can be provided.

FIG. 31A shows a smartphone 4000. FIG. FIG. 31B shows a portable game machine 5000. FIG. FIG. 31C shows a notebook personal computer 6000. FIG.

The use of the wiring board 100 in these electrical devices enables high-density mounting. Therefore, it becomes possible to reduce the size and improve the performance of the electrical equipment.

The embodiments described above are described to facilitate understanding of the present disclosure, and are not described to limit the present disclosure. Therefore, each element disclosed in the above embodiments is intended to include all design changes and equivalents that fall within the technical scope of the present disclosure.

(Modification 1)
The first embodiment of the present disclosure shows an example in which the distance DL2 from the top surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 is longer than the distance DL1 from the top surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141. However, it is not limited to this. FIG. 32 is a cross-sectional view of the wiring board 100-6. As shown in FIG. 32, even if the distance DL2 is shorter than the distance DL1 in the wiring board 100-6, the same effect as in the wiring board 100 can be obtained.

(Modification 2)
In the first embodiment of the present disclosure, an example in which the upper surface of conductive portion 150-1 and the upper surface of conductive portion 150-2 have a convex shape is shown, but the present invention is not limited to this. FIG. 25 is a cross-sectional view of the wiring board 100-7. As shown in FIG. 33, wiring substrate 100-7 may have concave portions on the upper surface of conductive portion 150-1 and the upper surface of conductive portion 150-2. The wiring board 100-7 can also have the same effects as the wiring board 100. FIG.

(Modification 3)
In the first embodiment of the present disclosure, an example in which the conductive portion 150-2 is not connected to the lower wiring 120 is shown, but the conductive portion 150-2 may be connected to a conductive portion different from the lower wiring 120. FIG. FIG. 34 shows a top view of the wiring board 100-8, and FIG. 27 shows a cross-sectional view of the wiring board 100-8 along A1-A2. As shown in FIGS. 34 and 35, wiring board 100-8 includes substrate 110, lower wiring 120, insulating layer 130, via portion 141, dummy via portion 143, conductive portion 150-1, conductive portion 150-2, and upper wiring. In addition to 160, it has a conductive portion 122. FIG.

The conductive portion 122 is arranged on the substrate 110 in the same manner as the lower wiring 120 . Also, the conductive portion 122 is arranged so as to overlap with the dummy via portion 143 and the conductive portion 150-2. At this time, distance DL1 from top surface 110A of substrate 110 to bottom portion 141D of via portion 141 and distance DL2 from top surface 110A of substrate 110 to bottom portion 143D of dummy via portion 143 may be equal. In the above, the conductive portion 122 and the conductive portion 150-2 are connected. Note that the conductive portion 122 does not have to function as an electrode. At this time, the region 150-2F provided in the dummy via portion 143 and the conductive portion 122 of the conductive portion 150-2 may not be components of the electric circuit. On the other hand, the region 150-2F above the region 150-2F in the conductive portion 150-2 is connected to the upper wiring 160. As shown in FIG. At this time, the region 150-2U and the upper wiring 160 may form part of an electric circuit.

By having the above structure, the shapes of via portion 141, dummy via portion 143, conductive portion 150-1, and conductive portion 150-2 are stabilized, and variations in height of terminals can be reduced as in wiring substrate 100. .

(Modification 4)
In the first embodiment of the present disclosure, the example in which the via section 141 and the dummy via section 143 are formed by photolithography has been described, but the present invention is not limited to this. Via portion 141 and dummy via portion 143 may be formed by a laser irradiation method.

When laser irradiation is performed, an excimer laser, a neodymium:Yag laser (Nd:YAG) laser, a femtosecond laser, or the like is used as the laser. When an excimer laser is used, light in the ultraviolet region is irradiated. For example, when using xenon chloride in an excimer laser, light with a wavelength of 308 nm is irradiated. Note that the hole diameters of the via portion 141 and the dummy via portion 143 are controlled by the laser irradiation diameter. At this time, the irradiation diameter of the laser may be 5 μm or more and less than 30 μm.

In the above, the laser output condition for forming the dummy via portion 143 may be lower than the laser output condition for forming the via portion 141 .

Note that when the insulating layer 130 is an inorganic insulating layer, a reactive ion etching method, a wet etching method, or a combination of a laser irradiation method and a wet etching method may be used. As an etchant for the wet etching method, any one of hydrofluoric acid (HF), nitric acid (HNO ₃ ), and an alkaline solution may be used.

(Modification 5)
As shown in FIGS. 21 to 26, in the multilayer wiring board 200 according to each of the above-described embodiments, a mode is depicted in which the height adjustment pattern is provided substantially immediately below the conductor pattern positioned on the surface layer in the lamination direction. However, it is not limited to this mode. For example, as long as the height positions of the conductor patterns positioned on the surface layer can be approximately matched, the height adjustment pattern may be positioned below at least a portion of the conductor patterns positioned on the surface layer in the stacking direction. That is, even if the height adjustment pattern is not directly below the conductor pattern located on the surface layer in the lamination direction, the height adjustment pattern is located at a position shifted in the in-plane direction (horizontal direction in the drawing) of the predetermined layer from the position directly below the lamination direction. may be located.

(Modification 6)
In the above embodiments, a multilayer wiring board having two or three wiring layers was described as an example, but the present invention is not limited to this aspect, and a board having four or more wiring layers may be used. good.

90... Wiring board, 100... Wiring board, 105... External terminal, 110... Substrate, 120... Lower wiring, 122... Conductive part, 130... Insulating layer, 141. Via portion 143 Dummy via portion 147 Seed layer 149 Resist film 150 Conductive portion 160 Upper wiring 165 Insulating layer 171 Via portion 173 Dummy via portion 180 Conductive portion 183 Conductive portion 185 Conductive portion 200 Multilayer wiring board 210 Substrate 211, 212, 213, 214, 215, 216, 217, 218, 261, 262, 263... conductor pattern, 221, 222, 223... insulating layer, 231, 232, 233... via (interlayer connection), 241 , 242, 281, 282... electrodes, 250, 251, 252... pattern for height adjustment, 300... light emitting element, 310... terminal, 320... reflector, 330... sealing 340...Lens 350...Protective member 500...Semiconductor device 600...Semiconductor element 620...High frequency element 650...Terminal 670...Semiconductor element 700...Interposer 750...Terminal 800...Package substrate 1000...Light emitting device 2000...Tiling LED 4000...Smartphone 5000...Portable game machine 6000・・・Laptop personal computer

Claims (10)

a substrate;
an insulating layer on the substrate;
a height adjuster provided in the insulating layer;
a first conductive portion provided on the insulating layer;
a second conductive portion adjacent to the first conductive portion and provided on the insulating layer and the height adjustment portion;
a lower wiring provided between the substrate and the insulating layer;
a via portion provided in the insulating layer and arranged on the lower wiring;
a third conductive portion provided between the substrate and the insulating layer and overlapping the second conductive portion and not forming part of an electric circuit;
including
the height adjustment portion is a dummy via portion provided in the insulating layer adjacent to the via portion;
the height from the top surface of the substrate to the top surface of the first conductive portion and the height from the top surface of the substrate to the top surface of the second conductive portion are substantially the same;
The first conductive portion is arranged on the insulating layer and the via portion, and is electrically connected to the lower wiring.
The second conductive portion is electrically connected to the third conductive portion,
wiring board. In a cross-sectional view, the difference between the height from the top surface of the substrate to the top of the first conductive portion and the height from the top surface of the substrate to the top of the second conductive portion is 1 μm or less.
The wiring board according to claim 1 . In a cross-sectional view, the distance between the center line of the first conductive portion and the center line of the second conductive portion is 10 μm or more and 100 μm or less.
The wiring board according to claim 1 . In a cross-sectional view, the distance between the center line of the first conductive portion and the center line of the second conductive portion is 20 μm or more and 50 μm or less.
The wiring board according to claim 1 . An upper diameter of the via portion and an upper diameter of the dummy via portion are 3 μm or more and 30 μm or less.
The wiring board according to claim 1 . An upper diameter of the via portion and an upper diameter of the dummy via portion are 5 μm or more and 10 μm or less.
The wiring board according to claim 1 . The upper surface of the first conductive portion and the upper surface of the second conductive portion are curved,
The wiring board according to claim 1 . further comprising an upper wiring disposed on the insulating layer;
The upper wiring and the second conductive part are electrically connected,
The wiring board according to claim 1 . A wiring board according to any one of claims 1 to 8 ;
A semiconductor device, comprising: a semiconductor element; The semiconductor device is a light-emitting device,
10. The semiconductor device according to claim 9 .

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