JP3295059B2 - Semiconductor device and semiconductor chip used therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-on-chip structure in which another semiconductor chip is superimposed on a surface of a semiconductor chip and bonded, and a flip-chip structure in which the surface of a semiconductor chip is bonded to a wiring board. The present invention relates to a semiconductor device having a chip bonding structure and a semiconductor chip used therefor.

[0002]

2. Description of the Related Art Conventionally, there has been known a semiconductor device having a chip-on-chip structure in which another semiconductor chip is superposed on and joined to the surface of a semiconductor chip. In a semiconductor device having such a chip-on-chip structure, for example, a plurality of bumps are formed so as to protrude at positions corresponding to each other on the surface of each semiconductor chip, and the bumps of one semiconductor chip are connected to the other semiconductor chip. By bonding to the bumps of the chip, one semiconductor chip (child chip) is supported on the other semiconductor chip (parent chip), and electrical connection between the semiconductor chips is achieved.

[0003]

The bump of each semiconductor chip is partially exposed by forming an opening in a surface protective film covering the outermost surface of the semiconductor chip in order to achieve electrical connection between the semiconductor chips. It is formed on the wiring. Therefore, the formation position of the bump is restricted by the pattern of the internal wiring, and depending on the internal wiring pattern, the bump may be formed unevenly on the surface of the semiconductor chip. For example, when the bumps of the child chip are formed unevenly on the chip surface, the child chip may be inclined on the parent chip.

Therefore, it is conceivable to provide a dummy bump which does not contribute to the electrical connection between the semiconductor chips in a region of the surface of the semiconductor chip where no bump (functional bump) is formed. By providing the dummy bumps, portions not supported by the functional bumps can be supported by the dummy bumps, thereby preventing the child chip from tilting on the parent chip. Further, when the semiconductor chips are sealed in the resin package, the stress applied to the semiconductor chips joined to each other from the sealing resin can be reduced.

When such a dummy bump is provided, it is preferable that the dummy bump is formed of the same material as the functional bump. By doing so, after forming an opening in the surface protection film of the parent chip and the child chip to partially expose the internal wiring, plating using a bump material is selected on the exposed internal wiring and the surface protection film. This is because the dummy bumps and the functional bumps can be formed in the same step, and the number of semiconductor chip manufacturing steps can be prevented from increasing.

However, when the dummy bump and the functional bump are formed in the same step, as shown in FIG. 5, the surface of the surface protection film 91 and the surface of the internal wiring 93 exposed from the opening 92 formed in the surface protection film 91 are formed. Since the heights are different, the protrusion amount of the dummy bumps 94 from the surface of the surface protection film 91 is larger than the protrusion amount of the functional bumps 95 by Δd.
In this manner, the protrusion amount of the dummy bump 94 is
When the semiconductor chip is used as a parent chip or a child chip, the functional bumps 95 are not well bonded to the functional bumps of other semiconductor chips, so that electrical connection between the semiconductor chips is achieved. Can not do it.

Accordingly, an object of the present invention is to solve the above-mentioned technical problems and to provide a semiconductor device capable of reliably connecting a semiconductor chip to a solid such as another semiconductor chip, and a semiconductor chip therefor. That is.

[0008]

Means for Solving the Problems and Effects of the Invention According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: An electrical connection for the electrical connection and a semiconductor chip formed by raising a dummy connection that does not contribute to the electrical connection with the solid, wherein the dummy connection is provided on a surface facing the solid surface. It is provided on the formed concave portion, the depth of the concave portion, the projecting amount of the dummy connecting portion with respect to the surface facing the solid surface is the projecting amount of the electrical connecting portion with respect to the surface facing the solid surface A semiconductor chip characterized by being determined to be substantially equal.

The solid may be another semiconductor chip or a wiring board such as a lead frame. According to the present invention, if the depth of the concave portion is properly determined, even if the heights of the electric connection portion and the dummy connection portion themselves are made the same after the formation of the concave portion, the electric connection portion with respect to the surface of the semiconductor chip and The protrusion amounts of the dummy connection portions can be made substantially the same. Therefore, the electric connection portion and the dummy connection portion can be reliably connected to the solid surface, and the electric connection by the electric connection portion can be reliably achieved between the semiconductor chip and the solid. Mechanical connection by the dummy connection portion can be reliably achieved.

[0010] Further, the electric connection portion and the dummy connection portion include:
Since it is only necessary to form the same height, it can be easily formed in the same step by performing a plating step or the like in the conventional manner. Therefore, by making the heights of the electrical connection portions and the dummy connection portions themselves different from each other, the semiconductor chip can be simplified compared to a method in which the protrusion amounts of the electrical connection portion and the dummy connection portion with respect to the surface of the semiconductor chip are almost the same. It can be manufactured in process.

In the case where the electric connection portion is formed on the internal wiring facing the opening formed in the surface protection film covering the outermost surface of the semiconductor chip, and the dummy connection portion is formed on the surface protection film, the concave portion may be formed. Is preferably formed on the surface of the surface protection film, and the depth of the concave portion is preferably set to be substantially the same as the depth from the surface of the surface protection film to the surface of the internal wiring. According to a second aspect of the present invention, there is provided a semiconductor device having a structure in which a surface of a semiconductor chip is joined to a solid surface so as to face each other, wherein the semiconductor chip according to the first aspect is used as the semiconductor chip. Semiconductor device.

According to the present invention, since the semiconductor chip of the first aspect is used, the same effect as that described in the first aspect can be obtained. According to a third aspect of the present invention, there is provided a semiconductor device having a structure in which a first solid and a second solid, at least one of which is a semiconductor chip, are joined with their surfaces facing each other. An electric connection portion that is provided so as to protrude from the first solid body and connects the first solid body and the second solid body at a predetermined interval, and electrically connects the first solid body and the second solid body; And a dummy connecting portion formed so as to protrude so that an amount of protrusion with respect to the surface is substantially equal to the predetermined distance, and not contributing to electrical connection between the first solid and the second solid. Semiconductor device.

According to the present invention, the projecting amount of the dummy connecting portion is made substantially equal to the interval formed between the first solid and the second solid, so that the dummy connecting portion is formed on the surface of the first solid. Connection can be made securely. Therefore, between the first solid and the second solid, the electrical connection by the electrical connection portion can be reliably achieved, and the mechanical connection by the electrical connection portion and the dummy connection portion can be reliably achieved.
Note that the first solid does not have a dummy connection portion that does not contribute to electrical connection between the first solid and the second solid, and the second solid has the first solid and the second solid. 2
It is preferable that the solids are joined at a predetermined interval, and that an electric connection portion for electrically connecting the first solid and the second solid is not formed. By doing so, the first solid and the second solid may be formed with the electrical connection portion or the dummy connection portion having a certain height, respectively, so that the first solid and the second solid can be formed in a simple process. it can.

[0014] More specifically, for example, as described in claim 4, for the connection, the tip of the electric connection portion fits into the surface of the second solid at a position corresponding to the electric connection portion. A concave portion is provided, and the dummy connection portion
A state in which the electric connection portion protrudes from the surface of the second solid by an amount substantially equal to the amount of the electric connection portion protruding from the surface of the first solid with respect to the connection concave portion of the electric connection portion is subtracted from the amount of protrusion of the electric connection portion. If it is formed, the amount of protrusion of the dummy connection portion with respect to the surface of the second solid becomes substantially equal to the predetermined interval.

According to a fifth aspect of the present invention, there is provided a semiconductor device having a structure in which a first solid and a second solid, at least one of which is a semiconductor chip, are joined with their surfaces facing each other. A first electrical connection portion provided on the surface of the solid so as to protrude and contribute to an electrical connection between the first solid and the second solid; and a first solid material provided on the surface of the first solid so as to be raised. A dummy connecting portion that does not contribute to the electrical connection between the first and second solids; and a first connecting portion on a surface of the second solid corresponding to the first electrical connecting portion.
The first electrical connection portion and the dummy connection portion are formed so as to protrude by an amount corresponding to a difference in the amount of protrusion between the first electrical connection portion and the dummy connection portion with respect to the surface of the solid, and are joined to the first electrical connection portion to form a gap between the first and second solids. And a second electrical connection part contributing to the electrical connection of the semiconductor device.

For example, in a case where the electric connection portion is formed on the internal wiring facing the opening formed in the surface protection film covering the outermost surface of the semiconductor chip, and the dummy connection portion is formed on the surface protection film, 1 If the electrical connection portion and the dummy connection portion are formed at the same height, the amount of protrusion of the first electrical connection portion and the dummy connection portion with respect to the surface of the first solid is from the surface of the surface protection film to the internal wiring. Differ by the depth of the Therefore, by forming the second electrical connection portion to compensate for the difference in the amount of protrusion, when the dummy connection portion is joined to the surface of the first solid, the first electrical connection portion and the second electrical connection portion are connected. Can be joined together. Thereby, the connection between the first solid and the second solid can be reliably achieved.

Also, the first solid may be formed with the first electric connection portion and the dummy connection portion each having a certain height, and the second solid may be formed with the second electric connection portion each having the certain height. The first and second solids can be manufactured in a simple process.

[0018]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device has a so-called chip-on-chip structure, in which a child chip 2 is superposed on and joined to a surface 11 of a parent chip 1 and then sealed with a resin and placed in a package 3. Have been.

The parent chip 1 is made of, for example, a silicon chip. The surface 11 of the parent chip 1 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. On this surface protection film, a plurality of pads 12 for external connection are arranged so as to be exposed near the periphery of the surface 11 of the parent chip 1 having a substantially rectangular planar shape. The external connection pad 12
It is connected to a lead frame 5 by a bonding wire 4.

The child chip 2 is made of, for example, a silicon chip. The surface 21 of the daughter chip 2 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on the semiconductor substrate, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. Child chip 2
Is bonded to the parent chip 1 by a so-called face-down method in which the surface 21 faces the surface 11 of the parent chip 1 and is supported by a plurality of bumps B provided between the parent chip 1 and the parent chip 1. .

On the plurality of bumps B, a functional bump which supports the child chip 2 on the parent chip 1 and contributes to electrical connection between the parent chip 1 and the child chip 2,
Is supported only on the parent chip 1 and does not contribute to the electrical connection between the parent chip 1 and the child chip 2. The dummy bump is provided in a region where the functional bump is not formed, and prevents the child chip 2 from tilting on the parent chip 1. Further, since the dummy bumps are provided, when the resin is sealed in the package 3, the stress applied to the parent chip 1 and the child chip 2 from the sealing resin can be reduced. The deformation of the child chip 2 can be prevented.

FIG. 2 is a sectional view showing a part of the parent chip 1 and a part of the child chip 2 in an enlarged manner. In this embodiment, the child chip 2 is a functional bump B of the parent chip 1 where the functional bump BF2 and the dummy bump BD2 face each other.
By being joined to the F1 and the dummy bump BD1, it is supported on the parent chip 1 and is electrically connected to the parent chip 1. That is, the bump B between the parent chip 1 and the child chip 2 is constituted by the functional bumps BF1 and BF2 or the dummy bumps BD1 and BD2 joined to each other.

An interlayer insulating film 13 made of, for example, silicon oxide is formed on a semiconductor substrate (not shown) serving as a base of the parent chip 1, and an internal wiring 14 is provided on the interlayer insulating film 13. Is established. The surfaces of the interlayer insulating film 13 and the wiring 14 are covered with a surface protection film 15 made of, for example, silicon nitride. The surface protective film 15 includes
An opening 16 for exposing a part of the wiring 14 is formed. On the wiring 14 exposed through the opening 16, a functional bump BF made of an oxidation-resistant metal such as gold, platinum, silver, palladium or iridium is provided.
1 is formed on the surface protection film 15 so as to protrude. In the surface protection film 15, a concave portion 17 which is one step lower than the periphery is formed in a region where the functional bump BF 1 is not formed, and the dummy bump BD 1 is formed on the concave portion 17.
Are formed to protrude.

On the other hand, the child chip 2 is also configured substantially in the same manner as the parent chip 1, and an interlayer insulating film 23 made of, for example, silicon oxide is formed on a semiconductor substrate (not shown) serving as a base of the child chip 2. Is formed, and this interlayer insulating film 2 is formed.
The internal wiring 24 is disposed on the reference numeral 3. Interlayer insulating film 23
The surface of the wiring 24 is covered with a surface protection film 25 made of, for example, silicon nitride. Surface protective film 25
Has an opening 26 for exposing a part of the wiring 24.
Are formed at positions corresponding to the functional bumps BF1 of the parent chip 1. Wiring 2 exposed through opening 26
4 is a sub chip 2 made of an oxidation resistant metal such as gold, platinum, silver, palladium or iridium.
Is formed on the surface protective film 25 so as to protrude. The surface protective film 25 has a functional bump B
In a region where F2 is not formed, a concave portion 27 which is one step lower than the periphery is formed at a position corresponding to the dummy bump BD1 of the parent chip 1, and a dummy bump BD2 of the child chip 2 is formed on the concave portion 27 so as to protrude. ing.

The dummy bumps BD1 and BD2 can be formed in the same process as the functional bumps BF1 and BF2 by using the same bump material as the functional bumps BF1 and BF2, respectively. Taking the parent chip 1 as an example, after an opening 16 is formed in the surface protection film 15, a resist pattern having an opening corresponding to the concave portion 17 is formed on the surface protection film 15, and this resist pattern is used as a mask. The recess 17 is formed by etching the surface protection film 15. Thereafter, plating using a bump material is selectively applied to the surface of the surface protective film 15 in which the opening 16 and the concave portion 17 are formed. Thereby, the functional bump BF1 and the dummy bump BD1 having substantially the same height are obtained.

The concave portion 17 is formed such that the bottom surface is substantially at the same height as the surface of the wiring 14 exposed through the opening 16. Therefore, in the plating step, the functional bump BF1 and the dummy bump BD1 can be formed at substantially the same height by depositing the bump material on the wiring 14 and the concave portion 17 in the same manner. Of the functional bump BF1 and the dummy bump BD
1 can be made substantially the same as the protrusion amount. Similarly, in the child chip 2, the functional bumps BF2 and the dummy bumps BD2 can be formed at substantially the same height, and the functional bumps BF2 with respect to the surface of the surface protection film 25 can be formed.
And the protrusion amount of the dummy bump BD2 can be made substantially the same.

Thus, when the child chip 2 is joined to the parent chip 1, the functional bumps BF2 and the dummy bumps BD2 of the child chip 2 can be reliably connected to the functional bumps BF1 and the dummy bumps BD1 of the parent chip 1, respectively. it can. Therefore, electrical connection by the functional bumps BF1 and BF2 can be reliably achieved between the parent chip 1 and the child chip 2, and the functional bumps BF1 and B
Mechanical connection by the F2 and the dummy bumps BD1 and BD2 can be reliably achieved.

FIG. 3 is an enlarged sectional view showing a part of a semiconductor device according to another embodiment of the present invention.
3 shows a state before joining the parent chip 1 and the child chip 2, and FIG. 3B shows a state where the parent chip 1 and the child chip 2 are joined. In FIG. 3, parts corresponding to the respective parts shown in FIG. 2 are denoted by the same reference numerals as in FIG. In this embodiment, no functional bump is provided on the sub chip 2, and a part of the surface of the internal wiring 24 is exposed through the opening 26 formed in the surface protection film 25. I have. When the parent chip 1 and the child chip 2 are joined, the tip of the functional bump BF1 formed on the parent chip 1 enters the opening 26 of the child chip 2 and the functional bump BF1 is connected to the internal wiring 24. It has become. The dummy bump BD2 is provided only on the child chip 2 without the dummy bump provided on the parent chip 1. Note that, unlike the first embodiment described above, no concave portion for adjusting the height of the dummy bump BD2 is formed in the surface protection film 25.

The dummy bump BD2 is formed by an amount substantially equal to the distance ΔD formed between the surface protection film 15 of the parent chip 1 and the surface protection film 25 of the child chip 2 when the parent chip 1 and the child chip 2 are joined. It is formed so as to protrude from the surface protection film 25. In other words, the dummy bump BD2
Is the protrusion amount Δ of the functional bump BF1 from the surface protection film 15.
It is formed so as to protrude from the surface protection film 25 by an amount substantially equal to the amount obtained by subtracting the fitting amount Δd2 of the functional bump BF1 into the opening 26 from d1.

Thus, the parent chip 1 and the child chip 2 can be joined to connect the functional bump BF1 of the parent chip 1 to the internal wiring 24 of the child chip 2,
The dummy bump BD2 formed on the child chip 2 can be bonded to the surface of the surface protection film 15 of the parent chip 1.
Therefore, similarly to the first embodiment described above, the parent chip 1 and the child chip 2 can be reliably electrically and mechanically connected. In addition, since the functional bumps BF1 and the dummy bumps BD2 having a certain height may be respectively formed on the parent chip 1 and the child chip 2, the parent chip 1 and the child chip 2 can be formed by a simple process. There is no fear that the manufacturing cost of the first and second chips 2 is high.

In this embodiment, the functional bumps BF1 are formed on the parent chip 1 and the dummy bumps BD2 are formed on the child chip 2. However, the dummy bumps are formed on the parent chip 1 and Opening 1 of chip 1
6 may be formed with functional bumps. In this case, the dummy bumps of the parent chip 1 have an amount substantially equal to an amount obtained by subtracting an amount of fitting of the functional bump into the opening 16 from an amount of protrusion of the functional bump from the surface of the surface protection film 25 of the child chip 2. It may be formed to protrude from the surface protection film 15.

FIG. 4 is an enlarged sectional view showing a part of a semiconductor device according to still another embodiment of the present invention, and FIG. 4 (a) shows a state before the parent chip 1 and the child chip 2 are joined. FIG. 4B shows a state where the parent chip 1 and the child chip 2 are joined. 4, parts corresponding to the respective parts shown in FIG. 2 are denoted by the same reference numerals as in FIG. In this embodiment, the parent chip 1
Has a functional bump BF1 and a dummy bump BD1 formed so as to protrude on the surface protective film 15. The functional bump BF1 and the dummy bump BD1 are formed at substantially the same height in the same step. On the other hand, in the child chip 2,
Although the functional bump BF2 is formed so as to protrude on the surface protection film 25, unlike the above-described first embodiment, a dummy bump that does not contribute to electrical connection with the parent chip 1 is not formed. Further, no recess for adjusting the height of the dummy bump BD1 is formed in the surface protection film 15 of the parent chip 1.

The functional bump BF2 of the child chip 2 is connected to the functional bump BF1 of the surface of the surface protection film 15 of the parent chip 1.
Of the dummy bump BD1 and the protrusion amount Δd4 of the dummy bump BD1.
Thereby, the parent chip 1 and the child chip 2 are joined,
The functional bumps BF1 of the parent chip 1 and the functional bumps BF2 of the child chip 2 can be connected, and the dummy bumps BD1 formed on the parent chip 1 can be joined to the surface of the surface protection film 25 of the child chip 2. . Therefore, similarly to the first and second embodiments, the parent chip 1 and the child chip 2 can be reliably electrically and mechanically connected.

Furthermore, the functional bumps BF1 and the dummy bumps BD1 each having a certain height may be formed on the parent chip 1, and the functional bumps BF2 each having a certain height may be formed on the child chip 2. The chip 2 can be made by a simple process, and there is no possibility that the manufacturing cost of the parent chip 1 and the child chip 2 is high. In this embodiment, the dummy bump BD1 is formed on the parent chip 1, but a dummy bump may be formed on the child chip 2 instead of the dummy bump BD1.

Although the three embodiments of the present invention have been described, the present invention is not limited to the above embodiments. For example, parent chip 1 and child chip 2
Although each of them is a chip made of silicon, a semiconductor chip using any other semiconductor material such as a compound semiconductor (for example, a gallium arsenide semiconductor) or a germanium semiconductor may be used instead of silicon. In this case, the semiconductor material of the parent chip 1 and the semiconductor material of the child chip 2 may be the same or different.

In the above-described embodiment, the chip-on-chip structure is described. However, the present invention can be applied to a flip-chip bonding structure in which the surface of a semiconductor chip is bonded to a wiring board so as to face the same. In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view showing a part of a parent chip and a child chip.

FIG. 3 is an enlarged sectional view showing a part of a semiconductor device according to another embodiment of the present invention;

FIG. 4 is an enlarged sectional view showing a part of a semiconductor device according to still another embodiment of the present invention;

FIG. 5 is a cross-sectional view for describing a problem that occurs in a semiconductor device having a conventional configuration.

[Explanation of symbols]

Reference Signs List 1 parent chip (first solid) 17 recess 2 child chip (second solid) 26 opening (connection recess) BD1, BD2 dummy bump (dummy connection) BF1 functional bump (electric connection, first electrical connection) BF2 Functional bump (electrical connection part, second electric connection part) Δd1 Projection amount (projection amount of electric connection part) Δd2 Fitting amount Δd3 Projection amount (projection amount of first electric connection part) Δd4 Projection amount (of dummy connection part) Δd5 An amount corresponding to the difference between the amount of protrusion Δd3 and the amount of protrusion Δd4 (the amount corresponding to the difference between the amount of protrusion of the first electrical connection portion and the amount of protrusion of the dummy connection portion) ΔD interval (the distance between the surface of the semiconductor chip and the solid surface) Predetermined interval between)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 311 H01L 21/60

Claims (5)

(57) [Claims] An electric connection part for electric connection with the solid and a dummy connection part not contributing to the electric connection with the solid are provided on a surface opposed to the solid surface and joined together. In the semiconductor chip formed so as to protrude, the dummy connection portion is provided on a concave portion formed on a surface facing the solid surface, and the depth of the concave portion is:
A semiconductor chip characterized in that a protrusion amount of the dummy connection portion with respect to a surface facing the solid surface is substantially equal to a protrusion amount of the electric connection portion with respect to a surface facing the solid surface. 2. A semiconductor device having a structure in which a semiconductor chip is joined to a solid surface with the surface of the semiconductor chip facing the semiconductor chip, wherein the semiconductor chip according to claim 1 is used as the semiconductor chip. apparatus. 3. A semiconductor device having a structure in which a first solid and a second solid, at least one of which is a semiconductor chip, are joined with their surfaces facing each other, wherein the first solid and the second solid protrude from the surface of the first solid. An electric connection portion for connecting the first solid and the second solid at a predetermined interval and electrically connecting the first solid and the second solid to each other; And a dummy connection portion formed so as to protrude so that an amount of protrusion with respect to the surface is substantially equal to the predetermined distance and not contributing to electrical connection between the first solid and the second solid. apparatus. 4. The surface of the second solid is provided with a connection recess at a position corresponding to the electrical connection portion, into which a tip of the electrical connection portion fits. The first solid is formed to protrude from the surface of the second solid by an amount substantially equal to the amount of protrusion of the electric connection from the surface of the second solid minus the amount of fitting of the electric connection into the recess for connection. The semiconductor device according to claim 3, wherein: 5. A semiconductor device having a structure in which a first solid and a second solid, at least one of which is a semiconductor chip, are joined with their surfaces facing each other, wherein the first solid and the second solid protrude from the surface of the first solid. A first electrical connection portion provided to contribute to an electrical connection between the first solid and the second solid; and a first electrical connection portion provided on the surface of the first solid so as to protrude, between the first solid and the second solid. And a dummy connection part that does not contribute to the electrical connection of the first solid connection part and a dummy connection part with respect to the surface of the first solid body at a position corresponding to the first electrical connection part on the surface of the second solid body. A second electrical connection formed to be raised by an amount corresponding to the difference in the amount of protrusion and joined to the first electrical connection and contributing to an electrical connection between the first and second solids. Characteristic semiconductor device.