JP3246826B2 - Semiconductor package - Google Patents

Abstract

PURPOSE:To provide a semiconductor package which is low in cost, compact in structure, and high in reliability. CONSTITUTION:A semiconductor package is equipped with a board 6 provided with a wiring circuit 6a which includes a connector 6b formed on its primary surface, a semiconductor chip 7 mounted on the primary surface of the board 7 in a face-down manner, a resin layer 10 filled between the semiconductor chip 7 and the board 6, and a plane-type outer connection terminal 9 electrically connected to the semiconductor element 7 and, if necessary, led out and exposed on the other primary surface of the board 7 through a blind viahole connection, wherein the wiring circuit 6a which includes the connector 6b formed on the primary surface of the board 6 is formed nearly flush with the surface of the board 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a small and thin semiconductor package suitable for a card-type external storage medium.

[0002]

2. Description of the Related Art In the construction of various memory cards,
Since the size and thickness of the card are limited, it is required to reduce the thickness of the semiconductor package that contributes to the memory function and the like, and at the same time, it is desired to reduce the size of the semiconductor package as much as possible to the size of a semiconductor chip.

In order to meet such requirements for thin mounting, for example, mounting in a space of 1 mm or less in the thickness direction, flip chip mounting, COB (Chip on Board)
The law is known. As a thin package, for example, as shown in a sectional view of a main part in FIG. 3, a circuit board 1 provided with a wiring circuit 1a including a connected part on one main surface.
A semiconductor chip (flip chip) 2 mounted and mounted on one main surface of the circuit board 1, and an external connection terminal 4 led out to the other main surface side of the circuit board 1 via a through hole 3.
There is known a module having a configuration including a semiconductor layer and a resin layer 5 for sealing an area surface such as between the semiconductor chip 2 and the circuit board 1. In this type of thin package configuration, when the external dimensions of the semiconductor chip 2 to be mounted and mounted are, for example, 15 × 5 × 0.25 mm, the external dimensions are as follows.
A circuit board 1 of 20 × 10 × 0.2 mm is selected. Here, as the circuit board 1, for example, one using alumina, aluminum nitride, glass / epoxy or the like as an insulator is used. In FIG. 3, reference numeral 1b denotes a connection pad made of silver paste disposed on the surface to be connected of the wiring circuit 1a, and 2a denotes a connection bump provided on the electrode terminal surface of the semiconductor chip 2.

[0004]

However, in the case of the flip chip mounting and the COB method, the KGN (Kno
The problem is how to secure wn Good Die). It is difficult to develop burn-in in a chip state, and there is a problem in reliability because a semiconductor chip to be used cannot usually be burned in advance. In other words, this type of semiconductor chip cannot perform so-called burn-in, which is to detect a defect that will appear in the near future as the chip itself. Therefore, there is a possibility that a trouble will occur in the early stage of practical use after mounting and modularization, and it can be said that there is a problem in reliability. Further, in terms of compactness, the COB method requires a larger mounting area than flip-chip mounting, which hinders compactness. In the case of a packaged module using the one-side mold, in a general (normal) sealing resin application / filling step, the space between the semiconductor chip 2 and the circuit board 1 is densely filled with the sealing resin. It is often difficult to fill and seal. That is, since the circuit wiring 1a including the connected part formed and arranged on one main surface of the circuit board 1 generally has a thickness of about 35 μm, the circuit wiring 1a protrudes about 35 μm from the surface of the circuit board 1. It will be taken. Since the distance between the circuit board 1 and the semiconductor chip 2 is set to be narrow, the circuit wiring 1a protruding by about 35 μm is filled with a sealing resin in a sealing step, for example, by a capillary phenomenon. During the process of injecting and filling the sealing resin between the circuit board 1 and the semiconductor chip 2 surface by, for example, the smooth inflow of the sealing resin.
Filling is likely to be hindered and dense filling and sealing may not be achieved. Here, the fact that it is difficult to perform the dense filling of the sealing resin means that bubbles and the like are likely to remain in the resin sealing region, and as a packaged module, the temperature is increased when the required driving is performed. Bubbles become enormous, and the integrity between the circuit board 1 and the semiconductor chip 2 is impaired. In other words, disconnection of the connecting portion is likely to occur,
There are problems with reliability and yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor package which can be reduced in cost and size and can guarantee high reliability.

[0006]

Means for Solving the Problems A first semiconductor package according to the present invention is provided with a substrate provided with a wiring circuit including a portion to be connected on one main surface, and a face-down type mounted on one main surface of the substrate. A semiconductor chip, a resin layer filling the space between the semiconductor chip and the substrate surface, and a planar external connection terminal electrically connected to the semiconductor chip and led out and exposed to the other main surface side of the substrate. a semiconductor package comprising comprises a wiring circuit including a connected part of one main surface of the substrate prior to
Being embedded in the substrate, the upper surface of the wiring circuit and the substrate surface are formed substantially in the same plane. In addition, a second semiconductor package according to the present invention includes a substrate having a wiring circuit including a connected portion on one main surface, a semiconductor chip mounted face-down on one main surface of the substrate, chip - a resin layer filling between the substrate surface, said semiconductor chip electrically connected, and the external connection Brine <br/> de-via-hole connection with derived-exposed on the other main surface of the substrate the flat A wiring circuit including a connected part on one main surface of the substrate, wherein the wiring circuit is embedded in the substrate, and a top surface of the wiring circuit is provided.
The present invention is characterized in that the substrate surfaces are formed substantially in the same plane.

The present invention provides: (a) a resin-based substrate or a ceramic-based substrate in which a wiring circuit including a portion to be connected on one main surface is arranged (installed) so as to form substantially the same plane as a circuit substrate. (B) One main surface (one side) of this circuit board
(C) A compact encapsulation resin layer is formed and provided on the semiconductor chip-circuit board surface to reduce the size and thickness of the semiconductor package while maintaining reliability. The main point is to improve such things.

In the present invention, a wiring circuit including a connected portion on a circuit board surface on which a semiconductor chip is mounted and mounted is buried so as to be flush with the circuit board surface.
Its flatness (flatness) is not strict, and in general,
When the thickness of the wiring circuit is about 35 μm, the allowable range is ± 10 μm. And such a circuit board is a green sheet method when the insulating material used is ceramic,
In the case of resin, it can be prepared by a method using a prepreg.

Further, in the configuration of the circuit board, if necessary, a wiring circuit including a connected portion formed on one main surface of the circuit board and / or a wiring circuit arranged in an inner layer on the circuit board may be separately provided. , Around those wiring circuits,
A dummy wiring pattern having a width of, for example, about 0.1 to 2 mm may be provided in the non-circuit formation region at the outer peripheral edge portion while being electrically insulated and separated. That is, if the dummy wiring pattern is provided, the occurrence of warpage of the circuit board can be suppressed and prevented, and noise countermeasures can be taken. It is preferable that the installation position of the dummy wiring pattern is not more than about 2 mm from the outer peripheral end face, that is, as close as possible to the outer peripheral end face.

Furthermore, the arrangement of the planar external connection terminals led out and exposed to the back side of the circuit board is not particularly limited, but when a regular pitch lattice is used, this type of semiconductor package is standardized. It is also possible to provide a dummy connection terminal at a corner portion of a part of the external connection terminal, for example, when the arrangement of the external connection terminal is biased. It becomes easier to perform flat mounting.

[0011]

In the first semiconductor package according to the present invention, the circuit board surface on which the semiconductor chip is mounted and mounted is filled with a wiring circuit including a connected portion and maintains flatness. The denseness of the sealing resin layer to be sealed is reliably ensured. In other words, since the gap between the semiconductor chip and the circuit board surface is flat and the resin easily flows, a highly reliable bonding is formed in order to form and hold a dense sealing layer without voids.

Further, in the second semiconductor package according to the present invention, in the configuration of the first semiconductor package,
Bra India via holes connected to the other main surface of the substrate, by which is derived, exposing the external connection terminals of the flat, as compared with the case where is derived, exposed through hole connection, filling and
The sealing resin for sealing is also prevented from flowing out to the back side,
The denseness of the sealing resin layer can be more easily ensured, and the thinness and appearance of the semiconductor package can be ensured.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a cross-sectional view showing an example of a configuration of a main part of a semiconductor package according to the present invention. Numeral 6 denotes a 20 mm long, 10 mm wide and 10 mm thick wiring circuit 6a including a connected part on one main surface. 0.2
A circuit board 7 of mm is a semiconductor chip (such as an IC chip) having a length of 15 mm, a width of 5 mm, and a thickness of 0.25 mm mounted and mounted on one main surface of the circuit board 6. Here, the wiring circuit 6a formed on one main surface of the circuit board 6 is buried so as to form the same plane as the one main surface of the circuit board 6, and the semiconductor chip 7 to be mounted and mounted is provided. A connected portion (connection pad) 6b made of silver paste is provided in a region where the connection bump 7a arranged on the electrode terminal is connected. Further, in the circuit board 6, a flat external connection terminal 9 is provided on the back surface (other main surface) through a through hole 8 electrically connected to the wiring circuit 6a on one main surface thereof. It is led out and exposed so as to be flush with the surface. Examples of the circuit board 6 include an alumina-based circuit board, an aluminum nitride-based circuit board, a glass / epoxy resin-based circuit board, and a BT resin-based circuit board.
Commonly used. Further, in the circuit board 6, a solid pattern such as a solid pattern is provided on the outer peripheral edge of the main surface of the circuit board 6 (preferably on the outer peripheral edge within about 2 mm from the outer peripheral end face) as a measure for preventing warpage and noise. A dummy wiring pattern (not shown) may be provided. Further, reference numeral 10 denotes a resin layer which fills and seals a gap formed between the semiconductor chip 7 mounted and mounted on one main surface of the circuit board 6 and the surface of the circuit board 6.

Next, an example of manufacturing the semiconductor package having the above configuration will be described.

First, a circuit wiring 5a including a connected portion for flip-chip mounting on one surface (on one main surface) and, if necessary, a circuit wiring having a solid dummy wiring pattern and including a connected portion An alumina-based circuit board 6 is provided which is connected to 6a and has a flat external connection terminal 9 led out in a lattice-like arrangement on the back surface (other main surface) via a through hole 8. Here, the alumina-based circuit board 6 is formed by a so-called green sheet method, and the circuit wiring 6a including the connected portion and the planar type external connection terminal 9 are substantially the same as the surface of the alumina-based circuit board 6 respectively. It takes a form embedded so as to form the same flat surface. The alumina-based circuit board 6 has a length of 20 mm, a width of 10 mm, and a thickness of 0.2 mm.
The semiconductor chip 7 having a length of 15 mm, a width of 5 mm and a thickness of 0.25 mm is mounted and mounted face-down type.

Next, the alumina-based circuit board 6 is fixed on, for example, a stage of a screen printing machine having a vacuum suction mechanism, and the alumina-based circuit board 6 on the alumina-based board 6 corresponding to the electrode (connection) pad 7a of the semiconductor chip 7 is mounted. The connection pad 6b is formed on the connected portion. That is, using a metal mask having an opening (for example, 150 × 150 μm) corresponding to the electrode pad (for example, 100 × 100 μm) 7 a of the semiconductor chip 7, a silver paste (for example, A silver particle diameter of 1 μm and a viscosity of 1000 ps) are screen-printed to form a connection pad 6b having a diameter of 150 μm and a height of about 80 μm on the surface of the portion to be connected. On the other hand, on the electrode terminal surface, a gold bump 7a for connection by electroplating or a gold ball bump (for example, height
A semiconductor chip 7 having 30 μm, 100 × 100 μm) 7a is prepared.

Thereafter, the semiconductor chip 7 is connected to the corresponding connection pads 6 on one main surface of the alumina-based substrate 6.
b, and the gold bump 7a for connection are aligned and arranged,
By pressurizing the connected portions, the connection pads 6b are press-fitted so as to embed at least the distal ends of the connection bumps 7a and are fixedly connected to assemble the semiconductor package. In this state, so-called flip-chip bonding is performed by thermosetting the silver paste forming the connection pad 6b.

Next, a treatment with a sealing resin is performed. That is, a sealing resin (for example, a low-viscosity epoxy resin) is dropped onto one end of the exposed area surface of the peripheral portion of the alumina-based circuit board 6 and then heated to about 60 to 80 ° C. In the gap between the lower surface and the upper surface of the alumina-based circuit board 6,
The sealing resin is poured and filled from one end of the gap by utilizing the capillary phenomenon. In this resin treatment, it is preferable that a sufficient amount of the resin 9 is filled in the gap and a part of the gap goes around the side surface of the semiconductor chip 7. After the required resin treatment is performed in this manner, the filled resin is cured (solidified) by heat or the like, whereby a semiconductor package having a configuration as shown in a cross section in FIG. 1 is obtained.

Here, the semiconductor chip 7 of the semiconductor package is not only better fixed to the surface of the alumina-based circuit board 6 by the filled resin layer 10, but also the alumina-based circuit of the semiconductor chip 7 is improved. Substrate 6
Insulation protection for the surface is also achieved. On the other hand, although the upper surface of the semiconductor chip 7 is exposed, the exposed surface of the semiconductor chip 7 is protected because the material silicon is dense and robust, so that the reliability is not a problem. confirmed.

The periphery of the semiconductor chip 7 is surely
And densely resin-sealed, the alumina-based substrate 6
Thus, a strong bond was secured, and the device functioned as a highly reliable semiconductor package. Furthermore, when a solid pattern is formed and arranged on the outer peripheral edge of one main surface of the circuit board 6, this semiconductor package is thin and has a thickness of at most about 0.3 mm due to its reinforcing effect.
The generation of cracks and the generation of warpage were effectively suppressed, and a good yield was obtained, and the handling operation was simple. Moreover, when this semiconductor package was used as a functional part of a memory card, it was also confirmed that noise suppression was good.

In the above description, a configuration example using an alumina-based substrate having a rectangular external shape as the circuit substrate 6 has been described, but a rectangular shape may be used.

Embodiment 2 A circuit board 6 'is shown in FIG. That is, one main surface has a circuit wiring 6a provided with a silver paste connection pad 6b on a surface to be connected for flip-chip mounting, and a space between the circuit wiring 6a and the circuit wiring 6a via a blind via hole 8 '. An alumina-based circuit board (or aluminum nitride-based circuit board) 6 ′ in which planar external connection terminals 9 are led out and arranged in a grid-like arrangement on the back surface (other main surface) was prepared. In this circuit board 6 ', the circuit wiring 6a including the connected portion and the planar external connection terminal 9 are also provided.
Is embedded so as to form a flat surface substantially the same as the surface of the circuit board 6 '. On the other hand, gold bumps for connection (30 μm in height, 100 ×
100μm) Semiconductor chip with 7a (flip chip)
7 was prepared. The alumina-based substrate 6 'has a length
Flip chip (semiconductor chip) 7 has a length of 15 mm, a width of 5 mm, and a thickness of 0.25 mm.
The flip chip is mounted and mounted face-down type.

Next, the alumina-based circuit board 6 'and the flip chip 7 were positioned and arranged on the stage surface of the flip chip bonder. That is, after the alumina-based circuit board 6 'was vacuum-adsorbed, the gold bumps 7a were aligned and arranged on the gold connection pads 6b of the alumina-based circuit board 6' on the electrode terminal surfaces of the flip chip 7. Then, a load (pressurization) is applied from above the flip chip 7 in order to bring the both connected portions of the connection pad 6b and the gold bump 7a into close contact.
The connection pads 6b and the gold bumps 7a were joined and integrated by mutual diffusion while maintaining the temperature of about 100 to 150 ° C. for about 30 to 120 minutes while adding. Thereafter, the sealing resin 10 was filled between the alumina-based circuit board 6 'and the flip chip 7 under the same conditions as in the first embodiment. In the resin filling process, when the temperature is appropriately increased, the capillary phenomenon is promoted, and the resin filling process can be performed more easily. After the required resin filling process is performed, a heating process is performed to cure the filled resin, so that the flip chip 7
Was manufactured with the semiconductor package fixed and held.

In the above configuration, the flat external connection terminals 9 led out and arranged on the back side of the circuit board 6 'are:
Although it may be random, a grid-like arrangement with a constant pitch is preferable in terms of standardization and the like. In the case of a configuration in which the margin on the outer side is relatively large, the outside of the required flat external connection terminal 9 is required. Alternatively, a configuration in which dummy external connection terminals are provided at each corner may be adopted.

[0026]

As can be understood from the above description, in the semiconductor package according to the present invention, the circuit board surface on which the semiconductor chip is mounted / mounted is embedded with the wiring circuit including the connected portion, and the flatness is maintained. The denseness of the sealing resin layer that fills and seals this region is also ensured. That is, since the resin is easily flowed between the semiconductor chip and the circuit board surface, and is flat, the dense sealing layer without voids is easily formed and held, so that highly reliable sealing and bonding is formed. . Furthermore, in Brine Dohoru connected to the other main surface of the substrate, when was derived, exposing the external connection terminal of the planar type, as compared with the case where is derived, exposed through hole connection, filling and sealing It is also possible to easily prevent the encapsulating resin from flowing out to the back side, so that the denseness of the encapsulating resin layer can be more easily secured, and the thinness and aesthetic appearance of the semiconductor package can be ensured. Become. Furthermore, to be mentioned, the semiconductor package of the present invention has features such as the above-described reliability, thinness, and detachability, and can be said to be suitable for, for example, a memory card.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a configuration of a main part of a semiconductor package according to the present invention.

FIG. 2 is a sectional view showing another example of the configuration of the main part of the semiconductor package according to the present invention.

FIG. 3 is a sectional view showing an example of a configuration of a main part of a semiconductor package outside the present invention.

[Explanation of symbols]

1,6,6 '... circuit board 1a, 6a ... wiring circuit 1b,
6b: Connection pad (connected part) 2, 7: Semiconductor chip
2a, 7a: Connection bump 3, 8: Through hole
4, 9 ... flat type external connection terminal 5, 10 ... sealing resin layer 7 '... blind via hole

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 23/12 H01L 21/60

Claims (3)

(57) [Claims] A substrate provided with a wiring circuit including a portion to be connected on one main surface; a semiconductor chip mounted face-down on one main surface of the substrate; and a space between the semiconductor chip and the substrate surface. A semiconductor package comprising: a resin layer; and a planar external connection terminal electrically connected to the semiconductor chip and led out and exposed to the other main surface of the substrate. the substrate wiring circuit including a connected part of the main surface
Wherein the upper surface of the wiring circuit and the substrate surface are substantially flush with each other. 2. A substrate provided with a wiring circuit including a portion to be connected on one principal surface; a semiconductor chip mounted face-down on one principal surface of the substrate; and a space between the semiconductor chip and the substrate surface. and a resin layer, wherein the semiconductor chip are electrically connected, and a semiconductor package formed by and a external connection terminal bra India via-hole connection flat derived-exposed on the other main surface side of the substrate The wiring circuit including the connected portion on one main surface of the substrate is
Wherein the upper surface of the wiring circuit and the substrate surface are substantially flush with each other. 3. The semiconductor package according to claim 1, wherein the planarity of the wiring circuit including the connected portion, which is substantially flush with the substrate surface , is in a range of ± 10 μm.