JPH11121477A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain mounting efficiency degree approximate to degree of bare chip mounting, by electrically connecting chip pad electrodes and board pad electrodes of a wiring board which has electrodes and board pad electrode working as external terminals of an integrated circuit and whose outer shape is smaller than that of a semiconductor chip, and sealing the electrodes from the outside. SOLUTION: Chip pad electrodes are formed on one surface of a semiconductor chip 1, arranged along the edge of the semiconductor chip 1 and electrically connected with an integrated circuit. A board foot print 22 is formed on the mounting surface of a mounting board (circuit board) 21. Bump electrodes 8 for mounting face the mounting surface of the mounting board 21 and are connected with the foot print 22 formed on the mounting surface, and a desired electric product is constituted. That is, mounting to the mounting board 21 is enabled as it is, and the size is identical to the outer shape of the chip 1. As a result, mounting to the mounting board 21 is enabled with extremely high mounting density, e.g. practical efficiency of degree approximate to bare chip mounting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a package of the same size as a semiconductor chip and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device has a form in which a semiconductor chip on which an integrated circuit is formed is housed in a package having a size larger than the chip. 2. Description of the Related Art A semiconductor device plays a central role in an electric product, and most of current electric products include a mounting board on which the semiconductor device is mounted to achieve a desired electric function.

In recent years, the number and types of semiconductor devices mounted on a mounting substrate have increased remarkably due to the sophistication of functions of electrical products. For this reason, improvement in mounting density is desired. An effective means for improving the packaging density is to reduce the size of the package.

In view of the above circumstances, recently, a chip scale package (CSP) having a chip size equivalent to a package size has been actively developed. However, most CSPs also have a structure in which a chip has electrodes serving as external terminals and is mounted on a wiring board larger than the chip. For this reason, the package is larger than the chip.

FIG. 10 shows a conventional flip-chip connection type CSP. As shown in FIG.
1 is a wiring board 102 larger than the chip 101
Are connected via a bump electrode 103. Wiring board 1
Between the chip 02 and the chip 101, a sealing resin 104 is formed so that, for example, the bump electrode 103 is not exposed to the outside. On the mounting surface side of the package substrate 102, mounting bump electrodes 105 are formed. The mounting bump electrode 105 is connected to a mounting substrate (not shown).

FIG. 11 shows a cross section of a conventional wire bonding type CSP. As shown in FIG. 11, the semiconductor chip 101 is bonded to a package substrate 102 larger than the chip 101 with an adhesive 106,
They are connected via bonding wires 107. The sealing resin 108 is formed so as to cover the bonding wires 107 and the chip 101 from above the package substrate 102. On the mounting surface side of the package substrate 102, a mounting bump electrode 105 is formed.
Through a mounting board (not shown).

[0007]

As described above, the package is usually larger than the chip. For this reason,
Conventionally, mounted components (semiconductor devices) have become larger, and the mounting efficiency has been significantly reduced as compared with a case where a semiconductor chip is directly mounted on a substrate.

The present invention has been made in view of the above circumstances, and an object of the present invention is to achieve the same level of reliability as a normal packaged product and to achieve the same level of mounting efficiency as bare chip mounting. And a method of manufacturing the same.

[0009]

In order to achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor chip having chip pad electrodes electrically connected to an integrated circuit, and a semiconductor chip disposed on the semiconductor chip. A wiring board having an outer shape equal to or smaller than the outer shape of the semiconductor chip, each having an electrode serving as an external terminal of the integrated circuit and a substrate pad electrode electrically connected to the electrode; the chip pad electrode and the substrate pad Connection means for electrically connecting the electrodes,
And sealing means for sealing the substrate pad electrode and the connection means from the outside.

According to a second aspect of the present invention, there is provided a semiconductor chip having a chip pad electrode electrically connected to an integrated circuit, an electrode disposed on the semiconductor chip and serving as an external terminal of the integrated circuit, A wiring board having an outer shape substantially equal to the outer shape of the semiconductor chip, having a substrate pad electrode electrically connected to the electrode, and an opening corresponding to the chip pad electrode; Connecting means for electrically connecting the substrate pad electrode to the substrate via the opening, and sealing means for sealing the chip pad electrode, the substrate pad electrode, and the connecting means from the outside. Features.

Further, the sealing means is made of a resin. Further, the wiring board further includes a resin dam formed so as to surround an area where the electrode serving as the external terminal is formed, wherein at least the connection means is sealed with a resin and the area surrounded by the resin dam Is exposed to the outside.

Further, the upper surface of the resin and the upper surface of the electrode serving as the external terminal are on the same plane. Further, the semiconductor device has a wiring pattern to which an electrode serving as an external terminal of the semiconductor device is connected, and further includes a mounting substrate electrically connected to the semiconductor device to form a desired electric product.

Further, according to the manufacturing method, an electrode serving as an external terminal of the integrated circuit and a substrate pad electrically connected to the electrode are provided on a semiconductor chip having a chip pad electrode electrically connected to the integrated circuit. Bonding a wiring board having a size equal to or less than the outer shape of the semiconductor chip, each having an electrode, electrically connecting the chip pad electrode and the substrate pad electrode, and connecting the chip pad electrode, the substrate pad electrode and the connection Each of the means is sealed from the outside.

The sealing of the chip pad electrode, the substrate pad electrode, and the connection means from the outside is performed by covering the chip with a resin, and after covering the chip with the resin, The surface of the resin is receded, and the upper surface of the resin and the upper surface of the electrode serving as the external terminal are positioned on the same plane.

According to the semiconductor device having the above configuration, a wiring board having electrodes serving as external terminals and having a size substantially equal to or smaller than the outer shape of the chip is arranged on the chip. For this reason, the size can be made substantially the same as the outer shape of the chip, and for example, an extremely high mounting density comparable to that of bare chip mounting can be achieved.

Further, the semiconductor device has sealing means for sealing the chip pad electrode, the substrate pad electrode and the connecting means from the outside. Therefore, the same level of reliability as a normal packaged product can be realized.

Further, if the wiring substrate has an opening corresponding to the chip pad electrode, the opening can be filled with sealing means, and the sealing property of the connection means is improved. Therefore, the reliability can be further improved.

Further, according to the configuration having the resin dam surrounding the region where the electrode serving as the external terminal is formed, it is possible to eliminate the situation that the resin adheres to the electrode serving as the external terminal. In addition, the occurrence of poor contact and the like can be suppressed, and easier mounting can be realized.

Further, according to the configuration in which the upper surface of the resin and the upper surface of the electrode serving as the external terminal are on the same plane, it is possible to obtain a structure in which the electrode serving as the external terminal is not exposed by the resin when mounted on a mounting board. And a highly reliable structure can be obtained more easily.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings. FIG.
FIG. 1A is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line BB in FIG. 1A.

As shown in FIGS. 1A and 1B, a chip pad electrode 2 is formed on one surface of a semiconductor chip 1. The chip pad electrodes 2 are arranged along the edge of the chip 1 and are electrically connected to an integrated circuit (not shown) formed inside the chip 1. One surface of the chip 1 is covered with a passivation film 3. The passivation film 3 has an opening 4 communicating with the chip pad electrode 2.

On the passivation film 3, a wiring board 5 smaller than the outer shape of the chip 1 is bonded via an adhesive layer 6. The wiring board 5 in this embodiment is large enough to be arranged inside the pad area where the chip pad electrodes 2 are arranged.

The wiring board 5 has substrate pad electrodes 7 arranged along the edge thereof, and has mounting bump electrodes 8 arranged in a matrix inside a region where the substrate pad electrodes 7 are arranged. . The board pad electrodes 7 correspond to the mounting bump electrodes 8, for example, on a one-to-one basis. The corresponding board pad electrodes 7 and the mounting bump electrodes 8 are mutually connected via a wiring layer 9 formed in the wiring board 5. Connected. The substrate pad electrode 7 is electrically connected to the chip pad electrode 2 via a bonding wire 10. Thereby, an integrated circuit (not shown) formed in the chip 1 is electrically connected to the mounting bump electrodes 8. The mounting bump electrode 8
It functions as an external electrode (outer lead) of this semiconductor device.

The chip pad electrode 2, the wiring board 5, the substrate pad electrode 7, and the wire 10 are each sealed with a resin 11 formed on one surface of the chip 1. In addition,
A part of the mounting bump electrode 8 is exposed from the resin 11.

Next, the manufacturing method will be described. FIG.
4A to 4A are plan views showing the semiconductor device according to the first embodiment in the order of main manufacturing steps. FIGS. 2B to 4B respectively show (A)
It is sectional drawing which follows the BB line | wire in a figure.

First, as shown in FIGS. 2A and 2B,
In the chip 1, a chip pad electrode 2, a passivation film 3, and an opening 4 communicating with the chip pad electrode 2 in the passivation film 3 are sequentially formed. Next, an adhesive resin is applied onto the passivation film 3 inside the pad area, or an adhesive sheet 6 is placed or attached as shown in FIG.

In a step different from that of the above-described chip 1, a wiring layer 9, a substrate pad electrode 7, and a mounting bump electrode 8 are formed on the wiring substrate 5, respectively. Then, the wiring board 5 on which the mounting bump electrodes 8 are formed is placed on the adhesive sheet 6 as shown in FIGS. 3A and 3B, and is bonded to the chip 1 via the adhesive sheet 6.

Next, as shown in FIGS. 4A and 4B,
The chip pad electrode 2 and the substrate pad electrode 7 are connected to each other by a bonding wire 10 using a wire bonding method.

Next, as shown in FIGS. 1A and 1B,
For example, using a method such as potting, the chip pad electrode 2, the wiring substrate 5, the substrate pad electrode 7, and the wire 10 are sealed in a state where a part of the mounting bump electrode 8 is exposed.

As described above, the semiconductor device according to the first embodiment is manufactured. FIG. 5 is a diagram illustrating a state in which the semiconductor device according to the first embodiment is mounted on a mounting board.

As shown in FIG. 5, a mounting board (circuit board)
A board footprint 22 is formed on the mounting surface 21. The mounting bump electrode 8 of the device according to the first embodiment faces the mounting surface of the mounting substrate 21 and is connected to a footprint 22 formed on the mounting surface, thereby forming a desired electrical product.

According to the semiconductor device according to the first embodiment, as shown in FIG.
1, and the size is the same as the outer shape of the chip 1. Therefore, it can be mounted on the mounting board 21 at an extremely high mounting density, for example, at the same mounting efficiency as bare chip mounting.

The chip pad electrode 2, the substrate pad electrode 7, and the wire 10, that is, the portion for electrically connecting the chip 1 to the wiring board 5 are sealed with a resin 11. Therefore, the same level of reliability as a normal packaged product can be realized.

The electrical connection between the chip 1 and the wiring board 5 is performed by a wire bonding method.
For example, as compared with the connection by the flip-chip connection method, the non-defective rate particularly regarding the connection is increased. Also, compared to the TAB technique, the wire bonding method can similarly suppress the yield rate and the manufacturing cost. Since the increase in assembly cost can be suppressed in this manner, the device according to the present invention can be produced at lower cost, and has an advantage that a lower-cost semiconductor device can be provided to the market.

FIG. 6A is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 6B is a plan view of FIG.
It is sectional drawing which follows the BB line | wire in a middle. FIG. 6 (A), (B)
As shown in FIG. 2, in the second embodiment, a wiring board 5 having the same size as the outer shape of the chip 1 and having openings 31 corresponding to the chip pad electrodes 2 is used. The wire 10 connects the chip pad electrode 2 and the substrate pad electrode 7 via the opening 31.

According to the semiconductor device according to the second embodiment, the wiring board 5 provides the opening 31 in which the resin 11 can be filled around the wire 10. 10 has the effect of improving the sealing performance.

The aperture 31 is formed as shown in FIGS. 6A and 6B.
As shown in the above, one chip pad electrode 2 may be formed one by one, a plurality of chip pad electrodes 2 may be formed one by one, or a chip pad arranged along one side of the chip 1 It may be formed in a slit shape so that all of the electrodes 2 are exposed.

[0038] Even if deformed in this manner, an opening portion in which the resin 11 can be filled around the wire 10 can be obtained, so that the same effect as described above can be obtained. Also, the size of the wiring board 5 need not be the same as the outer shape of the chip 1 as long as it covers the chip pad electrode 2 and can form the opening 31.

FIG. 7A is a plan view of a semiconductor device according to the third embodiment of the present invention, and FIG. 7B is a plan view of FIG.
It is sectional drawing which follows the BB line | wire in a middle. FIG. 7 (A), (B)
As shown in FIG. 5, in the third embodiment, a resin dam 4 for preventing the resin 11 from being applied to the mounting bump electrodes 8 inside the region where the substrate pad electrodes 7 are arranged on the wiring substrate 5.
1 is formed.

According to the semiconductor device according to the third embodiment, the resin dam 41 can prevent the resin 11 from being applied to the mounting bump electrodes 8. For this reason, it is possible to suppress poor contact with the mounting substrate due to, for example, the resin 11 attached to the surface of the mounting bump electrode 8.

The resin dam 41 according to the third embodiment
Can also be formed on the wiring board 5 having the opening 31 according to the second embodiment. FIG. 8A is a plan view of a semiconductor device according to a fourth embodiment of the present invention, and FIG.
FIG. 9B is a cross-sectional view taken along the line BB in FIG.

As shown in FIGS. 8A and 8B, in the fourth embodiment, the upper surface of the resin 11 and the upper surface of the mounting bump electrode 8 are positioned on the same plane, The bump electrode 8 is made flat.

As shown in FIG. 9A, first, as shown in FIG. 9A, the chip 1 is sealed with a resin 11 so that the mounting bump electrodes 8 are buried, and then as shown in FIG. Next, the resin 11 is shaved by machining or the like so that the mounting bump electrodes 8 are exposed.

According to the semiconductor device according to the fourth embodiment, for example, when mounted on the mounting board 21, the mounting bump electrodes 8 can be covered with the resin 11, and the mounting bump electrodes 8 are not exposed to the outside. I can do it. Therefore, high reliability can be obtained in a mounted state.

The apparatus according to the fourth embodiment in which the upper surface of the resin 11 and the upper surface of the mounting bump electrode 8 are located on the same plane is the same as that of the first, second, and third embodiments. It can be applied to any of them.

[0046]

As described above, according to the present invention, a semiconductor device having the same level of efficiency as that of a bare chip while realizing the same level of reliability as a normal packaged product, and its manufacture. We can provide a method.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor device according to a first embodiment, and FIG. 1B is a cross-sectional view taken along line BB in FIG. 1A.

FIG. 2A is a plan view showing one manufacturing step of the semiconductor device according to the first embodiment, and FIG. 2B is FIG. 2A.
Sectional drawing which follows the BB line | wire in a middle.

FIG. 3A is a plan view showing one manufacturing step of the semiconductor device according to the first embodiment, and FIG. 3B is a view showing FIG. 3A;
Sectional drawing which follows the BB line | wire in a middle.

FIG. 4A is a plan view showing one manufacturing step of the semiconductor device according to the first embodiment, and FIG. 4B is a view showing FIG. 4A;
Sectional drawing which follows the BB line | wire in a middle.

FIG. 5 is a view showing a mounting state of the semiconductor device according to the first embodiment;

FIG. 6A is a plan view of a semiconductor device according to a second embodiment, and FIG. 6B is a cross-sectional view taken along line BB in FIG. 6A.

7A is a plan view of a semiconductor device according to a third embodiment, and FIG. 7B is a cross-sectional view taken along line BB in FIG. 7A.

FIG. 8A is a plan view of a semiconductor device according to a fourth embodiment, and FIG. 8B is a cross-sectional view taken along line BB in FIG. 8A.

FIGS. 9A and 9B are cross-sectional views of a semiconductor device according to a fourth embodiment in one manufacturing step.

FIG. 10 is a cross-sectional view of a conventional semiconductor device.

FIG. 11 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Chip pad electrode, 3 ... Passivation film, 4 ... Opening part, 5 ... Wiring board, 6 ... Adhesive layer (adhesive sheet), 7 ... Board pad electrode, 8 ... Bump electrode for mounting, 9 ... wiring layer, 10 ... bonding wire, 11 ... resin, 21 ... mounting board, 22 ... footprint, 31 ... opening, 41 ... resin dam.

Claims (8)

[Claims] A semiconductor chip having a chip pad electrode electrically connected to an integrated circuit; an electrode disposed on the semiconductor chip and serving as an external terminal of the integrated circuit; and electrically connected to the electrode. A wiring board having a size equal to or smaller than the outer shape of the semiconductor chip, each having a substrate pad electrode; connecting means for electrically connecting the chip pad electrode to the substrate pad electrode; the chip pad electrode; and the substrate pad electrode And a sealing means for sealing the connection means from the outside. 2. A semiconductor chip having a chip pad electrode electrically connected to an integrated circuit; an electrode disposed on the semiconductor chip and serving as an external terminal of the integrated circuit; and electrically connected to the electrode A wiring board having a substrate pad electrode and an opening corresponding to the chip pad electrode, the wiring board having a size substantially equal to the outer shape of the semiconductor chip; and forming the opening in the chip pad electrode and the substrate pad electrode. And a sealing means for electrically sealing the chip pad electrode, the substrate pad electrode, and the connection means from the outside. 3. The semiconductor device according to claim 1, wherein said sealing means is a resin. 4. The semiconductor device according to claim 1, further comprising a resin dam formed so as to surround a region of the wiring board on which the electrode serving as the external terminal is formed, wherein at least the connection unit is sealed with a resin and surrounded by the resin dam. 3. The semiconductor device according to claim 1, wherein the exposed region is exposed to the outside. 5. The semiconductor device according to claim 3, wherein an upper surface of the resin and an upper surface of the electrode serving as the external terminal are on the same plane. 6. A semiconductor device comprising a wiring pattern to which an electrode serving as an external terminal of the semiconductor device is connected, and a mounting substrate electrically connected to the semiconductor device to form a desired electrical product. The semiconductor device according to claim 1. 7. On a semiconductor chip having a chip pad electrode electrically connected to an integrated circuit, an electrode serving as an external terminal of the integrated circuit and a substrate pad electrode electrically connected to the electrode are provided. A step of bonding a wiring board having a size equal to or smaller than the outer shape of the semiconductor chip; a step of electrically connecting the chip pad electrode to the substrate pad electrode; the chip pad electrode, the substrate pad electrode, and the connection means And sealing each of the semiconductor devices from the outside world. 8. The step of sealing the chip pad electrode, the substrate pad electrode, and the connection means from the outside, respectively, is a step of covering the chip with a resin. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of retreating and positioning an upper surface of the resin and an upper surface of an electrode serving as the external terminal on the same plane.