JPH1084076A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a package of MCM IC (Multi-Chip Module). SOLUTION: A MCM IC 51 is provided with a small chip 10, a large chip 20, a wiring board 30 with electrical wiring 38 electrically connected between each of internal terminals 33 and each of external terminals 36, and an auxiliary frame 40 with electrical wiring 47 electrically connected between each of terminals 43 of the chips and each of terminals 46 of the board. The small chip 10 is arranged on the center of the wiring board 30 and each of electrode pads 13 is connected to each of the internal terminals 33 by each of connecting terminals 14. The auxiliary frame 40 engages the perimeter of the small chip 10 and each of the terminals 46 of the board is connected to each of the internal terminals 33 by each of connecting terminals 48. The large chip 20 is overlaid on the small chip 10 and the auxiliary frame 40 and each of electrode pads 23 is connected to each of the internal terminals 33 by each of connecting terminals 24. This enables a multifunction, multion, MCM IC of CSP (Chip Size Package) to be enabled by diverting various chips which have been developed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology for reducing a size of a package.
The present invention relates to a technology that is effective when used in a semiconductor integrated circuit device (hereinafter, referred to as an IC) having an ultra chip module package.

[Prior art]

In general, an MCM package has a plurality of semiconductor chips (hereinafter, referred to as chips) two-dimensionally arranged on a single wiring board, and is sealed with a resin sealing body or an airtight sealing body. It is configured.

[0003] As an example of the description of the MCM package, see "VLSI Packaging Technology (Lower)" P213 to P213-M issued on May 31, 1993 by Nikkei BP Co., Ltd.
253.

[0004]

As electronic devices using ICs become smaller and thinner, there is a demand for smaller IC packages. Therefore, a chip having a size equal to or substantially equal to the size of a semiconductor chip (hereinafter, referred to as a chip) in which an integrated circuit including a semiconductor element is built.
Size Package (Chip Size Packa)
ge or Chip Scale Package. Hereinafter, it is called CSP. ) Has been developed. The demand for reducing the size of the IC package is based on the fact that the
C is no exception.

However, in the conventional MCM package, since a plurality of chips are two-dimensionally arranged on one wiring board, the area in plan is smaller than the total area of the chips in plan. Will also be large.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of reducing a package of a semiconductor device having a plurality of semiconductor chips.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in the semiconductor device, a plurality of semiconductor chips having different main surface sizes are arranged so as to be stacked from the bottom on the first main surface of the wiring board in ascending order, and the internal terminals facing each other are arranged. It is characterized by being mechanically and electrically connected to the group.

In the above-described method of manufacturing a semiconductor device, the wiring in which the internal terminal group is formed on the first main surface and the external terminal group is formed on the second main surface, and each internal terminal is electrically connected to each external terminal. A wiring board preparing step in which a substrate is prepared; a semiconductor chip preparing step in which a plurality of semiconductor chips having different main surface sizes are prepared; And a connection step of being mechanically and electrically connected to the internal terminal groups facing each other.

In the semiconductor device described above, since a plurality of semiconductor chips are stacked on the wiring board, the area in plan view is substantially equal to the size of the semiconductor chip having the maximum plan view area.

According to the method of manufacturing a semiconductor device described above,
Since multiple semiconductor chips can be mounted without changing the function and internal structure, new development of ICs and major design changes can be omitted, and new products equivalent to one-chip packages can be developed. The period and various costs can be significantly reduced.

[0013]

1A and 1B show a semiconductor device according to an embodiment of the present invention. FIG. 1A is a partially cutaway plan view with a part omitted, and FIG. 1B is a bb line of FIG. Front sectional view along
(C) is a front sectional view taken along line cc of (a). FIG. 2 is an explanatory view of each step showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

In the present embodiment, the semiconductor device according to the present invention is an IC (hereinafter, referred to as M) having an MCM package.
CM / IC. ). As shown in FIG. 1, the MCM / IC 51 includes a chip 10 and a chip 20 whose plane shapes are different in size, and a group of internal terminals 33 formed on a first main surface 32 of a substrate main body 31.
A wiring board 30 on which a group of external terminals 36 is formed on the main surface 35 and each internal terminal 33 and each external terminal 36 are electrically connected by each electric wiring 38, and a first main surface 42 of the frame main body 41 on the chip side A group of terminals 43 is formed, a group of substrate-side terminals 46 is formed on the second main surface 45, and an auxiliary frame 40 in which each chip-side terminal 43 and each substrate-side terminal 46 are electrically connected by each electric wiring 47. ing.

The small chip 10 is arranged at the center of the first main surface 32 of the wiring board 30, and is mechanically and electrically connected to each internal terminal 33 facing each electrode pad 13 by each connection terminal 14. Have been. The auxiliary frame 40 is fitted on the outer periphery of the small chip 10, and each of the board-side terminals 46 is mechanically connected to each of the internal terminals 33 arranged on the periphery of the first main surface 32 of the wiring board 30 by each of the connection terminals 48. Connected electrically and electrically. The large chip 20 is disposed so as to overlap the small chip 10 and the auxiliary frame 40, and each electrode pad 23 is mechanically and electrically connected to each of the internal terminals 33 facing each other by the connection terminals 24. . The small chip 10, the large chip 20, and the auxiliary frame 40 are resin-sealed by a resin sealing body 50 formed on the first main surface 32 of the wiring board 30.

Hereinafter, an embodiment of the present invention will be described.
A method for manufacturing an IC will be described. By this explanation, the M
Details of the configuration of the CM / IC will be clarified.

As shown in FIG. 2, in the MCM / IC manufacturing method according to the present embodiment, a chip 10 having a small planar shape (hereinafter referred to as a small chip) and a small chip 10 having a planar shape are provided. (Hereinafter, referred to as a large chip) 20 is prepared. In both the small chip 10 and the large chip 20, desired semiconductor integrated circuits are formed in the state of a semiconductor wafer (not shown) in a so-called pre-process of the IC, and the small chip 10 and the large chip 20 are formed on the first main surface on the active area side. An electrode pad for electrically taking out the semiconductor integrated circuit to the outside is formed. In the dicing step, which is the first step of the so-called post-processing of the IC, the semiconductor wafer is divided into small square flat plates, so that the small chips 10 and the large chips 20 are manufactured.

As shown in FIGS. 2A and 2B, a first chip on the active area side of the small chip 10 is formed.
On the main surface 11, a large number of electrode pads 13 are arranged in a matrix over substantially the entire surface. Each electrode pad 1
Reference numeral 3 is configured to be mechanically and electrically connectable to bumps of a wiring board described later. Note that reference numeral 12 denotes a second main surface opposite to the active area side.

As shown in FIGS. 2C and 2D, a first chip on the active area side of the large chip 20 is formed.
A large number of electrode pads 23 are arranged on the main surface 21 in an array at the periphery. Each electrode pad 23 is configured so as to be able to be mechanically and electrically connected to a bump of a wiring board described later. The size of the large chip 20 in a plan view is set so as to be larger than the small chip 10 by at least the amount by which the rows of the electrode pads 23 protrude.
Reference numeral 22 denotes a second main surface opposite to the active area side.

On the other hand, in a wiring board preparation step, the wiring board 30 shown in FIG. 3 is manufactured. The wiring substrate 30 shown in FIG. 3 is a substrate main body (hereinafter, referred to as a substrate) formed of an insulating substrate such as ceramic or glass impregnated epoxy resin.
It is called the body. The main body 31 is formed in a square plate shape having an outer diameter slightly larger than the outer diameter of the auxiliary frame 40 described later.

On the first main surface 32 of the main body 31, a large number of internal terminals 33 are arranged in a matrix over substantially the entire surface. Each internal terminal 33 has an internal terminal bump (hereinafter, referred to as a bump).
34 (referred to as inner bumps). Internal terminal 33
Are set so as to be the sum of the number of electrode pads 13 of the small chip 10 and the number of electrode pads 23 of the large chip 20, and the arrangement of the internal terminals 33 is And the arrangement of the electrode pads 23 of the large chip 20 are set. The inner bumps 34 are formed of an appropriate protrusion such as a hemisphere by using a conductive material such as gold (Au) by a plating method, a vapor deposition method, a wire bonding method, or the like. The outer diameter of the inner bump 34 is set to be slightly larger than the outer diameter of each of the electrode pads 13 and 23.

On the second main surface 35 of the main body 31, a large number of external terminals 36 are arranged in an array at the outer peripheral portion. The external terminals 36 are external terminal bumps (hereinafter referred to as external bumps) 37. Is protruding. The number of the external terminals 36 is set to be equal to the number of the internal terminals 33, and the arrangement of the external terminals 36 is set so as to conform to the standard of a mounting board (not shown). The outer bumps 37 are formed of an appropriate protrusion such as a hemisphere by using a solder material generally used when mounting an IC and by welding a solder ball or the like.

Inside the main body 31, a number of electric wires 38 for electrically connecting the internal terminals 33 and the external terminals 36 are laid so as to be electrically independent of each other.

In this embodiment, the auxiliary frame 40 shown in FIG. 4 is manufactured. The auxiliary frame 40 shown in FIG. 4 has a frame main body 41 formed in a frame shape by an insulating material such as ceramic or glass impregnated epoxy resin, and the frame main body 41 is slightly larger than the outer diameter of the small chip 10. And an outer diameter slightly smaller than the outer diameter of the wiring board 30. Frame body 41
Is set to be substantially equal to the thickness of the small chip 10.

A plurality of chip-side terminals 43 are arranged in an array on the first main surface 42 of the frame main body 41, and each chip-side terminal 43 has a frame bump 44 projecting therefrom. The number of chip terminals 43 is set to be equal to the number of electrode pads 23 of the large chip 20.
Are set so as to correspond to the positions of the electrode pads 23 of the large chip 20. The frame bumps 44 are formed of an appropriate protrusion such as a hemisphere by using a conductive material such as gold (Au) by a plating method, a vapor deposition method, a wire bonding method, or the like. The outer diameter of the frame bump 44 is set to be slightly larger than the outer diameter of the electrode pad 23 of the large chip 20.

On the second main surface 45 of the frame body 41, the same number of substrate-side terminals 46 as the chip-side terminals 43 are arranged in an array. Are set to correspond to the external terminals 36 in the outer peripheral portion. A large number of electric wires 47 for electrically connecting the chip-side terminals 43 and the substrate-side terminals 46 are laid inside the frame main body 41 so as to be electrically independent from each other.

The small chip 10 is mounted on the wiring board 30 having the above structure prepared in the wiring board preparing step, and is mechanically and electrically connected by the flip chip method as shown in FIG. 5 in the small chip connecting step. Connected. That is,
As shown in FIG. 5A, the small chip 10
With the main surface 11 side facing the first main surface 32 side of the wiring board 30,
In addition, the electrode pads 13 of the small chip 10 are aligned concentrically with the inner bumps 34 at the center of the group of the inner bumps 34 of the wiring board 30. When the small chip 10 and the wiring board 30 are pressed against each other under heating, the respective electrode pads 13 and the respective inner bumps 34 are thermocompression-bonded to form the connection terminals 14 shown in FIG. Therefore, the small chip 10 and the wiring board 30 are mechanically and electrically connected.

The assembly in which the small chip 10 and the wiring board 30 are connected as described above is provided with the auxiliary frame 4 having the above configuration.
0 are mechanically and electrically connected by the flip chip method in the auxiliary frame connecting step as shown in FIG. That is, as shown in FIG.
When the auxiliary frame 40 is fitted on the outer periphery of the small chip 10 with the second main surface 45 side facing the first main surface 32 side of the wiring board 30, each substrate-side terminal 46 of the auxiliary frame 40 and the wiring board The inner bumps 34 exposed at the outer peripheral portion of the small chip 10 among the 30 inner bumps 34 are aligned. When the auxiliary frame 40 and the wiring board 30 are pressed against each other under heating, each of the board-side terminals 46
And the respective inner bumps 34 are thermocompression-bonded to form the connection terminals 48 shown in FIG. 6B, respectively, so that the auxiliary frame 40 and the wiring board 30 are mechanically and electrically connected. State.

As described above, the large chip 20 is attached to the assembly in which the small chip wiring board assembly and the auxiliary frame 40 are connected.
Are mechanically and electrically connected by a flip chip method as shown in FIG. 7 in a large chip connecting step. That is, as shown in FIG.
The large chip 20 is arranged concentrically with the first main surface 21 side facing the second main surface 12 side of the small chip 10, and the electrode pads 23 of the large chip 20 and the frame bumps 44 of the auxiliary frame 40 are arranged.
And are matched. When the large chip 20 and the auxiliary frame 40 are pressed against each other under heating, the electrode pads 23 and the frame bumps 44 are thermocompression-bonded, and the connection terminals 24 shown in FIG.
Are formed, the large chip 20 and the auxiliary frame 40 are formed.
Is in a state of being mechanically and electrically connected. Since the auxiliary frame 40 is electrically connected to the wiring board 30 by the connection terminal 48, the large chip 20 is electrically connected to the wiring board 30 via the auxiliary frame 40.

In the resin sealing body forming step (not shown), the resin sealing body 50 shown in FIG. 1 is attached to the wiring board 30 to which the small chip 10 and the large chip 20 are connected as described above. Small chip 10, large chip 20, and auxiliary frame 4
0 is molded so as to be sealed with resin. In this state, the semiconductor integrated circuit of the small chip 10
3, the connection terminals 14, the internal terminals 33 of the wiring board 30, the electric wiring 38, and the external bumps 37 are electrically drawn to the outer bumps 37 of the wiring board 30 via the external terminals. Further, the semiconductor integrated circuit of the large chip 20 includes the electrode pad 2
3, connection terminal 24, chip-side terminal 43 of auxiliary frame 40, electric wiring 47, board-side terminal 46, connection terminal 48, internal terminal 33 of wiring board 30, electric wiring 38 and external terminal 36
Through the outer bumps 37 of the wiring board 30 through the wiring board 30.

According to the above embodiment, the following effects can be obtained. A package is arranged by arranging large and small chips from the bottom in the ascending order on the first main surface of the wiring board, and mechanically and electrically connecting the electrode pads of each chip to the internal terminal groups facing each other. Can be reduced to be almost equal to the size of a large chip.
Can be realized.

Since various chips already developed as large and small chips constituting the MCM / IC can be used without changing the functions and the internal structure, new development of the MCM / IC and significant design changes are omitted. Can be one-
The development time and costs of a new product equivalent to a chip package can be significantly reduced.

FIG. 8 shows a semiconductor device according to a second embodiment of the present invention, wherein FIG.
(B) is a front sectional view taken along line bb of (a), and (c) is a front sectional view taken along line cc of (a).

The second embodiment is different from the first embodiment in that the auxiliary frame is omitted and formed by external bumps (not shown) arranged on the outer peripheral portion of the first main surface 32 of the wiring board 30. The large-sized chip 20 is directly and mechanically and electrically connected to the wiring board 30 by the tall connection terminals 25 formed as described above.

According to the second embodiment, in addition to the effect of the first embodiment, since the auxiliary frame is omitted, the effect that the manufacturing cost can be further reduced can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various changes can be made without departing from the gist of the invention. Needless to say.

The number of chips to be stacked is not limited to two large and small, but may be three large, medium, and small or more.

The bumps for forming the connection terminals are not limited to being provided on the wiring board, but may be provided on each chip.

The sealing body for sealing the chip and the connection terminal group is as follows:
The present invention is not limited to a resin-sealed body, but may be a hermetically sealed body.

The outer leads projecting from the external terminals of the wiring board are formed by solder ball bumps and grids (b).
The configuration is not limited to an all grid array structure, but may be a pin grid array (pin grid array).
ray) structure or the like.

In the above description, the invention made mainly by the present inventor is referred to as the MCM, which is the field of application that served as the background.
The case where the present invention is applied to an IC has been described. However, the present invention is not limited to this. The present invention can be applied to a general semiconductor device on which a plurality of chips are mounted, such as a hybrid IC. In particular, the present invention can achieve excellent effects when applied to a semiconductor device having a multi-function, multi-pin, and small package.

[0042]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

The large and small chips are arranged so as to be stacked on the first main surface of the wiring board from the bottom in ascending order.
By mechanically and electrically connecting the electrode pads of each chip to the opposing internal terminal groups, the package size can be reduced approximately equal to the size of a large chip, so that it is multifunctional and has many pins. A semiconductor device with a small package can be formed.

Since various chips already developed as large and small chips constituting the semiconductor device can be used without changing the functions and the internal structure, it is possible to omit the new development of the semiconductor device and major design changes. And one chip
The development time and costs of new products equivalent to packages can be significantly reduced.

[Brief description of the drawings]

1A and 1B show a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a partially cutaway plan view with a part omitted, FIG. 1B is a front sectional view taken along line bb of FIG. (C) is a front sectional view taken along line cc of (a).

FIGS. 2A and 2B are a partially cut front view and a partially omitted bottom view showing a small chip. (C) and (d) are a partially cut front view and a partially omitted bottom view showing a large chip.

3A and 3B show a wiring board used in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A is a partially cut front view, FIG. Half is a bottom view.

4 (a) is a partially cut front view, FIG. 4 (b) is a plan view of an upper half, and a bottom view of a lower half.

5A and 5B show a small chip connecting step in a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 5A is a partially cut front view at the time of connection, and FIG. It is a front view.

6A and 6B also show an auxiliary frame connecting step, in which FIG. 6A is a partially cut front view at the time of connection, and FIG. 6B is a partially cut front view after connection.

FIG. 7 also shows a large chip connection step, and (a)
Is a partially cut front view at the time of connection, and (b) is a partially cut front view after connection.

8A and 8B show a semiconductor device according to a second embodiment of the present invention, wherein FIG. 8A is a partially cutaway plan view with a part omitted, FIG. 8B is a front sectional view taken along line bb of FIG. (C) is a front sectional view taken along line cc of (a).

[Explanation of symbols]

10: small chip (semiconductor chip), 11: first main surface, 1
2: second main surface, 13: electrode pad, 14: connection terminal, 2
0: large chip (semiconductor chip), 21: first main surface, 22
... 2nd main surface, 23 ... electrode pad, 24 ... connection terminal, 25
... tall connection terminals, 30 ... wiring board, 31 ... substrate body, 32 ... first main surface, 33 ... internal terminals, 34 ... internal terminal bumps (inner bumps), 35 ... second main surface, 36 ... external Terminals, 37: external terminal bumps (outer bumps), 38: electric wiring, 40: auxiliary frame, 41: frame body, 42: first main surface,
43: chip side terminal, 44: frame bump, 45: second main surface, 46: substrate side terminal, 47: electric wiring, 48: connection terminal, 50: resin sealing body, 51: MCM / IC (semiconductor device) .

Claims (6)

[Claims] A wiring board in which an internal terminal group is formed on a first main surface and an external terminal group is formed on a second main surface, and each internal terminal is electrically connected to each external terminal; And a plurality of semiconductor chips having different sizes, wherein the semiconductor chips are arranged so as to be stacked on the first main surface of the wiring board from below in ascending order, and the internal terminal groups facing each other A semiconductor device that is mechanically and electrically connected to the semiconductor device. 2. A small semiconductor chip is disposed at the center of the first main surface of the wiring substrate and is mechanically and electrically connected to a group of opposing internal terminals. And a connection terminal group of an auxiliary frame which is disposed concentrically on the first wiring board and which is disposed on the periphery of the first main surface of the wiring board and mechanically and electrically connected to the internal terminals on the periphery. 2. The semiconductor device according to claim 1, wherein the semiconductor device is mechanically and electrically connected to the semiconductor device. 3. A small semiconductor chip is disposed at the center of the first main surface of the wiring board and mechanically and electrically connected to opposing internal terminals. 2. The wiring board according to claim 1, wherein the wiring board is arranged so as to be concentric with the wiring board, and is mechanically and electrically connected to an internal terminal group around the first main surface of the wiring board. Semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 1, comprising the following steps: (a) an internal terminal group is formed on a first main surface, and an external terminal group is formed on a second main surface. A wiring board preparing step in which a wiring board in which each internal terminal and each external terminal are electrically connected is prepared; (b) a semiconductor chip preparing step in which a plurality of semiconductor chips having different main surface sizes are prepared; (C) a connection in which the semiconductor chips are arranged from the bottom in the ascending order so as to be stacked on the first main surface of the wiring substrate, and are mechanically and electrically connected to the internal terminal groups facing each other; Process. 5. In the connecting step, a small semiconductor chip is arranged at the center of the first main surface of the wiring board and mechanically and electrically connected to a group of internal terminals facing each other. Connection of an auxiliary frame disposed concentrically on the chip and disposed at the periphery of the first main surface of the wiring board and mechanically and electrically connected to the internal terminals at the periphery The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is mechanically and electrically connected to the terminal group. 6. In the connecting step, a small semiconductor chip is arranged at the center of the first main surface of the wiring substrate and mechanically and electrically connected to a group of opposing internal terminals. 5. The semiconductor device according to claim 4, wherein the semiconductor device is disposed concentrically on the chip and is mechanically and electrically connected to a group of internal terminals in a peripheral portion of the first main surface of the wiring board. Of manufacturing a semiconductor device.