JPH0955400A - Electronic part and method for mounting electronic part - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount an electronic part on a wiring board accurately and readily. SOLUTION: A plurality of first dummy bumps 15 are formed on an electronic part 11, and second dummy bumps 17 having the melting point between a first bump 13 and the first dummy bump 15 are formed. Thus, the position deviation is corrected, and the mounting can be performed. A plurality of the first dummy bumps 15 are formed on the electronic part 11, and a plurality of the second dummy bumps 17 are formed. At the same time, a plurality of third dummy bumps and a plurality of fourth dummy bumps are formed. Then, the positions of the first dummy bumps 15 and the respective third dummy bumps are aligned, and the bumps are bonded. The respective second dummy bump 17 and the respective fourth dummy bump are bonded. The respective first bump 13 and the respective second bump are bonded. Thus, the position deviation is corrected, and the mounting can be performed.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIGS. 8 and 9) Problems to be Solved by the Invention (FIGS. 8 and 9) Means for Solving the Problems (FIGS. 1 to 7) Embodiments of the Invention (FIGS. 1 to 7) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component and a method for mounting the electronic component, and is suitable for application to, for example, a bare chip and a mounting method for mounting the bare chip on a wiring board.

[0003]

2. Description of the Related Art Conventionally, semiconductor integrated circuits (hereinafter referred to as I
There is a so-called bare chip in which a wafer on which a plurality of (C circuits) are formed is cut and separated into individual chips for each IC circuit.

Usually, in the mounting work of this kind of electronic component, a plurality of bonding bumps (hereinafter referred to as chip side bumps) made of solder are respectively provided on a plurality of electrodes formed on the circuit surface of the bare chip. After each chip-side bump is positioned and mounted on the wiring board so as to come into contact with the bonding bumps made of solder provided on the corresponding electrodes of the wiring board (hereinafter referred to as board-side bumps), These chip-side bumps and substrate-side bumps are heated and melted (hereinafter referred to as reflow) and joined (hereinafter referred to as a first mounting method). Therefore, as shown in FIG. 8, the bare chip 2 mounted on the wiring board 1 by such a first mounting method has electrodes 4 on the wiring board 1 side corresponding to the electrodes 3 on the bare chip 2 side. Then, each chip-side bump is mounted on the wiring board 1 in a state of being bonded to the corresponding board-side bump via the bump 5 formed by fusion and integration.

In addition to the first mounting method as described above,
As shown in FIG. 9 in which parts corresponding to those in FIG. 8 are denoted by the same reference numerals, a metal film (hereinafter referred to as a chip-side metal film) 7 is formed at a predetermined position on the circuit surface 6A of the bare chip 6. At the same time, a metal film (hereinafter referred to as a substrate-side metal film) 9 having substantially the same shape is formed at a position of the wiring substrate 8 facing the chip-side metal film 7, and the chip-side metal film 7 and the substrate-side metal film A method of mounting on the insulating substrate 8 by bonding the film 9 and the bumps 10 with the bumps 10 having substantially the same melting point (hereinafter,
This is called the second mounting method).

In this case, generally, when the bare chip 6 is mounted on the wiring board 8, the bumps 5 are formed on the respective bumps 5 due to a temperature change during reflow and after reflow due to a difference in thermal expansion coefficient between the bare chip 6 and the wiring board 8. Although thermal stress is generated, according to this second mounting method, the thermal stress can be dispersed in the bump 10 portion between the chip-side metal film 7 and the substrate-side metal film 9, and thus the thermal stress is applied to each bump 5. There is an advantage that stress concentration can be avoided. Further, according to this second mounting method, at the time of mounting, the chip side metal film 7 and the substrate side metal film 9 are mounted.
When each of the above bumps is reflowed and melted, there is an advantage that a slight misalignment of the bare chip 6 with respect to the wiring board 8 is corrected by the self-alignment effect of the melted solder.

[0007]

However, according to the first and second mounting methods as described above, when mounting the bare chip 2 on the wiring board 1, the chip-side bumps and the board-side bumps are surely separated from each other. There is a problem that it is necessary to perform highly accurate alignment using X-rays or the like in order to join the two. In addition, in these alignment operations, the chip bumps and the corresponding board bumps are aligned one by one or in plurals, so that the bare chip 2 is mounted on the wiring substrate 1 without causing positional displacement. Requires a long working time, and there is a problem that the mounting tact time per one bare chip 2 becomes long.

Further, in the above-described first and second mounting methods, when the chip-side bumps and the corresponding substrate-side bumps are aligned and then joined by a method such as reflow, hot air or the like generated in the reflow furnace is used. Due to
There is a problem in that each chip side bump and each corresponding substrate side bump are misaligned.

Further, in the first and second mounting methods, when the bare chip 2 is aligned on the wiring board 1, the bare chip 2 may be displaced relative to the wiring board 1 in the rotational direction. In the first and second mounting methods, there is a problem of mounting without correcting the positional deviation of the bare chip 2 with respect to the wiring board 1 in the rotational direction.

The present invention has been made in consideration of the above points, and an object thereof is to propose an electronic component and an electronic component mounting method which can be mounted on a wiring board with high accuracy and easily.

[0011]

In order to solve such a problem, in the first invention, a plurality of first bumps for bonding are formed on one surface, and each of the first bumps is formed on a predetermined surface of a wiring board. In the electronic component to be mounted on the wiring board by being bonded to the corresponding second bumps for bonding, which are formed in the central portion of one surface,
One or a plurality of first dummy bumps having a melting point temperature characteristic lower than that of the first bumps, and a melting point temperature of the first bumps and a melting point temperature of the first dummy bumps which are formed so as to surround the first dummy bumps on one surface. A single or a plurality of second dummy bumps having a predetermined melting point temperature characteristic set between the temperatures is provided, and each first dummy bump has the same melting point temperature characteristic as the first dummy bump. In addition, each second dummy bump is bonded to a third dummy bump formed corresponding to a predetermined surface of the wiring board, and each second dummy bump has the same melting point temperature characteristic as that of the second dummy bump. The wiring board is mounted on the wiring board by being joined to the fourth dummy bump formed corresponding to the surface.

Further, in the second invention, a plurality of first bumps for bonding are formed on one surface, and each of the first bumps is bonded.
In the method of mounting an electronic component on the wiring board by bonding the bumps of the above to the corresponding second bumps for bonding formed on the predetermined surface of the wiring substrate, the first part is formed on the central portion of the one surface of the electronic component. One or a plurality of first dummy bumps having a melting point temperature characteristic lower than that of the first bump are formed, and a predetermined melting point temperature characteristic set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump on one surface. A second dummy bump or bumps having a first dummy bump
And surrounding the first dummy bump and the second dummy bump on the predetermined surface of the wiring substrate facing the first dummy bump and the second dummy bump when mounting the electronic component on the wiring substrate. Forming a single or a plurality of third dummy bumps having the same, and forming a single or a plurality of fourth dummy bumps having the same melting point temperature characteristics as the second dummy bump, and each first dummy bump of the electronic component. And a second step of aligning and joining the corresponding third dummy bumps of the wiring board,
A third step of joining the second dummy bumps of the electronic component and the corresponding fourth dummy bumps of the wiring substrate together with the first bumps of the electronic component and the corresponding second bumps of the wiring substrate are performed. And a fourth step of joining.

As a result, in the first invention, a single or a plurality of first bumps having a melting point temperature characteristic lower than that of the first bumps is formed in the central portion of one surface of the electronic component on which the plurality of first bumps for bonding are formed. A dummy bump is formed, and one or more second dummy bumps having predetermined melting point temperature characteristics set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump so as to surround the first dummy bump on one surface. And each first dummy bump is joined to a third dummy bump that has the same melting point temperature characteristics as the first dummy bump and is formed corresponding to a predetermined surface of the wiring board. Each of the second dummy bumps has a fourth melting point characteristic which is the same as that of the second dummy bump and is formed so as to correspond to a predetermined surface of the wiring board. By joining the first and third dummy bumps and the second and fourth dummy bumps to each other, the self-alignment effect is exerted by the surface tension of the metal formed by melting the first and third dummy bumps, and the X , Y direction and rotation direction can be mounted while correcting the positional deviation.

In the second invention, a single or a plurality of first dummy bumps having melting point temperature characteristics lower than those of the first bumps are formed in a central portion of one surface of an electronic component on which a plurality of first bumps for bonding are formed. And forming a single or a plurality of second dummy bumps having a predetermined melting point temperature characteristic set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump on one surface so as to surround the first dummy bump. Which has the same melting point temperature characteristic as that of the first dummy bump on a predetermined surface of the wiring substrate facing the first dummy bumps and the second dummy bumps when the electronic component is mounted on the wiring substrate. And the fourth dummy bump having the same melting point temperature characteristic as the second dummy bump are formed, and then the third dummy bump is formed. The first dummy bumps of the component and the corresponding third dummy bumps of the wiring board are aligned and joined together, and then the second dummy bumps of the electronic component and the corresponding fourth dummy bumps of the wiring board are connected. A metal formed by melting the first dummy bumps and the third dummy bumps by joining the first bumps of the electronic component and the corresponding second bumps of the wiring board. The self-alignment effect is activated by the surface tension of the metal and after the positional deviation of the electronic component with respect to the wiring board in the X and Y directions is corrected, the surface tension of the metal formed by melting the second dummy bumps and the fourth dummy bumps. As a result, the self-alignment effect works and the positional deviation of the electronic component with respect to the wiring board in the rotational direction can be corrected.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

1 (A) to 2 (B), the structure of the bare chip 11 and the wiring board 21 to which the present invention is applied is shown. First, as shown in FIGS. 1 (A) and 1 (B), the bare chip 11 has a plurality of electrodes (hereinafter, referred to as chip-side electrodes) 12 in a predetermined pitch along the outermost periphery of the circuit surface 11A.
Are arranged. On each of these chip side electrodes 12,
Bonding bumps 13 (hereinafter, referred to as chip-side bumps) 13 made of, for example, high melting point solder, are formed so as to project to a predetermined height.

In the bare chip 11, a rectangular first metal film (hereinafter referred to as a first chip side metal film) is formed on the passivation film (not shown) in the central portion of the circuit surface 11A. 14 are provided. At the center of the first chip-side metal film 14, a dummy bump having a melting point lower than that of the chip-side bump 13, for example, a low-melting-point solder (hereinafter, this is used for correcting misalignment in the X and Y directions during mounting). Is referred to as a first chip side dummy bump) 15 is formed so as to project at the same height as the chip side bump 13.

Further, in the bare chip 11, four passivation films around the first chip-side metal film 14 in the shape of a quadrangle are provided on the passivation film around the vertices in the shape of a quadrangle. (Hereinafter, these are referred to as a second chip side metal film) 16. On each of these second chip-side metal films 16, chip-side bumps 13 are respectively provided for positional deviation correction in the rotation direction during mounting.
Lower melting point than the first chip side dummy bump 1
Each second chip-side metal is formed so that the dummy bumps 17 having a melting point higher than 5 and made of, for example, eutectic solder (hereinafter, referred to as second chip-side dummy bumps) have the same height as the chip-side bumps 13. It is formed in an arched shape so as to match the shape of the film 16.

In this case, in the bare chip 11, the circuit surface 11
The sum of the areas of the first chip-side metal film 14 and each second chip-side metal film 16 is selected so that the area is about 1/10 to 1/4 of the area A. As a result, in the bare chip 11, the first chip-side dummy bump 1
5 and each of the second chip-side dummy bumps 17 can have a large surface area, thus increasing the surface tension when the first chip-side dummy bumps 15 and each of the second chip-side dummy bumps 17 are melted. Has been done.

On the other hand, as shown in FIGS. 2 (A) and 2 (B),
On the mounting surface 21A of the wiring board 21, each chip side electrode 12 of the bare chip 11, the first chip side metal film 14,
A plurality of electrodes (hereinafter referred to as substrate side electrodes) 22 corresponding to the respective second chip side metal films 16;
Metal film (hereinafter, referred to as a first substrate-side metal film) 2
3 and a plurality of second metal films (hereinafter, referred to as a second substrate-side metal film) 24.

Bonding bumps 25 (hereinafter referred to as substrate bumps) 25 are formed on each substrate electrode 22 so as to have the same shape as each substrate electrode 22 at a predetermined height. It is composed of the same composition as each chip-side bump 13 formed on each chip-side electrode 12 (FIG. 1). Further, on the first substrate-side metal film 23, the first dummy bumps (hereinafter, referred to as the first substrate-side dummy bumps) 26 have the same height as the substrate-side bumps 25 and the first substrate-side metal. It is formed to have the same shape as the film 23 and has the same composition as the first chip-side dummy bump 15 formed on the first chip-side metal film 14 (FIG. 1). Further, second dummy bumps 27 (hereinafter, referred to as second substrate side dummy bumps) 27 are formed on the respective second substrate side metal films 24 at the same height as the substrate side bumps 25. The second chip-side dummy bumps 17 are formed so as to have the same shape as the metal film 24 and are formed on the second chip-side metal films 16 (FIG. 1), and have the same composition.

As a result, in the wiring substrate 21, the bumps 25 on the substrate side, the dummy bumps 26 on the first substrate side, the dummy bumps 27 on the second substrate side, and the bare chip 1 respectively.
The corresponding one chip-side bump 13, the first chip-side dummy bump 15 and the second chip-side dummy bump 17 can be positioned and mounted, and the bare chip 11 can be mounted in that state.

In practice, this bare chip 11 is shown in FIG.
~ It can be mounted on the wiring board 21 by the following procedure shown in FIG. That is, as shown in FIG. 3, first, the bare chip 11 is held on the mounting surface 21A of the wiring board 21 so that the circuit surfaces 11A face each other at a predetermined interval, and in this state, the first substrate-side metal film 23 is held. The center of the first chip-side dummy bumps 15 formed on the first chip-side metal film 14 is positioned at the center of the first substrate-side dummy bumps 26 formed above.

Next, as shown in FIG. 4, each chip-side bump 13, each chip-side bump 13 of the bare chip 11 with respect to each board-side bump 25, the first board-side dummy bump 26 and each second board-side dummy bump 27 of the wiring board 21, The first chip-side dummy bumps 15 and the respective second chip-side dummy bumps 17 are aligned and brought into contact with each other.

Then, as shown in FIG.
The wiring substrate 21 temporarily fixed to the substrate is placed in a reflow furnace (not shown), and the temperature is such that only the first chip-side dummy bumps 15 and the first substrate-side dummy bumps 26 are melted (for example, low melting point solder The first chip-side dummy bumps 15 and the first substrate-side dummy bumps 26 are melted and joined by heating at a melting temperature of about 150 ° C.).

By the way, when the bare chip 11 is aligned on the wiring board 21, the first chip side dummy bumps 1 are formed.
A misalignment may occur between the central part of No. 5 and the central part of the first substrate-side dummy bump 26. However, this misalignment is corrected to the correct alignment state by the self-alignment effect of the solder when the first chip-side dummy bump 15 and the first substrate-side dummy bump 26 are melted.

Next, as shown in FIG. 6, the chip-side bumps 13 and the board-side bumps 25 of the wiring board 21 do not melt, but the second chip-side dummy bumps 17 and the second board-side dummy bumps 27 melt. By heating at a temperature (for example, a temperature of about 183 [° C.] at which the eutectic solder is melted) for each second chip-side dummy bump 17
Then, the second substrate-side dummy bumps 27 are melted and joined.

By the way, when the bare chip 11 is aligned on the wiring board 21, or when the positional deviation between the central portion of the first chip side dummy bump 15 and the central portion of the first substrate side dummy bump 26 is corrected by reflow. In addition, there may be a displacement (that is, a displacement in the rotational direction) between each second chip-side dummy bump 17 and each second substrate-side dummy bump 27. However, this positional deviation in the rotational direction is corrected to the correct alignment state by the self-alignment effect of the solder when the second chip-side dummy bumps 17 and the corresponding second substrate-side dummy bumps 27 are melted.

Subsequently, as shown in FIG. 7, the wiring substrate 21 is heated at a temperature at which the chip-side bumps 13 and the substrate-side bumps 25 are melted (for example, a temperature at which the high melting point solder is melted), The chip-side bumps 13 and the corresponding substrate-side bumps 25 are melted and joined. This allows the bare chip 11 to be mounted on the wiring board 21 while sequentially correcting the positional deviation of the bare chip 11 with respect to the wiring board 21 in the X, Y and rotation directions.

In this embodiment, the first chip-side dummy bump 15 having a melting point lower than that of the chip-side bump 13 for bonding is provided at the center of the circuit surface 11A of the bare chip 11, and the first chip-side dummy bump 15 is provided. A plurality of second chip-side dummy bumps 17 having a lower melting point than the chip-side bumps 13 and a higher melting point than the first chip-side dummy bumps 15 are provided around the chip-side dummy bumps 15, while the mounting surface 21A of the wiring board 21 is provided. The first chip-side dummy bumps 15 and the second chip-side dummy bumps 17 corresponding to the first chip-side dummy bumps 15 and the respective second chip-side dummy bumps 17 of the bare chip 11 are the same as above. A first substrate side dummy bump 26 and a second substrate side dummy bump 27 having a melting point are provided.

Next, this bare chip 11 is connected to the wiring board 21.
After positioning and mounting so that the corresponding bumps come into contact with each other (FIGS. 3 and 4), the wiring board 21 is put in a reflow furnace and the first chip side dummy bumps 15 and the first substrate side dummy bumps 26 are placed. The first chip-side dummy bumps 15 and the first substrate-side dummy bumps 26 are melted and integrated by heating at a temperature to such an extent that they melt (FIG. 5). Subsequently, the temperature inside the reflow furnace is raised to a temperature at which the second chip-side dummy bumps 17 and the second substrate-side dummy bumps 27 are melted, so that the second chip-side dummy bumps 17 and the second substrate-side dummy bumps 27 are melted. Are melted and integrated (FIG. 6). Further, the temperature inside the reflow furnace is controlled by the bump 13 on the chip side.
By raising the temperature to such a degree that the substrate-side bumps 25 are melted, the chip-side bumps 13 and the substrate-side bumps 25 are melted and integrated, and thus the bare chip 11
Are electrically and physically bonded onto the wiring board 21 (FIG. 7).

In this case, as described above, the positional deviation generated between the central portion of the first chip side dummy bump 15 and the central portion of the first substrate side dummy bump 26 is the same as that of the first chip side dummy bump 15 and When the first substrate-side dummy bumps 26 are melted, the self-alignment effect of the solder corrects them to correct alignment. Further, the positional deviation (that is, the positional deviation in the rotational direction) between the second chip-side dummy bumps 17 and the respective second substrate-side dummy bumps 27 is caused by the respective second chip-side dummy bumps 17 and the corresponding first-side dummy bumps 17. Substrate side dummy bump 27
When the solder melts, the self-alignment effect of the solder corrects each to the correct alignment.

Accordingly, in this mounting method, the positional deviation of the bare chip 11 with respect to the wiring board 21 in the X, Y and rotational directions can be sequentially corrected by gradually increasing the temperature and reflowing during mounting. . As a result, the alignment time can be shortened without the need for precise alignment using X-rays or the like before reflow, and thus 1
It is possible to reduce the mounting tact tom per one bear chip 11.

Further, in this embodiment, the first chip side metal film 14 of the bare chip 11 and each second chip side metal film 16 are provided.
And the sum of the areas of the first board-side metal film 23 and the second board-side metal film 24 of the wiring board 21 with respect to the surface area of the circuit surface 11A of the bare chip 11 by 10 minutes. 1
Therefore, the surface area of the first chip side dummy bumps 15 and the respective second chip side dummy bumps 17, the first substrate side dummy bumps 26 and the respective second substrate side dummy bumps 27 are Can be secured sufficiently large, and thus the surface tension can also be sufficiently large. As a result, it is possible to minimize the positional deviation of the bare chip 11 with respect to the wiring board 21 in the X, Y and rotation directions during the reflow.

According to the above construction, each chip-side bump 13 is provided at the same height as the original plurality of chip-side bumps 13 for bonding at the center of the circuit surface 11A of the bare chip 11.
A plurality of second chip sides each having a bow shape having a lower melting point than each of the chip side bumps 13 and a higher melting point than the first chip side dummy bumps 15. The dummy bumps 17 are formed so as to surround the first chip-side dummy bumps 15, and the bare chips 11 are formed on the mounting surface 21A of the wiring board 21.
Of the first chip-side dummy bumps 15 and the respective second chip-side dummy bumps 17 of
The chip-side dummy bumps 15, the first substrate-side dummy bumps 26 having the same melting point as the second chip-side dummy bumps 17, and the second substrate-side dummy bumps 27 are the same as the plurality of substrate-side bumps 25 for original bonding. It is formed to a height, and then the bare chip 11 is positioned and placed on a predetermined position of the wiring board 21, and the first chip side dummy bump 1
5 and the first substrate-side dummy bumps 26 are heated and melt-bonded at a temperature at which they melt, and then each second chip-side dummy bump 17 and each second substrate-side dummy bump 2
7 is heated at their melting temperature to be melt-bonded, and subsequently each chip-side bump 13 and each substrate-side bump 22 is heated at their melting temperature to be melt-bonded to place the bare chip 11 on the wiring board 21. Due to the mounting, the positional deviation of the central portion between the first chip-side dummy bumps 15 and the first substrate-side dummy bumps 26 and each second chip-side dummy bump 17 and each second substrate-side dummy bump 2 is performed.
The positional deviation in the rotational direction from 7 can be sequentially corrected to a correct alignment state by the self-alignment effect of the molten solder, and thus an electronic component and an electronic component mounting method that can be easily and accurately mounted on a wiring board. Can be realized.

In the above embodiment, the present invention is applied to the bare chip 11 and the mounting method for mounting the bare chip 11 on the wiring board 21, but the present invention is not limited to this. Instead, it can be widely applied to other electronic components and a mounting method for mounting the electronic components on a wiring board.

In the above embodiment, the second chip side dummy bump 1 is formed on the bare chip 11 and the wiring board 21.
7 and the second substrate-side dummy bumps 27 are formed in the number of four, respectively, but the present invention is not limited to this, and the bare chip 11 and the wiring substrate 21 may have a predetermined number of three or less or five or more. They may be formed one by one.

Further, in the above-described embodiment, the sum of the areas of the first chip-side metal film 14 of the bare chip 11 and the plurality of second chip-side metal films 16 and the first substrate-side metal film of the wiring board 21. The case where the sum of the areas of 23 and the plurality of second substrate-side metal films 24 is selected to be about 1/10 to 1/4 of the surface area of the circuit surface 11A of the bare chip 11 will be described. However, the present invention is not limited to this, and the surface area may be selected to have another size.

In the above embodiment, the first chip side dummy bump 1 is formed on the bare chip 11 and the wiring board 21.
The case where the first dummy bumps 26 and the first substrate-side dummy bumps 26 are formed one by one has been described, but the present invention is not limited to this, and a plurality of dummy bumps 26 may be formed.

Further, in the above-described embodiment, the first chip-side dummy bumps 15 of the bare chip 11 are formed so as to project in a spherical shape, and the first substrate-side dummy bumps 26 of the wiring board 21 are formed.
Although the case where the protrusions are formed to have the same shape as the first substrate-side metal film 23 has been described, the present invention is not limited to this, and the protrusions may be formed to have various shapes.

Further, in the above-described embodiment, the plurality of second chip-side dummy bumps 17 of the bare chip 11 and the plurality of second substrate-side dummy bumps 27 of the wiring board 21 are respectively connected to the first chip-side metal film 14 and the first chip-side metal film 14. The case where the apexes are formed so as to surround the respective vertices of the substrate-side metal film 23 in a bow shape has been described.
If the positional deviation in the rotation direction can be corrected, for example, dummy bumps having various shapes such as an elliptical shape may be formed to project so as to surround a predetermined area in the central portion of the bare chip 11 in a circular shape.

[0042]

As described above, according to the present invention, a single or a plurality of ones having a melting point temperature characteristic lower than that of the first bump is formed in the central portion of one surface of the electronic component on which the plurality of first bumps for bonding are formed. A first dummy bump is formed, and a single or a plurality of ones having a predetermined melting point temperature characteristic set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump are formed so as to surround the first dummy bump on one surface. Third dummy bumps formed with second dummy bumps, each first dummy bump having the same melting point temperature characteristic as each first dummy bump and corresponding to a predetermined surface of the wiring board. And the second dummy bumps having the same melting point temperature characteristics as those of the second dummy bumps and being formed so as to correspond to the predetermined surface of the wiring board. By joining the bumps to each other, the self-alignment effect is exerted by the surface tension of the metal formed by melting the first and third dummy bumps and the second and fourth dummy bumps, and the X-axis of the electronic component with respect to the wiring board. , The Y direction and the rotation direction can be corrected while mounting, and thus an electronic component that can be mounted on the wiring board with high accuracy and easily can be realized.

As described above, according to the present invention, a single or a plurality of melting point temperature characteristics lower than those of the first bumps are provided in the central portion of one surface of the electronic component on which the plurality of first bumps for bonding are formed. The first dummy bump is formed, and one or more second dummy bumps having a predetermined melting point temperature characteristic set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump are formed on one surface of the first dummy bump. The same melting point temperature characteristics as those of the first dummy bumps are formed on a predetermined surface of the wiring board which is formed so as to surround the dummy bumps and which is opposed to the first dummy bumps and the second dummy bumps when the electronic component is mounted on the wiring board. Forming a single or a plurality of third dummy bumps having the same, and forming a single or a plurality of fourth dummy bumps having the same melting point temperature characteristic as the second dummy bumps. Then, the first dummy bumps of the electronic component and the corresponding third dummy bumps of the wiring substrate are aligned and joined together, and subsequently, the second dummy bumps of the electronic component and the corresponding fourth dummy bumps of the wiring substrate are connected. By joining the dummy bumps and then the first bumps of the electronic component and the corresponding second bumps of the wiring board, the first dummy bumps and the third dummy bumps are melted. A metal formed by melting the second dummy bumps and the fourth dummy bumps after the self-alignment effect is actuated by the surface tension of the formed metal and the positional deviation of the electronic component with respect to the wiring board in the X and Y directions is corrected. The self-alignment effect is exerted by the surface tension of the wire, and the positional deviation of the electronic component with respect to the wiring board in the rotational direction can be corrected. It is possible to realize the electronic part mounting method capable of instrumentation.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing the structure of a bare chip according to an embodiment of the present invention.

FIG. 2 is a plan view and a cross-sectional view showing a configuration of a wiring board according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining alignment in mounting a bare chip and a wiring board according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a positional deviation before reflow in mounting a bare chip and a wiring board according to an embodiment of the present invention.

5 is a sectional view taken along the line AA ′ in FIG. 2 for explaining the positional deviation correction in the X and Y directions in mounting the bare chip and the wiring board according to the embodiment of the present invention.

FIG. 6 is a sectional view taken along the line AA ′ in FIG. 2 for explaining the positional deviation correction in the rotation direction in mounting the bare chip and the wiring board according to the embodiment of the present invention.

FIG. 7 is a sectional view taken along the line AA ′ in FIG. 2 for explaining a bare chip mounted on a wiring board according to an embodiment of the present invention.

FIG. 8 is a sectional view for explaining a conventional mounting method for a bare chip.

FIG. 9 is a sectional view for explaining a conventional mounting method for a bare chip.

[Explanation of symbols]

1, 8, 21 ... Wiring board, 2, 6, 11 ... Bare chip, 3, 4 ... Electrode, 5, 10 ... Bump, 6A ... Circuit surface, 7 ... Chip side metal film, 9 ... Substrate side metal film, 1
1A ... Circuit surface, 12 ... Chip side electrode, 13 ... Chip side bump, 14 ... First chip side metal film, 15 ...
First chip-side dummy bump, 16 ... Second chip-side metal film, 17 ... Second chip-side dummy bump, 21A
... Mounting surface, 22 ... Substrate side electrode, 23 ... First substrate side metal film, 24 ... Second substrate side metal film, 25 ... Substrate side bump, 26 ... First substrate side dummy bump , 27 ...
… Second substrate-side dummy bump.

Claims (4)

[Claims] 1. A plurality of first bumps for bonding are formed on one surface, and each of the first bumps is bonded to a corresponding second bump for bonding formed on a predetermined surface of a wiring board. As a result, in the electronic component mounted on the wiring board, one or a plurality of first dummy bumps formed in the central portion of the one surface and having a melting point temperature characteristic lower than that of the first bump, and the first dummy bump on the one surface. A dummy dummy bump having a predetermined melting point temperature characteristic set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump. The first dummy bumps are formed so as to have the same melting point temperature characteristics as the first dummy bumps and correspond to the predetermined surface of the wiring board. Thereby bonding the third dummy bump, the respective second dummy bumps,
It is characterized in that it has the same melting point temperature characteristic as that of the second dummy bump and is mounted on the wiring board by being joined to the fourth dummy bump formed corresponding to the predetermined surface of the wiring board. Electronic components. 2. The sum of the surface areas of each of the first dummy bumps and each of the second dummy bumps is 1 of the surface area of the one surface.
The electronic component according to claim 1, wherein the electronic component is selected to be about one-zero to one-fourth. 3. A plurality of bonding first bumps are formed on one surface, and each of the first bumps is bonded to a corresponding bonding second bump formed on a predetermined surface of a wiring board. Thereby, in the mounting method of the electronic component to be mounted on the wiring board, a single or a plurality of first dummy bumps having a melting point temperature characteristic lower than that of the first bump is formed in a central portion of the one surface of the electronic component, A single or a plurality of second melting points having predetermined melting point temperature characteristics set between the melting point temperature of the first bump and the melting point temperature of the first dummy bump on the one surface.
Dummy dummy bumps are formed so as to surround the first dummy bumps, and when the electronic component is mounted on the wiring board, the predetermined dummy bumps on the wiring board facing the first dummy bumps and the second dummy bumps are mounted on the wiring board. On the surface
A single or a plurality of third dummy bumps having the same melting point temperature characteristics as the first dummy bumps are formed, and a single or a plurality of fourth dummy bumps having the same melting point temperature characteristics as the second dummy bumps are formed. A second step of aligning and joining the first dummy bumps of the electronic component with the corresponding third dummy bumps of the wiring board; and the second dummy bumps of the electronic component And a third step of joining the corresponding fourth dummy bumps of the wiring board, and joining the first bumps of the electronic component and the corresponding second bumps of the wiring board. A method for mounting an electronic component, comprising: a fourth step. 4. The sum of the surface areas of the first dummy bump and each of the second dummy bumps is 10 of the surface area of the one surface.
4. The mounting method for an electronic component according to claim 3, wherein the amount is selected to be about 1/4 to 1/4.