JPH05175275A - Method of mounting semiconductor chip and mounting structure - Google Patents
Method of mounting semiconductor chip and mounting structureInfo
- Publication number
- JPH05175275A JPH05175275A JP3356586A JP35658691A JPH05175275A JP H05175275 A JPH05175275 A JP H05175275A JP 3356586 A JP3356586 A JP 3356586A JP 35658691 A JP35658691 A JP 35658691A JP H05175275 A JPH05175275 A JP H05175275A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- chip
- wiring board
- lsi
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップを配線基
板上にフェイスダウンで実装するときの半導体チップの
実装方法および実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting method and structure for mounting a semiconductor chip face down on a wiring board.
【０００２】[0002]
【従来の技術】従来、ＬＳＩチップなどの半導体チップ
をフェイスダウンで配線基板上に実装させるに当たって
は、半導体チップの突起電極を配線基板の電極パッドに
重ね合わせ、その状態で加熱リフローして半田付けして
いた。この種の従来の実装方法を図３によって説明す
る。2. Description of the Related Art Conventionally, when mounting a semiconductor chip such as an LSI chip face down on a wiring board, the protruding electrodes of the semiconductor chip are superposed on the electrode pads of the wiring board, and in that state they are heated and reflowed for soldering Was. A conventional mounting method of this type will be described with reference to FIG.
【０００３】図３は従来の半導体チップの実装方法を説
明するための実装部分の断面図で、同図（ａ）は実装前
の状態を示し、同図（ｂ）は位置決め状態を示し、同図
（ｃ）は半田付け終了後の状態を示す。FIG. 3 is a sectional view of a mounting portion for explaining a conventional semiconductor chip mounting method. FIG. 3A shows a state before mounting, FIG. 3B shows a positioning state, and FIG. FIG. 6C shows a state after the soldering is completed.
【０００４】これらの図において、１は半導体チップと
してのＬＳＩチップ、２はこのＬＳＩチップ１に設けら
れたバンプ状外部接続端子である。このバンプ状外部接
続端子２は、ランド１ａ上に形成されており、予備半田
３によって覆われている。すなわち、バンプ状外部接続
端子２と予備半田３とによってＬＳＩチップ１の突起電
極が構成されている。In these drawings, 1 is an LSI chip as a semiconductor chip, and 2 is a bump-shaped external connection terminal provided on the LSI chip 1. The bump-shaped external connection terminal 2 is formed on the land 1 a and covered with the preliminary solder 3. That is, the bump-shaped external connection terminals 2 and the preliminary solder 3 form the protruding electrodes of the LSI chip 1.
【０００５】４は前記ＬＳＩチップ１が実装される配線
基板で、この配線基板４上のＬＳＩ接続用パッド４ａに
は予備半田５が設けられている。Reference numeral 4 denotes a wiring board on which the LSI chip 1 is mounted. A preliminary solder 5 is provided on the LSI connection pad 4a on the wiring board 4.
【０００６】６は前記配線基板４に対してＬＳＩチップ
１を位置決めするための位置合わせマークである。Reference numeral 6 is an alignment mark for positioning the LSI chip 1 with respect to the wiring board 4.
【０００７】配線基板４上にＬＳＩチップ１をフェイス
ダウンで実装するに当たっては、図３（ａ）に示すよう
に、予め、ＬＳＩチップ１のバンプ状外部接続端子２に
予備半田３を設けると共に、配線基板４のＬＳＩ接続用
パッド４ａに予備半田５を設けておく。When mounting the LSI chip 1 face down on the wiring board 4, as shown in FIG. 3A, the bump-shaped external connection terminals 2 of the LSI chip 1 are preliminarily provided with preliminary solder 3, and Preliminary solder 5 is provided on the LSI connection pad 4a of the wiring board 4.
【０００８】実装するには、先ず、図３（ｂ）に示すよ
うに、位置合わせマーク６を目印にしてＬＳＩチップ１
を配線基板４上に位置づけ、配線基板側の予備半田５に
バンプ状外部接続端子２の予備半田３を重ね合わせる。
次に、その状態で加熱リフローして予備半田３，５を溶
融させる。For mounting, first, as shown in FIG. 3B, the LSI chip 1 is made with the alignment mark 6 as a mark.
Is placed on the wiring board 4, and the preliminary solder 3 of the bump-shaped external connection terminal 2 is superposed on the preliminary solder 5 on the wiring board side.
Next, heat reflow is performed in that state to melt the preliminary solders 3 and 5.
【０００９】そして、予備半田３，５を凝固させて図３
（ｃ）に示すように半田付けが終了する。なお、図３
（ｃ）中符号７は凝固後の半田を示す。Then, the preliminary solders 3 and 5 are solidified, and
Soldering is completed as shown in FIG. Note that FIG.
Reference numeral 7 in (c) indicates solder after solidification.
【００１０】[0010]
【発明が解決しようとする課題】しかるに、上述したよ
うに位置合わせマーク６を目印にしてＬＳＩチップ１を
配線基板４に対して位置決めしたのでは、位置決めを正
確に行うにも限度があり、位置決めが不正確になりやす
い。また、位置合わせマーク６を厳格な精度をもって形
成しなければならない。However, if the LSI chip 1 is positioned with respect to the wiring board 4 by using the alignment mark 6 as a mark as described above, there is a limit to accurate positioning, and the positioning is difficult. Is likely to be inaccurate. Also, the alignment mark 6 must be formed with strict accuracy.
【００１１】すなわち、位置合わせマーク６を利用する
位置決め方法を採ると、配線基板４側の予備半田５とＬ
ＳＩチップ１側の予備半田３とが位置ずれを起こしやす
く、加熱リフロー後にオープンやショートが生じやすく
なってしまう。That is, when the positioning method using the positioning mark 6 is adopted, the preliminary solder 5 and L on the wiring substrate 4 side are connected.
The spare solder 3 on the side of the SI chip 1 is likely to be displaced, and an open or short circuit is likely to occur after the heat reflow.
【００１２】[0012]
【課題を解決するための手段】本発明に係る半導体チッ
プの実装方法は、実装前に、配線基板に半導体チップの
突起電極が嵌入する凹部を形成してその凹部内に電極パ
ッドを形成し、その後、半導体チップの突起電極を前記
凹部に臨ませた状態で突起電極を電極パッドに半田付け
するものである。According to a method of mounting a semiconductor chip of the present invention, before mounting, a concave portion into which a protruding electrode of the semiconductor chip is fitted is formed in a wiring board, and an electrode pad is formed in the concave portion. After that, the projecting electrodes of the semiconductor chip are soldered to the electrode pads with the projecting electrodes facing the recesses.
【００１３】本発明に係る半導体チップの実装構造は、
配線基板に、半導体チップの突起電極が嵌入する凹部を
形成すると共に、この凹部内に電極パッドを形成したも
のである。The semiconductor chip mounting structure according to the present invention is
A wiring board is provided with a recess into which a protruding electrode of a semiconductor chip is fitted, and an electrode pad is formed in the recess.
【００１４】[0014]
【作用】配線基板の凹部に半導体チップの突起電極を嵌
入させることで半導体チップが配線基板に対して位置決
めされる。The semiconductor chip is positioned with respect to the wiring board by fitting the protruding electrodes of the semiconductor chip into the recesses of the wiring board.
【００１５】[0015]
【実施例】以下、本発明の一実施例を図１および図２に
よって詳細に説明する。図１は本発明に係る半導体チッ
プの実装方法を説明するための実装部の断面図で、同図
（ａ）は実装前の状態を示し、同図（ｂ）は配線基板上
にＬＳＩチップを仮置きした状態を示し、同図（ｃ）は
半田付け終了後の状態を示す。図２は実装部を拡大して
示す断面図である。これらの図において前記図３で説明
したものと同一もしくは同等部材については、同一符号
を付し詳細な説明は省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. 1A and 1B are cross-sectional views of a mounting portion for explaining a semiconductor chip mounting method according to the present invention. FIG. 1A shows a state before mounting, and FIG. 1B shows an LSI chip on a wiring board. The state of temporary placement is shown, and FIG. 7C shows the state after completion of soldering. FIG. 2 is an enlarged cross-sectional view of the mounting portion. In these figures, the same or equivalent members as those described in FIG. 3 are designated by the same reference numerals and detailed description thereof will be omitted.
【００１６】これらの図において、１１は配線基板４に
形成された凹部で、この凹部１１はＬＳＩチップ１の突
起電極（バンプ状外部接続端子２および予備半田３）が
嵌入できる寸法に形成されている。そして、この凹部１
１の内面および上部開口縁部には導体メタライズが施さ
れている。この導体メタライズが配線基板４の凹型ＬＳ
Ｉ接続用パッド１２を構成している。なお、導体メタラ
イズとしては、Ｃｕ，Ｎｉ，ＡｕあるいはＡｇ等から形
成されている。In these figures, 11 is a concave portion formed in the wiring board 4, and the concave portion 11 is formed in such a size that the protruding electrodes (the bump-shaped external connection terminals 2 and the preliminary solder 3) of the LSI chip 1 can be fitted therein. There is. And this recess 1
Conductor metallization is applied to the inner surface of 1 and the upper opening edge. This conductor metallization is the concave LS of the wiring board 4.
The I connection pad 12 is configured. The conductor metallization is made of Cu, Ni, Au, Ag or the like.
【００１７】前記凹部１１はレーザエッチング法によっ
て形成される。すなわち、例えばポリイミド多層配線基
板の場合においては、基板表面にポリイミドを塗布後キ
ュアさせ、ＬＳＩチップ１の突起電極と対応する位置を
レーザエッチングにより凹ませる。このようにして凹部
１１が形成される。その後、その凹み部分に導電性薄膜
メタライズ等を施すことで凹部１１に凹型ＬＳＩ接続用
パッド１２が形成されることになる。The recess 11 is formed by a laser etching method. That is, for example, in the case of a polyimide multilayer wiring board, polyimide is applied to the surface of the board and then cured, and the position corresponding to the protruding electrode of the LSI chip 1 is recessed by laser etching. In this way, the recess 11 is formed. After that, by applying a conductive thin film metallization or the like to the recessed portion, the recessed LSI connecting pad 12 is formed in the recessed portion 11.
【００１８】凹部１１および凹型ＬＳＩ接続用パッド１
２の寸法としては、図２に示すように、ＬＳＩチップ１
の突起電極（予備半田３が設けられたバンプ状外部接続
端子２）と同等もしくはそれ以上の寸法が適当である。
また、深さに関しては、前記突起電極が嵌合する程度の
深さが必要である。例えば、突起電極が０．４mmピッチ
で径ａが約０．２mmである場合、それに対応する凹型Ｌ
ＳＩ接続用パッド１２のくぼみ大きさｂは、前記突起電
極と同等の約０．２mmが適当である。深さｃは約０．１
mmが適当である。Recessed portion 11 and recessed type LSI connecting pad 1
The dimensions of the LSI chip 1 are as shown in FIG.
It is suitable to have a size equal to or larger than that of the bump electrode (the bump-shaped external connection terminal 2 provided with the preliminary solder 3).
Further, regarding the depth, it is necessary that the protrusion electrodes are fitted to each other. For example, when the protruding electrodes have a pitch of 0.4 mm and the diameter a is about 0.2 mm, the corresponding concave L
A suitable size b of the SI connecting pad 12 is about 0.2 mm, which is the same as the bump electrode. Depth c is about 0.1
mm is suitable.
【００１９】なお、図中符号１３は凹型ＬＳＩ接続用パ
ッド１２内に設けられた予備半田である。また、本実施
例で使用するＬＳＩチップ１のバンプ状外部接続端子２
としては、半田バンプやタングステン等のメタルバンプ
が用いられている。Reference numeral 13 in the drawing is a preliminary solder provided in the concave LSI connection pad 12. Further, the bump-shaped external connection terminals 2 of the LSI chip 1 used in this embodiment
As the solder bump, a metal bump such as a solder bump or tungsten is used.
【００２０】次に、本発明に係る半導体チップの実装方
法について説明する。先ず、図１（ａ）に示すように、
ＬＳＩチップ１のバンプ状外部接続端子２と、配線基板
４の凹型ＬＳＩ接続用パッド１２のくぼみ部分に、予備
半田３，１３をそれぞれ施す。Next, a semiconductor chip mounting method according to the present invention will be described. First, as shown in FIG.
Preliminary solders 3 and 13 are applied to the bump-shaped external connection terminals 2 of the LSI chip 1 and the recessed portions of the concave LSI connection pads 12 of the wiring board 4, respectively.
【００２１】予備半田３，１３としては、例えばＳｎ／
Ｐｂ（63／37 WT ％）等の半田を使用した。また、凹型
ＬＳＩ接続用パッド１２に予備半田１３を塗布するに
は、例えばステンレスなどのメタルマスクを用いた半田
印刷によって行なったり、凹型ＬＳＩ接続用パッド１２
が形成された配線基板４上で半田ボール（図示せず）を
転がし、くぼみ部分に半田ボールを入れてそれを予備半
田１３とすることも可能である。但し、凹型ＬＳＩ接続
用パッド１２に設ける予備半田１３は、供給する半田の
量は凹型ＬＳＩ接続用パッド１２のくぼみ部分を埋めな
い程度に行なう必要がある。また、ＬＳＩチップ１のバ
ンプ状外部接続端子２に設ける予備半田３も、凹型ＬＳ
Ｉ接続用パッド１２内に嵌入できる程度に半田量を調整
することが必要である。The preliminary solders 3, 13 are, for example, Sn /
Solder such as Pb (63/37 WT%) was used. The preliminary solder 13 is applied to the concave LSI connecting pad 12 by solder printing using a metal mask such as stainless steel, or the concave LSI connecting pad 12 is applied.
It is also possible to roll a solder ball (not shown) on the wiring board 4 on which is formed and put the solder ball in the recessed portion to use it as the preliminary solder 13. However, the preliminary solder 13 provided on the concave LSI connection pad 12 needs to be supplied so that the amount of solder to be supplied does not fill the recessed portion of the concave LSI connection pad 12. Further, the preliminary solder 3 provided on the bump-shaped external connection terminal 2 of the LSI chip 1 is also the concave LS.
It is necessary to adjust the amount of solder to such an extent that it can be fitted into the I connection pad 12.
【００２２】次に、図１（ｂ）に示すように、ＬＳＩチ
ップ１の突起電極（バンプ状外部接続端子２，予備半田
３）を配線基板４の凹型ＬＳＩ接続用パッド１２のくぼ
み部分に嵌入させる。Next, as shown in FIG. 1B, the protruding electrodes (bump-shaped external connection terminals 2, preliminary solder 3) of the LSI chip 1 are fitted into the recessed portions of the concave LSI connection pads 12 of the wiring board 4. Let
【００２３】この状態では、予備半田３が凹型ＬＳＩ接
続用パッド１２内の予備半田１３に重ね合わせられる
が、両者の正確な位置決めは必要ない。In this state, the preliminary solder 3 is superposed on the preliminary solder 13 in the concave LSI connection pad 12, but accurate positioning of both is not required.
【００２４】その後、加熱リフローを行なう。リフロー
時には、予備半田３，１３としてＳｎ／Ｐｂ（63／37 W
T ％）を使用している場合は、２３０℃で加熱する。リ
フローを行うと、図１（ｃ）に示すように予備半田３，
１３が溶融して半田７となり、ＬＳＩチップ１のバンプ
状外部接続端子２と配線基板４の凹型ＬＳＩ接続用パッ
ド１２とが接続される。Then, heating reflow is performed. When reflowing, Sn / Pb (63/37 W
If used, heat at 230 ° C. When the reflow is performed, as shown in FIG.
13 melts to become solder 7, and the bump-shaped external connection terminals 2 of the LSI chip 1 and the concave LSI connection pads 12 of the wiring board 4 are connected.
【００２５】このとき、溶融した半田７の表面張力によ
り、ＬＳＩチップ１が配線基板４に対して自動的に位置
合わせされることになる。At this time, the LSI chip 1 is automatically aligned with the wiring board 4 by the surface tension of the melted solder 7.
【００２６】リフロー後、冷却，洗浄を行なって実装工
程が終了する。After the reflow, cooling and cleaning are performed, and the mounting process is completed.
【００２７】[0027]
【発明の効果】以上説明したように本発明に係る半導体
チップの実装方法は、実装前に、配線基板に半導体チッ
プの突起電極が嵌入する凹部を形成してその凹部内に電
極パッドを形成し、その後、半導体チップの突起電極を
前記凹部に臨ませた状態で突起電極を電極パッドに半田
付けするものであり、本発明に係る半導体チップの実装
構造は、配線基板に、半導体チップの突起電極が嵌入す
る凹部を形成すると共に、この凹部内に電極パッドを形
成したものであるため、配線基板の凹部に半導体チップ
の突起電極を嵌入させることで半導体チップが配線基板
に対して位置決めされる。As described above, in the method of mounting a semiconductor chip according to the present invention, before mounting, a concave portion into which the protruding electrode of the semiconductor chip is fitted is formed in the wiring board, and the electrode pad is formed in the concave portion. Then, the protruding electrode of the semiconductor chip is soldered to the electrode pad in a state where the protruding electrode of the semiconductor chip is exposed to the concave portion. Since the concave portion into which is fitted is formed and the electrode pad is formed in this concave portion, the semiconductor chip is positioned with respect to the wiring board by fitting the protruding electrode of the semiconductor chip into the concave portion of the wiring board.
【００２８】したがって、半導体チップをフェイスダウ
ンで実装するときの位置決めを正確にかつ短時間で行な
うことができる。このため、位置ずれが生じ難くなり、
オープンやショートなどのない安定した半田付けが可能
となる。Therefore, when the semiconductor chip is mounted face down, the positioning can be performed accurately and in a short time. For this reason, it becomes difficult for positional deviation to occur,
Stable soldering without open or short circuit is possible.
【００２９】また、凹部内の電極パッドに予備半田を設
けると、位置ずれが生じ難くなるばかりでなく、半田付
け時の濡れ性が高まって接続上の信頼性も向上する。Further, if the electrode pad in the recess is provided with the preliminary solder, not only the positional deviation does not easily occur, but also the wettability at the time of soldering is enhanced and the reliability of connection is also improved.
【図１】本発明に係る半導体チップの実装方法を説明す
るための実装部の断面図で、同図（ａ）は実装前の状態
を示し、同図（ｂ）は配線基板上にＬＳＩチップを仮置
きした状態を示し、同図（ｃ）は半田付け終了後の状態
を示す。FIG. 1 is a sectional view of a mounting portion for explaining a semiconductor chip mounting method according to the present invention. FIG. 1A shows a state before mounting, and FIG. 1B shows an LSI chip on a wiring board. Is temporarily placed, and FIG. 7C shows a state after the soldering is completed.
【図２】実装部を拡大して示す断面図である。FIG. 2 is an enlarged sectional view showing a mounting portion.
【図３】従来の半導体チップの実装方法を説明するため
の実装部分の断面図で、同図（ａ）は実装前の状態を示
し、同図（ｂ）は位置決め状態を示し、同図（ｃ）は半
田付け終了後の状態を示す。FIG. 3 is a sectional view of a mounting portion for explaining a conventional semiconductor chip mounting method, where FIG. 3A shows a state before mounting, FIG. 3B shows a positioning state, and FIG. c) shows the state after completion of soldering.
１ ＬＳＩチップ ２ バンプ状外部接続端子 ３ 予備半田 ４ 配線基板 １１ 凹部 １２ 凹型ＬＳＩ接続用パッド １３ 予備半田 1 LSI Chip 2 Bump-shaped External Connection Terminal 3 Preliminary Solder 4 Wiring Board 11 Recess 12 Recessed LSI Connection Pad 13 Preliminary Solder
Claims (2)
ウンで実装して配線基板の電極パッドに半導体チップの
突起電極を半田付けする半導体チップの実装方法におい
て、実装前に、配線基板に前記突起電極が嵌入する凹部
を形成してその凹部内に電極パッドを形成し、その後、
半導体チップの突起電極を前記凹部に臨ませた状態で突
起電極を電極パッドに半田付けすることを特徴とする半
導体チップの実装方法。1. A method of mounting a semiconductor chip in which a semiconductor chip is mounted face down on a wiring board and a protruding electrode of the semiconductor chip is soldered to an electrode pad of the wiring board. To form a recess into which the electrode pad is formed, and thereafter,
A method of mounting a semiconductor chip, comprising: soldering a protruding electrode to an electrode pad in a state where the protruding electrode of the semiconductor chip faces the recess.
ウンで実装され配線基板の電極パッドに半導体チップの
突起電極が半田付けされる半導体チップの実装構造にお
いて、前記配線基板に、前記突起電極が嵌入する凹部を
形成すると共に、この凹部内に電極パッドを形成したこ
とを特徴とする半導体チップの実装構造。2. A semiconductor chip mounting structure in which a semiconductor chip is mounted face down on a wiring board, and protruding electrodes of the semiconductor chip are soldered to electrode pads of the wiring board. In the mounting structure of the semiconductor chip, the protruding electrodes are fitted into the wiring board. A mounting structure for a semiconductor chip, characterized in that a concave portion is formed and an electrode pad is formed in the concave portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3356586A JPH05175275A (en) | 1991-12-25 | 1991-12-25 | Method of mounting semiconductor chip and mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3356586A JPH05175275A (en) | 1991-12-25 | 1991-12-25 | Method of mounting semiconductor chip and mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05175275A true JPH05175275A (en) | 1993-07-13 |
Family
ID=18449770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3356586A Pending JPH05175275A (en) | 1991-12-25 | 1991-12-25 | Method of mounting semiconductor chip and mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05175275A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4446471A1 (en) * | 1994-12-23 | 1996-06-27 | Fraunhofer Ges Forschung | Chip contacting method and electronic circuit produced therewith |
| JPH08330360A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Semiconductor device and its manufacture |
| JPH0923099A (en) * | 1995-07-04 | 1997-01-21 | Nec Corp | Semiconductor component and its mounting method |
| US5783865A (en) * | 1995-07-31 | 1998-07-21 | Fujitsu Limited | Wiring substrate and semiconductor device |
| EP0834917B1 (en) * | 1995-05-12 | 2002-02-13 | Nitto Denko Corporation | Film carrier and method of forming a semiconductor device using the same |
| JP2008021751A (en) * | 2006-07-11 | 2008-01-31 | National Institute Of Advanced Industrial & Technology | Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method |
| WO2011037185A1 (en) * | 2009-09-24 | 2011-03-31 | 京セラ株式会社 | Mounting substrate, light emitting body, and method for manufacturing mounting substrate |
| KR101233486B1 (en) * | 2011-09-15 | 2013-02-14 | 한국과학기술원 | Method for fabricating receiving structure for conductinve bump with hollow configuration, receiving structure fabricated by the same and method for connecting chips using the same |
| JP2013098701A (en) * | 2011-10-31 | 2013-05-20 | Daishinku Corp | Piezoelectric vibration device and manufacturing method of piezoelectric vibration device |
| JP2015167257A (en) * | 2003-09-22 | 2015-09-24 | インテル コーポレイション | Compact electronic apparatus, formation method thereof, and system |
| CN112185896A (en) * | 2020-09-30 | 2021-01-05 | 赵海洪 | Lamp string and manufacturing method thereof |
-
1991
- 1991-12-25 JP JP3356586A patent/JPH05175275A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4446471A1 (en) * | 1994-12-23 | 1996-06-27 | Fraunhofer Ges Forschung | Chip contacting method and electronic circuit produced therewith |
| EP0834917B1 (en) * | 1995-05-12 | 2002-02-13 | Nitto Denko Corporation | Film carrier and method of forming a semiconductor device using the same |
| JPH08330360A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Semiconductor device and its manufacture |
| JPH0923099A (en) * | 1995-07-04 | 1997-01-21 | Nec Corp | Semiconductor component and its mounting method |
| US5783865A (en) * | 1995-07-31 | 1998-07-21 | Fujitsu Limited | Wiring substrate and semiconductor device |
| JP2015167257A (en) * | 2003-09-22 | 2015-09-24 | インテル コーポレイション | Compact electronic apparatus, formation method thereof, and system |
| JP2008021751A (en) * | 2006-07-11 | 2008-01-31 | National Institute Of Advanced Industrial & Technology | Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method |
| WO2011037185A1 (en) * | 2009-09-24 | 2011-03-31 | 京セラ株式会社 | Mounting substrate, light emitting body, and method for manufacturing mounting substrate |
| JPWO2011037185A1 (en) * | 2009-09-24 | 2013-02-21 | 京セラ株式会社 | Mounting substrate, light emitter, and manufacturing method of mounting substrate |
| KR101233486B1 (en) * | 2011-09-15 | 2013-02-14 | 한국과학기술원 | Method for fabricating receiving structure for conductinve bump with hollow configuration, receiving structure fabricated by the same and method for connecting chips using the same |
| JP2013098701A (en) * | 2011-10-31 | 2013-05-20 | Daishinku Corp | Piezoelectric vibration device and manufacturing method of piezoelectric vibration device |
| CN112185896A (en) * | 2020-09-30 | 2021-01-05 | 赵海洪 | Lamp string and manufacturing method thereof |
| CN112185896B (en) * | 2020-09-30 | 2023-05-02 | 江西橙子光电科技有限公司 | Manufacturing method of lamp string and lamp string |
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