JPH0923099A - Semiconductor component and its mounting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent position deviation when a semiconductor component is mounted on a printed wiring board. SOLUTION: Auxiliary electrodes 2a, 2b are formed on the lower surface of a semiconductor package 5. The auxiliary electrodes 2a are arranged parallel with the leading-out direction of electrodes 1a. The auxiliary electrodes 2b are arranged parallel with the leading-out direction of electrodes 1b. On a printed board, mounting pads are formed together with other circuit patterns, at positions corresponding to the auxiliary electrodes 2a, 2b. When the semiconductor package 5 is to be mounted on the printed wiring board, solder paste is printed on the mounting pads on the printed board, the semiconductor package 5 is mounted, and then the whole is heated. The solder is fused by the heating, and positions are corrected between the auxiliary electrodes 2a, 2b and the mounting pads by the effect of surface tension of solder, so that the position deviation of the semiconductor package can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor component and a method of mounting the same, and more particularly, to a semiconductor component and a method of mounting the same which prevent the semiconductor component from being displaced.

[0002]

2. Description of the Related Art Conventional semiconductor components use only external electrodes for soldering. Further, as a measure for preventing displacement during mounting, a method of forming a groove, a hole, a projection, or the like for positioning a semiconductor component on a printed wiring board has been proposed (for example, Japanese Patent Application Laid-Open Nos. 4-179221 and 4-179221). 2-1
No. 22551, JP-A-2-89390, JP-A-1-3
21681, JP-A-63-269551, JP-A-5
No. 8-121654, and Japanese Utility Model Application Laid-Open No. 61-27272, each gazette).

[0003]

However, this conventional method for preventing misalignment has a problem in that processing is costly when grooves or projections are provided on the printed wiring board. Further, even when a hole is formed in the printed wiring board, the effect of preventing the displacement is not always sufficient due to the positional accuracy and allowance (clearance) of the hole.

[0004]

In order to solve the above-mentioned problems, according to the present invention, in addition to electrodes for leading signal lines to the outside, positioning for soldering is performed on a surface facing a printed circuit board on which semiconductor components are mounted. A member is provided.

On the printed circuit board on which the semiconductor components are mounted, mounting portions are provided at positions corresponding to the positioning members.
The positioning member and the mounting portion are soldered to position the semiconductor component.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. Figure 1 shows the QFP
It is a top view of the example which applied the present invention to semiconductor package 5 called (Quat Flat Package). FIG. 2 is similar to FIG.
2 is a sectional view taken along line AA of FIG. Conventional QFP electrodes are:
Although only the electrodes 1a and 1b for leading out the signal lines are provided, in the present invention, auxiliary electrodes 2a and 2b as positioning members are arranged to prevent displacement.

The auxiliary electrodes 2a and 2b are formed of a solderable material, for example, a copper frame plated with tin. The auxiliary electrodes 2a are elongated in parallel with the direction in which the electrodes 1a are drawn out (X direction in FIG. 1). In the example of FIG.
In addition, the auxiliary electrodes 2b are elongated and arranged in parallel with the direction in which the electrodes 1b are pulled out (the Y direction in FIG. 1). In the example of FIG. The auxiliary electrodes 2a and 2b are connected to the package 5 similarly to the electrodes 1a and 1b.
Is provided by resin sealing or the like.

On the other hand, as shown in FIG. 2, a mounting pad 3 corresponding to the electrode 1a is formed on the printed wiring board 6, and a mounting pad 4 as an attachment portion is provided at a position corresponding to the auxiliary electrode 2b. It is formed over substantially the same length as the electrode 2b. Since the mounting pad 4 is formed using a printing technique together with other circuit patterns (such as the mounting pad 3 in FIG. 2), the mounting pad 4 is formed on the substrate 6 with high positioning accuracy. In the drawings, the auxiliary electrodes 2a,
2b, the thickness of the mounting pad 4 is slightly exaggerated (the same applies to FIGS. 4 and 5).

With the above configuration, the semiconductor package 5
Is mounted on the printed wiring board 6 by reflow soldering. That is, after the solder paste is printed on the pads 3 and 4 on the printed wiring board 6 and the semiconductor package 5 is mounted, the whole is heated. This heating melts the solder, and the position between the auxiliary electrode 2 and the mounting pad 4 is corrected by the surface tension of the solder. Thereby, the semiconductor package 5 is correctly positioned. That is, when the solder is contacted with the solder, its surface tension is corrected by the auxiliary electrode 2a for the displacement in the Y direction and by the auxiliary electrode 2b for the displacement in the X direction. 5 is positioned and mounted in the correct position.

Since the mounting pads 4 to which the auxiliary electrodes 2a and 2b are soldered have high positional accuracy as described above, the semiconductor package 5 is also positioned on the pattern wiring board 6 with higher accuracy than before.

FIG. 3 is a diagram showing an SOP (Small Outline) according to the present invention.
An example in which the present invention is applied to a semiconductor package called “Package” is shown. 4 and 5 are a sectional view taken along line BB and a sectional view taken along line CC of FIG. 3, respectively.

A semiconductor package 5, which is a surface-mount type semiconductor component, is mounted on a printed circuit board 6, and an auxiliary electrode 7 as a solderable positioning member is attached to a surface facing the printed circuit board 6. . Auxiliary electrode 7
Are provided at the upper and lower ends of the package 5 in FIG. 3 in parallel with the drawing direction of the electrode 1 for drawing the signal line of the semiconductor package 5 to the outside. The material and forming method of the auxiliary electrode 7 are the same as those in the example of FIG.

As shown in FIGS. 4 and 5, on the printed wiring board 6, mounting pads 8 as mounting portions are formed at positions corresponding to the auxiliary electrodes 7 over substantially the same length as the auxiliary electrodes 7.

With the above configuration, the auxiliary electrode 7 and the mounting pad 8 are soldered by flow soldering in the same manner as in the above example. Since the auxiliary electrode 7 is arranged in parallel with the extraction direction of the electrode 1, the arrangement of the electrodes 1 (vertical direction in FIG. 3) can be regulated and the positioning can be performed with high accuracy.

In the present invention, the positioning member is
The present invention is not limited to the above example, that is, it is not necessary to arrange the semiconductor component along the lead-out direction of the electrode, and it may be arranged in any shape and form on the semiconductor package (for example, Good).

Further, by using the auxiliary electrodes 2a, 2b, 7 as ground, a design resistant to noise can be obtained.

[0017]

As described above, according to the present invention,
A positioning member that can be soldered is provided on the surface of the surface-mounted semiconductor component facing the printed wiring board, and the positioning member is soldered to the print, thereby accurately positioning the semiconductor device on the printed wiring board. be able to.

[Brief description of drawings]

FIG. 1 is a plan view showing an example in which the present invention is applied to a QFP.

FIG. 2 is a sectional view taken along line AA of FIG. 1;

FIG. 3 is a plan view showing an example in which the present invention is applied to an SOP.

FIG. 4 is a sectional view taken along line BB of FIG.

FIG. 5 is a sectional view taken along line CC of FIG. 3;

[Explanation of symbols]

 1a, 1b electrode 2a, 2b auxiliary electrode 3 pad 4 pad 5 semiconductor package 6 printed wiring board

Claims (4)

[Claims] 1. A semiconductor component, wherein a surface mountable semiconductor component is provided with a solderable positioning member on a surface facing a printed board on which the semiconductor component is mounted. 2. The semiconductor component according to claim 1, wherein the positioning member is a member which is arranged in the vicinity of an electrode for pulling out the signal line of the semiconductor component to the outside in an elongated shape in parallel with the pulling direction of the electrode. 3. A solderable positioning member is provided on a surface of a surface-mounted semiconductor component facing a printed circuit board on which the semiconductor component is mounted, and the printed circuit board is provided with a positioning member.
A method of mounting a semiconductor component, wherein an attachment portion is formed at a position corresponding to the positioning member, and the positioning member and the attachment portion are soldered to position the semiconductor component. 4. The mounting method according to claim 3, wherein the soldering is reflow soldering.