JPS62299098A - Method of mounting parts on printed wiring board - Google Patents
Method of mounting parts on printed wiring boardInfo
- Publication number
- JPS62299098A JPS62299098A JP14223286A JP14223286A JPS62299098A JP S62299098 A JPS62299098 A JP S62299098A JP 14223286 A JP14223286 A JP 14223286A JP 14223286 A JP14223286 A JP 14223286A JP S62299098 A JPS62299098 A JP S62299098A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- conductive
- solder paste
- conductive foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 239000011888 foil Substances 0.000 claims description 43
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 238000005476 soldering Methods 0.000 claims description 11
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
3、発明の詳細な説明
(産業上の利用分野)
本発明は、本体部の端面から等間隔で導出された多数の
接続端子を有し面実装される電子部品の印刷配線基板に
関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a surface-mounted electronic component having a large number of connection terminals led out at equal intervals from an end face of a main body. This invention relates to printed wiring boards.
(発明の概要)
本発明は、本体部の端面から等間隔で導出された多数の
接続端子を有し面実装される電子部品の印刷配線基板に
おいて、前2印刷配線U板上の導電箔群のうち両端に位
置する導電箔に対してリフローはんだ付のためのはんだ
ペーストを前記両端に位置する導電箔の面積より充分に
大きく塗布することにより、面実装される電子部品の接
続端子の接続不良を防出するようにしたものである。(Summary of the Invention) The present invention provides a printed wiring board for a surface-mounted electronic component having a large number of connection terminals led out at equal intervals from an end surface of a main body, and a group of conductive foils on the front two printed wiring U boards. By applying solder paste for reflow soldering to the conductive foil located at both ends of the conductive foil in an area sufficiently larger than the area of the conductive foil located at both ends, connection failures of connection terminals of surface-mounted electronic components can be prevented. It is designed to prevent.
(従来の技術)
従来、本体部の端面から等間隔で導出された多数の接続
端子を有する面実装部品を印刷配線V板に半田付けする
場合には、上記面実装部品の多数の接続端子を上記印刷
配線基板上に等間隔ぐ配置j9された導電箔のそれぞれ
に予じめ上記印刷配線基板上に第3図のように設けた−
まんだペースト6によって接合するりフO−はんだ付(
プ法が採用される。例えば、日刊工業新聞社出版の第2
65第6号P、45−47にリフ【]−ソルダリングに
ついて説明されている。(Prior Art) Conventionally, when soldering a surface mount component having a large number of connection terminals led out at equal intervals from the end surface of a main body to a printed wiring V board, it is necessary to solder a large number of connection terminals of the surface mount component to a printed wiring V board. Each of the conductive foils arranged at equal intervals on the printed wiring board was preliminarily provided on the printed wiring board as shown in FIG.
Join with paste 6 and solder (
The first method is adopted. For example, the second edition published by Nikkan Kogyo Shimbunsha
65 No. 6 P, 45-47 describes riff[]-soldering.
(発明が解決しようとする問題点)
しかし従来の印刷配線基板への面実装部品の取付法では
、フラットパックtC等の面実装部品は第2図に示すよ
うに印刷配線基板1へ電子部品2の接続端子3.3・・
・に対応する関係位置へ導電箔4.4・・・を配冒し、
第4図に例示するように接続端子3.3・・・と導電箔
4.4・・・との間をリフローはんだ付は方法によって
はんだ付けを行なった場合、はんだ5が接続端子に接触
せずに第4図のA部分で示すように両端に位置する導電
箔と接VC端子が接続不良を起こしてしまうという欠点
があった。これは、電子部品2の接続端子3.3・・・
のうら両端に位置する接続端子のみ他のすべての接続端
子の成形角度よりばらつきが非常に大きいために発生す
るものと考えられる。そこで両端に位置する接Rg子の
接続不良の欠点を除去するため、接続端子の曲がりの矯
正を行なう必要がある。このような接続端子の矯正は、
ビンセット等を用いて人手により一本ずつ行うことも可
能であるが、作業能率が極めて悪く、製造原価高をまね
くとともに、接続端子の角度調節が非常に困難であった
。(Problems to be Solved by the Invention) However, in the conventional mounting method of surface mount components on a printed wiring board, a surface mount component such as a flat pack TC is attached to a printed wiring board 1 with an electronic component 2 as shown in FIG. Connection terminal 3.3...
Distribute the conductive foil 4.4... to the relevant position corresponding to .
As illustrated in Fig. 4, when reflow soldering is performed between the connection terminals 3.3... and the conductive foil 4.4..., the solder 5 does not come into contact with the connection terminals. However, as shown in part A in FIG. 4, there is a problem in that a connection failure occurs between the conductive foil and the VC terminal located at both ends. This is the connection terminal 3.3 of the electronic component 2...
This is thought to occur because the forming angle of the connection terminals located at both ends of the back of the screen is much larger than that of all other connection terminals. Therefore, in order to eliminate the defect of poor connection of the contact Rg terminals located at both ends, it is necessary to correct the bending of the connection terminals. To correct such connection terminals,
Although it is possible to do this one by one manually using a bottle set or the like, the work efficiency is extremely low, leading to high manufacturing costs, and it is extremely difficult to adjust the angle of the connecting terminals.
また、特許出願公開昭61−12052にフラットパッ
ク部品のリード矯正方法が開示されている。Moreover, a lead correction method for flat pack components is disclosed in Japanese Patent Application Publication No. 12052/1983.
しかし、成形機があらゆるフラットパックICの接続端
子の成形を行なうため、接続端子を加圧する型を非常に
多く必要とするし、しかも接続端子のスプリングバック
などの影響を無くし、精密に矯正する型の設計は非常に
困難であるという欠点があった。しかるに、この欠点が
面部品実装工程の増加による製造原価高をまねいた。However, since the molding machine molds the connection terminals of all flat pack ICs, it requires a large number of molds to press the connection terminals, and also molds to precisely straighten the connection terminals to eliminate springback and other effects. The disadvantage was that it was extremely difficult to design. However, this drawback led to an increase in manufacturing costs due to an increase in the number of surface component mounting steps.
本発明はこのような従来の欠点を解消するものであり、
その目的とすることは印刷配線基板上に等開隔で配設さ
れた導電箔群のうち両端に位置する導電箔と相対する面
実装電子部品の接続端子とのtよんだによる接続不良を
防止することができる印刷配置i1基板への面実装部品
の取付法を提供することにある。The present invention solves these conventional drawbacks,
The purpose of this is to prevent connection failures caused by contact between the conductive foils located at both ends of the group of conductive foils arranged at equal intervals on the printed wiring board and the connecting terminals of the opposing surface-mounted electronic components. An object of the present invention is to provide a method for attaching a surface mount component to a printed layout i1 board that can be used.
(問題点を解決するための手段)
前記問題点を解決するために本発明は、印刷配線基板上
の導電箔群のうち両端に位置する導電的に対してリフロ
ーはんだ付けのためのはんだペーストを前記両端に位置
する81電泗の面積より充分に大きく孕布し、はんだに
よるfl続不良を防止するようにした。(Means for Solving the Problems) In order to solve the above problems, the present invention applies a solder paste for reflow soldering to the conductive foils located at both ends of the conductive foil group on the printed wiring board. The area is sufficiently larger than the area of the 81 wires located at both ends to prevent defective fl connection due to solder.
(作用)
この取付法によると、はんだペーストは導電箔群のうち
両端に位置する導電箔に対して、前記両端に位置する導
電箔の面積より充分に大きく、かつ、隣接する導電的が
ない方向に塗布されるため、スクリーン印刷等の手法で
多少の位置ずれを生じても互に隣合うはんだペーストと
接触することなく一様に塗布することができ、リフロー
はんだ付は時にはんだペーストは前記両端に位置する導
電箔の部分に表面張力で引き寄せられ、隣接する導電箔
との間で短絡することなく、前記両端に位置する導電箔
と相対する接続端子との間で接続不良を起こすことが防
止される。(Function) According to this mounting method, the solder paste is applied to the conductive foils located at both ends of the conductive foil group in a direction that is sufficiently larger than the area of the conductive foils located at both ends, and where there is no adjacent conductive foil. Because the solder paste is applied to both ends, even if there is some misalignment due to screen printing or other methods, the solder paste can be applied uniformly without contacting adjacent solder pastes. During reflow soldering, the solder paste is applied to both ends The conductive foil is attracted by surface tension to the part of the conductive foil located at the ends of the conductive foil, preventing a short circuit between adjacent conductive foils and preventing a connection failure between the conductive foil located at both ends and the opposing connection terminal. be done.
(実施例)
以下、本発明について実施例の図面と共に説明する。第
1図は本発明の一実施例を示し、印刷配線基板1の導電
箔4.4・・・の並列配置の群のうち両端に位置する導
電的に対してはんだペースト6を前記両端に位dする導
電的の面積より2〜3倍前後に大きく、かつ、隣接する
導電箔がない方向に塗布し、次いで面実装部品2を搭載
してリフローはんだ付けする。このようにリフローはん
だ飼けすると、前記両端に位置する導電箔に塗布された
はんだペーストは、互に隣合うはんだペーストと交わる
ことなく、前記両端に位置する導電箔において溶融され
、はんだ5となる。したがって、前述したように電子部
品2の接続端子3,3・・・のうち両端に位置する接続
端子の成形角度のばらつきが非常に大きい為、はんだ5
が接続端子に接触せずに第4図のA部分で示すように両
端に位置する導電箔と接続端子が接続不良を起こす恐れ
は全くなくなるのである。ここで、前記はんだペースト
の塗布面積を2〜3倍前徴に選lυだ理由を説明する。(Example) Hereinafter, the present invention will be described with reference to drawings of examples. FIG. 1 shows an embodiment of the present invention, in which solder paste 6 is placed at both ends of a group of conductive foils 4, 4, . It is applied in a direction that is about 2 to 3 times larger than the area of the conductive foil d and where there is no adjacent conductive foil, and then the surface mount component 2 is mounted and reflow soldered. When reflow soldering is performed in this way, the solder paste applied to the conductive foils located at both ends is melted at the conductive foils located at both ends without intersecting with the solder paste adjacent to each other, and becomes solder 5. . Therefore, as mentioned above, among the connection terminals 3, 3, etc. of the electronic component 2, there is a very large variation in the forming angle of the connection terminals located at both ends, so the solder 5
Since the conductive foils do not come into contact with the connecting terminals, there is no possibility that a connection failure will occur between the conductive foils located at both ends and the connecting terminals, as shown in part A in FIG. Here, the reason why the solder paste application area is selected to be 2 to 3 times larger will be explained.
はんだペースト塗布量を多くするほど、接続の不良率は
小さくなる。しかし、はlυだペーストの塗布量をあま
り多くすると、互に隣合うはんだペーストが交わり、導
電的間で余剰分のtまんだによる短絡事故が発生する恐
れがある。また、はんだペースト塗布面積が導電箔面積
と同等位だと、短絡事故の発生する恐れはなくなるが、
接続の不良率が大きくなる。そこで、はんだペースト塗
布量とはんだ欠陥不良率の関係を調べてみると、両端に
位置する導電箔に対してはんだペーストを前記両端に位
置する導電箔の面積より2〜3倍前後に大きく塗布する
ように選ぶと、不良率が最小となり、適正であることが
分かる。The greater the amount of solder paste applied, the lower the defective connection rate. However, if the amount of solder paste applied is too large, adjacent solder pastes will intersect with each other, and there is a risk that a short circuit will occur due to the excess solder paste between conductors. Also, if the solder paste application area is the same as the conductive foil area, there is no risk of short circuits, but
Connection failure rate increases. Therefore, when we investigated the relationship between the amount of solder paste applied and the solder defect defect rate, we found that the solder paste is applied to the conductive foils located at both ends to an area 2 to 3 times larger than the area of the conductive foils located at both ends. It can be seen that if this is selected, the defective rate will be minimized and it is appropriate.
以上のような実施例において、印刷配線基板1の導電箔
4,4・・・の並列配置の群のうち両端に位置する導電
箔に対し−(はんだペースト6を前記両端に位置する導
電箔の面積より2〜3倍前後に大きく、かつ、隣接する
導電箔がない方向に塗布し、接続端子3.3・・・のう
ち両端に位置する接続端子の成形角度のばらつきが10
〜20°あるフラットパックIC等の面実装部品を搭載
してリフローはんだ付けしても、接続不良事故を起こす
ことがなく、良好なはんだ付けができる。In the embodiment described above, the solder paste 6 is applied to the conductive foils located at both ends of the group of conductive foils 4, 4, etc. arranged in parallel on the printed wiring board 1. It is applied in a direction that is about 2 to 3 times larger than the area and there is no adjacent conductive foil, and the variation in the forming angle of the connecting terminals located at both ends of the connecting terminals 3.3... is 10
Even when surface-mounted components such as flat pack ICs with an angle of ~20° are mounted and reflow soldered, good soldering can be achieved without causing connection failures.
(発明の効果)
本発明は以上説明したように、印刷配線基数上に等間隔
で配設された導電箔群のうら両端に位置する導電箔の面
積より2〜3倍前後に大きく、かつ、隣接する導電箔が
ない方向に塗布するため、はんだ吊の調整が非常に容易
にでき、リフローはんだ付は時のフラットパックIC等
の接続不良率を大幅に下げることができる。また、従来
のフラットパックIC等の接続端子の曲がりの矯正を行
なう必要がない為、実装工程を著しく簡素化でき、製造
原画を抑える等の効果を達成できるものである。(Effects of the Invention) As explained above, the present invention has an area approximately two to three times larger than the area of the conductive foils located at both ends of the conductive foil group arranged at equal intervals on the printed wiring base, and Since it is applied in a direction where there are no adjacent conductive foils, adjustment of the solder suspension can be made very easily, and reflow soldering can greatly reduce the connection failure rate of flat pack ICs and the like. In addition, since there is no need to correct the bending of the connection terminals of conventional flat pack ICs, the mounting process can be significantly simplified, and the number of manufacturing originals can be reduced.
第1図aは本発明の一実施例を示す正面図、第1図すは
その部分拡大斜視図、第2図は一般的なフラットバック
ICを印刷配線1に板へ搭載することを示す説明用斜視
図、第3図aは従来のはんだペースト塗布例を示す正面
図、第3FAbはその部分拡大斜視図、第4図aは一般
的なフラットパックICが印舅配I2基板にはんだ付け
された状態を示す正面図、第4図すはその部分拡大斜視
図である。
1・・・印刷配線基板
2・・・面実装部品
3・・・接続端子
4・・・3g導電
箔・・・はんだ
6・・・はんだペースト
A・・・はんだによる接続不良
出願人 セイコー電子工業株式会社
代理人 弁理士 最 上 務
(他1名)
図面の浄書(内容に変更なし)
第1図
第2図
図面の浄書(内容に変更なし)
図面の浄書(内容に変更なし)
手 続 補 正 −1F (方式)
%式%
2発明の名称
団刷配線基板の実装方法
l 補正とする者
昭和61年 8月26BFig. 1a is a front view showing an embodiment of the present invention, Fig. 1 is a partially enlarged perspective view thereof, and Fig. 2 is an explanation showing mounting a general flat back IC on a printed wiring board 1. Figure 3a is a front view showing an example of conventional solder paste application, Figure 3FAb is a partially enlarged perspective view of the same, and Figure 4a is a typical flat pack IC soldered to an I2 board. FIG. 4 is a partially enlarged perspective view. 1...Printed wiring board 2...Surface mount component 3...Connection terminal 4...3g Conductive foil...Solder 6...Solder paste A...Poor connection due to solder Applicant: Seiko Electronic Industries Agent Co., Ltd. Patent Attorney Mogami (1 other person) Engraving of drawings (no change in content) Engraving of drawings of Figures 1 and 2 (no change in content) Engraving of drawings (no change in content) Procedure supplement Correct -1F (Method) % formula % 2 Name of the invention Method for mounting double-printed wiring boards l Person making the amendment August 26B, 1985
Claims (1)
を有し面実装される電子部品を印刷配線基板上に搭載し
、前記電子部品の多数の接続端子を前記印刷配線基板上
に等間隔で配設された導電箔のそれぞれにリフローはん
だ付けによって固定するものにおいて、前記印刷配線基
板上の導電箔群のうち両端に位置する導電箔に対してリ
フローはんだ付けのためのはんだペーストを前記両端に
位置する導電箔の面積より充分に大きく塗布したことを
特徴とする印刷配線基板の実装方法。A surface-mounted electronic component having a large number of connecting terminals led out from the end surface of the main body at equal intervals is mounted on a printed wiring board, and the numerous connecting terminals of the electronic component are mounted at equal intervals on the printed wiring board. In the method of fixing conductive foils arranged on the printed wiring board by reflow soldering, solder paste for reflow soldering is applied to the conductive foils located at both ends of the group of conductive foils on the printed wiring board. A method for mounting a printed wiring board, characterized in that the area of the conductive foil is sufficiently larger than the area of the conductive foil located at the surface of the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14223286A JPS62299098A (en) | 1986-06-18 | 1986-06-18 | Method of mounting parts on printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14223286A JPS62299098A (en) | 1986-06-18 | 1986-06-18 | Method of mounting parts on printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62299098A true JPS62299098A (en) | 1987-12-26 |
Family
ID=15310496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14223286A Pending JPS62299098A (en) | 1986-06-18 | 1986-06-18 | Method of mounting parts on printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62299098A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01259594A (en) * | 1988-04-08 | 1989-10-17 | Fujitsu Ltd | Method of mounting of printed wiring board |
| JPH09186445A (en) * | 1997-02-10 | 1997-07-15 | Fujitsu Ltd | How to print solder cream |
-
1986
- 1986-06-18 JP JP14223286A patent/JPS62299098A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01259594A (en) * | 1988-04-08 | 1989-10-17 | Fujitsu Ltd | Method of mounting of printed wiring board |
| JPH09186445A (en) * | 1997-02-10 | 1997-07-15 | Fujitsu Ltd | How to print solder cream |
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