JPH06112463A - Semiconductor device and mounting method thereof - Google Patents

Semiconductor device and mounting method thereof

Info

Publication number
JPH06112463A
JPH06112463A JP4256219A JP25621992A JPH06112463A JP H06112463 A JPH06112463 A JP H06112463A JP 4256219 A JP4256219 A JP 4256219A JP 25621992 A JP25621992 A JP 25621992A JP H06112463 A JPH06112463 A JP H06112463A
Authority
JP
Japan
Prior art keywords
bump
chip
bumps
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4256219A
Other languages
Japanese (ja)
Inventor
Yoshihiro Kashiba
良裕 加柴
Goro Ideta
吾朗 出田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4256219A priority Critical patent/JPH06112463A/en
Publication of JPH06112463A publication Critical patent/JPH06112463A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145Material
    • H01L2224/14505Bump connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81143Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device where flip chips are easily mounted high in density and a mounting method thereof. CONSTITUTION:First bumps 5 and second bumps 6 smaller than the first bumps 5 in size but higher in melting point are provided between an IC chip 2 and a first bump 5. First of all, a self-alignment process is carried out when the first bumps 5 are formed by fusing, and then the IC chip 2 and the board 1 are very precisely positioned and connected. Then, the IC chip 2 and the board 1 are connected high in density with the second bumps 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は複数のバンプを介してI
Cチップと基板との電気的信号のやりとりを行うための
半導体装置及びその実装方法に係り、特に高密度フリッ
プチップ実装技術に関する。
FIELD OF THE INVENTION The present invention uses I through a plurality of bumps.
The present invention relates to a semiconductor device for exchanging electrical signals between a C chip and a substrate and a mounting method thereof, and particularly to a high density flip chip mounting technique.

【0002】[0002]

【従来の技術】図5(a)(b)の断面模式図に、従来から
一般的に用いられている、例えば日本金属学会会報第2
3巻第12号 (1984) 1004〜1013頁に記載されたフリッ
プチップ実装の手順を示す。即ち、フリップチップ実装
においてはICチップ2に例えば蒸着法によって成膜さ
れた、例えば 直径100μm程度のPb−Snはんだから
構成されるバンプ5を形成しておく。一方、基板1にも
同様のバンプ5を形成する。このようにして形成された
ICチップ2上のバンプ5を基板1上のバンプ5と位置
ぎめする。このときの位置合わせは、突き合わせする前
にハーフミラーを用いて行う。この後、突き合わせて加
熱溶融すると接合が完了する。はんだバンプ5は溶融す
るとはんだの表面張力によって正確な位置にセルフアラ
イメントされる。なお、上記バンプ5はICチップ2も
しくは基板1のいずれか一方に形成されていてもほぼ同
様の効果が期待できる。なお、3は入出力電極、4は薄
膜である。
2. Description of the Related Art In the schematic cross-sectional views of FIGS.
The flip-chip mounting procedure described in Vol. 3, No. 12 (1984), pages 1004 to 1013 is shown. That is, in flip-chip mounting, bumps 5 made of, for example, Pb-Sn solder having a diameter of about 100 μm, which are formed by vapor deposition, are formed on the IC chip 2. On the other hand, the same bump 5 is formed on the substrate 1. The bumps 5 on the IC chip 2 thus formed are positioned with the bumps 5 on the substrate 1. The alignment at this time is performed using a half mirror before the butting. After that, when they are butted and heated and melted, the joining is completed. When the solder bumps 5 are melted, they are self-aligned at correct positions by the surface tension of the solder. Even if the bumps 5 are formed on either the IC chip 2 or the substrate 1, substantially the same effect can be expected. In addition, 3 is an input / output electrode, and 4 is a thin film.

【0003】また、高密度化を目的としたフリップチッ
プ実装に関しては特開平4ー155866号公報に記載された半
導体装置がある。すなわち、超高速光通信用のホトダイ
オードではバンプの直径が30μm程度と小さくなり、表
面張力によるセルフアライメント方式が困難となるた
め、別の方法が提案されている。図6の模式断面図に、
ここで示された装置を示す。これによれば、OEIC1
上の電極3に凹形の金めっき4を形成し、この中にSn
8を蒸着する。いっぽう、ホトダイオード2上の電極3
には凸形の金めっき4を形成する。このような装置にお
いては、凹形凸形それぞれの金めっきが、はめ合いによ
り高精度な位置合わせができ、加熱によりAu−Sn共
晶合金が形成され接合が達成できるとされている。
Regarding flip chip mounting for the purpose of high density, there is a semiconductor device described in JP-A-4-155866. That is, in a photodiode for ultrahigh-speed optical communication, the diameter of the bump is as small as about 30 μm, and the self-alignment method by surface tension becomes difficult, so another method has been proposed. In the schematic sectional view of FIG.
2 shows the device shown here. According to this, OEIC1
A concave gold plating 4 is formed on the upper electrode 3 and Sn is
8 is vapor-deposited. On the other hand, the electrode 3 on the photodiode 2
On this, a convex gold plating 4 is formed. In such an apparatus, it is said that the concave and convex gold platings can be aligned with each other with high precision by fitting, and the Au-Sn eutectic alloy is formed by heating to achieve the bonding.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、高密度
化に対して図5に示した方法を用いると、バンプサイズ
が小さくなるため、位置ぎめが困難となり、かつ表面張
力も小さくなるため十分なセルフアライメント効果が期
待できなくなり、所望のバンプ接続が不可能となる。そ
の結果、歩留まりが大幅に低下するという問題が生ず
る。
However, when the method shown in FIG. 5 is used for increasing the density, the bump size becomes small, which makes positioning difficult and the surface tension also becomes small. The alignment effect cannot be expected and the desired bump connection becomes impossible. As a result, there arises a problem that the yield is significantly reduced.

【0005】一方、高密度化対応として図6に示した方
法では、複雑な形状のバンプ形成が必要となるため、半
導体レーザ等の高価なICチップの接続用にしか用いる
ことができない。また、位置の確認は比較的容易にな
り、接続の信頼性は向上するものの、固相状態ではめ合
いを利用して接続するため、誤差10μm以下の高精度
の位置ぎめ装置は不可欠であり、実装コストもアップし
汎用の部品実装には適用できない。
On the other hand, the method shown in FIG. 6 for high density requires the formation of bumps having a complicated shape, and therefore can be used only for connecting expensive IC chips such as semiconductor lasers. Further, although the position can be confirmed relatively easily and the reliability of the connection is improved, since the connection is made by using the fitting in the solid state, a highly accurate positioning device with an error of 10 μm or less is indispensable. The mounting cost also increases and it cannot be applied to general-purpose component mounting.

【0006】本発明は、かかる問題点を解決するために
なされたものであり、高密度化したフリップチップ実装
においても、容易にかつ信頼性高く接続できる汎用的な
半導体装置及びその実装方法を提供するものである。
The present invention has been made to solve the above problems, and provides a general-purpose semiconductor device which can be connected easily and with high reliability even in high-density flip-chip mounting, and a mounting method thereof. To do.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は、
ICチップと基板とを接続するバンプをセルフアライメ
ントを行う第一のバンプ、及びこの第一のバンプより融
点が高くサイズの小さい第二のバンプで構成するように
したものである。
The semiconductor device of the present invention comprises:
The bumps that connect the IC chip and the substrate are composed of first bumps that perform self-alignment and second bumps that have a higher melting point and a smaller size than the first bumps.

【0008】また、本発明の半導体装置の実装方法は、
ICチップまたは基板に溶融接合後第一のバンプを形成
する第一のバンプ材と溶融接合後第二のバンプを形成す
る第二のバンプ材とを形成する工程、第一のバンプ材の
みを溶融させて第一のバンプを形成し上記ICチップの
高精度位置ぎめをする工程、並びに位置ぎめ工程後第一
のバンプ及び第二のバンプ材を溶融・加圧し第二のバン
プを形成する工程を施すものである。
The semiconductor device mounting method of the present invention is
A step of forming a first bump material for forming a first bump after fusion bonding on an IC chip or a substrate and a second bump material for forming a second bump after fusion bonding, melting only the first bump material Then, the step of forming the first bump to form the high-precision positioning of the IC chip, and the step of melting and pressing the first bump and the second bump material after the positioning step to form the second bump are performed. It is something to give.

【0009】さらに、第一及び第二のバンプを溶融させ
た状態で加圧力を除去した後冷却しバンプを凝固させる
工程を施す。
Further, a step of cooling the first and second bumps in a molten state after removing the applied pressure and solidifying the bumps is performed.

【0010】そして、ICチップまたは基板のいずれか
一方に第一のバンプ材と第二のバンプ材とを同じ材料で
同じ高さに形成し、他方には第一バンプ材のみを上記材
料と異なる材料で形成するようにした。
Then, the first bump material and the second bump material are formed of the same material at the same height on one of the IC chip and the substrate, and on the other, only the first bump material is different from the above material. It is made of material.

【0011】[0011]

【作用】本発明の半導体装置においては、融点が低くサ
イズの大きい第一のバンプでセルフアライメントを行い
容易に高精度に位置ぎめ接続でき、融点が高くサイズの
小さい第二のバンプを用いて高密度の接続ができる。
In the semiconductor device of the present invention, self-alignment is performed by the first bump having a low melting point and a large size, and it is possible to easily position and connect with high precision, and the second bump having a high melting point and a small size is used. Allows density connections.

【0012】また、実装方法においては、まず第一のバ
ンプ材のみを溶融させて高精度な位置ぎめ装置を用いず
ともセルフアライメントによる高精度位置ぎめができ
る。次に第二のバンプ材を溶融・加圧接触させて接続す
るため、セルフアライメント時には第二のバンプ材は固
相状態であり、第二のバンプが誤って接続されることを
防止でき、高い信頼性で第二のバンプにより高密度の接
続ができる。
Further, in the mounting method, first, only the first bump material is melted and high-precision positioning can be performed by self-alignment without using a high-precision positioning device. Next, since the second bump material is melted and pressure-contacted to be connected, the second bump material is in a solid phase state during self-alignment, and it is possible to prevent the second bump material from being accidentally connected. The second bump provides reliable connection with high density.

【0013】さらに、第一及び第二のバンプを溶融させ
た状態で加圧力を除去した後冷却し、バンプを凝固させ
たため、前記の作用に加えてバンプの形状を制御でき、
接合部の長期信頼性が向上する。
Further, since the pressure is removed after the first and second bumps are melted and then cooled to solidify the bumps, the shape of the bumps can be controlled in addition to the above-mentioned action.
The long-term reliability of the joint is improved.

【0014】そして、ICチップまたは基板のいずれか
一方に第一バンプ材と第二バンプ材を同じ材料で同じ高
さに形成し、他方には第一バンプ材のみを上記材料と異
なる材料で形成しており、バンプ材の形成プロセスが簡
略化できる。
Then, the first bump material and the second bump material are formed on the one of the IC chip and the substrate with the same material and at the same height, and on the other, only the first bump material is formed with a material different from the above material. Therefore, the bump material forming process can be simplified.

【0015】[0015]

【実施例】実施例1.以下、本発明の実施例を図につい
て説明する。図1(a)〜(c)は本発明の一実施例の半導
体装置、及びその実装方法を工程順に示す断面模式図で
ある。図において、1は基板、2はICチップ、3は入
出力電極、4は入出力電極3上に形成された密着性を確
保するための例えばAuからなる薄膜、5はセルフアラ
イメントを行うための例えば融点が190℃のPb40
Sn60のはんだからなる第一のバンプ、5aはICチ
ップ2に形成された,5Aは基板1に形成された第一の
バンプ材で、この場合はそれぞれ直径100μm、高さ100
μmで、第一のバンプ5と同じPb40Sn60のはん
だからなる。6は第一のバンプ5より融点が高くサイズ
の小さい例えば融点が260℃のPb70Sn30から
なる第二のバンプ、6aはICチップ2に形成された,
6Aは基板1に形成された第二のバンプ材で、この場合
はそれぞれ直径30μm、高さ30μmで、第二のバンプ5
と同じPb70Sn30からなる。7は第二のバンプを
接触させるための加圧力である。
EXAMPLES Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1A to 1C are schematic sectional views showing a semiconductor device according to an embodiment of the present invention and a mounting method thereof in the order of steps. In the figure, 1 is a substrate, 2 is an IC chip, 3 is an input / output electrode, 4 is a thin film made of, for example, Au formed on the input / output electrode 3 for ensuring adhesion, and 5 is for self-alignment. For example, Pb40 with a melting point of 190 ° C
A first bump made of Sn60 solder, 5a is formed on the IC chip 2, 5A is a first bump material formed on the substrate 1, and in this case, the diameter is 100 μm and the height is 100 μm.
It is made of Pb40Sn60 solder which is the same as the first bump 5 in μm. 6 is a second bump made of Pb70Sn30 having a higher melting point and a smaller size than the first bump 5, for example, a melting point of 260 ° C., and 6a is formed on the IC chip 2.
6A is a second bump material formed on the substrate 1. In this case, the second bump 5 has a diameter of 30 μm and a height of 30 μm.
The same Pb70Sn30 is used. Reference numeral 7 is a pressing force for contacting the second bump.

【0016】まず、第一のバンプ材5a,5A、第二の
バンプ材6a,6Aを上記組成のPb、Snをそれぞれ
厚さを変えて積層蒸着したのち窒素雰囲気中で加熱溶融
することによって基板1とICチップ2上に形成する。
基板1上にICチップ2を位置ぎめし、接触させる(図
1(a))。このとき第一のバンプ材5a,5Aは接触す
るが、第二のバンプ材6a,6Aはまだ離れた状態に保
たれる。次に第一のバンプ5、即ち第一のバンプ材5
a,5Aの融点以上、第二のバンプ6、即ち第二のバン
プ材6a,6Aの融点以下に例えばホットプレートによ
って210℃に加熱する。その結果第一のバンプ材5
a,5Aのみが溶融し接続され、第一のバンプ5が形成
される(図1(b))。この際、セルフアライメントによ
り高精度に位置ぎめされる。さらに第二のバンプ材6
a,6Aの融点以上、例えば280℃に加熱・接触させ
ることによって接続し第二のバンプ6を形成する(図1
(c))。なお、このとき、第一のバンプ5は表面張力に
よってある一定の高さを維持するため、第二のバンプ材
6a,6Aを接触させるためにはICチップ2を加圧し
てやる必要がある。第二のバンプ材6a,6Aを融点以
上に加熱するには、例えばホットプレートの温度を急激
に上昇させても良いが、一般的にはホットプレートは熱
容量が大きいため、加圧治具を瞬時加熱する方が好まし
い。この結果、基板1上に複数のICチップ2が搭載さ
れていても、加圧兼加熱治具を用いることによって順次
高密度接合が可能となる。ICチップ2を加圧した状態
にて冷却することによって、接続は完了する。
First, the first bump materials 5a and 5A and the second bump materials 6a and 6A are laminated and vapor-deposited with Pb and Sn having the above-mentioned compositions, respectively, and then melted by heating in a nitrogen atmosphere. 1 and the IC chip 2 are formed.
The IC chip 2 is positioned and brought into contact with the substrate 1 (FIG. 1 (a)). At this time, the first bump materials 5a and 5A are in contact with each other, but the second bump materials 6a and 6A are still kept apart. Next, the first bump 5, that is, the first bump material 5
It is heated to 210 ° C. by a hot plate, for example, above the melting point of a, 5A and below the melting point of the second bump 6, that is, the second bump material 6a, 6A. As a result, the first bump material 5
Only a and 5A are melted and connected to form the first bump 5 (FIG. 1B). At this time, the positioning is performed with high accuracy by self-alignment. Further the second bump material 6
a and 6A or higher, for example, 280 ° C. to form a second bump 6 by connecting by heating and contacting (FIG. 1).
(c)). At this time, since the first bump 5 maintains a certain height due to the surface tension, it is necessary to press the IC chip 2 in order to bring the second bump materials 6a and 6A into contact with each other. In order to heat the second bump members 6a and 6A to a temperature equal to or higher than the melting point, for example, the temperature of the hot plate may be rapidly increased. It is preferable to heat. As a result, even if a plurality of IC chips 2 are mounted on the substrate 1, high-density bonding can be sequentially performed by using the pressing / heating jig. The connection is completed by cooling the IC chip 2 under pressure.

【0017】この実施例においては、融点が低くサイズ
の大きい第一のバンプ、即ち第一のバンプ材のみを溶融
させて高精度な位置ぎめ装置を用いずともセルフアライ
メントにより容易に高精度に位置ぎめ接続ができる。こ
の際、第二のバンプ材は固相状態であり、第二のバンプ
が誤って接続されることを防止でき、次いで位置ぎめさ
れた状態で第二のバンプ材を溶融し融点が高くサイズの
小さい第二のバンプにより容易に高い信頼性で高密度の
接続ができる。高精度位置ぎめ装置を用いなくとも従来
の装置でセルフアライメントによって接続ミスを生じる
ことなく高密度フリップチップ実装ができる。
In this embodiment, only the first bump having a low melting point and a large size, that is, the first bump material is melted and the self-alignment can be performed easily and highly accurately without using a highly accurate positioning device. Gime connection is possible. At this time, the second bump material is in a solid phase state, which can prevent the second bump from being erroneously connected, and then melts the second bump material in a positioned state to have a high melting point and a large size. The small second bump facilitates reliable, high density connections. Even if a high-precision positioning device is not used, high-density flip-chip mounting can be performed without causing connection errors due to self-alignment in the conventional device.

【0018】実施例2.図1に示す半導体装置の実装方
法の他の実施例を説明する。第二のバンプ6の融点以上
に加熱するまでは上記実施例1のプロセスと同様である
が、第一のバンプ5、第二のバンプ6が溶融した状態で
加圧力を取り除き、冷却しバンプを凝固させる。而して
加圧力の分だけ第一のバンプ5、第二のバンプ6の高さ
が高くなる。この時、第二のバンプ6がくびれて分離し
ないよう、第一のバンプ5と第二のバンプ6、即ち第一
のバンプ材5a,5A、第二のバンプ材6a,6Aの数
とサイズを力の釣合から設計してやることによって、第
一,第二のバンプ5,6の形状をコントロールすること
が可能となる。バンプの形状が接合部の長期信頼性に影
響することは、良く知られている(日本金属学会会報第
23巻第12号参照)が、サイズの小さい第二のバンプ
6の形状をいわゆる鼓形にすることによって大幅な長寿
命化が図れる。
Example 2. Another embodiment of the method of mounting the semiconductor device shown in FIG. 1 will be described. The process is the same as that of the first embodiment until the second bump 6 is heated to a temperature equal to or higher than the melting point, but the applied pressure is removed in a molten state of the first bump 5 and the second bump 6, and the bump is cooled. Solidify. Therefore, the height of the first bump 5 and the second bump 6 is increased by the amount of the pressing force. At this time, the numbers and sizes of the first bumps 5 and the second bumps 6, that is, the first bump materials 5a and 5A and the second bump materials 6a and 6A are set so that the second bumps 6 do not constrict and separate. The shape of the first and second bumps 5 and 6 can be controlled by designing from the balance of forces. It is well known that the shape of the bumps affects the long-term reliability of the joint (see Proceedings of the Japan Institute of Metals, Vol. 23, No. 12). By doing so, the life can be significantly extended.

【0019】次に、上記実施例の半導体装置の実装方法
におけるセルフアライメントの効果を図2(a)〜(c)の
断面模式図により説明する。ここでは例えば、第一のバ
ンプ材5a,5Aのサイズとして直径 100μm、第二の
バンプ材6a,6A,6b,6Bのサイズとして直径50
μm、バンプ間の距離として40μm程度を想定する。図
2(a)に示すようにバンプ位置ずれが横方向に60μm、
紙面の前後方向に30μm発生したとすると、第一のバン
プ5はそれぞれ所定のバンプ材5a,5Aと接触するも
のの、第二のバンプ6は設計とは異なる回路が第二のバ
ンプ材6Bと6aで形成されることになる。しかし、図
2(b)に示すように、第一のバンプ5が溶融した時点で
矢印で示す方向に表面張力が働き、表面張力の働かない
固相状態の第二のバンプ材6B、6aの誤った回路は開
放される。この結果、図2(c)に示すようにセルフアラ
イメントが可能となる。さらに、第二のバンプの融点以
上に加熱・接触させることによって接続は完了する。こ
のように、フリップチップによるフェイスダウンアッセ
ンブリにおいて50μmピッチレベルの高密度化が信頼性
高く行える。
Next, the effect of self-alignment in the semiconductor device mounting method of the above embodiment will be described with reference to the schematic sectional views of FIGS. 2 (a) to 2 (c). Here, for example, the diameter of the first bump material 5a, 5A is 100 μm, and the size of the second bump material 6a, 6A, 6b, 6B is 50 μm.
It is assumed that the distance between the bumps is about 40 μm. As shown in FIG. 2 (a), the bump position shift is 60 μm in the lateral direction,
If 30 μm is generated in the front-back direction of the paper surface, the first bumps 5 come into contact with the predetermined bump materials 5a and 5A, respectively, but the second bumps 6 have circuits different from the design and the second bump materials 6B and 6a. Will be formed in. However, as shown in FIG. 2B, when the first bumps 5 are melted, surface tension acts in the direction indicated by the arrow, and the second bump materials 6B and 6a in the solid state in which the surface tension does not act The wrong circuit is opened. As a result, self-alignment becomes possible as shown in FIG. Further, the connection is completed by heating and contacting the melting point of the second bump or higher. As described above, in the face-down assembly using the flip chip, the high density of 50 μm pitch level can be achieved with high reliability.

【0020】また、図1、図2に示すように上記実施例
においては、第一のバンプ5、即ち第一のバンプ材5
a,5AはICチップ2の隅に形成したが、有効な表面
張力が働けば、ここに限定するわけではない。すなわ
ち、図3(a)(b)の平面図に示すように、平行方向の位
置ずれに関してはバンプがICチップ面内のどこに形成
されていても同様の表面張力が働く。しかし、回転方向
に関してはICチップの周辺では回転力として働くが、
中心では効果がない。したがって、第一のバンプ5の位
置、形状は以上の点を考慮して、配置する。
Further, as shown in FIGS. 1 and 2, in the above embodiment, the first bump 5, that is, the first bump material 5 is used.
Although a and 5A are formed at the corners of the IC chip 2, they are not limited to these as long as effective surface tension works. That is, as shown in the plan views of FIGS. 3 (a) and 3 (b), with respect to the positional deviation in the parallel direction, the same surface tension acts wherever the bump is formed in the IC chip surface. However, as for the rotation direction, it works as a rotation force around the IC chip,
No effect at the center. Therefore, the position and shape of the first bump 5 are arranged in consideration of the above points.

【0021】また、表面張力はバンプそれぞれに働き、
その力の総和でもってICチップ2を動かすため、第一
のバンプ5の数はこの点を考慮すれば容易に設計でき
る。
The surface tension acts on each bump,
Since the IC chip 2 is moved by the total of the forces, the number of the first bumps 5 can be easily designed by considering this point.

【0022】なお、図1、図2の上記実施例においては
第一のバンプ5、即ち第一のバンプ材5a,5Aの形状
は球形として説明したが、この形状に限ることはなく、
第一のバンプ5の表面張力によってICチップ2が移動
し、高精度位置ぎめができれば良い。たとえば、ICチ
ップ2の外周近傍に沿った複数の直方体にすることによ
っても表面張力が働き、セルフアライメントが可能とな
る。但し、バンプが長くなるとバンプ材料の流動が生
じ、基板1とICチップ2間のクリアランスが変化し、
不良の原因となるので注意を要する。
Although the shape of the first bump 5, that is, the first bump material 5a, 5A has been described as a spherical shape in the above embodiments of FIGS. 1 and 2, the shape is not limited to this.
It suffices that the IC chip 2 be moved by the surface tension of the first bumps 5 and highly accurate positioning be performed. For example, by forming a plurality of rectangular parallelepipeds along the vicinity of the outer periphery of the IC chip 2, the surface tension also works and self-alignment becomes possible. However, as the bump becomes longer, the flow of the bump material occurs and the clearance between the substrate 1 and the IC chip 2 changes,
Be careful as it may cause defects.

【0023】また、上記実施例においてははんだバンプ
の場合について説明したが、はんだ以外のほかの材料に
おいても蒸着などの方法で形成でき、かつ同様の効果を
期待できることはいうまでもない。
Further, in the above-mentioned embodiment, the case of the solder bump has been described, but it goes without saying that the material can be formed by a method such as vapor deposition with a material other than the solder and the same effect can be expected.

【0024】また、上記実施例においてはバンプ材を基
板側,ICチップ側両方に形成した場合について説明し
たが、必ずしも両方に形成する必要はなく、少なくとも
どちらか一方に形成すれば良い。
In the above embodiment, the case where the bump material is formed on both the substrate side and the IC chip side has been described, but it is not always necessary to form it on both sides, and it may be formed on at least one of them.

【0025】さらに、上記実施例においてはバンプ材を
バンプと同一材料で形成した場合について説明したが、
バンプ材をバンプと異なる材料とし、基板側,ICチッ
プ側のバンプ材により所望のバンプ材料(組成)となる
ようにしても良い。
Further, in the above embodiment, the case where the bump material is formed of the same material as the bump has been described.
The bump material may be different from the material of the bump, and the desired bump material (composition) may be obtained by the bump material on the substrate side and the IC chip side.

【0026】実施例3.この例を図4の断面模式図にて
説明する。基板1側には第一のバンプ材5A、5Bのみ
を形成し、ICチップ2側には第一のバンプ材5a、5
b及び第二のバンプ材6a、6bを形成する。材料とし
ては、例えば基板1側の第一のバンプ材5A、5Bには
Snを、ICチップ2側の第一のバンプ材5a、5b、
第二のバンプ材6a、6bにはそれぞれ95Pb5Sn
を選定する。以上のような半導体装置を構成した場合の
製造方法は前記と同様であるが、第一のバンプ材の材料
が基板側とICチップ側で異なるため、加熱によりまず
基板1側の第一のバンプ材5A、5BとICチップ側の
第一のバンプ材5a、5bとが反応しPbSnの合金組
成になり、溶融する。この反応形成されたPbSn、即
ち第一のバンプの組成比すなわち融点は基板1、ICチ
ップ2側のそれぞれの第一のバンプ材のサイズによって
制御できる。例えば上記組成でサイズが同一であれば第
一のバンプはPb47.5Sn52.5の組成で融点は約 200℃
となり、第二のバンプ即ち第二のバンプ材の融点(約 3
10℃)より低くなり、かつサイズは倍になる。次に、第
二のバンプの融点以上に加熱・加圧接触させることによ
って接続される。要は第二のバンプが第一のバンプより
融点が高くかつサイズが小さくなるよう半導体装置を構
成すれば、上記実施例と同様の効果が得られる。なお、
この実施例においては、バンプ材を形成する箇所とバン
プ材の種類を特定したため、すなわち基板側とICチッ
プ側それぞれに同一種類・同一高さのバンプ材を形成す
るのみで良くしたため、バンプ材の形成プロセスが簡略
化でき、工業的価値は大幅に向上する。
Example 3. This example will be described with reference to the schematic sectional view of FIG. Only the first bump materials 5A and 5B are formed on the substrate 1 side, and the first bump materials 5a and 5B are formed on the IC chip 2 side.
b and the second bump materials 6a and 6b are formed. As the material, for example, Sn is used for the first bump materials 5A, 5B on the substrate 1 side, and the first bump materials 5a, 5b on the IC chip 2 side are used.
95Pb5Sn is used for the second bump materials 6a and 6b, respectively.
Is selected. The manufacturing method when the semiconductor device as described above is configured is similar to the above, but since the material of the first bump material is different between the substrate side and the IC chip side, the first bump on the substrate 1 side is first heated by heating. The materials 5A and 5B react with the first bump materials 5a and 5b on the IC chip side to become an alloy composition of PbSn and melt. The composition ratio of the PbSn thus formed, that is, the composition ratio of the first bump, that is, the melting point, can be controlled by the size of the first bump material on the substrate 1 side and the IC chip 2 side. For example, if the above composition has the same size, the first bump has a composition of Pb47.5Sn52.5 and a melting point of about 200 ° C.
Becomes the melting point of the second bump, that is, the second bump material (about 3
10 ° C) lower and double the size. Next, the second bumps are connected by heating and press contact with each other at a temperature higher than the melting point of the second bumps. In short, if the semiconductor device is configured such that the second bump has a higher melting point and a smaller size than the first bump, the same effect as that of the above embodiment can be obtained. In addition,
In this embodiment, since the location where the bump material is formed and the type of the bump material are specified, that is, it is sufficient to form the bump material of the same type and the same height on the substrate side and the IC chip side, respectively. The forming process can be simplified and the industrial value is greatly improved.

【0027】なお、上記実施例においては第一のバン
プ、第二のバンプともに入出力電極上に形成したが、第
一のバンプを位置ぎめ用のダミーバンプ、第二のバンプ
をICチップと基板の電気的信号のやりとりを行う入出
力電極上のバンプとしても差し支えない。
In the above embodiment, both the first bump and the second bump were formed on the input / output electrodes. However, the first bump is a dummy bump for positioning, and the second bump is formed on the IC chip and the substrate. It may also be a bump on the input / output electrodes for exchanging electrical signals.

【0028】[0028]

【発明の効果】以上説明したように、本発明の半導体装
置は、ICチップと基板とを接続するバンプをセルフア
ライメントを行う第一のバンプ、及びこの第一のバンプ
より融点が高くサイズの小さい第二のバンプで構成する
ようにしたので、第一のバンプでセルフアライメントを
行い容易に高精度に位置ぎめ接続でき、第二のバンプを
用いて高密度の接続ができ、実装の高密度化に対応でき
る。高精度位置ぎめ装置を用いなくとも従来の装置でセ
ルフアライメントによって接続ミスを生じることなく高
密度フリップチップ接合ができる。
As described above, the semiconductor device of the present invention has the first bump for self-aligning the bump connecting the IC chip and the substrate, and the melting point higher and the size smaller than the first bump. Since it is configured with the second bump, self-alignment can be easily performed with the first bump for highly accurate positioning and connection, and high density connection can be achieved by using the second bump for higher packaging density. Can handle. Even if a high-precision positioning device is not used, high-density flip-chip bonding can be performed by a conventional device without causing connection errors due to self-alignment.

【0029】また、上記半導体装置の実装方法は、IC
チップまたは基板に 溶融接合後第一のバンプを形成す
る第一のバンプ材と溶融接合後第二のバンプを形成する
第二のバンプ材とを形成する工程、第一のバンプ材のみ
を溶融させて第一のバンプを形成し上記ICチップの高
精度位置ぎめをする工程、並びに位置ぎめ工程後第一の
バンプ及び第二のバンプ材を溶融・加圧し第二のバンプ
を形成する工程を施すものである。
The method of mounting the semiconductor device is
A step of forming a first bump material for forming a first bump after fusion bonding and a second bump material for forming a second bump after fusion bonding on a chip or a substrate, melting only the first bump material. A step of forming a first bump by high-precision positioning of the IC chip, and a step of melting and pressing the first bump and the second bump material to form a second bump after the positioning step. It is a thing.

【0030】さらに、第一及び第二のバンプを溶融させ
た状態で加圧力を除去した後冷却し、バンプを凝固させ
るようにしたので、接続後のバンプの形状を制御するこ
とによって、長期信頼性を向上することができる。
Furthermore, since the applied pressure is removed in the molten state of the first and second bumps and then the bumps are cooled to solidify the bumps, long-term reliability is ensured by controlling the shape of the bumps after connection. It is possible to improve the property.

【0031】そして、ICチップまたは基板のいずれか
一方に第一バンプ材と第二バンプ材を同じ材料で同じ高
さに形成し、他方には第一バンプ材のみを上記材料と異
なる材料で形成するようにしたので、バンプ材の形成プ
ロセスが簡略化できる。
Then, the first bump material and the second bump material are formed on the one of the IC chip and the substrate with the same material and at the same height, and on the other, only the first bump material is formed with a material different from the above material. As a result, the bump material forming process can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の半導体装置の実装方法を工
程順に示す断面模式図である。
FIG. 1 is a schematic sectional view showing a method of mounting a semiconductor device according to an embodiment of the present invention in the order of steps.

【図2】本発明の半導体装置の実装方法に係わる動作を
説明する断面模式図である。
FIG. 2 is a schematic cross-sectional view explaining the operation relating to the method for mounting a semiconductor device of the present invention.

【図3】本発明に係わる第一のバンプの位置とセルフア
ライメントの効果を説明する平面図である。
FIG. 3 is a plan view illustrating a position of a first bump and an effect of self-alignment according to the present invention.

【図4】本発明の他の実施例の半導体装置の実装方法を
示す断面模式図である。
FIG. 4 is a schematic sectional view showing a method of mounting a semiconductor device according to another embodiment of the present invention.

【図5】従来の半導体装置の実装方法を順に示す断面模
式図である。
5A to 5C are schematic cross-sectional views sequentially showing a method of mounting a conventional semiconductor device.

【図6】従来の高密度化された半導体装置を示す断面模
式図である。
FIG. 6 is a schematic sectional view showing a conventional semiconductor device having a high density.

【符号の説明】[Explanation of symbols]

1 基板 4 薄膜 5 第一のバンプ 5a,5A,5b,5B 第一のバンプ材 6 第二のバンプ 6a,6A,6b,6B 第二のバンプ材 7 加圧力 1 Substrate 4 Thin Film 5 First Bump 5a, 5A, 5b, 5B First Bump Material 6 Second Bump 6a, 6A, 6b, 6B Second Bump Material 7 Pressure

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成4年12月17日[Submission date] December 17, 1992

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】請求項4[Name of item to be corrected] Claim 4

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0010[Correction target item name] 0010

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0010】そして、ICチップまたは基板のいずれか
一方に第一のバンプ材と第二のバンプ材とを同じ材料
成し、他方には第一バンプ材のみを上記材料と異なる
材料で形成するようにした。
The first bump material and the second bump material are made of the same material on either the IC chip or the substrate.
Form shape, the other was only the first bump materials so as to form a different material as the material.

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0014[Correction target item name] 0014

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0014】そして、ICチップまたは基板のいずれか
一方に第一バンプ材と第二バンプ材を同じ材料で形
し、他方には第一バンプ材のみを上記材料と異なる材料
で形成しており、バンプ材の形成プロセスが簡略化でき
る。
[0014] Then, form the shape of the first bump material and the second bump material to either the IC chip or the substrate of the same material, the other forms only the first bump materials with different material as the material The bump material forming process can be simplified.

【手続補正4】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0026[Correction target item name] 0026

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0026】実施例3.この例を図4の断面模式図にて
説明する。基板1側には第一のバンプ材5A、5Bのみ
を形成し、ICチップ2側には第一のバンプ材5a、5
b及び第二のバンプ材6a、6bを形成する。材料とし
ては、例えば基板1側の第一のバンプ材5A、5Bには
Snを、ICチップ2側の第一のバンプ材5a、5b、
第二のバンプ材6a、6bにはそれぞれ95Pb5Sn
を選定する。以上のような半導体装置を構成した場合の
製造方法は前記と同様であるが、第一のバンプ材の材料
が基板側とICチップ側で異なるため、加熱によりまず
基板1側の第一のバンプ材5A、5BとICチップ側の
第一のバンプ材5a、5bとが反応しPbSnの合金組
成になり、溶融する。この反応形成されたPbSn、即
ち第一のバンプの組成比すなわち融点は基板1、ICチ
ップ2側のそれぞれの第一のバンプ材のサイズによって
制御できる。例えば上記組成でサイズが同一であれば第
一のバンプはPb47.5Sn52.5の組成で融点は約 200℃
となり、第二のバンプ即ち第二のバンプ材の融点(約 3
10℃)より低くなり、かつサイズは倍になる。次に、第
二のバンプの融点以上に加熱・加圧接触させることによ
って接続される。要は第二のバンプが第一のバンプより
融点が高くかつサイズが小さくなるよう半導体装置を構
成すれば、上記実施例と同様の効果が得られる。なお、
この実施例においては、バンプ材を形成する箇所とバン
プ材の種類を特定したため、すなわち基板側とICチッ
プ側それぞれに同一種類・ほぼ同一高さのバンプ材を形
成するのみで良くしたため、バンプ材の形成プロセスが
簡略化でき、工業的価値は大幅に向上する。
Example 3. This example will be described with reference to the schematic sectional view of FIG. Only the first bump materials 5A and 5B are formed on the substrate 1 side, and the first bump materials 5a and 5B are formed on the IC chip 2 side.
b and the second bump materials 6a and 6b are formed. As the material, for example, Sn is used for the first bump materials 5A, 5B on the substrate 1 side, and the first bump materials 5a, 5b on the IC chip 2 side are used.
95Pb5Sn is used for the second bump materials 6a and 6b, respectively.
Is selected. The manufacturing method when the semiconductor device as described above is configured is similar to the above, but since the material of the first bump material is different between the substrate side and the IC chip side, the first bump on the substrate 1 side is first heated by heating. The materials 5A and 5B react with the first bump materials 5a and 5b on the IC chip side to become an alloy composition of PbSn and melt. The composition ratio of the PbSn thus formed, that is, the composition ratio of the first bump, that is, the melting point, can be controlled by the size of the first bump material on the substrate 1 side and the IC chip 2 side. For example, if the above composition has the same size, the first bump has a composition of Pb47.5Sn52.5 and a melting point of about 200 ° C.
Becomes the melting point of the second bump, that is, the second bump material (about 3
10 ° C) lower and double the size. Next, the second bumps are connected by heating and press contact with each other at a temperature higher than the melting point of the second bumps. In short, if the semiconductor device is configured such that the second bump has a higher melting point and a smaller size than the first bump, the same effect as that of the above embodiment can be obtained. In addition,
In this embodiment, since the place where the bump material is to be formed and the type of the bump material are specified, that is, it is sufficient to form the bump material of the same type and substantially the same height on each of the substrate side and the IC chip side. The formation process of can be simplified and the industrial value is greatly improved.

【手続補正5】[Procedure Amendment 5]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0031[Correction target item name] 0031

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0031】そして、ICチップまたは基板のいずれか
一方に第一バンプ材と第二バンプ材を同じ材料で形
し、他方には第一バンプ材のみを上記材料と異なる材料
で形成するようにしたので、バンプ材の形成プロセスが
簡略化できる。
[0031] Then, form the shape of the first bump material and the second bump material to either the IC chip or the substrate of the same material, on the other so as to form only the first bump materials with different material as the material Therefore, the bump material forming process can be simplified.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/15 8934−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 27/15 8934-4M

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 複数のバンプを介してICチップと基板
との電気的信号のやりとりを行う半導体装置において、
上記バンプをセルフアライメントを行う第一のバンプ、
及びこの第一のバンプより融点が高くサイズの小さい第
二のバンプで構成するようにしたことを特徴とする半導
体装置。
1. A semiconductor device for exchanging electrical signals between an IC chip and a substrate through a plurality of bumps,
The first bump that self-aligns the above bump,
And a semiconductor device comprising a second bump having a higher melting point and a smaller size than the first bump.
【請求項2】 請求項第1項記載の第一及び第二のバン
プを介してICチップと基板が接合される半導体装置の
実装方法において、上記ICチップまたは基板に溶融接
合後第一のバンプを形成する第一のバンプ材と溶融接合
後第二のバンプを形成する第二のバンプ材を形成する工
程、第一のバンプ材のみを溶融させて第一のバンプを形
成し上記ICチップの高精度位置ぎめをする工程、並び
に位置ぎめ工程後第一のバンプ及び第二バンプ材を溶融
・加圧し第二のバンプを形成する工程を施すことを特徴
とする半導体装置の実装方法。
2. A method for mounting a semiconductor device, wherein an IC chip and a substrate are bonded via the first and second bumps according to claim 1, wherein the first bump after fusion bonding to the IC chip or the substrate. A step of forming a second bump material for forming a second bump after fusion bonding with a first bump material for forming the first bump material, and forming a first bump by melting only the first bump material to form the first bump material. A method of mounting a semiconductor device, comprising: performing a step of performing highly accurate positioning; and a step of forming a second bump by melting and pressing the first bump and the second bump material after the positioning step.
【請求項3】 第一及び第二のバンプを溶融させた状態
で加圧力を除去した後冷却しバンプを凝固させる工程を
施すことを特徴とする請求項第2項記載の半導体装置の
実装方法。
3. The method for mounting a semiconductor device according to claim 2, wherein a step of cooling the first and second bumps in a molten state after removing the applied pressure to solidify the bumps is performed. .
【請求項4】 ICチップまたは基板のいずれか一方に
第一のバンプ材と第二のバンプ材を同じ材料で同じ高さ
に形成し、他方には第一のバンプ材のみを上記材料と異
なる材料で形成するようにしたことを特徴とする請求項
第2項または第3項記載の半導体装置の実装方法。
4. A first bump material and a second bump material are formed of the same material at the same height on either one of an IC chip or a substrate, and on the other, only the first bump material is different from the above material. 4. The method for mounting a semiconductor device according to claim 2, wherein the mounting method is made of a material.
JP4256219A 1992-09-25 1992-09-25 Semiconductor device and mounting method thereof Pending JPH06112463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4256219A JPH06112463A (en) 1992-09-25 1992-09-25 Semiconductor device and mounting method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4256219A JPH06112463A (en) 1992-09-25 1992-09-25 Semiconductor device and mounting method thereof

Publications (1)

Publication Number Publication Date
JPH06112463A true JPH06112463A (en) 1994-04-22

Family

ID=17289592

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH06112463A (en)

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