JPH05190553A - Mounting structure of semiconductor component and manufacture of its solder bump - Google Patents

Mounting structure of semiconductor component and manufacture of its solder bump

Info

Publication number
JPH05190553A
JPH05190553A JP186692A JP186692A JPH05190553A JP H05190553 A JPH05190553 A JP H05190553A JP 186692 A JP186692 A JP 186692A JP 186692 A JP186692 A JP 186692A JP H05190553 A JPH05190553 A JP H05190553A
Authority
JP
Japan
Prior art keywords
melting point
pad
solder
circuit board
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP186692A
Other languages
Japanese (ja)
Inventor
Yutaka Azumaguchi
裕 東口
Hiroyuki Otaguro
浩幸 太田黒
Akiko Matsui
亜紀子 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP186692A priority Critical patent/JPH05190553A/en
Publication of JPH05190553A publication Critical patent/JPH05190553A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide the mounting structure for a PGA type semiconductor component and a method of manufacturing solder bumps which are used at mounting, where an aligning operation is easily carried out in the mounting structure concerned and the solder bumps of composite structure are composed of high melting point solder bumps and low melting point, solder bumps. CONSTITUTION:In a semiconductor device where a PGA type semiconductor element 5 is surface-mounted on a circuit board by reflow soldering, high melting point solder bumps 20 are formed on general pads 2-2 arranged on a circuit board 1 corresponding to the general pins 6-2 of the PGA type semiconductor element 5 and also on selected pads 2-1 arranged corresponding to selected pins 6-1 arranged on the periphery of the PGA type semiconductor element 5 and low melting point solder bumps 21 are formed on the tops of the high melting point solder bumps 20 arranged on the periphery of the PGA type semiconductor element 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体部品特に、PG
A(Pin Grid Array Package) 型半導体部品の実装構
造、及び実装時に用いる半田バンプの製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a mounting structure of an A (Pin Grid Array Package) type semiconductor component and a method of manufacturing solder bumps used at the time of mounting.

【0002】半導体部品の多ピン化に伴い、近年はパッ
ケージの下面に多数(約500 ピン)のピンを近接(ピン
ピッチは約0.9 mm)してマトリックス状に植立したPG
A型半導体部品が提供されている。
With the increase in the number of pins of semiconductor parts, in recent years, a large number (about 500 pins) of pins (close to a pin pitch of about 0.9 mm) are planted in a matrix on the bottom surface of the package.
A type semiconductor components are provided.

【0003】このようなPGA型半導体部品は、それぞ
れのピンをリフロー半田付けして対応するパッドに接続
し、回路基板に表面実装するのが一般である。この際、
総てのピンとパッドとの位置ずれの検査を実施すること
は非能率的であるので、電源ピン,アースピン,或いは
信号ピンのなかから特定の数ピンを選択して、光学的手
段或いは電気的特性測定手段により、ピンとパッドとの
位置ずれの検査を実施している。
In such a PGA type semiconductor component, it is general that each pin is reflow-soldered to be connected to a corresponding pad and surface-mounted on a circuit board. On this occasion,
Since it is inefficient to check the displacement of all the pins and pads, it is necessary to select a certain number of pins from the power supply pin, the ground pin, or the signal pin, and use optical means or electrical characteristics. The measuring means inspects the displacement between the pin and the pad.

【0004】[0004]

【従来の技術】図4は従来例の図であって、(A) は表面
実装後の断面図、(B) は実装前の要所断面図である。
2. Description of the Related Art FIGS. 4A and 4B are views of a conventional example, in which FIG. 4A is a sectional view after surface mounting, and FIG.

【0005】図4において、5は、パッケージの下面に
千鳥の格子状に電極7を設け、それぞれの電極7にピン
6を銀ろう付けすることで植立配設したPGA型半導体
部品である。
In FIG. 4, reference numeral 5 denotes a PGA type semiconductor component in which electrodes 7 are provided in a zigzag lattice pattern on the lower surface of the package, and pins 6 are silver-brazed to the respective electrodes 7 so as to stand upright.

【0006】このようなPGA型半導体部品5は、それ
ぞれのピン6を対応するパッド2にリフロー半田付け
(半田8)することで、回路基板1に表面実装される。
ところで、0.9 mmピッチ等の微細ピッチで配列したパッ
ド2上に、スクリーン印刷法等でリフロー用の半田層を
設けることは、パッド2に塗布形成するクリーム状半田
の寸法のばらつき、及びクリーム状半田のパッド上から
の流出等に起因して、近接したパッド間に絶縁不良が発
生する恐れがある。
The PGA type semiconductor component 5 as described above is surface-mounted on the circuit board 1 by reflow soldering (solder 8) the respective pins 6 to the corresponding pads 2.
By the way, providing a solder layer for reflow by a screen printing method or the like on the pads 2 arranged at a fine pitch such as a pitch of 0.9 mm is because the size of the cream-like solder applied and formed on the pad 2 varies and Insulation failure may occur between adjacent pads due to the outflow from the above pads.

【0007】したがって、従来は図4の(B) に図示した
ように、それぞれのパッド2上に半田バンプ10を設け、
この半田バンプ10を加熱しリフロー半田付けすること
で、PGA型半導体部品5を回路基板1に実装してい
る。
Therefore, conventionally, as shown in FIG. 4B, a solder bump 10 is provided on each pad 2,
The PGA type semiconductor component 5 is mounted on the circuit board 1 by heating the solder bumps 10 and performing reflow soldering.

【0008】[0008]

【発明が解決しようとする課題】ところで、リフロー半
田付けして回路基板に表面実装したPGA型半導体部品
は、前述のようにピンとパッドとの位置ずれ検査を行
う。この際位置ずれ不良が検出されると、PGA型半導
体部品の周囲から熱風をパッケージの下部に吹き込ん
で、パッドとピンとを接続している半田を加熱しリフロ
ー状態にし、PGA型半導体部品の位置を調整して、ピ
ンとパッドとの位置合わせを再度実施し、その後溶融状
態の半田を硬化させて、PGA型半導体部品を再実装し
ている。
By the way, the PGA type semiconductor component surface-mounted on the circuit board by reflow soldering is subjected to the positional deviation inspection between the pin and the pad as described above. At this time, if misalignment is detected, hot air is blown into the lower part of the package from the periphery of the PGA type semiconductor component to heat the solder connecting the pads and the pins to a reflow state, and the position of the PGA type semiconductor component is changed. After adjustment, the pins and pads are aligned again, and then the molten solder is cured to remount the PGA type semiconductor component.

【0009】しかしながら、PGA型半導体部品のパッ
ケージと回路基板との狭い間隙に熱風を吹き込むことが
困難であるので、パッケージの中心部に配列したピンを
半田付けしている半田は溶け難い。このためにPGA型
半導体部品の位置を正しい方向にずらすことが困難で、
満足するような位置合わせを実施することができないと
いう問題点があった。
However, since it is difficult to blow hot air into the narrow gap between the package of the PGA type semiconductor component and the circuit board, the solder for soldering the pins arranged in the center of the package is difficult to melt. For this reason, it is difficult to shift the position of the PGA type semiconductor component in the correct direction,
There is a problem in that it is not possible to carry out a satisfactory alignment.

【0010】本発明はこのような点に鑑みて創作された
もので、位置合わせ作業が容易な半導体部品の実装構造
を提供することにある。また他の目的は、高融点半田バ
ンプと低融点半田バンプとよりなる複合構造の半田バン
プの製造方法を提供することにある。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a mounting structure of a semiconductor component which can be easily aligned. Another object is to provide a method for manufacturing a solder bump having a composite structure including a high melting point solder bump and a low melting point solder bump.

【0011】[0011]

【課題を解決するための手段】上記の目的を達成するた
めに本発明は図1に例示したように、PGA型半導体部
品をリフロー半田付けして回路基板に表面実装する装置
において、回路基板1に配列した、PGA型半導体部品
5の一般ピン6-2 を半田付けする一般パッド2-2 上に
は、高融点半田バンプ20を形成し、回路基板1に配列し
た、PGA型半導体部品5の外周部の選択したピン6-1
を半田付けする選択したパッド2-1 上には、高融点半田
バンプ20を形成し、さらにこの高融点半田バンプ20の上
部に低融点半田バンプ21を重畳して形成した構成とす
る。
In order to achieve the above-mentioned object, the present invention, as illustrated in FIG. 1, is an apparatus for surface-mounting a PGA type semiconductor component on a circuit board by reflow soldering. The high-melting-point solder bumps 20 are formed on the general pads 2-2 for soldering the general pins 6-2 of the PGA-type semiconductor components 5 arranged on the circuit board 1 and arranged on the circuit board 1. Perimeter selected pin 6-1
A high-melting-point solder bump 20 is formed on the selected pad 2-1 to be soldered, and a low-melting-point solder bump 21 is further formed on the high-melting-point solder bump 20.

【0012】またその製造方法は、図3に図示したよう
に、回路基板1の表面に、選択したパッド2-1 及び一般
パッド2-2 の上部に窓を有する、耐熱性樹脂よりなる第
1のレジスト膜31を設けた後に、選択したパッド2-1 及
び一般パッド2-2 の表面に高融点クリーム状半田25を塗
布し、高融点クリーム状半田25を所定の温度に加熱し
て、それぞれの選択したパッド2-1 , 一般パッド2-2 上
にそれぞれ半田を析出して、高融点半田バンプ20を設け
る。
Further, as shown in FIG. 3, the manufacturing method is a first heat resistant resin having a window on the surface of the circuit board 1 above the selected pad 2-1 and general pad 2-2. After providing the resist film 31 of, the high melting point cream solder 25 is applied to the surfaces of the selected pad 2-1 and general pad 2-2, and the high melting point cream solder 25 is heated to a predetermined temperature, respectively. Solder is deposited on the selected pad 2-1 and general pad 2-2, respectively, to provide the high melting point solder bump 20.

【0013】次に、選択したパッド2-1 の高融点半田バ
ンプ20の上部に窓を有する、耐熱性樹脂よりなる第2の
レジスト膜32を回路基板1上に設け、選択したパッド2-
1 の高融点半田バンプ20の表面に、低融点クリーム状半
田26を塗布し、低融点クリーム状半田26を所定の温度に
加熱して、それぞれの選択したパッド2-1 の高融点半田
バンプ20上に半田を析出して、低融点半田バンプ21を重
畳形成する。
Next, a second resist film 32 made of a heat-resistant resin having a window above the high melting point solder bumps 20 of the selected pad 2-1 is provided on the circuit board 1 and the selected pad 2-
The low melting point cream solder 26 is applied to the surface of the high melting point solder bump 20 of 1 and the low melting point cream solder 26 is heated to a predetermined temperature, and the high melting point solder bump 20 of each selected pad 2-1 is applied. Solder is deposited on top of this to form low-melting-point solder bumps 21 in an overlapping manner.

【0014】その後、第2のレジスト膜32及び第1のレ
ジスト膜31をエッチングして除去するものとする。
After that, the second resist film 32 and the first resist film 31 are etched and removed.

【0015】[0015]

【作用】本発明は、図2の(A) に図示したように、低融
点半田バンプ21の溶融温度に加熱して、低融点半田バン
プ21のみをリフローさせて、選択したピン6-1 と選択し
たパッド2-1 のみを低融点半田21A でリフロー半田付け
して、PGA型半導体部品5を回路基板1に仮実装す
る。そしてこの選択したピン6-1 と選択したパッド2-1
との位置ずれの検査を実施する。
In the present invention, as shown in FIG. 2A, the low melting point solder bumps 21 are heated to the melting temperature to reflow only the low melting point solder bumps 21 and the selected pins 6-1 and Only the selected pad 2-1 is reflow-soldered with the low melting point solder 21A to temporarily mount the PGA type semiconductor component 5 on the circuit board 1. And this selected pin 6-1 and selected pad 2-1
Check the positional deviation between and.

【0016】この際位置ずれ不良が検出された場合に、
熱風でこの低融点半田21A を溶かすのであるが、この選
択したピン6-1 は、PGA型半導体部品5の外周部に配
列したものであるから、容易にリフロー状態にすること
ができる。
At this time, if a misalignment is detected,
The low melting point solder 21A is melted by hot air, but the selected pins 6-1 are arranged on the outer peripheral portion of the PGA type semiconductor component 5, so that the reflow state can be easily achieved.

【0017】そして、位置ずれ調整が終了すると、高融
点半田バンプ20の溶融温度まで加熱して、高融点半田バ
ンプ20をリフローさせて、図2の(B) に図示したよう
に、総ての選択したパッド2-1 と選択したピン6-1 、及
び他の一般パッド2-2 と一般ピン6-2 とを高融点半田20
A でリフロー半田付けするものとする。このようにする
ことで、簡単に位置合わせ作業が行われる。
When the positional deviation adjustment is completed, the high melting point solder bumps 20 are heated to the melting temperature to reflow the high melting point solder bumps 20 and, as shown in FIG. Solder the selected pad 2-1 and the selected pin 6-1 and the other general pad 2-2 and the general pin 6-2 with high melting point solder 20
Reflow soldering shall be done at A. By doing so, the alignment work is easily performed.

【0018】また、前述の半田バンプの製造方法によれ
ば、選択したパッドの高融点半田バンプ上に、低融点半
田バンプを重畳することができ、他の一般パッドには高
融点半田バンプのみを形成することができる。
Further, according to the above-described solder bump manufacturing method, the low melting point solder bump can be superimposed on the high melting point solder bump of the selected pad, and only the high melting point solder bump can be used for the other general pads. Can be formed.

【0019】[0019]

【実施例】以下図1乃至図3を参照しながら、本発明を
具体的に説明する。なお、全図を通じて同一符号は同一
対象物を示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to FIGS. The same reference numerals denote the same objects throughout the drawings.

【0020】図1は本発明の実施例の図で、(A) は要所
断面図、(B )は回路基板の平面図、図2の(A),(B) は本
発明の作用を説明する図、図3は本発明の製造工程を示
す断面図図である。
FIG. 1 is a diagram of an embodiment of the present invention. (A) is a sectional view of a main part, (B) is a plan view of a circuit board, and (A) and (B) of FIG. 2 show the operation of the present invention. 3A and 3B are cross-sectional views showing the manufacturing process of the present invention.

【0021】図1の(A) に図示したように、PGA型半
導体部品5は、パッケージの下面に千鳥の格子状に電極
7を設け、それぞれの電極7にピンを銀ろう付けして植
立配設している。
As shown in FIG. 1A, in the PGA type semiconductor component 5, electrodes 7 are provided in a zigzag lattice on the lower surface of the package, and pins are silver-soldered on each electrode 7 to be planted. It is arranged.

【0022】この配列したピンのうち、外周部に配列し
た電源ピン,アースピン,或いは信号ピンのなかから特
定の数ピンを選んで選択したピン6-1 として、光学的手
段或いは電気的特性測定手段により、この選択したピン
6-1 と対応するパッドとの位置ずれの検査を実施し、こ
れらの選択したピン6-1 が位置ずれしていない場合は、
他の一般ピン6-2 も位置合わせがされていると、判定し
ている。
Among the arranged pins, a pin 6-1 selected by selecting a specific number of pins from the power supply pin, the ground pin, and the signal pin arranged on the outer peripheral portion is used as an optical means or an electrical characteristic measuring means. By this selected pin
Perform a misalignment check between 6-1 and the corresponding pad and if these selected pins 6-1 are not misaligned,
It is determined that the other general pins 6-2 are also aligned.

【0023】一方、回路基板1の表面に千鳥の格子状に
配列したパッドのうち、この選択したピン6-1 をリフロ
ー半田付けするパッドは、図1の(B) に斜線で図示した
選択したパッド2-1 である。
On the other hand, among the pads arranged in a zigzag grid pattern on the surface of the circuit board 1, the pads for reflow soldering the selected pins 6-1 are selected by hatching in FIG. 1 (B). Pad 2-1.

【0024】そして、図1の(A) に図示したように、選
択したパッド2-1 及び他の一般パッド2-2 上に、高融点
半田バンプ(融点 270℃〜 280℃)20を形成している。
また、選択したパッド2-1 のみには、この高融点半田バ
ンプ20の上部に、低融点半田バンプ(融点 230℃〜 240
℃)21を形成している。
Then, as shown in FIG. 1A, a high melting point solder bump (melting point 270 ° C. to 280 ° C.) 20 is formed on the selected pad 2-1 and other general pad 2-2. ing.
In addition, only the selected pad 2-1 has a low melting point solder bump (melting point 230 ° C to 240 ° C) above the high melting point solder bump 20.
21) is formed.

【0025】上述のように半田バンプを設けた回路基板
1に、PGA型半導体部品5を実装するには、先ずそれ
ぞれのピンを対応するパッドに位置合わせして、PGA
型半導体部品5を回路基板1に載せ、低融点半田バンプ
21の溶融温度に回路基板1を加熱する。
In order to mount the PGA type semiconductor component 5 on the circuit board 1 provided with the solder bumps as described above, first the respective pins are aligned with the corresponding pads, and the PGA is arranged.
Type semiconductor component 5 is placed on the circuit board 1, and low melting point solder bumps
The circuit board 1 is heated to a melting temperature of 21.

【0026】このことにより選択したパッド2-1 の低融
点半田バンプ21がリフローして、図2の(A) に図示した
ように、選択したピン6-1 と選択したパッド2-1 とが、
低融点半田21A で半田付けされる。
As a result, the low melting point solder bump 21 of the selected pad 2-1 is reflowed, and the selected pin 6-1 and the selected pad 2-1 are separated as shown in FIG. 2 (A). ,
Solder with low melting point solder 21A.

【0027】そしてこの選択したピン6-1 と選択したパ
ッド2-1 との位置ずれの検査を実施する。この際位置ず
れ不良が検出された場合に、熱風でこの低融点半田21A
を溶かすのであるが、この選択したピン6-1 は、PGA
型半導体部品5の外周部に配列したものであるから、容
易に加熱されリフロー状態となる。したがって、位置ず
れの調整ができる。
Then, the inspection of the positional deviation between the selected pin 6-1 and the selected pad 2-1 is carried out. If misalignment is detected at this time, the low melting point solder 21A
The selected pin 6-1 will melt the PGA.
Since they are arranged on the outer peripheral portion of the mold semiconductor component 5, they are easily heated and brought into a reflow state. Therefore, the displacement can be adjusted.

【0028】次に、位置ずれ調整が終了すると、回路基
板1を高融点半田バンプ20の溶融温度まで加熱する。こ
のことにより、図2の(B) に図示したように、高融点半
田バンプ20がリフローして、総ての選択したパッド2-1
と選択したピン6-1 、及び他の一般パッド2-2 と一般ピ
ン6-2 とが高融点半田20A で半田付けされる。
Next, when the positional deviation adjustment is completed, the circuit board 1 is heated to the melting temperature of the high melting point solder bump 20. This causes the high melting point solder bumps 20 to reflow, as shown in FIG.
The selected pin 6-1, the other general pad 2-2 and the general pin 6-2 are soldered with the high melting point solder 20A.

【0029】以下、この二重構造の半田バンプの製造方
法について述べる。図3の(A) に図示したように、回路
基板1の表面にポリイミド樹脂等の耐熱性の樹脂を塗布
し硬化させた後に、フォトリソグラフィ手段により、択
したパッド2-1 及び一般パッド2-2 の上部に窓を有する
第1のレジスト膜31を、回路基板1の表面に被着形成す
る。
A method of manufacturing the solder bump having the double structure will be described below. As shown in FIG. 3A, a heat-resistant resin such as polyimide resin is applied to the surface of the circuit board 1 and cured, and then the selected pad 2-1 and general pad 2-by photolithography means. A first resist film 31 having a window on the upper side of 2 is deposited on the surface of the circuit board 1.

【0030】次に図3の(B) に図示したように、選択し
たパッド2-1 , 一般パッド2-2 の上面を含む第1のレジ
スト膜31の表面の全面に、析出用の高融点クリーム状半
田25を塗布する。
Next, as shown in FIG. 3B, a high melting point for precipitation is formed on the entire surface of the first resist film 31 including the upper surfaces of the selected pad 2-1 and general pad 2-2. Apply creamy solder 25.

【0031】そして、高融点クリーム状半田25を所定の
温度に(高融点半田の溶融温度+30℃)に加熱し、半田
析出反応を進行させる。そして、回路基板1を洗浄し未
反応の高融点クリーム状半田25を除去して、図3の(C)
に図示したように、選択したパッド2-1 及び他の一般パ
ッド2-2 の表面に、断面がほぼ矩形状の高融点半田バン
プ20を設ける。
Then, the high melting point creamy solder 25 is heated to a predetermined temperature (melting temperature of the high melting point solder + 30 ° C.) to advance the solder deposition reaction. Then, the circuit board 1 is washed to remove the unreacted high melting point cream-like solder 25, and then, as shown in FIG.
As shown in FIG. 2, the high melting point solder bump 20 having a substantially rectangular cross section is provided on the surfaces of the selected pad 2-1 and the other general pad 2-2.

【0032】次に、高融点半田バンプ20上及び第1のレ
ジスト膜31上に、ポリイミド樹脂等の耐熱性の樹脂を塗
布し硬化させた後に、フォトリソグラフィ手段により、
図3の(D) に図示したように、選択したパッド2-1 の上
部に即ち選択したパッド2-1の高融点半田バンプ20の上
面が開口する窓を備えた、第2のレジスト膜32を被着形
成する。
Next, after a heat resistant resin such as a polyimide resin is applied and cured on the high melting point solder bumps 20 and the first resist film 31, by photolithography means.
As shown in FIG. 3D, the second resist film 32 having a window above the selected pad 2-1, that is, the upper surface of the high melting point solder bump 20 of the selected pad 2-1 is opened. Are formed.

【0033】そして、図3の(E) に図示したように、こ
の選択したパッド2-1 上の高融点半田バンプ20の上面を
含む第2のレジスト膜32の表面の全面に、析出用の低融
点クリーム状半田26を塗布し、低融点クリーム状半田26
を所定の温度に(低融点半田の溶融温度+30℃)に加熱
し、半田析出反応を進行させて、選択したパッド2-1上
に設けた高融点半田バンプ20の上部に、断面がほぼ矩形
状の低融点半田バンプ21を重畳して設ける。
Then, as shown in FIG. 3E, the surface of the second resist film 32 including the upper surface of the high-melting-point solder bump 20 on the selected pad 2-1 is entirely deposited on the surface of the second resist film 32. Apply the low melting point cream solder 26 and apply the low melting point cream solder 26.
Is heated to a predetermined temperature (melting temperature of low melting point solder + 30 ° C.) to promote a solder deposition reaction, and the cross section is almost rectangular at the upper part of the high melting point solder bump 20 provided on the selected pad 2-1. Low-melting-point solder bumps 21 having a shape are provided so as to overlap each other.

【0034】そして、図3の(F) に図示したように、回
路基板1を洗浄し未反応の低融点クリーム状半田26を除
去し、その後エッチングして第2のレジスト膜32及び第
1のレジスト膜31を除去する。
Then, as shown in FIG. 3F, the circuit board 1 is washed to remove the unreacted low melting point cream solder 26, and then etched to etch the second resist film 32 and the first resist film 32. The resist film 31 is removed.

【0035】上述のようにすることで、一般パッド2-2
上には高融点半田バンプ20のを設け、選択したパッド2-
1 上には高融点クリーム状半田25を、さらにこの高融点
半田バンプ20の上部に低融点半田バンプ21を重畳して設
けることができる。
By doing the above, the general pad 2-2
High-melting point solder bumps 20 are provided on the top, and the selected pads 2-
A high melting point cream-like solder 25 may be provided on the top of the 1, and a low melting point solder bump 21 may be provided on the high melting point solder bump 20 in an overlapping manner.

【0036】[0036]

【発明の効果】以上説明したように本発明は、PGA型
半導体部品の一般ピンをリフロー半田付けする回路基板
の一般パッドには、高融点半田バンプのみを設け、PG
A型半導体部品の外周部の選択したピンをリフロー半田
付けする回路基板の選択したパッドには、高融点半田バ
ンプ上に低融点半田バンプを重畳した複合バンプを設け
た、半導体部品の実装構造であって、PGA型半導体部
品のピンと回路基板のパッドをリフロー半田付けした後
の、位置合わせの調整作業が簡単で、且つ位置合わせ精
度が高いという、実用上で優れた効果を備えている。
As described above, according to the present invention, only the high melting point solder bumps are provided on the general pads of the circuit board on which the general pins of the PGA type semiconductor component are reflow soldered.
A semiconductor component mounting structure in which a composite bump in which a low melting point solder bump is superimposed on a high melting point solder bump is provided on a selected pad of a circuit board for reflow soldering a selected pin on the outer periphery of an A-type semiconductor component. Therefore, after the reflow soldering of the pin of the PGA type semiconductor component and the pad of the circuit board, the adjustment work of the alignment is easy and the alignment accuracy is high, which is an excellent effect in practical use.

【0037】また、本発明の複合バンプの製造方法によ
れば、必要とする選択したパッドに形成した高融点半田
バンプのみに、高融点半田バンプの全表面を覆うことな
く、その上面に塔状に重畳して低融点半田バンプを設け
ることができる。
Further, according to the method of manufacturing a composite bump of the present invention, only the high melting point solder bumps formed on the necessary selected pads do not cover the entire surface of the high melting point solder bumps, but the tower shape is formed on the upper surface thereof. The low-melting-point solder bump can be provided so as to overlap with.

【0038】即ち、塔状に重畳した複合バンプであるの
で、得られるバンプの平面視形状をパッドの平面視形状
よりも所望に小さくすることが容易である。したがっ
て、半田バンプをリフロー半田付けしても、パッド上か
ら流出する恐れがなくて、近接してパッド間の絶縁の信
頼度が高い。
That is, since the composite bumps are stacked in a tower shape, it is easy to make the plan shape of the obtained bump smaller than the plan shape of the pad. Therefore, even if the solder bumps are reflow-soldered, there is no fear of flowing out from the pads, and the reliability of insulation between the adjacent pads is high.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例の図で、 (A)は要所断面図 (B ) は回路基板の平面図FIG. 1 is a diagram of an embodiment of the present invention, in which (A) is a cross-sectional view of a main part and (B) is a plan view of a circuit board.

【図2】 (A),(B) は本発明の作用を説明する図2 (A) and (B) are views for explaining the operation of the present invention.

【図3】 (A),(B),(C),(D),(E),(F) は本発明の製造工
程を示す断面図
3 (A), (B), (C), (D), (E), and (F) are sectional views showing the manufacturing process of the present invention.

【図4】 従来例の図で、 (A)は表面実装後の断面図 (B)は実装前の要所断面図FIG. 4 is a view of a conventional example, (A) is a cross-sectional view after surface mounting, and (B) is a cross-sectional view of a main part before mounting.

【符号の説明】[Explanation of symbols]

1 回路基板 2 パッド 2-1 選択したパッド 2-2 一般パ
ッド 5 PGA型半導体部品 6 ピン 6-1 選択したピン 6-2 一般ピ
ン 10 半田バンプ 20 高融点
半田バンプ 20A 高融点半田 21 低融点
半田バンプ 21A 低融点半田 25 高融点
クリーム状半田 26 低融点クリーム状半田 31 第1の
レジスト膜 32 第2のレジスト膜
1 circuit board 2 pad 2-1 selected pad 2-2 general pad 5 PGA type semiconductor component 6 pin 6-1 selected pin 6-2 general pin 10 solder bump 20 high melting point solder bump 20A high melting point solder 21 low melting point solder Bump 21A Low melting point solder 25 High melting point creamy solder 26 Low melting point creamy solder 31 First resist film 32 Second resist film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 8617−4M Q ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location 8617-4M Q

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 PGA型半導体部品をリフロー半田付け
して回路基板に表面実装する装置において、 該回路基板(1) に配列した、該PGA型半導体部品(5)
の一般ピン(6-2) に対応する一般パッド(2-2) 上に、高
融点半田バンプ(20)が形成され、 該回路基板(1) に配列した、該PGA型半導体部品(5)
の外周部の選択したピン(6-1) に対応する選択したパッ
ド(2-1) 上に、高融点半田バンプ(20)が形成され、さら
に該高融点半田バンプ(20)の上部に低融点半田バンプ(2
1)が重畳して形成されてなることを特徴とする導体部品
の実装構造。
1. A device for surface-mounting a PGA type semiconductor component on a circuit board by reflow soldering, wherein the PGA type semiconductor component (5) arranged on the circuit board (1).
The high-melting point solder bumps (20) are formed on the general pads (2-2) corresponding to the general pins (6-2) of the PGA type semiconductor components (5) arranged on the circuit board (1).
A high-melting point solder bump (20) is formed on the selected pad (2-1) corresponding to the selected pin (6-1) on the outer periphery of the high-melting point solder bump (20). Melting point solder bump (2
1) A mounting structure of a conductor component, which is formed by overlapping.
【請求項2】 回路基板(1) の表面に、選択したパッド
(2-1) 及び一般パッド(2-29)の上部に窓を有する、耐熱
性樹脂よりなる第1のレジスト膜(31)を設けた後に、 該選択したパッド(2-1) 及び該一般パッド(2-2) の表面
に高融点クリーム状半田(25)を塗布し、該高融点クリー
ム状半田(25)を所定の温度に加熱して、それぞれの該選
択したパッド(2-1),一般パッド(2-2) 上にそれぞれ半田
を析出させて、高融点半田バンプ(20)を設け、 次に、該選択したパッド(2-1) の高融点半田バンプ(20)
の上部に窓を有する、耐熱性樹脂よりなる第2のレジス
ト膜(32)を該回路基板(1) 上に設け、 その後、該選択したパッド(2-1) の高融点半田バンプ(2
0)の表面に、低融点クリーム状半田(26)を塗布し、該低
融点クリーム状半田(26)を所定の温度に加熱して、それ
ぞれの該選択したパッド(2-1) の高融点半田バンプ(20)
上に半田を析出させて、低融点半田バンプ21を重畳形成
し、 次に該第2のレジスト膜(32)及び該第1のレジスト膜(3
1)を除去することを特徴とする半田バンプの製造方法。
2. Selected pads on the surface of the circuit board (1)
(2-1) and the general pad (2-29) having a window above the first resist film (31) made of a heat-resistant resin, the selected pad (2-1) and the general pad (2-1) The high melting point creamy solder (25) is applied to the surface of the pad (2-2), and the high melting point creamy solder (25) is heated to a predetermined temperature, and each of the selected pads (2-1) Then, solder is deposited on each of the general pads (2-2) to provide high melting point solder bumps (20), and then the high melting point solder bumps (20) of the selected pad (2-1) are provided.
A second resist film (32) made of a heat resistant resin having a window on the upper side of the circuit board (1) is provided on the circuit board (1), and then the high melting point solder bump (2) of the selected pad (2-1) is formed.
The low melting point creamy solder (26) is applied to the surface of (0) and the low melting point creamy solder (26) is heated to a predetermined temperature, and the high melting point of each selected pad (2-1) is melted. Solder bump (20)
A low melting point solder bump 21 is superposedly formed by depositing solder on the second resist film (32) and the first resist film (3).
A method of manufacturing a solder bump, which comprises removing 1).
JP186692A 1992-01-09 1992-01-09 Mounting structure of semiconductor component and manufacture of its solder bump Withdrawn JPH05190553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP186692A JPH05190553A (en) 1992-01-09 1992-01-09 Mounting structure of semiconductor component and manufacture of its solder bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP186692A JPH05190553A (en) 1992-01-09 1992-01-09 Mounting structure of semiconductor component and manufacture of its solder bump

Publications (1)

Publication Number Publication Date
JPH05190553A true JPH05190553A (en) 1993-07-30

Family

ID=11513474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP186692A Withdrawn JPH05190553A (en) 1992-01-09 1992-01-09 Mounting structure of semiconductor component and manufacture of its solder bump

Country Status (1)

Country Link
JP (1) JPH05190553A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6094832A (en) * 1997-12-08 2000-08-01 Micron Technology, Inc. Method for depositing solder paste on a pad
US6858941B2 (en) 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
US7149372B2 (en) 2001-12-26 2006-12-12 Fujitsu Limited Optical device
JP2007027576A (en) * 2005-07-20 2007-02-01 Rohm Co Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6094832A (en) * 1997-12-08 2000-08-01 Micron Technology, Inc. Method for depositing solder paste on a pad
US6858941B2 (en) 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
US6921018B2 (en) 2000-12-07 2005-07-26 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
US7149372B2 (en) 2001-12-26 2006-12-12 Fujitsu Limited Optical device
JP2007027576A (en) * 2005-07-20 2007-02-01 Rohm Co Ltd Semiconductor device

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