JP3373274B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3373274B2 JP3373274B2 JP33504593A JP33504593A JP3373274B2 JP 3373274 B2 JP3373274 B2 JP 3373274B2 JP 33504593 A JP33504593 A JP 33504593A JP 33504593 A JP33504593 A JP 33504593A JP 3373274 B2 JP3373274 B2 JP 3373274B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- external electrode
- carrier
- electrodes
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子をプリント
基板に高密度，高信頼性で実装することを可能とした半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of mounting semiconductor elements on a printed circuit board with high density and high reliability.
【０００２】[0002]
【従来の技術】図５は従来の半導体装置の断面図を示し
ている。図５において、１は半導体素子、２は絶縁性基
体からなる半導体キャリア、３は底面に格子状に配列さ
れた外部電極端子、４は外部電極端子３に形成された半
田バンプ、５はエポキシ系樹脂、６はプリント基板、７
はパッド、８は半導体素子１を接続する電極である。2. Description of the Related Art FIG. 5 is a sectional view of a conventional semiconductor device. In FIG. 5, 1 is a semiconductor element, 2 is a semiconductor carrier made of an insulating substrate, 3 is an external electrode terminal arranged in a grid pattern on the bottom surface, 4 is a solder bump formed on the external electrode terminal 3, and 5 is an epoxy system. Resin, 6 is printed circuit board, 7
Is a pad, and 8 is an electrode for connecting the semiconductor element 1.
【０００３】図５に示すように、従来の半導体装置は、
半導体素子１に対応した半導体キャリア２の上面に複数
の電極８とその底面に格子状に配列された外部電極端子
３を有した絶縁性基体からなる半導体キャリア２と、半
導体キャリア２上面の複数の電極８と半田もしくは導電
性接着剤により電極が接続された半導体素子１と、半導
体素子１と半導体キャリア２との間隔および半導体素子
１の周辺部を充填被覆しているエポキシ系樹脂５からな
る。As shown in FIG. 5, the conventional semiconductor device is
A plurality of electrodes 8 on the upper surface of the semiconductor carrier 2 corresponding to the semiconductor element 1 and a semiconductor carrier 2 made of an insulating substrate having external electrode terminals 3 arranged on the bottom surface thereof in a grid pattern; The semiconductor element 1 has electrodes 8 connected to the electrodes by solder or a conductive adhesive, and an epoxy resin 5 filling and covering the space between the semiconductor element 1 and the semiconductor carrier 2 and the peripheral portion of the semiconductor element 1.
【０００４】半導体キャリア２の外部電極端子３に形成
された半田バンプ４が実装すべきプリント基板６のそれ
ぞれのパッド７に合致されるように積載して、加熱する
ことで、半田バンプ４を溶融させ、半導体キャリア２の
外部電極端子３をパッド７に接続させる。The solder bumps 4 formed on the external electrode terminals 3 of the semiconductor carrier 2 are loaded so that they are aligned with the respective pads 7 of the printed circuit board 6 to be mounted, and the solder bumps 4 are melted by heating. Then, the external electrode terminal 3 of the semiconductor carrier 2 is connected to the pad 7.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな構成の半導体装置は、半導体キャリアの外部電極端
子が半導体素子を接続する複数の電極の底面にあるた
め、プリント基板に実装後の面積が最低でも半導体素子
の大きさ分必要となり、このことが高密度実装を妨げる
要因となっていた。However, in the semiconductor device having such a structure, since the external electrode terminals of the semiconductor carrier are located on the bottom surfaces of the plurality of electrodes for connecting the semiconductor elements, the area after mounting on the printed circuit board is the minimum. However, the size of the semiconductor element is required, which is a factor that hinders high-density mounting.
【０００６】また、半導体キャリアの材質は半導体素子
をフリップチップ工法により実装する際、その容易さか
らセラミック材料が選択されることが多い。その場合、
半導体素子が駆動され、高温となると半導体キャリアと
樹脂材料で構成されたプリント基板の線膨張係数の違い
により、接続後の半田バンプに剪断歪が生じ、クラック
が発生し、接続信頼性が低くなるという問題となってい
た。[0006] Further, as the material of the semiconductor carrier, a ceramic material is often selected because of its easiness when the semiconductor element is mounted by the flip chip method. In that case,
When the semiconductor element is driven and the temperature becomes high, due to the difference in the linear expansion coefficient of the semiconductor carrier and the printed circuit board made of resin material, shear distortion occurs in the solder bumps after connection, cracks occur, and the connection reliability decreases. Was a problem.
【０００７】本発明は、上記従来技術の問題を解決する
ものであり、プリント基板に高密度，高信頼性で実装で
きる半導体装置を提供することを目的とする。The present invention solves the above-mentioned problems of the prior art, and an object of the present invention is to provide a semiconductor device which can be mounted on a printed circuit board with high density and high reliability.
【０００８】[0008]
【課題を解決するための手段】半導体素子と複数の電極
で接続され、それらの電極と電気的接続がなされた外部
電極端子を有した絶縁性基体からなる半導体キャリアに
おいて、Ｌ字型に構成される半導体キャリアと、半導体
キャリア上に半導体素子を接続する複数の電極と、半導
体キャリアにプリント基板と接続する外部電極端子とを
有し、外部電極端子は半導体素子を接続する複数の電極
を半導体キャリアの底面とは異なる位置に配し、半導体
キャリアの半導体素子を接続する複数の電極を有した部
分と外部電極端子を有した部分とが、ガラス繊維エポキ
シ等の樹脂材料あるいはアルミナ等のセラミック材料等
の、同一の絶縁材料か、またはそれぞれ異なる絶縁材料
から成るように構成したものである。A semiconductor carrier which is connected to a semiconductor element by a plurality of electrodes and has an external base terminal which is electrically connected to the electrodes and which has an external base, is formed into an L-shaped semiconductor carrier. A semiconductor carrier, a plurality of electrodes for connecting a semiconductor element on the semiconductor carrier, and an external electrode terminal for connecting a semiconductor substrate to a printed circuit board. The external electrode terminal is a semiconductor carrier for connecting a plurality of electrodes for connecting the semiconductor element. Placed at a position different from the bottom surface of the semiconductor carrier, a portion having a plurality of electrodes for connecting the semiconductor elements of the semiconductor carrier and a portion having external electrode terminals are made of a resin material such as glass fiber epoxy or a ceramic material such as alumina. Of the same insulating material or different insulating materials.
【０００９】[0009]
【作用】上記構成によれば、Ｌ字型に構成された半導体
キャリアにおいて、外部電極端子が半導体素子を接続す
る複数の電極の底面とは異なり、より面積の小さい部分
に配することにより、実装後の面積が半導体素子以下と
なり、高密度な実装が可能となる。また、外部電極端子
が形成されている半導体キャリアの材質とプリント基板
の材質を同一とすることで、半田付けされた半田バンプ
に生じる剪断歪を低減させ、高信頼性の接続を行うこと
ができる。According to the above construction, in the semiconductor carrier formed in the L-shape, the external electrode terminals are arranged on a portion having a smaller area, unlike the bottom surface of the plurality of electrodes for connecting the semiconductor elements. The area afterward becomes less than or equal to the semiconductor element, and high-density mounting becomes possible. Further, by making the material of the semiconductor carrier on which the external electrode terminals are formed and the material of the printed circuit board the same, it is possible to reduce the shear strain generated in the soldered solder bumps and perform a highly reliable connection. .
【００１０】[0010]
【実施例】次に図面を参照して実施例を詳細に説明す
る。図１は本発明の実施例における半導体装置の断面図
を示している。また、従来例と同一作用効果のものには
同一符号を付し詳細な説明は省略する。図１において、
２a，２bは分割されＬ字型に構成された半導体キャリア
である。Embodiments will now be described in detail with reference to the drawings. FIG. 1 shows a sectional view of a semiconductor device according to an embodiment of the present invention. Further, the same functions and effects as those of the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG.
Reference numerals 2a and 2b denote semiconductor carriers which are divided and configured in an L shape.
【００１１】図１に示すように、半導体キャリア２a，
２bは分割されＬ字型に構成され、互いに接着剤を介し
て接続されている。外部電極端子３は半導体素子１を接
続する複数の電極８の底面とは異なる位置に配されてい
る。半導体キャリア２bの外部電極端子３に形成された
半田バンプ４が実装すべきプリント基板６のそれぞれの
パッド７に合致されるように積載して、加熱すること
で、半田バンプ４を溶融させ、半導体キャリア２bの外
部電極端子３をパッド７に接続させる。As shown in FIG. 1, semiconductor carriers 2a,
2b is divided into L-shapes and connected to each other via an adhesive. The external electrode terminal 3 is arranged at a position different from the bottom surface of the plurality of electrodes 8 connecting the semiconductor element 1. The solder bumps 4 formed on the external electrode terminals 3 of the semiconductor carrier 2b are stacked so as to match the pads 7 of the printed circuit board 6 to be mounted, and heated to melt the solder bumps 4 The external electrode terminal 3 of the carrier 2b is connected to the pad 7.
【００１２】図２は従来の半導体装置(1)および本発明
の実施例における半導体装置(2)の斜視図および断面図
を示している。図３は従来の半導体装置と本実施例の半
導体装置の実装面積の違いの断面図を示している。図４
は本実施例の半導体装置の半導体キャリア２a，２bの構
成材料が同一の場合(1)，構成材料が異なる場合(2)の断
面図を示している。FIG. 2 shows a perspective view and a sectional view of a conventional semiconductor device (1) and a semiconductor device (2) in an embodiment of the present invention. FIG. 3 is a sectional view showing a difference in mounting area between the conventional semiconductor device and the semiconductor device of this embodiment. Figure 4
Shows cross-sectional views when the semiconductor carriers 2a and 2b of the semiconductor device of the present embodiment have the same constituent material (1) and different constituent materials (2).
【００１３】例えば、Ｌが18mm角の半導体素子１を実装
する場合を例として説明する。図２(1)に示す従来例の
ように、半導体キャリア２に外部電極端子３が半導体素
子１を接続する複数の電極８の底面にある場合、例え
ば、半導体素子１を実装する半導体キャリア２のＭを20
mm角とすると、実装面積は20×20＝400mm2となる(実装
面積は最低でも半導体素子１の大きさＬ×Ｌが必要とな
る)。For example, a case where the semiconductor element 1 having L of 18 mm square is mounted will be described as an example. As in the conventional example shown in FIG. 2 (1), when the external electrode terminals 3 are on the bottom surface of the plurality of electrodes 8 connecting the semiconductor element 1 to the semiconductor carrier 2, for example, 20 for M
If the area is mm square, the mounting area is 20 × 20 = 400 mm 2 (the mounting area requires at least the size L × L of the semiconductor element 1).
【００１４】それに対して、図２(2)に示す本発明のＬ
字型の半導体キャリアにおいては、外部電極端子３を形
成する半導体キャリア２bは、例えば、Ｍ×Ｎを20mm×1
0mmとすることにより実装面積は200mm2と半分になり、
図３に示したように実装密度を上げることができる。外
部電極端子３のピッチＰをさらに小さくすれば、よりＮ
を小さくでき、実装面積を減らすことが可能である。On the other hand, the L of the present invention shown in FIG.
In the V-shaped semiconductor carrier, the semiconductor carrier 2b forming the external electrode terminal 3 has, for example, M × N of 20 mm × 1.
By setting it to 0 mm, the mounting area is halved to 200 mm 2 .
As shown in FIG. 3, the mounting density can be increased. If the pitch P of the external electrode terminals 3 is further reduced, N
Can be reduced, and the mounting area can be reduced.
【００１５】半導体キャリア２a，２bを構成する材質と
しては、図４(1)に示したように、半導体キャリア２a，
２b共にアルミナ等のセラミック材料、もしくはガラス
繊維エポキシ等の樹脂材料等、同一の材質を用いたも
の、また図４(2)に示したように、半導体キャリア２a，
２bでセラミック材料と樹脂材料といった材質の異なる
ものを組み合わすこともできる。As a material for forming the semiconductor carriers 2a and 2b, as shown in FIG.
2b are made of the same material, such as a ceramic material such as alumina or a resin material such as glass fiber epoxy, and as shown in FIG. 4 (2), the semiconductor carrier 2a,
In 2b, it is possible to combine different materials such as a ceramic material and a resin material.
【００１６】そこで、外部電極端子３が形成される半導
体キャリア２bの部分の材質をプリント基板６の材質と
同一のものとすることにより、半導体素子１が駆動し高
温となった場合においても、半導体キャリアとプリント
基板６の間に線膨張係数の差がないため、半田接続部に
かかる剪断歪を低減し、高信頼性な接続を行うことがで
きる。Therefore, by making the material of the portion of the semiconductor carrier 2b on which the external electrode terminals 3 are formed the same as the material of the printed circuit board 6, even when the semiconductor element 1 is driven and the temperature becomes high, the semiconductor Since there is no difference in the coefficient of linear expansion between the carrier and the printed circuit board 6, it is possible to reduce the shear strain applied to the solder connection portion and perform highly reliable connection.
【００１７】[0017]
【発明の効果】以上のように本発明によると、Ｌ字型に
構成された半導体キャリアにおいて、外部電極端子を半
導体素子と接続する複数の電極の底面とは異なり、より
面積の小さい部分に配することにより、実装後の面積が
半導体素子の面積以下となり、高密度な実装が行える。
また、外部電極端子が形成される部分の半導体キャリア
の材質をプリント基板の材質を同一にすることにより、
線膨張係数の違いにより半田接続部に生じる剪断歪を低
減でき、高信頼性な接続を行える。As described above, according to the present invention, in an L-shaped semiconductor carrier, it is arranged in a portion having a smaller area, unlike the bottom surface of a plurality of electrodes for connecting external electrode terminals to semiconductor elements. By doing so, the area after mounting becomes equal to or smaller than the area of the semiconductor element, and high-density mounting can be performed.
Also, by making the material of the semiconductor carrier of the portion where the external electrode terminals are formed the same as the material of the printed circuit board,
It is possible to reduce the shear strain generated in the solder connection portion due to the difference in the linear expansion coefficient, and to perform highly reliable connection.
【図１】本発明の実施例における半導体装置を示す断面
図である。FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体装置(1)および本発明の実施例に
おける半導体装置(2)の斜視図および断面図である。FIG. 2 is a perspective view and a sectional view of a conventional semiconductor device (1) and a semiconductor device (2) according to an embodiment of the present invention.
【図３】従来の半導体装置および本発明の実施例の実装
面積の違いを示す断面図である。FIG. 3 is a sectional view showing a difference in mounting area between a conventional semiconductor device and an embodiment of the present invention.
【図４】本発明の実施例における半導体装置の半導体キ
ャリア２a，２bの構成材料が同一の場合(1)および構成
材料が異なる場合(2)の断面図である。FIG. 4 is a cross-sectional view when the semiconductor carriers 2a and 2b of the semiconductor device in the embodiment of the present invention have the same constituent material (1) and different constituent materials (2).
【図５】従来の半導体装置を示す断面図である。FIG. 5 is a sectional view showing a conventional semiconductor device.
１…半導体素子、 ２，２a，２b…半導体キャリア、
３…外部電極端子、 ４…半田バンプ、 ５…エポキシ
系樹脂、 ６…プリント基板、 ７…パッド、８…電
極。1 ... Semiconductor element, 2, 2a, 2b ... Semiconductor carrier,
3 ... External electrode terminals, 4 ... Solder bumps, 5 ... Epoxy resin, 6 ... Printed circuit board, 7 ... Pads, 8 ... Electrodes.
Claims (3)
れらの電極と電気的接続がなされた外部電極端子を有し
た絶縁性基体からなる半導体キャリアにおいて、Ｌ字型
に構成される半導体キャリアと、該半導体キャリア上に
半導体素子を接続する複数の電極と、前記半導体キャリ
アにプリント基板と接続する外部電極端子とを有し、該
外部電極端子は前記半導体素子を接続する複数の電極を
設けた前記半導体キャリアの底面とは異なる位置に配す
ることを特徴とする半導体装置。1. A semiconductor carrier comprising an L-shaped semiconductor carrier which is connected to a semiconductor element by a plurality of electrodes and has an external electrode terminal electrically connected to the electrodes. , A plurality of electrodes for connecting a semiconductor element on the semiconductor carrier, and an external electrode terminal for connecting to a printed circuit board on the semiconductor carrier, wherein the external electrode terminal is provided with a plurality of electrodes for connecting the semiconductor element A semiconductor device, which is arranged at a position different from the bottom surface of the semiconductor carrier.
接続する複数の電極を有した部分と外部電極端子を有し
た部分とが、ガラス繊維エポキシ等の樹脂材料あるいは
アルミナ等のセラミック材料等の、同一の絶縁材料から
成ることを特徴とする請求項１記載の半導体装置。2. In a semiconductor carrier, a portion having a plurality of electrodes for connecting semiconductor elements and a portion having external electrode terminals are made of the same resin material such as glass fiber epoxy or ceramic material such as alumina. The semiconductor device according to claim 1, wherein the semiconductor device is made of an insulating material.
接続する複数の電極を有した部分と外部電極端子を有し
た部分とが、ガラス繊維エポキシ等の樹脂材料あるいは
アルミナ等のセラミック材料等の、異なる絶縁材料から
成ることを特徴とする請求項１記載の半導体装置。3. In a semiconductor carrier, a portion having a plurality of electrodes for connecting semiconductor elements and a portion having an external electrode terminal are made of different insulating materials such as a resin material such as glass fiber epoxy or a ceramic material such as alumina. The semiconductor device according to claim 1, which is made of a material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33504593A JP3373274B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33504593A JP3373274B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07201916A JPH07201916A (en) | 1995-08-04 |
| JP3373274B2 true JP3373274B2 (en) | 2003-02-04 |
Family
ID=18284130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33504593A Expired - Fee Related JP3373274B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3373274B2 (en) |
-
1993
- 1993-12-28 JP JP33504593A patent/JP3373274B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07201916A (en) | 1995-08-04 |
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