JPH04240741A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04240741A JPH04240741A JP3006998A JP699891A JPH04240741A JP H04240741 A JPH04240741 A JP H04240741A JP 3006998 A JP3006998 A JP 3006998A JP 699891 A JP699891 A JP 699891A JP H04240741 A JPH04240741 A JP H04240741A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode pattern
- melting point
- low melting
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052737 gold Inorganic materials 0.000 claims abstract description 16
- 239000010931 gold Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 11
- 229910000807 Ga alloy Inorganic materials 0.000 claims abstract description 7
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- 238000013508 migration Methods 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、コンピュータや一般電
子機器に用いられる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices used in computers and general electronic equipment.
【０００２】0002
【従来の技術】図２は従来の半導体装置の断面図を示し
ており、１は半導体チップであり、２はその表面にある
外部電極用アルミニウム電極であり、３はその表面に金
ワイヤーを接合して切断したスタッド状金バンプ、４は
その下側にガラス，セラミック等の実装基板５上の銅箔
電極パターン６との接続用の銀ペーストである。７は全
体をカバーする樹脂コートである。[Prior Art] FIG. 2 shows a cross-sectional view of a conventional semiconductor device, in which 1 is a semiconductor chip, 2 is an aluminum electrode for an external electrode on the surface of the chip, and 3 is a gold wire bonded to the surface. The stud-shaped gold bumps 4 are cut under the stud-shaped gold bumps, and a silver paste is placed on the underside thereof for connection with a copper foil electrode pattern 6 on a mounting board 5 made of glass, ceramic, or the like. 7 is a resin coat that covers the entire surface.
【０００３】また図３は図２の半導体装置の透視外観斜
視図である。次にその製法について説明する。アルミニ
ウム電極２の表面にワイヤーボンド機を用いて金ワイヤ
ーを付け、切断し、この後この高さを揃えるため上より
治具で押える。このようにしてスタッド状金バンプ３を
作成し、この先端に銀ペースト４を少量かつ一定量付け
る。FIG. 3 is a perspective view of the semiconductor device shown in FIG. 2. As shown in FIG. Next, the manufacturing method will be explained. A gold wire is attached to the surface of the aluminum electrode 2 using a wire bonding machine and cut, and then it is pressed down with a jig from above in order to equalize the height. In this way, a stud-shaped gold bump 3 is created, and a small but fixed amount of silver paste 4 is applied to the tip of the bump.
【０００４】これを実装基板５の表面の電極パターン６
の所定の位置に位置合わせをして、上よりのせた後、加
熱し銀ペースト４を硬化させる。この後、樹脂コート７
を塗布、硬化させる。このように、上記従来の半導体装
置でも高密度に実装することができる。[0004] This is an electrode pattern 6 on the surface of the mounting board 5.
After aligning it to a predetermined position and placing it on top, the silver paste 4 is heated to harden. After this, resin coat 7
Apply and cure. In this way, even the conventional semiconductor device described above can be mounted with high density.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら上記従来
の半導体装置では、金バンプ３と実装基板５の電極パタ
ーン６を銀ペースト４で接続しているため、高温高湿下
で銀のマイグレーションによる電極間のショートが起こ
るという課題があった。さらに銀ペーストのため接続抵
抗が大きく、電流を多く流す回路では電圧降下が大きい
という課題があった。However, in the conventional semiconductor device described above, since the gold bumps 3 and the electrode pattern 6 of the mounting board 5 are connected with the silver paste 4, the gap between the electrodes due to silver migration occurs under high temperature and high humidity. There was a problem that short circuits occurred. Furthermore, since the silver paste has a high connection resistance, there was a problem that a circuit that carries a large amount of current would have a large voltage drop.
【０００６】本発明はこのような従来の課題を解決する
ものであり、高信頼性に優れた半導体装置を提供するこ
とを目的とするものである。The present invention is intended to solve these conventional problems, and aims to provide a highly reliable semiconductor device.
【０００７】[0007]
【課題を解決するための手段】この目的を達成するため
に本発明は、半導体チップを金バンプの先端部に付与さ
れたインジウム・ガリウム合金等の低融点金属を介して
実装基板上の電極パターンに接続して実装した構成より
なる。[Means for Solving the Problems] In order to achieve this object, the present invention provides an electrode pattern on a mounting board through which a semiconductor chip is attached to the tip of a gold bump through a low melting point metal such as an indium-gallium alloy. It consists of a configuration that is connected and implemented.
【０００８】[0008]
【作用】この構成によって、常温で液状の低融点金属を
用いて接続しているので、マイグレーションが起こらず
、接続抵抗も小さくなる。[Operation] With this configuration, since the connection is made using a low melting point metal that is liquid at room temperature, migration does not occur and the connection resistance is reduced.
【０００９】[0009]
【実施例】図１は本発明の一実施例の半導体装置の断面
図を示すものであり、１１は半導体チップ、１２はその
表面のアルミニウム電極、１３はアルミニウム電極１２
上に金ワイヤーをボンデイングした後切断したスタッド
状金バンプ、１４はインジウム・ガリウム合金等の低融
点金属、１５はガラス板やアルミナ等のセラミックから
なる実装基板、１６は実装基板１５上の電極パターン、
１７は全体を機械的，化学的に保護するための樹脂コー
トである。Embodiment FIG. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention, in which 11 is a semiconductor chip, 12 is an aluminum electrode on the surface thereof, and 13 is an aluminum electrode 12.
A stud-shaped gold bump is cut after bonding a gold wire thereon, 14 is a low melting point metal such as an indium-gallium alloy, 15 is a mounting board made of a glass plate or ceramic such as alumina, and 16 is an electrode pattern on the mounting board 15. ,
17 is a resin coat for mechanically and chemically protecting the whole.
【００１０】次に上記構成の製法について説明する。ア
ルミニウム電極１２の表面に形成したスタッド状金バン
プ１３はその後高さを約５０μに揃えるため、上より治
具で加圧する。その後、これをインジウム・ガリウムの
合金からなる常温で液状の低融点金属１４の入った底の
浅い約２５μの容器に浸し、金バンプ１３の先端に低融
点金属１４を少量かつ一定量付ける。これを実装基板１
５の表面に形成された電極パターン１６の所定の位置に
正確に合わし、上よりのせる。この後全体にシリコンや
エポキシ樹脂等の樹脂コート１７を塗布し硬化させる。Next, a method for manufacturing the above structure will be explained. The stud-shaped gold bumps 13 formed on the surface of the aluminum electrode 12 are then pressurized from above with a jig in order to make the height uniform to about 50 μm. Thereafter, this is immersed in a shallow container of approximately 25 μm in bottom containing a low melting point metal 14 made of an alloy of indium and gallium that is liquid at room temperature, and a small but constant amount of the low melting point metal 14 is applied to the tip of the gold bump 13. Mount this on board 1
5, and place it on top of the electrode pattern 16 formed on the surface of the electrode pattern 16. After this, a resin coat 17 such as silicone or epoxy resin is applied to the entire surface and hardened.
【００１１】このように上記実施例によれば、金バンプ
１３と電極パターン１６の接続をインジウム・ガリウム
合金のような液状の低融点金属１４を用いて行なうこと
により、銀ペーストを用いた時の銀のマイグレーション
も起らず、接続抵抗も低いという効果を有する。[0011] According to the above embodiment, the gold bumps 13 and the electrode patterns 16 are connected using a liquid low melting point metal 14 such as an indium-gallium alloy, thereby making it possible to It has the effect that silver migration does not occur and connection resistance is low.
【００１２】さらに常温で液状のため金バンプ１３と電
極パターン１６とのギャップの微小のばらつきをも、そ
の表面張力でギャップの大小も吸収することができる。
また半導体チップ１１と実装基板１５との熱膨張係数の
違いによる収縮ひずみも、液状であるため吸収すること
ができる効果を有する。Furthermore, since it is in a liquid state at room temperature, it is possible to absorb minute variations in the gap between the gold bump 13 and the electrode pattern 16 as well as the size of the gap using its surface tension. Further, since it is in a liquid state, it has the effect of being able to absorb shrinkage strain caused by the difference in thermal expansion coefficients between the semiconductor chip 11 and the mounting board 15.
【００１３】[0013]
【発明の効果】以上のように本発明は半導体チップを金
バンプの先端部に付与されたインジウム・ガリウム合金
等の低融点金属を介して実装基板上の電極パターンに接
続して実装した構成によるので、金属のマイグレーショ
ンが起らず、接続抵抗も低く、金バンプと電極パターン
とのギャップの違いも吸収することができ、さらに半導
体チップと実装基板との熱膨張係数の違いによる収縮ひ
ずみも吸収できる半導体装置を提供できる。[Effects of the Invention] As described above, the present invention has a configuration in which a semiconductor chip is mounted by connecting it to an electrode pattern on a mounting board via a low melting point metal such as an indium-gallium alloy applied to the tip of a gold bump. Therefore, metal migration does not occur, the connection resistance is low, and it is possible to absorb differences in the gap between the gold bump and the electrode pattern, as well as absorb shrinkage strain due to the difference in thermal expansion coefficient between the semiconductor chip and the mounting board. It is possible to provide semiconductor devices that can
【図１】本発明の一実施例の半導体装置の拡大断面図FIG. 1 is an enlarged cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【
図２】従来の半導体装置の拡大断面図[
Figure 2: Enlarged cross-sectional view of a conventional semiconductor device
【図３】図２の従
来の半導体装置の透視外観斜視図FIG. 3 is a transparent external perspective view of the conventional semiconductor device in FIG. 2;
１１ 半導体チップ １２ アルミニウム電極（電極） １３ 金バンプ １４ 低融点金属 １５ 実装基板 １６ 電極パターン 11 Semiconductor chip 12 Aluminum electrode (electrode) 13 Gold bump 14 Low melting point metal 15 Mounting board 16 Electrode pattern
Claims (1)
された金バンプと実装基板上の電極パターンを接続する
半導体装置において、前記半導体チップを前記金バンプ
の先端部に付与されたインジウム・ガリウム合金等の低
融点金属を介して前記実装基板上の電極パターンに接続
して実装したことを特徴とする半導体装置。1. A semiconductor device in which a gold bump formed on an external connection electrode on a semiconductor chip is connected to an electrode pattern on a mounting board, wherein the semiconductor chip is connected to an indium layer provided at the tip of the gold bump. A semiconductor device, characterized in that the semiconductor device is mounted by being connected to the electrode pattern on the mounting substrate via a low melting point metal such as a gallium alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3006998A JPH04240741A (en) | 1991-01-24 | 1991-01-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3006998A JPH04240741A (en) | 1991-01-24 | 1991-01-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04240741A true JPH04240741A (en) | 1992-08-28 |
Family
ID=11653783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3006998A Pending JPH04240741A (en) | 1991-01-24 | 1991-01-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04240741A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994018698A1 (en) * | 1993-02-09 | 1994-08-18 | Hans Peter Peloschek | METHOD FOR ELECTRICALLY CONDUCTIVE CONNECTING AND MECHANICAL FASTENING OF ICs ON CONDUCTING PATTERNS OF SUBSTRATES AND THE APPLICATION THEREOF |
| US9204551B2 (en) | 2010-11-22 | 2015-12-01 | Lenovo Innovations Limited (Hong Kong) | Mounting structure and mounting method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58130540A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Mounting structure for semiconductor element |
| JPH02159047A (en) * | 1988-12-13 | 1990-06-19 | Fujitsu Ltd | Fluxless joining method |
-
1991
- 1991-01-24 JP JP3006998A patent/JPH04240741A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58130540A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Mounting structure for semiconductor element |
| JPH02159047A (en) * | 1988-12-13 | 1990-06-19 | Fujitsu Ltd | Fluxless joining method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994018698A1 (en) * | 1993-02-09 | 1994-08-18 | Hans Peter Peloschek | METHOD FOR ELECTRICALLY CONDUCTIVE CONNECTING AND MECHANICAL FASTENING OF ICs ON CONDUCTING PATTERNS OF SUBSTRATES AND THE APPLICATION THEREOF |
| US9204551B2 (en) | 2010-11-22 | 2015-12-01 | Lenovo Innovations Limited (Hong Kong) | Mounting structure and mounting method |
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