JPH04314355A - Chip carrier and soldering method thereof - Google Patents

Abstract

PURPOSE:To prevent short-circuitting and opening due to positional displacement by providing a lower surface with a plurality of positioning pads each being greater than a connection pad in its area. CONSTITUTION:A pad 4 is provided on the lower surface of a chip carrier 1 and a positioning pad 2 is provided at four corners, and further the area of the positioning pad 2 is formed to be greater than the area of the pad 4. For this, a preliminary solder for the positioning pad 2 is made higher than a preliminary solder 5a of the pad 4. Then, the tip end of positioning pad 2 of the chip carrier 1 is superimposed so as to ride on a conductor circuit 6 of a substrate 7. Thereupon, it becomes unnecessary to position the preliminary solder 5a of the pad 4 of the chip carrier 1 with the conductor circuit 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier used in electronic devices and a method for soldering a chip carrier to a substrate.

0002

2. Description of the Related Art FIGS. 4(a), 4(b), and 4(c) are cross-sectional views showing each step of a conventional chip carrier and its soldering method.

As shown in FIG. 4(a), pads 22 of the same shape are provided in a grid pattern on the lower surface of the chip carrier 21, preliminary solder 23 is provided on the pads 22, and the pads 22 of the chip carrier 21 are provided on the substrate 26. A conductor circuit 24 is provided at a position corresponding to the pad 22, and the preliminary solder 23 of the pad 22 of the chip carrier 21 is applied to the conductor circuit 24 of the substrate 26, using the alignment mark 25 as a guide, as shown in FIG. 4(b). When they are stacked, heated, reflowed, and cooled, the preliminary solder 23 changes to solder 27, as shown in FIG. 4(c), and the soldering is completed.

0004

[Problems to be Solved by the Invention] In the conventional chip carrier and its soldering method described above, when positioning the chip carrier, the preliminary solder 23 of all the pads 22 of the chip carrier 21 is not deposited onto the conductor circuit 24 of the substrate 26. As the size and pitch of the pads 22 of the chip carrier 21 and the conductor circuits 24 of the substrate 26 become finer, there will be less margin in the allowable range for misalignment that occurs during positioning, and the tolerance for misalignment will be exceeded. It has the disadvantage that opens and shorts may occur if it is mounted in a closed state.

[0005]

[Means for Solving the Problems] A chip carrier of the present invention is a chip carrier having a plurality of connection pads on the bottom surface as a connection circuit with the outside, and a plurality of positioning pads having a larger area than the connection pads. Has it on the bottom surface.

Furthermore, the soldering method of the present invention applies the same to all of the plurality of connection pads provided on the bottom surface of the chip carrier as external connection circuits and the plurality of positioning pads having a larger area than the connection pads. A first step of providing different kinds of preliminary solder, and after this first step, a connecting conductor circuit is provided corresponding to the connecting pad, and a connecting conductor circuit having an area smaller than the connecting conductor circuit corresponding to the positioning pad is provided. a second step of positioning the chip carrier on a substrate provided with a large positioning conductor circuit so that the tip of the preliminary solder provided on the positioning pad rests on the positioning conductor circuit; After the step, there is a third step of heating and reflowing the preliminary solder, and a fourth step of applying a load from the upper surface of the chip carrier after the third step.

Furthermore, in the soldering method of the present invention, a high melting point preliminary solder is provided on a plurality of connection pads as external connection circuits provided on the bottom surface of the chip carrier, and A first step of providing preliminary solder with a low melting point to a plurality of positioning pads having a larger area than the connection pads, and after this first step, connection conductor circuits are provided corresponding to the connection pads and the positioning is performed. Place the chip on a substrate on which a positioning conductor circuit having a larger area than the connection conductor circuit is provided corresponding to the connection pad so that the tip of the preliminary solder provided on the positioning pad rests on the positioning conductor circuit. a second step of positioning the carrier; and after this second step, heating at a temperature that melts the preliminary solder provided on the positioning pads of the chip carrier and does not melt the preliminary solder provided on the connection pads; a third step of performing reflow, a fourth step of applying a load from the top surface of the chip carrier after this third step, and a preliminary solder provided on all of the connection pads after this fourth step. and a fifth step of heating and reflowing the material at a temperature at which it melts.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a perspective view of a chip carrier according to claim 1. Pads 4 are provided on the lower surface of the chip carrier 1 shown in FIG. 1, and positioning pads 2 are provided at the four corners. The area of the positioning pad 2 is made larger than the area of the pad 4.

FIG. 2 is a cross-sectional view showing step-by-step the steps of the chip carrier soldering method according to claim 2 of the present invention.

As shown in FIG. 2(a), preliminary solder 3a and preliminary solder 5a are provided on the positioning pads 2 and pads 4 on the lower surface of the chip carrier 1, respectively. Preliminary solder 3
a and the preliminary solder 5a are Sn/Pb (63/37w
The same type of solder such as t%) is used. Since the area of the positioning pad 2 is larger than the area of the pad 4, the preliminary solder 3a of the positioning pad 2 is higher than the preliminary solder 5a of the pad 4. The substrate 7 on which the chip carrier 1 is mounted includes
A conductor circuit 6 and a conductor circuit 8 are provided at positions corresponding to the positioning pads 2 and pads 4 on the chip carrier 1, respectively.Similar to the chip carrier 1, the area of the conductor circuit 6 on the substrate 7 is equal to the area of the conductor circuit 8. It is set larger.

Next, as shown in FIG. 2(b), the tip of the preliminary solder 3a of the positioning pad 2 of the chip carrier 1 is overlapped so that it rests on the conductor circuit 6 of the substrate 7. Preliminary solder 5a of pad 4 and board 7
It is not necessary to align the conductor circuits 8 of Since the area of the conductor circuit 6 on the substrate 7 is larger than the area of the conductor circuit 8, the tolerance for deviation during alignment is large, and the alignment of the chip carrier 1 can be easily performed.

Next, heating reflow is performed, for example, Sn is added to the preliminary solder.
/Pb (63/37wt%), by heating at 230°C, the preliminary solder 3a melts and turns into solder 9a, as shown in FIG. 2 and the conductor circuit 6 of the substrate 7 are connected. At this time, the chip carrier 1 and the substrate 7 are automatically aligned accurately due to the surface tension of the melted solder 9a.

Furthermore, as shown in FIG. 2(d), by applying a load A from the top surface of the chip carrier 1 in this state, the preliminary solder 5a of the pad 4 of the chip carrier 1 is connected to the conductor circuit 8 of the substrate 7. Change to solder 10a.

Finally, by cooling and washing,
Complete the entire process.

FIG. 3 is a cross-sectional view showing step-by-step the steps of a method for soldering a chip carrier according to claim 3 of the present invention.

As shown in FIG. 3(a), preliminary solder 3b and preliminary solder 5b are provided on the positioning pads 2 and pads 4 on the lower surface of the chip carrier 1, respectively. Preliminary solder 3b
For this purpose, a solder material having a melting point lower than that of the preliminary solder 5b is used. For example, the preliminary solder 3b contains Sn /Pb /Bi (4
3/43/14wt%), and Sn was used as the preliminary solder 5b.
/Pb (63/37wt%) is used. Since the area of the positioning pad 2 is larger than the area of the pad 4, the preliminary solder 3b of the positioning pad 2 is higher than the preliminary solder 5b of the pad 4. Substrate 7 mounted on chip carrier 1
The positioning pads 2 and 4 of the chip carrier 1 are
A conductor circuit 6 and a conductor circuit 8 are provided at positions corresponding to the chip carrier 1, and the area of the conductor circuit 6 on the substrate 7 is larger than the area of the conductor circuit 8, similarly to the chip carrier 1.

Next, as shown in FIG. 3(b), the tip of the preliminary solder 3b of the positioning pad 2 of the chip carrier 1 is overlapped so that it rests on the conductor circuit 6 of the substrate 7. Preliminary solder 5b of pad 4 and board 7
It is not necessary to align the conductor circuits 8 of Since the area of the conductor circuit 6 on the substrate 7 is larger than the area of the conductor circuit 8, the tolerance for deviation during alignment is large, and the alignment of the chip carrier 1 can be easily performed.

Next, the preliminary solder 3b is melted, and the preliminary solder 5b is melted.
Heating reflow at a temperature that does not melt the material, e.g. preliminary solder 3b
Sn/Pb/Bi (43/43/14wt%)
using Sn/Pb (63/37
wt%), by heating to 175°C, the preliminary solder 3b melts and turns into solder 9b, as shown in FIG. Circuit 6 is connected. At this time, the chip carrier 1 and the substrate 7 are automatically aligned due to the surface tension of the melted solder 9b.

Next, as shown in FIG. 3(d), by applying a load A from the top surface of the chip carrier 1, the tips of the preliminary solder 5b of the pads 4 of the chip carrier 1 touch the substrate 7.
contact with the conductor circuit 8.

Next, the preliminary solder 5b is heated and reflowed at a temperature that melts it, for example, the preliminary solder 5b is coated with Sn/Pb (63/
37 wt%), by heating at 230° C., the preliminary solder 5b is changed to solder 10b, and the pads 4 of the chip carrier 1 and the conductive circuits 8 of the substrate 7 are connected.

Finally, by cooling and washing,
Complete the entire process.

[0023]

Effects of the Invention: The chip carrier and soldering method of the present invention can easily and quickly align the chip carrier on the substrate, and the chip carrier can be stably aligned without short circuits or open circuits due to misalignment even during heating reflow. It has the effect of soldering.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an embodiment of a chip carrier of the present invention.

FIG. 2 is a cross-sectional view showing step-by-step an embodiment of the soldering method of the present invention.

FIG. 3 is a cross-sectional view showing step-by-step another embodiment of the soldering method of the present invention.

FIG. 4 is a vertical cross-sectional view showing a conventional chip carrier soldering method.

[Explanation of symbols]

1, 21 Chip carrier 2 Positioning pads 3a, 3b, 5a, 5b, 23 Preliminary solder 4, 2
2 Pads 6, 8, 24 Conductor circuits 7, 26 Boards 9a, 9b, 10a, 10b, 27 Solder 25
alignment mark

Claims (3)

[Claims] 1. A chip carrier having a plurality of connection pads on a lower surface as a connection circuit with the outside, the chip carrier having a plurality of positioning pads on the lower surface having a larger area than the connection pads. 2. A first method in which preliminary solder of the same type is applied to all of a plurality of connection pads provided on the lower surface of the chip carrier as external connection circuits and a plurality of positioning pads having a larger area than the connection pads. This process and this first
After the process, a connecting conductor circuit is provided corresponding to the connecting pad, and a positioning conductor circuit having a larger area than the connecting conductor circuit is provided corresponding to the positioning pad. a second step of positioning the chip carrier so that the tip of the preliminary solder provided on the pad rests on the positioning conductor circuit;
A method for soldering a chip carrier, comprising: a third step of heating and reflowing preliminary solder after the step; and a fourth step of applying a load from the upper surface of the chip carrier after the third step. 3. Preliminary solder with a high melting point is provided on a plurality of connection pads provided on the bottom surface of the chip carrier as connection circuits with the outside, and the plurality of connection pads having a larger area than the connection pads provided on the bottom surface of the chip carrier are provided with high melting point preliminary solder. a first step of applying low-melting-point preliminary solder to the positioning pads; and after this first step, connecting conductor circuits are provided corresponding to the connection pads; a second step of positioning the chip carrier on a substrate on which a positioning conductor circuit having a larger area than the positioning conductor circuit is provided so that the tip of the preliminary solder provided on the positioning pad is on the positioning conductor circuit; After this second step, a third step of performing heating reflow at a temperature where the preliminary solder provided on the positioning pads of the chip carrier is melted and the preliminary solder provided on the connection pads is not melted. , after this third step, a fourth step of applying a load from the top surface of the chip carrier; and after this fourth step, a fifth step of heating and reflowing at a temperature that melts the preliminary solder provided on the connection pads. A method for soldering a chip carrier, comprising the steps of: