US6441477B2 - Substrate mounting an integrated circuit package with a deformed lead - Google Patents

Substrate mounting an integrated circuit package with a deformed lead Download PDF

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Publication number
US6441477B2
US6441477B2 US09/772,891 US77289101A US6441477B2 US 6441477 B2 US6441477 B2 US 6441477B2 US 77289101 A US77289101 A US 77289101A US 6441477 B2 US6441477 B2 US 6441477B2
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United States
Prior art keywords
land
lead
integrated circuit
solder
circuit package
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US20020008313A1 (en
Inventor
Hajime Maeda
Yasunori Ikeda
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to mounting an integrated circuit to a substrate, and in particular to connection between IC leads in an integrated circuit package and lands for mounting on a substrate.
  • An integrated circuit package of a type which is mounted on the surface of a substrate is provided with a plurality of IC leads each being a part to be connected with the substrate. These IC leads are electrically connected reliably with a plurality of lands for mounting on the substrate by the use of a melting conductive material such as solder, in general.
  • FIG. 1 shows solder 92 -n (n: an integer) supplied on lands 32 -n (n: an integer), and corresponding IC leads 12 -n (n: an integer) in an integrated circuit package 10 .
  • a connecting process therefor is carried out as described hereinafter.
  • each solder 92 -n (n: an integer) is supplied on each land 32 -n (n: an integer) in accordance with a predetermined printing manner, and then each IC lead 12 -n (n: an integer) is located to be rested thereat. Thereafter, the solder is melted by means of, for example, reflow soldering, whereby each IC lead 12 -n is electrically connected to each land 32 -n (n: an integer).
  • the integrated circuit package 10 When the integrated circuit package 10 is connected to the substrate 30 , the integrated circuit package 10 can send and receive signals to and from other components of the substrate 30 through each leader line wiring 34 -n (n: an integer).
  • FIG. 1 shows the end IC lead 12 - 1 which has been deformed.
  • deformation means herein a case where, for instance, a part of the IC lead is bent upwards, so that there is no predetermined twodimensional contact with respect to a substrate.
  • FIG. 2 shows a state where the end IC lead 12 - 1 is connected to the land 32 - 1 by means of solder 92 - 1 wherein since the end IC lead 12 - 1 has been deformed upwards, either the end IC lead 12 - 1 is not i n contact with the solder 92 - 1 or only a part thereof is in contact with the solder 92 - 1 .
  • FIG. 2 shows a state where the end IC lead 12 - 1 is connected to the land 32 - 1 by means of solder 92 - 1 wherein since the end IC lead 12 - 1 has been deformed upwards, either the end IC lead 12 - 1 is not i n contact with the solder 92 - 1 or only a part thereof is in contact with the solder 92 - 1 .
  • FIG. 1 shows a state where the end IC lead 12 - 1 is connected to the land 32 - 1 by means of solder 92 - 1 wherein since the end IC lead 12 - 1
  • Japanese Patent Laid-Open No. 169153/1994 discloses such a technology that a more amount of solder is to be supplied to an end pad.
  • this technology is the one to be applied for an end pad having a wider area than that of a usual end pad. Accordingly, when an end pad contains a wide area, a movable range of solder expands, so that a deformed end IC lead cannot be connected in a sufficiently firm condition after all.
  • An object of the present invention is to provide a method for connecting reliably a deformed IC lead to a land.
  • Another object of the present invention is to provide a substrate for mounting an integrated circuit package connected by means of the method as described above.
  • a method for mounting an integrated circuit package on a substrate comprises a step of supplying conductive material on a land on the substrate wherein an amount of the conductive material larger than that of the first land is supplied to the second land; and melting the conductive material supplied to connect a leald in the integrated circuit package with the land wherein the conductive material molten on the first land extends in the vertical direction with respect to the substrate with a first height thereby connecting the first lead with the first land, while the conductive material molten on the second land extends with a second height higher than the first height due to surface tension thereby connecting the second lead with the second land.
  • the integrated circuit package includes a plurality of leads and the second lead is an end lead positioned at the end of the plurality of leads.
  • the step for supplying the conductive material onto the second land is a step for supplying a much larger amount of the conductive material onto the second land at a position opposed to the first land.
  • a substrate for mounting an integrated circuit package comprises an integrated circuit package provided with a first lead and a deformed second lead, the first lead being nondeformed and the second lead being deformed; the substrate provided with a first land and a second land; a conductive material on the first land, which has a first height in the vertical direction with respect to the substrate and which connects the first lead with the first land; an amount of the conductive material on the second land larger than that of the conductive material on the first land, which has a second height higher than the first height due to surface tension produced in the case where the conductive material is melted and which connects the second lead with the second land.
  • the integrated circuit package includes a plurality of leads and the second lead is an end lead positioned at the end of the plurality of leads.
  • FIG. 1 is a perspective view of solder supplied on lands and corresponding IC leads in a prior art integrated circuit package
  • FIG. 2 is a schematic side view of a deformed IC lead to which a land is connected by means of molten solder.
  • FIG. 3A is a perspective view of a substrate for mounting integrated circuit package manufactured by a method according to the present invention.
  • FIG. 3B is a plan view of a substrate as illustrated in FIG. 3A;
  • FIG. 4 is a schematic view of portions of solder supplied on lands and corresponding IC leads in an integrated circuit package
  • FIG. 5 is a schematic side view of a deformed IC lead to which a land is connected by means of molten solder;
  • FIGS. 3A and 3B illustrate a substrate 100 for mounting an integrated circuit package manufactured by a method according to the present invention.
  • FIG. 3A shows a perspective view of the substrate 100 which includes an integrated circuit package 10 and a substrate 30 .
  • the integrated circuit package 10 contains a plurality of IC leads 12 -n (n: an integer), while the substrate 30 contains a plurality of lands 32 -n (n: an integer).
  • the substrate 100 is formed by connecting each IC lead 12 -n (n: an integer) in each integrated circuit package 10 with each land 32 -n (n: an integer) in the substrate 30 by means of a melting conductive material (e.g., solder) 22 -n (n: an integer) which has been previously molten, and as a result, an electrically and physically firmly connected product is obtained.
  • a melting conductive material e.g., solder 22 -n (n: an integer
  • the land 32 -n (n: an integer) is stereoscopically shown in the accompanying drawings, it is made for convenience, and the land may be in the form of a flat thin metal foil.
  • the IC lead 12 - 1 positioned at the end of the integrated circuit package 10 is a lead which is specified as the deformed one.
  • deformed means that, for instance, a part of the IC lead is bent upwards and has no flat contact with respect to the substrate 30 for ensuring a predetermined degree of reliable connection.
  • nondeformed means that, for instance, the IC lead has flat contact with respect to the substrate 30 for ensuring a predetermined degree of reliable connection.
  • FIG. 3B shows the substrate 100 containing deformed and nondeformed IC leads 12 -n (n: an integer) viewed from the front of the drawing.
  • an amount of solder 22 - 1 on an land 32 - 1 is larger than that of solder 22 -n (n: an integer) on a non-end land 32 -n (n: an integer) in the substrate 100 , wherein a non-end land 32 -n (n: an integer) is a land which is not positioned at the end of the integrated circuit package 10 and corresponds to a nondeformed IC lead.
  • the reason therefor resides in that, in case of melting the solder 22 - 1 , the solder 22 - 1 expands higher than a height of the solder 22 -n (n: an integer) on the non-end land 32 -n (n: an integer) in the vertical direction with respect to the substrate 30 due to surface tension, whereby the IC lead 12 - 1 deformed upwards is reliably connected by the solder 22 - 1 .
  • the end IC lead 12 - 1 as well as the one located in the same row at the other end of the integrated circuit package 10 are illustrated as the leads which have been deformed. In this respect, however, the number and the location of leads are not limited to the case shown in the FIGS. 3A and 3B.
  • a procedure for connecting the IC leads 12 -n (n: an integer) containing the deformed IC lead 12 - 1 to the lands 32 -n (n: an integer) in the substrate 30 is classified generally into two processes, i.e., a solder supplying process (FIG. 4) and a solder melting process (FIG. 5 ). In the following, these processes will be described in the order thereof.
  • FIG. 4 shows the solder 22 -n (n: an integer) supplied on the lands 32 -n (n: an integer) as well as the corresponding IC leads 12 -n (n: an integer) in the integrated circuit package 10 , respectively.
  • an amount of the solder 22 - 1 is larger than those of the solder 22 -n (n: an integer).
  • Adjustment for locations and an amount of solder to be supplied can be realized by applying a solder printing technology, wherein a thin sheet (not shown) provided with apertures at desired positions and with desired dimensions is utilized. More specifically, a position of the thin sheet is adjusted in such that apertures defined on the thin sheet are fit in the lands 32 -n (n: an integer) to which solder is supplied, respectively, then solder in paste form is spread over the thin sheet, and the solder is smoothed pressingly by the use of a pallet and the like. As a result, the solder is pushed out from the apertures, so that the solder is supplied on the lands 32 -n (n: an integer), respectively.
  • each amount of solder 22 -n (n: an integer) is adjusted as shown in FIG. 4 .
  • FIG. 5 shows the deformed IC lead 12 - 1 connected to the end land 32 - 1 by means of the molten solder 22 - 1 .
  • the solder portion 22 - 1 melts on the land 32 - 1 .
  • the molten solder 22 - 1 becomes a state where it maintains a predetermined height from the substrate 30 in the vertical direction without flowing out from the land 32 - 1 due to its surface tension, whereby the molten solder is in contact with the IC lead 12 - 1 in a sufficient area for connecting these members with each other.
  • a height of the solder portion in this case is higher than that of each solder portion molten in the non-end lands 32 -n (n: an integer).
  • solder 22 - 1 When solder 22 - 1 is cooled, it solidifies in a condition where it extends comparatively high in the vertical direction with respect to the substrate. As a result, the IC leads 12 -n (n: an integer) (FIG. 4) are connected reliably electrically and physically with the lands 32 -n (n: an integer) (FIG. 4 ).
  • solder 22 - 1 may contain, for example, the case where solder 22 - 1 is in contact with the deformed IC lead 12 - 1 in such a degree wherein solder 22 - 1 covers not only the whole lower surface of the IC lead 12 - 1 , but also the whole upper surface thereof.
  • soldering treatment is carried out also between each of non-end IC leads 12 -n (n: an integer) and each of non-end lands 32 -n (n: an integer), hence they are connected with each other.
  • the integrated circuit package 10 when the integrated circuit package 10 is connected with the substrate 30 , the integrated circuit package 10 can send and receive signals to and from other components of the substrate 30 through each leader line wiring 34 -n (n: an integer).
  • a procedure for supplying and melting the solder has been explained.
  • a location where solder is to be supplied it is adjusted in response to a spacing defined between the respective IC leads 12 -n (n: an integer) as described hereinafter.
  • a spacing defined between the IC lead 12 - 1 and its adjacent IC lead ( 12 - 2 ) is represented by a 1
  • a spacing defined between an IC lead 12 -n and another IC lead 12 -(n+1) is represented by a 2 .
  • spacings a 1 and a 2 are comparatively wide (for example, each of them is 1 mm), there is no particular relationship to be satisfied between spacings b 1 and b 2 wherein solder are supplied to lands with these spacings, respectively.
  • they may be b 1 ⁇ b 2 .
  • an amount of solder supplied to the land 32 - 1 is made to be comparatively large in the present invention, there is a fear of producing a solder bridge by which adjacent IC leads are electrically connected with each other.
  • solder bridge In the case when finely arranged IC leads 12 -n (n: an integer) are soldered, for instance, a larger amount of the solder may be supplied on the land 32 - 1 at a position opposed to its adjacent land 32 - 2 .
  • a possibility of producing solder bridge can be suppressed in low level at the time when solder printing was completed.
  • a possibility of producing solder bridge is suppressed also in low level, even after the solder was melted in accordance with reflow soldering process. The reason therefor is as follows.
  • solder 22 - 1 In the case where, for example, the IC lead 12 - 1 has been deformed upwards, a larger amount of the solder 22 - 1 is required in comparison with solder 22 -n (n: an integer), because a gap defined between IC lead 12 - 1 and the land 32 - 1 is larger than that defined between IC lead 12 -n and the land 32 -n. Accordingly, even if a large amount of the solder 22 - 1 is supplied, it is utilized for filling up the gap defined between the whole lower surface of the end IC lead 12 - 1 and the land 32 - 1 to connect them with each other, and hence, such large amount of the solder 22 - 1 is not an excessive amount sufficient for producing a solder bridge.
  • An amount of the solder 22 - 1 may be suitably selected dependent upon a degree of deformation in an IC lead and a range within which a solder bridge is not produced after melting the solder.
  • a minute wall for preventing solder from going into a gap between lands may be provided.
  • Such minute wall can be obtained by either applying, for example, a solder resist for repelling solder onto the surface of a land with a slightly thick thickness, or placing a s Amble insulating material in between lands. If such countermeasure as described above is applied before conducting solder printing, it is necessary for establishing a height of such minute wall to be a degree at which solder printing can be realized. This is because a thin sheet (not shown) containing apertures for printing solder lodges a minute wall(s) so that solder printing cannot be effected, if the height of minute wall is impertinent.
  • a deformed IC lead is an end IC lead 12 - 1 which is positioned at the end of the integrated circuit package 10 , it is not necessarily limited to the end IC lead, but it may be any non-end IC lead.
  • a much larger amount of solder is supplied to a land in case of soldering a deformed IC lead as compared with conventional soldering, so that solidified solder portion extended in the vertical direction with respect to its substrate with a height higher than that of the other portions of solder on the corresponding lands is obtained due to surface tension produced in the case where the solder is melted, whereby the deformed IC lead can be reliably connected to the corresponding land.
  • a deformed IC lead is an end lead, the end lead can be reliably connected to a land.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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Abstract

In an integrated circuit package, a deformed IC lead is reliably connected with a land for mounting. Such reliable connection between the deformed IC lead and a land is realized by a method for mounting an integrated circuit package wherein a non deformed first lead and a deformed second lead in the integrated circuit package are connected to a first land and a second land on a substrate, respectively. comprising a step for supplying a conductive material on a land wherein a larger amount of the conductive material than that of the first land is supplied to the second land; and a step for melting the conductive material supplied to connect a lead with a land wherein the conductive material molten on the first land extends in the vertical direction with respect to the substrate with a first height thereby connecting the first lead with the first land, while the conductive material molten on the second land extends with a higher second height than the first height due to surface tension thereby connecting the second lead with the second land.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to mounting an integrated circuit to a substrate, and in particular to connection between IC leads in an integrated circuit package and lands for mounting on a substrate.
2. Description of the Related Art
An integrated circuit package of a type which is mounted on the surface of a substrate is provided with a plurality of IC leads each being a part to be connected with the substrate. These IC leads are electrically connected reliably with a plurality of lands for mounting on the substrate by the use of a melting conductive material such as solder, in general. FIG. 1 shows solder 92-n (n: an integer) supplied on lands 32-n (n: an integer), and corresponding IC leads 12-n (n: an integer) in an integrated circuit package 10. A connecting process therefor is carried out as described hereinafter. Each solder 92-n (n: an integer) is supplied on each land 32-n (n: an integer) in accordance with a predetermined printing manner, and then each IC lead 12-n (n: an integer) is located to be rested thereat. Thereafter, the solder is melted by means of, for example, reflow soldering, whereby each IC lead 12-n is electrically connected to each land 32-n (n: an integer). When the integrated circuit package 10 is connected to the substrate 30, the integrated circuit package 10 can send and receive signals to and from other components of the substrate 30 through each leader line wiring 34-n (n: an integer).
There is a case where IC lead in the integrated circuit package 10 is deformed in handling the same in a preceding stage such as a manufacturing stage for mounting the integrated circuit package 10. Particularly, it is known that an end IC lead 12-1 positioned at the end of the integrated circuit package 10 is easily deformed. FIG. 1 shows the end IC lead 12-1 which has been deformed. The term “deformation” means herein a case where, for instance, a part of the IC lead is bent upwards, so that there is no predetermined twodimensional contact with respect to a substrate.
Heretofore, since an amount of each solder 92-n (n: an integer) to be supplied to each land 32-n (n: an integer) is equal, complete soldering could not have been performed between the end IC lead 12-1 and an land 32-1. FIG. 2 shows a state where the end IC lead 12-1 is connected to the land 32-1 by means of solder 92-1 wherein since the end IC lead 12-1 has been deformed upwards, either the end IC lead 12-1 is not i n contact with the solder 92-1 or only a part thereof is in contact with the solder 92-1. In this respect, FIG. 2 shows a state where the end IC lead 12-1 is in contact with the solder 92-1 in only a region A. The minuter region A brings about the higher possibility of disconnection due to some oscillation or the like. Under the circumstances, it is not concluded that soldering has been completed sufficiently. If the end IC lead 12-1 has not been essentially in contact with the solder 92-1, a purpose for soldering is never achieved. Such a resultant substrate is determined as a defective good as a result of inspection. Thus, for example as a rework, further solder is supplied manually onto the end IC lead 12-1, and then it has to be melted.
In this connection, for example, Japanese Patent Laid-Open No. 169153/1994 discloses such a technology that a more amount of solder is to be supplied to an end pad. However, this technology is the one to be applied for an end pad having a wider area than that of a usual end pad. Accordingly, when an end pad contains a wide area, a movable range of solder expands, so that a deformed end IC lead cannot be connected in a sufficiently firm condition after all.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for connecting reliably a deformed IC lead to a land.
Another object of the present invention is to provide a substrate for mounting an integrated circuit package connected by means of the method as described above.
According to the present invention, a method for mounting an integrated circuit package on a substrate, wherein the integrated circuit package includes a first lead being nondeformed and connected to a first land for mounting on the substrate, a second lead being deformed and connected to a second land for mounting on the substrate, comprises a step of supplying conductive material on a land on the substrate wherein an amount of the conductive material larger than that of the first land is supplied to the second land; and melting the conductive material supplied to connect a leald in the integrated circuit package with the land wherein the conductive material molten on the first land extends in the vertical direction with respect to the substrate with a first height thereby connecting the first lead with the first land, while the conductive material molten on the second land extends with a second height higher than the first height due to surface tension thereby connecting the second lead with the second land. As a result, one of the above described objects of the present invention is achieved.
Preferably, the integrated circuit package includes a plurality of leads and the second lead is an end lead positioned at the end of the plurality of leads.
For example, the step for supplying the conductive material onto the second land is a step for supplying a much larger amount of the conductive material onto the second land at a position opposed to the first land.
According to the present invention, a substrate for mounting an integrated circuit package comprises an integrated circuit package provided with a first lead and a deformed second lead, the first lead being nondeformed and the second lead being deformed; the substrate provided with a first land and a second land; a conductive material on the first land, which has a first height in the vertical direction with respect to the substrate and which connects the first lead with the first land; an amount of the conductive material on the second land larger than that of the conductive material on the first land, which has a second height higher than the first height due to surface tension produced in the case where the conductive material is melted and which connects the second lead with the second land. As a result, the other of the above described objects of the present invention is achieved.
Preferably, the integrated circuit package includes a plurality of leads and the second lead is an end lead positioned at the end of the plurality of leads.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1 is a perspective view of solder supplied on lands and corresponding IC leads in a prior art integrated circuit package; and
FIG. 2 is a schematic side view of a deformed IC lead to which a land is connected by means of molten solder.
FIG. 3A is a perspective view of a substrate for mounting integrated circuit package manufactured by a method according to the present invention;
FIG. 3B is a plan view of a substrate as illustrated in FIG. 3A;
FIG. 4 is a schematic view of portions of solder supplied on lands and corresponding IC leads in an integrated circuit package;
FIG. 5 is a schematic side view of a deformed IC lead to which a land is connected by means of molten solder;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A preferred embodiment of the present invention will be described hereinafter by referring to the accompanying drawings.
FIGS. 3A and 3B illustrate a substrate 100 for mounting an integrated circuit package manufactured by a method according to the present invention. FIG. 3A shows a perspective view of the substrate 100 which includes an integrated circuit package 10 and a substrate 30. The integrated circuit package 10 contains a plurality of IC leads 12-n (n: an integer), while the substrate 30 contains a plurality of lands 32-n (n: an integer). The substrate 100 is formed by connecting each IC lead 12-n (n: an integer) in each integrated circuit package 10 with each land 32-n (n: an integer) in the substrate 30 by means of a melting conductive material (e.g., solder) 22-n (n: an integer) which has been previously molten, and as a result, an electrically and physically firmly connected product is obtained. The expression “electrically and physically firm connection of an IC lead and a land with a conductive material” is simply expressed as “connection” hereinafter.
It is to be noted that while the land 32-n (n: an integer) is stereoscopically shown in the accompanying drawings, it is made for convenience, and the land may be in the form of a flat thin metal foil.
In the substrate 100, the IC lead 12-1 positioned at the end of the integrated circuit package 10 is a lead which is specified as the deformed one. The term “deformed” means that, for instance, a part of the IC lead is bent upwards and has no flat contact with respect to the substrate 30 for ensuring a predetermined degree of reliable connection. Further, the term “nondeformed” means that, for instance, the IC lead has flat contact with respect to the substrate 30 for ensuring a predetermined degree of reliable connection.
FIG. 3B shows the substrate 100 containing deformed and nondeformed IC leads 12-n (n: an integer) viewed from the front of the drawing. As shown in the same figure, an amount of solder 22-1 on an land 32-1 is larger than that of solder 22-n (n: an integer) on a non-end land 32-n (n: an integer) in the substrate 100, wherein a non-end land 32-n (n: an integer) is a land which is not positioned at the end of the integrated circuit package 10 and corresponds to a nondeformed IC lead. The reason therefor resides in that, in case of melting the solder 22-1, the solder 22-1 expands higher than a height of the solder 22-n (n: an integer) on the non-end land 32-n (n: an integer) in the vertical direction with respect to the substrate 30 due to surface tension, whereby the IC lead 12-1 deformed upwards is reliably connected by the solder 22-1. In FIGS. 3A and 3B, the end IC lead 12-1 as well as the one located in the same row at the other end of the integrated circuit package 10 are illustrated as the leads which have been deformed. In this respect, however, the number and the location of leads are not limited to the case shown in the FIGS. 3A and 3B.
A procedure for connecting the IC leads 12-n (n: an integer) containing the deformed IC lead 12-1 to the lands 32-n (n: an integer) in the substrate 30 is classified generally into two processes, i.e., a solder supplying process (FIG. 4) and a solder melting process (FIG. 5). In the following, these processes will be described in the order thereof.
FIG. 4 shows the solder 22-n (n: an integer) supplied on the lands 32-n (n: an integer) as well as the corresponding IC leads 12-n (n: an integer) in the integrated circuit package 10, respectively. As shown in FIG. 4 and as described above by referring to FIG. 3B, an amount of the solder 22-1 is larger than those of the solder 22-n (n: an integer).
Adjustment for locations and an amount of solder to be supplied can be realized by applying a solder printing technology, wherein a thin sheet (not shown) provided with apertures at desired positions and with desired dimensions is utilized. More specifically, a position of the thin sheet is adjusted in such that apertures defined on the thin sheet are fit in the lands 32-n (n: an integer) to which solder is supplied, respectively, then solder in paste form is spread over the thin sheet, and the solder is smoothed pressingly by the use of a pallet and the like. As a result, the solder is pushed out from the apertures, so that the solder is supplied on the lands 32-n (n: an integer), respectively. Accordingly, when dimension and position in respective apertures are adjusted, a desired amount of solder can be supplied to a land located at an arbitrary position. As described above, each amount of solder 22-n (n: an integer) is adjusted as shown in FIG. 4.
After the solder 22-n (n: an integer) are supplied on the lands 32-n (n: an integer), then the IC leads 12-n (n: an integer) are located to rest them on the lands 32-n (n: an integer) on which solder 22-n (n: an integer) have been supplied. Thereafter, these portions of solder are melted in accordance with, for example, a reflow soldering process. FIG. 5 shows the deformed IC lead 12-1 connected to the end land 32-1 by means of the molten solder 22-1.
As mentioned above, since a comparatively large amount of the solder 22-1 is supplied to the land 32-1, when these members are heat-treated in accordance with the reflow soldering process, the solder portion 22-1 melts on the land 32-1. The molten solder 22-1 becomes a state where it maintains a predetermined height from the substrate 30 in the vertical direction without flowing out from the land 32-1 due to its surface tension, whereby the molten solder is in contact with the IC lead 12-1 in a sufficient area for connecting these members with each other. A height of the solder portion in this case is higher than that of each solder portion molten in the non-end lands 32-n (n: an integer). When solder 22-1 is cooled, it solidifies in a condition where it extends comparatively high in the vertical direction with respect to the substrate. As a result, the IC leads 12-n (n: an integer) (FIG. 4) are connected reliably electrically and physically with the lands 32-n (n: an integer) (FIG. 4).
It is to be noted that the term “reliably physical contact” herein may contain, for example, the case where solder 22-1 is in contact with the deformed IC lead 12-1 in such a degree wherein solder 22-1 covers not only the whole lower surface of the IC lead 12-1, but also the whole upper surface thereof. Referring again to FIG. 4, usual soldering treatment is carried out also between each of non-end IC leads 12-n (n: an integer) and each of non-end lands 32-n (n: an integer), hence they are connected with each other. As a result of soldering as described above, when the integrated circuit package 10 is connected with the substrate 30, the integrated circuit package 10 can send and receive signals to and from other components of the substrate 30 through each leader line wiring 34-n (n: an integer).
As mentioned above, a procedure for supplying and melting the solder has been explained. As to a location where solder is to be supplied, it is adjusted in response to a spacing defined between the respective IC leads 12-n (n: an integer) as described hereinafter. Namely, a spacing defined between the IC lead 12-1 and its adjacent IC lead (12-2) is represented by a1, while a spacing defined between an IC lead 12-n and another IC lead 12-(n+1) is represented by a2. In this condition, when the spacings a1 and a2 are comparatively wide (for example, each of them is 1 mm), there is no particular relationship to be satisfied between spacings b1 and b2 wherein solder are supplied to lands with these spacings, respectively. For example, they may be b1<b2.
On the other hand, the spacing a1 and the spacing a2 are comparatively narrow (e.g., 0.3 to 0.4 mm), it is preferred that the spacings b1 and b2 wherein solder are supplied to lands with these spacings, respectively, are b1=b2, and further b1>b2. This is because an amount of solder supplied to the land 32-1 is made to be comparatively large in the present invention, there is a fear of producing a solder bridge by which adjacent IC leads are electrically connected with each other.
In the case when finely arranged IC leads 12-n (n: an integer) are soldered, for instance, a larger amount of the solder may be supplied on the land 32-1 at a position opposed to its adjacent land 32-2. Thus, a possibility of producing solder bridge can be suppressed in low level at the time when solder printing was completed. Moreover, a possibility of producing solder bridge is suppressed also in low level, even after the solder was melted in accordance with reflow soldering process. The reason therefor is as follows.
In the case where, for example, the IC lead 12-1 has been deformed upwards, a larger amount of the solder 22-1 is required in comparison with solder 22-n (n: an integer), because a gap defined between IC lead 12-1 and the land 32-1 is larger than that defined between IC lead 12-n and the land 32-n. Accordingly, even if a large amount of the solder 22-1 is supplied, it is utilized for filling up the gap defined between the whole lower surface of the end IC lead 12-1 and the land 32-1 to connect them with each other, and hence, such large amount of the solder 22-1 is not an excessive amount sufficient for producing a solder bridge. An amount of the solder 22-1 may be suitably selected dependent upon a degree of deformation in an IC lead and a range within which a solder bridge is not produced after melting the solder.
As a countermeasure for producing no solder bridge, a minute wall for preventing solder from going into a gap between lands may be provided. Such minute wall can be obtained by either applying, for example, a solder resist for repelling solder onto the surface of a land with a slightly thick thickness, or placing a s uitable insulating material in between lands. If such countermeasure as described above is applied before conducting solder printing, it is necessary for establishing a height of such minute wall to be a degree at which solder printing can be realized. This is because a thin sheet (not shown) containing apertures for printing solder lodges a minute wall(s) so that solder printing cannot be effected, if the height of minute wall is impertinent.
The preferred embodiment of the present invention has been made as described above. While the present invention has been explained in such that a deformed IC lead is an end IC lead 12-1 which is positioned at the end of the integrated circuit package 10, it is not necessarily limited to the end IC lead, but it may be any non-end IC lead.
According to the present invention, a much larger amount of solder is supplied to a land in case of soldering a deformed IC lead as compared with conventional soldering, so that solidified solder portion extended in the vertical direction with respect to its substrate with a height higher than that of the other portions of solder on the corresponding lands is obtained due to surface tension produced in the case where the solder is melted, whereby the deformed IC lead can be reliably connected to the corresponding land.
If a deformed IC lead is an end lead, the end lead can be reliably connected to a land.
When a much larger amount of a conductive material is supplied on a land which is to be connected to a deformed IC lead at a position opposed to its adjacent land, a possibility of production of a solder bridge is suppressed in low level at the time when solder was supplied and after the solder was melted in accordance with a reflow soldering process.
It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
The presently disclosed embodiment is therefore considered in all respects to be illustrated and not restrictive.

Claims (5)

What is claimed is:
1. A method for mounting an integrated circuit package on a substrate, wherein the integrated circuit package includes a first lead being nondeformed and connected to a first land for mounting on the substrate, a second lead being deformed and connected to a second land for mounting on the substrate, comprising the steps of:
supplying conductive material on a land on the substrate wherein an amount of the conductive material larger than that of the first land is supplied to the second land; and
melting the conductive material supplied to connect a lead in the integrated circuit package with the land wherein the conductive material molten on the first land extends in the vertical direction with respect to the substrate with a first height thereby connecting the first lead with the first land, while the conductive material molten on the second land extends with a second height higher than the first height due to surface tension thereby connecting the second lead with the second land.
2. A method for mounting the integrated circuit package as claimed in claim 1, wherein the integrated circuit package includes a plurality of leads and the second lead is an end lead positioned at the end of the plurality of leads.
3. A method for mounting the integrated circuit package as claimed in claim 2, wherein the s tep for supplying the conductive material onto the second land is a step for supplying a much larger amount of the conductive material onto the second land at a position opposed to the first land.
4. A substrate for mounting an integrated circuit package comprising:
an integrated circuit package provided with a first lead and a second lead, the first lead being nondeformed and the second lead being deformed;
the substrate provided with a first land and a second land for mounting, respectively;
a conductive material on the first land, which has a first height in the vertical direction with respect to the substrate and which connects the first lead with the first land;
an amount of the conductive material on the second land larger than that of the conductive material on the first land, which has a second height higher than the first height due to surface tension produced in the case where the conductive material is melted and which connects the second lead with the second land.
5. A substrate for mounting an integrated circuit package as claimed in claim 4, wherein the integrated circuit package includes a plurality of leads and the second lead is an end lead positioned at the end of the plurality of leads.
US09/772,891 2000-07-24 2001-01-31 Substrate mounting an integrated circuit package with a deformed lead Expired - Fee Related US6441477B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120176716A1 (en) * 2011-01-10 2012-07-12 Hamilton Sundstrand Corporation Vertical mount transient voltage suppressor array

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005103093A (en) * 2003-09-30 2005-04-21 Olympus Corp Insertion shape detecting probe
AU2004214572B2 (en) 2003-09-30 2010-04-29 Olympus Corporation Inserting shape detecting probe

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041901A (en) * 1989-05-10 1991-08-20 Hitachi, Ltd. Lead frame and semiconductor device using the same
JPH0415989A (en) 1990-05-09 1992-01-21 Fujitsu Ltd Printed board
JPH0563132A (en) * 1991-09-03 1993-03-12 Mitsubishi Electric Corp Lead shape in semiconductor package
JPH05343593A (en) * 1992-06-11 1993-12-24 Nec Corp Connecting terminal
US5291375A (en) * 1991-09-30 1994-03-01 Kabushiki Kaisha Toshiba Printed circuit board and electric device configured to facilitate bonding
JPH06169153A (en) 1992-11-30 1994-06-14 Ibiden Co Ltd Printed wiring board
JPH06232317A (en) * 1993-01-29 1994-08-19 Toshiba Corp Multiterminal electronic part and manufacturing method thereof
US5367124A (en) * 1993-06-28 1994-11-22 International Business Machines Corporation Compliant lead for surface mounting a chip package to a substrate
US5455446A (en) * 1994-06-30 1995-10-03 Motorola, Inc. Leaded semiconductor package having temperature controlled lead length
US5759730A (en) * 1995-12-04 1998-06-02 Delco Electronics Corporation Solder joint encapsulation material
US5880405A (en) * 1995-12-28 1999-03-09 Alps Electric Co., Ltd. Terminal structure for electronic part with stepped offset portions

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041901A (en) * 1989-05-10 1991-08-20 Hitachi, Ltd. Lead frame and semiconductor device using the same
JPH0415989A (en) 1990-05-09 1992-01-21 Fujitsu Ltd Printed board
JPH0563132A (en) * 1991-09-03 1993-03-12 Mitsubishi Electric Corp Lead shape in semiconductor package
US5291375A (en) * 1991-09-30 1994-03-01 Kabushiki Kaisha Toshiba Printed circuit board and electric device configured to facilitate bonding
JPH05343593A (en) * 1992-06-11 1993-12-24 Nec Corp Connecting terminal
JPH06169153A (en) 1992-11-30 1994-06-14 Ibiden Co Ltd Printed wiring board
JPH06232317A (en) * 1993-01-29 1994-08-19 Toshiba Corp Multiterminal electronic part and manufacturing method thereof
US5367124A (en) * 1993-06-28 1994-11-22 International Business Machines Corporation Compliant lead for surface mounting a chip package to a substrate
US5455446A (en) * 1994-06-30 1995-10-03 Motorola, Inc. Leaded semiconductor package having temperature controlled lead length
US5759730A (en) * 1995-12-04 1998-06-02 Delco Electronics Corporation Solder joint encapsulation material
US5880405A (en) * 1995-12-28 1999-03-09 Alps Electric Co., Ltd. Terminal structure for electronic part with stepped offset portions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120176716A1 (en) * 2011-01-10 2012-07-12 Hamilton Sundstrand Corporation Vertical mount transient voltage suppressor array
US8638535B2 (en) * 2011-01-10 2014-01-28 Hamilton Sundstrand Corporation Vertical mount transient voltage suppressor array

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