JP3498458B2 - Hybrid integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which electric parts are mounted on the surface of a circuit board.

[0002]

2. Description of the Related Art In a hybrid integrated circuit device in which an electric component such as a semiconductor chip is mounted on a circuit board, bumps provided on the electric component and the circuit board are used as a method of mounting the electric component on the circuit board. There is a method using a face-down bonding method for bonding with a provided land. In recent years, due to the progress of high integration technology and ultra-miniaturization technology, the electric component tends to be miniaturized even though it has many terminals, and accordingly, the bump is also miniaturized.

[0003]

However, when the bumps are miniaturized as described above, high positional accuracy is required when mounting the electric components on the circuit board. The reason will be described with reference to FIGS. 14 and 15. Figure 14
It is an example of an electric component used for a conventional hybrid integrated circuit device. On the soldered surface 130a of the electric component 130, 16 bumps 131 of the same size are arranged in a matrix of 4 rows × 4 rows. The bumps 131 are semicircular solder particles formed by placing solder on the soldered surface 130a. As shown in FIG. 15, when the bumps 131 are soldered to the lands 110 provided on the circuit board 150, if the position where the electrical component 130 is placed is displaced, the position where the electrical component is soldered is displaced, which causes The bonding area is smaller than that when the bump 131 is soldered near the center of the land 110 as designed. Therefore, there is a problem that the contact resistance between the bump 131 and the land 110 increases and the soldering strength of the electric component 130 also decreases. When the mounting position of the electrical component 130 is further displaced, the bump 131 is located between the lands 110, so that the bump 131 and the land 110 are not electrically connected to each other, or one bump 131 is adjacent to two lands. When the two lands 110 are joined across the 110, the two lands 110 may be short-circuited.

To address such problems, Japanese Patent Publication No. 6-262
In Japanese Patent Laid-Open No. 27, as shown in FIGS. 16 and 17, among the pads of the chips arranged in a matrix on the chip 101, the pads 105 at the four corners are formed to have a larger diameter than the other pads 102, and the substrate is further formed. The pads 106 at the four corners of the substrate pads arranged in a matrix in 104
There is disclosed a method of mounting a semiconductor chip having a larger diameter than other pads 103. According to this mounting method, the pad 1 of the chip is misaligned when the chip is placed.
02 and the pad 103 of the substrate are not in contact with each other, the pad 105 of the chip is in contact with the pad 106 of the substrate, the pad 102 is in contact with the pad 103 of the substrate due to the surface tension of the solder forming the pad 105. The chip can be moved to perform automatic alignment (hereinafter, referred to as “self-alignment”) as described above.

However, in Japanese Patent Publication No. 6-26227, pads 102 and 105 of substrates having different diameters are included in one chip.
However, in practice, it is difficult to make the pads 102 and 105 having different diameters the same height. That is, when a molten solder is placed on a chip to form a bump, the pad 105 having a large diameter is formed in a crushed shape as compared with the pad 102 having a small diameter due to the weight of the solder itself forming the pad 105. It Moreover, the degree of crushing changes depending on the viscosity of the solder supplied when forming the pad 105, the temperature of the chip surface, and the like. Therefore, the pad 10 is at the same height as the pad 102.
In order to form No. 5, it is necessary to accurately control the process conditions, and also to require sophisticated technology, know-how, and highly accurate equipment. Pad 105 compared to pad 102
When the pad is formed low, the pad 102 becomes the pad 10 of the substrate.
Pad 105 and substrate pad 1 when locked onto 3
Since the pad 106 and the pad 106 on the substrate are not contacted, the pad 105 and the pad 106 on the substrate are not joined. Further, since the pads 105 having large diameters are formed at the four corners, there is a problem that the chip size becomes large.

An object of the present invention is to provide a hybrid integrated circuit device which has a wide self-alignable area when an electric component is mounted on a circuit board and can easily form bumps.

[0007]

According to the hybrid integrated circuit device of the first aspect, since each bump has the same size, size management is easy. In addition, since the corner lands located at the four corners of the lands arranged in a rectangular shape are larger than the intermediate lands, the positional deviation width of the electrical component from the basic soldering position when mounting the electrical component on the land Even if the intermediate bump and the intermediate land are too large to be in contact with each other, if a part of the corner bump and the corner land are in contact with each other, the surface tension of solder forming the corner bump causes the electric component to Can be self-aligned.

According to the hybrid integrated circuit device of the second aspect, since the diameter f of the contact surface between each bump and each land is smaller than the width b of the intermediate land, the bump with respect to the surface tension of the solder forming each bump is bumped. Because the weight of is small,
The position correction force of the electric component based on this surface tension can be effectively worked. According to the hybrid integrated circuit device of claim 3, the distance from the side of the corner land facing the adjacent intermediate land to the outer circumference of the contact surface, the facing side of each adjacent intermediate land, and the adjacent side. Since the distance from the side of the intermediate land facing the corner land to the outer circumference of the contact surface is equal , the bumps can be arranged at equal intervals even if the corner land is larger than the intermediate land. This facilitates the formation of bumps.

According to another aspect of the hybrid integrated circuit device of the present invention, the width of the corner land is a on each side of the rectangle.
The width of the intermediate land is b, the distance between the adjacent lands is d, and the diameter of the contact surface between each bump and the corner land or the intermediate land when the solder constituting the bump group at the soldering basic position is melted. Where f is f, the positional deviation width g satisfies the following equations (1) to (3).

{G + (1/2) × (b−f)} <a <(b + f) (1) {g + (1/2) × (f−b)} <d (2) ) G <{(3/2) f + (1/2) b} (3) The meanings of the expressions (1) to (3) will be described below with reference to FIGS. 7 to 11. 7 to 11, 211 is a corner land, 212 is an intermediate land, 231 is a corner bump, 232
Is the middle bump. The corner bumps 231 and the intermediate bumps 232 are indicated by solid lines at the soldering basic positions, and by dotted lines when the positions for mounting the electric components are displaced by the displacement width g.

In the above formula (1), {g + (1/2) ×
The reason for (b−f)} <a is that, as shown in FIG.
When the 32 and the intermediate land 212 are not in contact with each other, in order to move the electric component (not shown) to the right in FIG. 7 by the self-alignment force based on the surface tension of the solder forming the corner bumps 231, the corner land is This is because the 211 needs a width a that allows a part of the corner bump 231 to be placed on the corner land 211.

The reason for setting a <(b + f) is as shown in FIG.
As shown in FIG. 6, when the entire corner bump 231 is placed on the corner land 211 when the middle bump 232 and the middle land 212 are not in contact with each other, the shape of the solder forming the corner bump 231 becomes stable. This is because the self-alignment force based on the surface tension of the solder does not work. In order to exert the self-alignment force based on the surface tension of the solder forming the corner bumps 231, a part of the corner bumps 231 is removed while the electric component moves to the position where the intermediate bumps 232 and the intermediate lands 212 contact each other. It is necessary to protrude from the corner land 211.

In the above equation (2), {g + (1/2)
The reason for setting x (f−b)} <d is as shown in FIG.
If the value of d is less than or equal to the range of the equation (2), the intermediate land 212
Since the intermediate bumps 232 to be bonded to the corner bumps 211 contact the adjacent corner lands 211, the intermediate bumps 23
This is because the surface tension of the solder constituting No. 2 acts so as to move the electric component to the left in FIG. Therefore, when the value of d is equal to or less than the range of the expression (2), the upper limit of the positional deviation width g is determined by d, and g <{d- (1/2) × (fb)} ... (4)

Further, as shown by the alternate long and short dash line in FIG. 10, when the intermediate bump 232 separates from the intermediate land 212, a part of the corner bump 231 needs to protrude from the corner 211, and the dotted line in FIG. As shown in FIG. 5, a part of the corner bump 231 needs to be in contact with the corner land 231. Therefore, the positional deviation width g is in a range that satisfies the above expression (3).

Although FIG. 2 to FIG. 6 show the case of b <d, as shown in FIG. 11, the above equations (1) to (4) are also valid when b> d.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 6 show a hybrid integrated circuit device according to a first embodiment of the present invention. This is an example of mounting a semiconductor chip on a printed circuit board by a face-down method.

The hybrid integrated circuit device 1 comprises a circuit board 50 and a semiconductor chip 54 mounted thereon. Figure 1
As shown in FIG. 5, the circuit board 50 has a conductor 53 printed on the surface of the substrate 51, and the glass 52 is formed on the conductor 53. A window 52a is provided in the glass 52 where the semiconductor chip 54 as an electric component is mounted, and the conductor 53 and the substrate 51 are exposed in the window 52a. The corner lands 11, 12, 13, 14 formed by the conductor 53 exposed in the window 52a and the intermediate land 15 located between them are the semiconductor chips 54.
Bumps 31, 32, 33, 34, which will be described later,
35 are arranged in a square shape corresponding to
The semiconductor chip 54 is mounted on the land group 10 formed by the corner lands 11, 12, 13, 14 and the intermediate land 15.

As shown in FIG. 3, a bump group 30 is formed on the semiconductor chip 54 by placing solder particles on terminals (not shown) arranged in a square shape on the surface to be soldered 54a. As shown in FIG. 1, this bump group 30
Are corner bumps 31, 3 located at the four corners of the square.
2, 33, 34 and intermediate bumps 35 located on the sides of the square between them. Corner bump 3
1, 32, 33, 34 and the intermediate bump 35 are formed to have the same size and are arranged at equal intervals. This makes it easy to form the bump group 30 and manage the size of each bump.

The semiconductor chip 5 shown by the dotted line in FIG.
The position 4 is a predetermined mounting position of the semiconductor chip 54 in the hybrid integrated circuit device 1, that is, a “soldering basic position” described in the claims. The shape of the bump group 30 shown by the dotted line in FIG. 1 indicates the contact surface between the bump group 30 and the land group 10 when the solder forming the bump group 30 is melted at the soldering basic position.

Here, with respect to the direction A parallel to one side of the square formed by the bump group 30, the width of the corner lands 11, 12, 13, 14 at the soldering basic position is a and the width of the intermediate land 15 is a. Width b, corner lands 11, 12,
The distance between the adjacent intermediate lands 15 and 13, 14 and the distance between the two adjacent intermediate lands 15 are d,
Further, the bump group 30 and the land group 1 when the solder constituting the bump group 30 is melted at the soldering basic position
The diameter of the contact surface with 0 is f, and the semiconductor chip 54
When the position for mounting on the circuit board 50 deviates from the soldering basic position, this misregistration is defined as a position deviation width capable of self-alignment. At this time, as shown in FIG. 1, b> f, and the positional deviation width g satisfies the following expressions (1) to (3).

{G + (1/2) × (b−f)} <a <(b + f) ... (1) {g + (1/2) × (f−b)} <d ... (2) ) G <{(3/2) f + (1/2) b} (3) In the first embodiment of the present invention, a = 200 μm and b = 130.
μm, d = 120 μm, f = 100 μm, and
The bump group 30 and the land group 10 are formed in a 90 ° rotationally symmetrical shape.

Further, as shown in FIG. 1, at the soldering basic position, the distance D1 'from the sides 11a and 12a of the corner lands 11 and 12 facing the adjacent intermediate land 15 to the outer periphery of the contact surface is , Two adjacent intermediate lands 1
5 opposing sides 15a and adjacent corner lands 1
It is equal to the distance from the side 15b of the intermediate land 15 facing the first and the second contact points 12 to the outer periphery of the contact surface. Therefore, from the outer periphery of the contact surface, the outer ends 11b, 1 of the corner lands 11, 12 are
The distance D2 to 2b is greater than the distance D1. In the first embodiment of the present invention, D1 = D1 '= 15 .mu.m and D2 = 8.
It is 5 μm.

In the hybrid integrated circuit device 1 having the above-described structure, the manner in which the positional deviation when the electric component 30 is placed on the circuit board 50 is self-aligned will be described with reference to FIGS. As shown in FIG. 3, from the soldering basic position, a positional deviation distance g1 that satisfies (1/2) × (f + b) <g1 <{(1/2) × (f + b) + f} (5) Only in FIG. 3, it is assumed that the electric component 30 is mounted at a position displaced to the left.

When the bump group 30 is melted in this state,
As shown in FIG. 4, the intermediate bumps 35 are separated from the intermediate lands 15, and the corner bumps 32 are separated from the corner lands 12. However, since the corner land 11 has the width a within the range of the above formula (1), a part of the corner bump 31 is in contact with the corner land 11. Although not shown, similarly, the corner bumps 33 and the corner lands 13 are separated from each other, and some of the corner bumps 34 are in contact with the corner lands 14.
Then, since the surface tension of the solder forming the corner bumps 31 and 34 for reducing the surface area of the corner bumps 31 and 34 in the molten state acts as a self-alignment force, the semiconductor chip 54 moves to the right in FIG. However, the displacement distance g1 gradually becomes smaller.

When the semiconductor chip 54 moves until g1 <(1/2) × (f + b) (6), a part of the intermediate bump 35 comes into contact with the intermediate land 15 and the corner bump 3
A part of 2, 33 contacts the corner lands 12, 13. As a result, in addition to the surface tension of the solder forming the corner bumps 31 and 34, the intermediate bump 35 and the corner bump 32,
The surface tension of the solder forming 33 acts as a self-alignment force, and the semiconductor chip 54 moves further to the right in FIG. 3, so that the displacement distance g1 becomes gradually smaller.

When the semiconductor chip 54 moves until g1 <{a− (1/2) × (b + f)} (7), as shown in FIG. 5, the contact surfaces of the corner bumps 31 and 34 are Since the whole is placed on the corner lands 11 and 14, the self-alignment force based on the surface tension of the solder forming the corner bumps 31 and 34 does not work. However, the intermediate bump 35 only partially contacts the intermediate land 15, and the corner bump 3
Since only a part of the reference numerals 2 and 33 is in contact with the corner lands 12 and 13, the intermediate bump 35 and the corner bumps 32 and 33 are included.
The semiconductor chip 54 is further moved to the right in FIG. 5 by the self-alignment force based on the surface tension of the solder constituting the semiconductor chip.

When the semiconductor chip 54 moves until g1 = (1/2) × (b−f) (8), corner bumps 31, 32, 33, 34 and The entire contact surface of the intermediate bump 35 is the corner land 11,
The semiconductor chip 54 is mounted on 12, 13, 14 and the intermediate land 15, and the self-alignment of the semiconductor chip 54 is completed.

FIG. 2 is a top view of the state shown in FIGS. 3 to 6, and the semiconductor chip 54, the corner bumps 31 and the intermediate bumps 35 are shown by the dotted lines in FIG. 3 and FIG.
The state in FIG. 6 is indicated by a chain line, and the state in FIG. 6 is indicated by a solid line. According to the first embodiment of the present invention,
In this way, the positional deviation distance g1 up to {(1/2) .times. (F + b) + f} can be corrected to be reduced to (1/2) .times. (B-f). That is, in the first embodiment, the position shift width g capable of self-alignment is set.
Is g <{(1/2) × (f + b) + f} (9).

On the other hand, in the conventional example shown in FIG. 14, the same length b
Since the land group 10 is composed of only the lands 110 having the above, all the bumps 131 are separated from the lands 110 when the electric component 130 is placed with a displacement distance g1 satisfying the above expression (5). Therefore, the electric component 130 cannot be self-aligned.
Therefore, according to the configuration of this conventional example, the position shift width g'that can be self-aligned is g '<(1/2) * (f + b) ... (10). According to the first embodiment of the present invention, it can be seen that the positional deviation width g becomes larger than the conventional example by the diameter f of the contact surface of the bump. As described above, the land group 10 has 9
Since it is formed in a 0 ° rotationally symmetrical shape, the direction A
The misalignment width g capable of self-alignment is the same also in the direction B orthogonal to. The values of a, b, d, and g with respect to the direction B may be different from those in the direction A as long as they satisfy the above (1) to (3).

As described above, according to the first embodiment of the present invention, the corner lands 11, 12, 1 are compared with the intermediate land 15.
By increasing 3 and 14, the positional deviation width g can be increased as compared with the conventional example shown in FIG. Also,
Unlike the conventional example shown in FIG. 16, the corner bumps 31, 32, 33, 34 and the intermediate bumps 35 forming the bump group 30 are formed.
Since they are formed in the same size as
The position shift width g can be increased without hindering the size reduction of No. 4. Furthermore, the corner bumps 31, 32, 33,
Since the bumps 34 and the intermediate bumps 35 are formed to have the same size and are arranged at equal intervals, it is easy to form the bump group 30 and manage the size of each bump.

In the above equation (5), the width a of the corner lands 11, 12, 13, 14 is set to a <(b + f) because the width a is more than this range at the stage of transition from the above to the above. Then, the intermediate bump 35 and the intermediate land 1
5 and corner bumps 32 and 33 and corner lands 12 and 13
Corner bump 3 before g1 becomes small until it contacts
This is because the entire contact surface of Nos. 1 and 34 is placed on the corner lands 11 and 14, and the semiconductor chip 54 cannot be self-aligned any more.

In the first embodiment, the semiconductor chip 5 is used.
The example in which the four terminals are arranged in a square shape has been described. However, in the case of a semiconductor chip in which the terminals are arranged in a rectangular shape, the corner land is larger than the intermediate land as in the first embodiment. By doing so, the misalignment width g capable of self-alignment can be increased. (Second Embodiment) FIG. 12 and FIG. 1 of the second embodiment of the present invention.
3 shows. The same reference numerals as those in the first embodiment indicate substantially the same components.

The circuit board 50 has the conductor 6 on the surface of the board 51.
3 is printed, and the glass 52 is formed on the conductor 63. Unlike the first embodiment in which the width a of the corner land 11 is determined by the shape of the conductor 53, in the second embodiment, the distance from the inner end 64b of the corner land to the window 62a provided in the glass 62 is determined. The width a determines the width a of the corner land 62. Since solder does not adhere to the portion where the glass 62 is formed, the positional deviation width g can be increased also in the second embodiment as in the first embodiment.

[Brief description of drawings]

FIG. 1 is a plan view showing a hybrid integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing how semiconductor chips are self-aligned in the hybrid integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a state in which a semiconductor chip is self-aligned in the hybrid integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a state in which semiconductor chips are self-aligned in the hybrid integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a state in which semiconductor chips are self-aligned in the hybrid integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a state in which a semiconductor chip is self-aligned in the hybrid integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is a schematic plan view showing a positional deviation width g in the present invention.

FIG. 8 is a schematic plan view showing a positional deviation width g in the present invention.

FIG. 9 is a schematic plan view showing a positional deviation width g in the present invention.

FIG. 10 is a schematic plan view showing a positional deviation width g in the present invention.

FIG. 11 is a schematic plan view showing a positional deviation width g in the present invention.

FIG. 12 is a plan view showing a hybrid integrated circuit device according to a second embodiment of the present invention.

13 is a sectional view taken along line XIII-XIII in FIG.

FIG. 14 is a plan view showing a conventional hybrid integrated circuit device.

FIG. 15 is a plan view showing a conventional hybrid integrated circuit device.

FIG. 16 is a plan view showing a conventional hybrid integrated circuit device.

FIG. 17 is a plan view showing a conventional hybrid integrated circuit device.

[Explanation of symbols]

1 Hybrid integrated circuit device 10 lands 11, 12, 13, 14 Corner land 15 Middle land 30 bumps 31, 32, 33, 34 Corner bump 35 Intermediate bump 50 circuit board 54 Semiconductor chips (electrical parts)

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuhiro Saito 1-1, Showa-cho, Kariya city, Aichi Japan Denso Co., Ltd. (56) References JP 62-73639 (JP, A) JP 6- 45402 (JP, A) JP-A 2-164045 (JP, A) Actual development Sho 56-106471 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12 501 H01L 21/60 311 H05K 1/18

Claims (4)

(57) [Claims] 1. The terminals are arranged in a rectangular shape and are arranged in the same manner as the terminals.
It consists of an electric component having bumps of the same size, and a circuit board having a land at a position corresponding to the bump. After mounting the electric component on the circuit board, the bumps are melted. By the hybrid integrated circuit device in which the electric component is soldered to the circuit board by the, the land consists of corner lands provided in the four corners of the rectangle and intermediate lands provided in other parts, The hybrid integrated circuit device, wherein the corner land is larger than the intermediate land. 2. A contact surface between the corner bump and the corner land when the bump is melted at the soldering basic position where the electric component is mounted at a predetermined position on the circuit board, and the intermediate bump and the middle portion. 2. The hybrid integrated circuit device according to claim 1, wherein the diameter f of the contact surface with the land is smaller than the width b of the intermediate land. 3. At the soldering basic position, the distance from the side of the corner land facing the adjacent intermediate land to the outer circumference of the contact surface is such that the adjacent sides of the adjacent intermediate lands are adjacent to each other. The distance from the side of the intermediate land facing the corner land to the outer periphery of the contact surface,
3. The hybrid integrated circuit device according to claim 2, wherein they are equal . 4. On each side of the rectangle, the width of the corner land is a, the width of the intermediate land is b, the distance between adjacent lands is d, and the electrical component is the circuit board. When the diameter of the contact surface between the corner bump and the corner land and the contact surface between the intermediate bump and the middle land at the time of melting the bump at the soldering basic position mounted at a predetermined position is f, The positional shift width g capable of automatically aligning the positional shift generated when the electric component is placed on the circuit board is {g + (1/2) × (b−f)} <a <(b + f) , {G + (1/2) × (f−b)} <d, g <{(3/2) f + (1/2) b}, are satisfied at the same time.
A hybrid integrated circuit device as described.