JPS6151945A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6151945A JPS6151945A JP59174649A JP17464984A JPS6151945A JP S6151945 A JPS6151945 A JP S6151945A JP 59174649 A JP59174649 A JP 59174649A JP 17464984 A JP17464984 A JP 17464984A JP S6151945 A JPS6151945 A JP S6151945A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor device
- hole
- connection terminal
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は半導体装置にかがシとくにいわゆるリードレス
・タイプの半導体装置の端子構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device, and particularly to a terminal structure of a so-called leadless type semiconductor device.
（従来技術）
従来いわゆるリードレヌタイプの半導体装置の外部接続
端子は該半導体装置のパッケージ周縁部に並べて作られ
ている。(Prior Art) Conventionally, external connection terminals of a so-called lead-lens type semiconductor device are arranged side by side at the periphery of the package of the semiconductor device.
これは、該外部接続端子と回路基板とを低融点ロー材等
によって電気的に接続する場合、その作業の確実に行な
われたか否かの判断が外観によって判定できること、半
導体装置回路基板とロー材間の熱膨張係数の相違からロ
ー材には機械的なストレスが負荷され、これによってロ
ー材が破断するおそれがちるが、これが周縁にもロー材
がちれば強度上右利になることなどのためである。This means that when electrically connecting the external connection terminal and the circuit board using a low melting point brazing material, etc., it is possible to judge from the appearance whether the work has been done reliably, and that the semiconductor device circuit board and the brazing material Due to the difference in the coefficient of thermal expansion between the two, mechanical stress is applied to the brazing material, which may cause the brazing material to break. However, if this also occurs at the periphery, the strength will be affected. It's for a reason.
しかるに、外部接続端子のピッチは互換性、汎用性を確
保するため規格化する必要がちり、かつ、最近の大規模
集積回路の如く、外部接続端子数が増加してくると、大
きな外形を有するパッケージを用意しなければならなく
なる。これでは回路基板上における半導体装置の占有面
積が大きくなシ高密度実装を指向する電子装置の要請に
反することになる。However, the pitch of external connection terminals tends to need to be standardized to ensure compatibility and versatility, and as the number of external connection terminals increases, as in recent large-scale integrated circuits, the external connection terminals have a large external shape. You will have to prepare a package. This goes against the demands of electronic devices that require high-density packaging in which the semiconductor device occupies a large area on the circuit board.
これらの状況において、外部接続端子をパンケージ周縁
に並べるばか夛でなく、内部にも設ける必要が生じてき
たが単に内部に設けるだけではそれら外部接続端子の回
路基板への電気的接続がうまくいく訳ではない。Under these circumstances, it has become necessary to provide external connection terminals not only on the periphery of the pan cage, but also inside the pancase, but simply providing them inside does not ensure a successful electrical connection of the external connection terminals to the circuit board. isn't it.
なぜなら、それらの外部接続端子を例えば半田で接続し
ようとすると使用した７ラツクスの逃げ場がない為有効
に機能せず、半田がうまく流れてくれない、７２ツクス
残渣の洗浄が５まくいかない、接続がうまくいったのか
否か外観的に確認することができない、半田量を大きく
取ることができず温度ブイタルの様な熱によるストレス
に対して弱い等々の欠点を生じてしまうからである。This is because if you try to connect these external connection terminals with solder, for example, the 72x used will not work effectively because there is no place for it to escape, the solder will not flow properly, the 72x residue will not be cleaned properly, and the connection will not work properly. This is because it is not possible to visually confirm whether or not the solder is successful, and it is not possible to use a large amount of solder, making it vulnerable to stress caused by heat such as temperature fluctuations.
したがって、どうしても行う必要がある場合には、あら
かじめ半田等の低融点ロー材を流してバンズ又はペテス
タルと称するロー材の小突起を作っておき、十分洗浄し
ておいて、接合すべき部材を不活性ガス雰囲気中で加熱
することになる。この方法は設備的にも作業工数的にも
費用のかかるものになってしまうのは明らかである。Therefore, if it is absolutely necessary to do this, pour a low-melting brazing material such as solder in advance to create small protrusions of the brazing material called buns or petestals, and thoroughly wash the soldering material beforehand. It will be heated in an active gas atmosphere. It is clear that this method is expensive in terms of equipment and man-hours.
（発明の目的）
本発明の目的は、上述の欠点を除去し得る半導体装置を
提供するものである。(Object of the Invention) An object of the present invention is to provide a semiconductor device that can eliminate the above-mentioned drawbacks.
（発明の構成）
かかる目的を達成するための本発明の構成は、外部接続
端子にパッケージ基体の上下面を貫通する孔を設けるこ
とである。(Structure of the Invention) The structure of the present invention for achieving the above object is to provide the external connection terminal with a hole penetrating the upper and lower surfaces of the package base.
（発明の作用、効果）
この様にすれば、外部接続端子がパッケージの ″内側
に存在していても、十分に接続端子としての機能を発揮
することができる。接続法として、半田等の低融点ロー
材粉末をバインダーを混ぜ”Ｃペースト状にして、回路
基板上にスクリーンを印刷する方法が知られているが、
この様な一般的な方法で十分対処できるのである。(Operations and Effects of the Invention) In this way, even if the external connection terminal exists inside the package, it can sufficiently function as a connection terminal. A known method is to mix melting point brazing material powder with a binder to form a "C paste" and then print a screen on a circuit board.
This general method can be used to deal with the problem.
即ち、外部接続端子に設けられた貫通孔がフラックスの
分解ガスの逃げ場となシ貫通孔に半田がはい上がって接
続の確認が外観ででき、貫通孔が半田等のロー材のたま
シとなって機械的強度を維持することができる。In other words, the through-hole provided in the external connection terminal serves as an escape for the decomposed gas of the flux, the solder creeps up into the through-hole, and the connection can be visually confirmed, and the through-hole serves as a receptacle for brazing material such as solder. mechanical strength can be maintained.
（実施例） 以下に本発明を実施例に基づき詳細に説明する。(Example) The present invention will be explained in detail below based on examples.
第１図は本発明の第一の実施例でろって半導体素子を樹
脂基板上に搭載した半導体装置についての横断面図であ
る。Ｃｕ等の全屈の配線層の一部に半導体装置の外部接
続端子位置に対応する接続端う−２を有するプリント基
板１上に、半導体装置３が半田４で接続されている。半
導体装置３の外部接続端子５には貫通孔６が設けられて
おシ第１図では半田４が充填されている。貫通孔６の周
辺部はいわゆるスルーホールメッキが施され、実装時の
半田のはい上りを容易にしている。溶融半田は、その表
面張力によって、プリント基板上の半導体装置の相対位
置ズレを修正する。半田量は半田が貫通孔の上部に達す
るに必要な量が好ましい。この半田量のコントロールは
プリント基板への半田印刷する際使用する印刷パターン
のマスクの厚みを加減して行うことができる。半田の組
成については共晶、高融点いずれであってもよい。使用
する半導体装置の材料特性、用途静から決定することが
望ましい。勿論、バーブ又はベテスタル金作りておく方
法にも適用できる。接続の際の加熱手段として所要の温
度槽に入れる方法以外に、その貫通孔の上からレーザー
ビームを照射する手段でもよい。さらに、半田をもちい
て接続する方法として浴融半田を用いたフロ一槽に浸漬
する方法も採用できる。貫通孔の為溶融半田が回路基板
と半導体装置のパッケージの間に入っていくからである
。半導体装置の基板への位置決めには、チップ抵抗、チ
ッズコンテン丈−等のいわゆるテッグ部品の位置決め固
定の為の紫外線硬化型又は熱硬化型の樹脂を利用できる
。この方法は量産性に富み低コストでの組立を可能にす
る。FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, in which a semiconductor element is mounted on a resin substrate. A semiconductor device 3 is connected by solder 4 to a printed circuit board 1 having a connection end 2 corresponding to an external connection terminal position of the semiconductor device on a part of a fully bent wiring layer made of Cu or the like. A through hole 6 is provided in the external connection terminal 5 of the semiconductor device 3 and is filled with solder 4 in FIG. The periphery of the through-hole 6 is plated with so-called through-hole plating to facilitate solder creep-up during mounting. The molten solder uses its surface tension to correct the relative positional deviation of the semiconductor device on the printed circuit board. The amount of solder is preferably the amount necessary for the solder to reach the top of the through hole. The amount of solder can be controlled by adjusting the thickness of the mask for the printing pattern used when printing solder on the printed circuit board. The composition of the solder may be either eutectic or high melting point. It is desirable to determine this based on the material characteristics and intended use of the semiconductor device to be used. Of course, it can also be applied to methods of making barb or betestal gold. As a heating means during connection, in addition to the method of placing the device in a required temperature bath, a method of irradiating a laser beam from above the through hole may be used. Furthermore, as a method of connecting using solder, a method of immersing in a bath using bath melting solder can also be adopted. This is because the through holes allow molten solder to enter between the circuit board and the package of the semiconductor device. For positioning the semiconductor device on the substrate, an ultraviolet curing or thermosetting resin can be used for positioning and fixing so-called TEG components such as chip resistors and chip content lengths. This method is highly suitable for mass production and enables assembly at low cost.
第２図は本発明の第２の実施例を示す横断面図である。FIG. 2 is a cross-sectional view showing a second embodiment of the invention.
本実施例では半田印刷技術を利用できない場合、例えば
他の半導体装置等の電子部品と混載されスクリーン印刷
がプリント基板側にも、半導体装置側にも行えない場合
に適する。プリント基板１には銅やリン竹銅のビン７を
所定の位置（半導体装置τＩ１１の外部接続端子位置に
対応）に設けておき、そのビンに半導体装置の貫通孔６
ｔ−利用して挿入する。This embodiment is suitable for cases where solder printing technology cannot be used, for example, when electronic components such as other semiconductor devices are mounted together and screen printing cannot be performed on either the printed circuit board side or the semiconductor device side. A bottle 7 made of copper or phosphor-bamboo copper is provided on the printed circuit board 1 at a predetermined position (corresponding to the position of the external connection terminal of the semiconductor device τI11), and the through-hole 6 of the semiconductor device is inserted into the bottle.
Insert using t-.
プリント基板に設けるビンは個別に挿入しておいても、
まとめてソケットの様な部品にしておいてもよい。ビン
の表面には半田に濡れやすいＳｎや５ｎ−ｐｂのメッキ
を施しておくと作業が容易になる。Even if the bins provided on the printed circuit board are inserted individually,
They may be put together into a component such as a socket. The work will be easier if the surface of the bottle is plated with Sn or 5n-PB, which is easily wetted by solder.
半導体装置をビンに挿入した後は半田ゴテによる半田付
等、公知の手段を利用して電気的に接続することができ
る。After the semiconductor device is inserted into the bottle, it can be electrically connected using known means such as soldering with a soldering iron.
以上、樹脂基板上に半導体端子を搭載した半導体装置に
ついて説明したが、これは、いわゆるセ２ミックバック
ージでもよく、半導体端子を搭載する材料として、電気
絶縁基体であって、導体配線が可能であれば踵部は問わ
ない。The semiconductor device in which semiconductor terminals are mounted on a resin substrate has been described above, but this may also be a so-called semi-conductor substrate, as long as the material on which the semiconductor terminals are mounted is an electrically insulating substrate and conductive wiring is possible. The heel part doesn't matter.
また、半導体装置側の外部接続端子の配列は格子状に配
列するビン・グリッドアレイタイプでも二列に配列する
デュアル・イン・ラインタイプでもよく、特に配列に制
約は受けないばかシかスルーホール穴を小さくあけるこ
とができれば高密度実装を実現することもできる。In addition, the arrangement of external connection terminals on the semiconductor device side may be a bin grid array type in which they are arranged in a grid pattern or a dual-in-line type in which they are arranged in two rows, and there are no particular restrictions on the arrangement. If the opening can be made small, high-density packaging can be achieved.
第１図は本発明の第一の実施例を示す横断面図である。
第２図は本発明の第二の実施例を示す横断面図である。
いずれもプリント基板に実装された状態を示している。
尚、図において１ ・プリント基板、２・・フ゛リント
基板側接続端子、３・半導体装置、４・・半田等の低融
点ロー材、５・・・半導体装置の外部接続端子、６・・
・貫通孔、７・・・ビン、８・・半導体端子、９・・・
接続用導体、１０・・封入用樹脂、１１・・・保護用樹
脂層。
箱 １ ン
勿５ ２ 図FIG. 1 is a cross-sectional view showing a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a second embodiment of the invention. Both are shown mounted on a printed circuit board. In the figure, 1. Printed circuit board, 2. Print board side connection terminal, 3. Semiconductor device, 4. Low melting point brazing material such as solder, 5. External connection terminal of semiconductor device, 6.
・Through hole, 7... Bin, 8... Semiconductor terminal, 9...
Connecting conductor, 10... Encapsulating resin, 11... Protective resin layer. Box 1 5 2 Figure
Claims (2)
体装置において、外部接続端子には、電気絶縁基体の上
下面を貫通する孔を有することを特徴とする半導体装置
。(1) A semiconductor device using an electrically insulating base having electrical conductor wiring, wherein the external connection terminal has a hole penetrating the upper and lower surfaces of the electrically insulating base.
点ろう材が充填されていることを特徴とする特許請求の
範囲第（１）項記載の半導体装置。(2) The semiconductor device according to claim (1), wherein the through hole provided in the external connection terminal is filled with a low melting point brazing material in advance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59174649A JPS6151945A (en) | 1984-08-22 | 1984-08-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59174649A JPS6151945A (en) | 1984-08-22 | 1984-08-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6151945A true JPS6151945A (en) | 1986-03-14 |
Family
ID=15982282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59174649A Pending JPS6151945A (en) | 1984-08-22 | 1984-08-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151945A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02199897A (en) * | 1988-11-30 | 1990-08-08 | Hughes Aircraft Co | Multilarger printed wiring board having single larger through hole |
| KR20020096640A (en) * | 2001-06-21 | 2002-12-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package & Mounting method to Motherboard the same |
-
1984
- 1984-08-22 JP JP59174649A patent/JPS6151945A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02199897A (en) * | 1988-11-30 | 1990-08-08 | Hughes Aircraft Co | Multilarger printed wiring board having single larger through hole |
| KR20020096640A (en) * | 2001-06-21 | 2002-12-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package & Mounting method to Motherboard the same |
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